Band-gap reference voltage output judgment circuit and device and electronic equipment

Abstract

The invention relates to a band-gap reference voltage output judgment circuit, a band-gap reference voltage output judgment device and electronic equipment, and determines whether band-gap reference voltage generated by a reference voltage generation circuit can be output to a load module or not by judging the conduction state of a switching tube in a signal comparison circuit. Only when the judgment signal comparison circuit outputs the high-level judgment signal, the band-gap reference voltage is output to the load module, the size of the band-gap reference voltage is judged, it is guaranteed that the band-gap reference voltage acts on the load module as the normal working voltage of the load module, and functional errors of the load module are avoided.

Description

Technical Field

[0001] The present application relates to the field of radio frequency identification technology, and in particular to an output judgment circuit, device and electronic equipment for a bandgap reference voltage. Background Art

[0002] In analog circuit operation, it is usually necessary to convert the external input power supply voltage into a reference voltage for the circuit to work, and the reference voltage is divided by resistor ratio for use by each load module. However, in the prior art, the load modules often fail to work properly. Summary of the invention

[0003] Based on this, it is necessary to provide a bandgap reference voltage output judgment circuit, device and electronic equipment that can ensure that all connected load modules work normally.

[0004] In a first aspect, a bandgap reference voltage output determination circuit is provided, the output determination circuit comprising: A reference voltage generating circuit, used for generating a bandgap reference voltage according to a power supply voltage at power-on; A judgment signal comparison circuit is connected to the reference voltage generating circuit and includes at least one switch tube, which is used to output a high-level judgment signal when the power supply voltage is greater than the conduction voltage of each of the switch tubes; the high-level judgment signal acts on the reference voltage generating circuit to control the bandgap reference voltage to be output to a load module, and the load module is connected to the reference voltage generating circuit.

[0005] In one of the embodiments, the judgment signal comparison circuit is also used to output a low-level judgment signal when the power supply voltage is less than or equal to the turn-on voltage of any of the switch tubes; the low-level judgment signal acts on the reference voltage generation circuit to control the bandgap reference voltage not to be output to the load module.

[0006] In one embodiment, the reference voltage generating circuit comprises: A starting circuit, used for generating a potential control voltage according to the power supply voltage; The core circuit is connected to the startup circuit and includes a plurality of mirror switch tubes for receiving the potential control voltage, stabilizing the gate potential of each mirror switch tube, controlling each mirror switch tube to close and conduct, and generating a bandgap reference voltage.

[0007] In one embodiment, the judgment signal comparison circuit includes: The first comparison circuit is connected to the startup circuit and the core circuit, and includes at least one switch tube, which is used to receive the component signals of the potential control voltage and the bandgap reference voltage, and when the power supply voltage is greater than the conduction voltage of each switch tube, controls each switch tube to close and conduct, and outputs a high-level judgment signal.

[0008] In one of the embodiments, the first comparison circuit is further used to control at least one of the switch tubes to be turned off and output a low-level judgment signal when the power supply voltage is less than the on-voltage of at least one of the switch tubes based on the component signals of the potential control voltage and the bandgap reference voltage received.

[0009] In one embodiment, the judgment signal comparison circuit further includes: The second comparison circuit is connected to the first comparison circuit and the startup circuit, and includes a current source for controlling the current source to maintain the low level state of the judgment signal when the first comparison circuit outputs the low level judgment signal and the startup circuit works normally.

[0010] In one embodiment, the first comparison circuit includes: a PMOS tube M9, a PMOS tube M11, a PMOS tube M10, a Schmitt trigger I2 and an inverter I3. The gate of the PMOS tube M9 is connected to the core circuit, the source of the PMOS tube M9 is connected to the gate of the PMOS tube M11, and the drain of the PMOS tube M9 is connected to the startup circuit; the source of the PMOS tube M11 is connected to the power supply voltage, and the drain of the PMOS tube M11 is connected to the input end of the Schmitt trigger I2; the output end of the Schmitt trigger I2 is connected to the input end of the inverter I3, and the output end of the inverter I3 outputs the judgment signal; the gate and source of the PMOS tube M10 are connected to the power supply voltage, and the drain of the PMOS tube M10 is connected to the gate of the PMOS tube M11; When the gate of the PMOS tube M9 receives the component signal of the bandgap reference voltage and is closed and turned on, the PMOS tube M11 is closed and turned on, and the inverter I3 outputs the high-level judgment signal; When the gate of the PMOS tube M9 receives the component signal of the bandgap reference voltage and is turned off, the PMOS tube M11 is turned off, and the inverter I3 outputs the low-level determination signal.

[0011] In one embodiment, the second comparison circuit includes a current source I4, an NMOS tube M13, a Schmitt trigger I1, a PMOS tube M8, an NMOS tube M12, and a transistor Q5. The source of the PMOS tube M8 is connected to the power supply voltage, the gate of the PMOS tube M8 is connected to the startup circuit, the drain of the PMOS tube M8 is connected to the drain of the NMOS tube M12, the gate of the NMOS tube M12 is connected to the startup circuit, the source of the NMOS tube M12 is connected to the emitter of the transistor Q5, and the base and collector of the transistor Q5 are connected to a common ground; the input end of the Schmitt trigger I1 is connected to the drain of the NMOS tube M12, the output end of the Schmitt trigger I1 is connected to the gate of the NMOS tube M13, the drain of the NMOS tube M13 is connected to the input end of the Schmitt trigger I2 in the first comparison circuit, and the source of the NMOS tube M13 is connected to a common ground; the current source I4 is connected between the source and the drain of the NMOS tube M13; When the NMOS tube M12 is turned off, the NMOS tube M13 is also turned off; the current source I4 pulls down the drain of the NMOS tube M13 to maintain the low level state of the determination signal.

[0012] In a second aspect, a bandgap reference voltage conversion device is provided, comprising the bandgap reference voltage output determination circuit as described in the first aspect.

[0013] According to a third aspect, an electronic device is provided, comprising an output judgment circuit for a bandgap reference voltage and a load module as described in the first aspect, wherein the output judgment circuit for a bandgap reference voltage is connected to the load module.

[0014] The above-mentioned bandgap reference voltage output judgment circuit, device and electronic device determine whether the bandgap reference voltage generated by the reference voltage generation circuit can be output to the load module by judging the conduction state of the switch tube in the signal comparison circuit. Only when the signal comparison circuit outputs a high-level judgment signal, the bandgap reference voltage is output to the load module, thereby realizing the size judgment of the bandgap reference voltage, ensuring that the bandgap reference voltage acts on the load module with the normal working voltage of the load module, and avoiding functional errors of the load module. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 A structural block diagram of an output determination circuit for a bandgap reference voltage according to an embodiment; Figure 2is a circuit diagram of a reference voltage generating circuit according to an embodiment; Figure 3 The level states of VN1 and VP1 before and after power-on in one embodiment; Figure 4 FIG. 4 is a circuit diagram of a judgment signal comparison circuit according to an embodiment. DETAILED DESCRIPTION

[0017] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0019] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor may be referred to as a second resistor, and similarly, a second resistor may be referred to as a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0020] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0021] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0022] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0023] Since the size of the bandgap reference voltage depends on the power supply voltage, if the power supply voltage is not large enough, the generated reference voltage will be much smaller than the voltage required for the normal operation of the load module, causing functional errors of the load module. Figure 1 As shown, a bandgap reference voltage output judgment circuit is provided, which includes a reference voltage generating circuit 10 and a judgment signal comparing circuit 20.

[0024] The reference voltage generating circuit 10 is used to generate a bandgap reference voltage V according to the power supply voltage VDD at power-on. bg .

[0025] The judgment signal comparison circuit 20 is connected to the reference voltage generation circuit 10 and includes at least one switch tube for generating a reference voltage when the power supply voltage VDD is greater than the conduction voltage V gs When the switch tubes are closed and turned on, a high-level judgment signal is output. The high-level judgment signal acts on the reference voltage generating circuit 10 to control the bandgap reference voltage V bg The voltage is output to a load module, and the load module is connected to the reference voltage generating circuit.

[0026] Preferably, the judgment signal comparison circuit 20 is further used for judging that when the power supply voltage VDD is less than or equal to the conduction voltage V gs When the corresponding switch tube is turned off, a low-level judgment signal is output; the low-level judgment signal acts on the reference voltage generating circuit 10 to control the bandgap reference voltage V bg No output to the load module.

[0027] In this embodiment, by judging the conduction state of the switch tube in the signal comparison circuit, it is determined whether the bandgap reference voltage generated by the reference voltage generation circuit can be output to the load module. Only when the signal comparison circuit outputs a high-level judgment signal, the bandgap reference voltage is output to the load module, thereby realizing the size determination of the bandgap reference voltage, ensuring that the bandgap reference voltage acts on the load module with the normal working voltage of the load module, and avoiding functional errors of the load module.

[0028] In one embodiment, the reference voltage generating circuit 10 includes a startup circuit 101 and a core circuit 102 .

[0029] The startup circuit 101 is used to generate a potential control voltage according to the power supply voltage.

[0030] The core circuit 102 is connected to the startup circuit 101 and includes a plurality of mirror switch tubes for receiving the potential control voltage, stabilizing the gate potential of each mirror switch tube, controlling each mirror switch tube to close and conduct, and generating a bandgap reference voltage Vbg .

[0031] like Figure 2 As shown, the core circuit 102 includes NMOS transistors M1, M2, PMOS transistors M3, M4, M5, transistors Q1, Q2, Q2, and resistors R1 and R2. The startup circuit 101 includes NMOS transistors M6, M7, transistors Q4, and resistor R3.

[0032] In the core circuit 102, the base of the transistor Q1 is connected to the base of the transistor Q2 and then connected to the common ground, the collector and the collector are connected to the common ground, the emitter of the transistor Q1 is connected to the source of the NMOS transistor M1, the emitter of the transistor Q2 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the emitter of the NMOS transistor M2. The drain of the NMOS transistor M1 is connected to its own gate and the drain of the PMOS transistor M4, the drain of the NMOS transistor M2 is connected to the drain of the PMOS transistor M3, and the drain of the PMOS transistor M3 is connected to its own gate. The source of the PMOS transistor M3, the source of the PMOS transistor M4, and the source of the PMOS transistor M5 are connected to the power supply voltage VDD. The drain of the PMOS transistor M5 is connected to one end of the resistor R2, the other end of the resistor R2 is connected to the emitter of the transistor Q3, and the base and collector of the transistor Q3 are connected to the common ground.

[0033] In the startup circuit 101, one end of the resistor R3 is connected to the external power supply voltage, the other end of the resistor R3 is connected to the drain of the NMOS tube M6, the source of the NMOS tube M6 is connected to the emitter of the transistor Q4, and the gate of the NMOS tube M6 is connected to the gate of the NMOS tube M1 in the core circuit 102. The gate of the NMOS tube M7 is connected to the other end of the resistor R3, the source of the NMOS tube M7 is connected to the emitter of the transistor Q4, and the drain of the NMOS tube M7 is connected to the gate of the PMOS tube M3 in the core circuit 102.

[0034] The gate of the NMOS transistor M1 in the core circuit 102 is connected to the gate of the NMOS transistor M2 and the gate of the NMOS transistor M6, and the gate potential after the connection is controlled by the gate voltage of the NMOS transistor M6 in the startup circuit 101. The gate of the PMOS transistor M3 in the core circuit 102 is connected to the gate of the PMOS transistor M4 and the gate of the PMOS transistor M5, and the gate potential after the connection is controlled by the drain voltage of the NMOS transistor M7 in the startup circuit 101.

[0035] In detail, the potential control voltage includes the drain voltage of the NMOS tube M7 and the gate voltage of the NMOS tube M6. Since the potentials of VN1 and VP1 are uncertain when power is on, when VN1 is low and VP1 is high, the NMOS tube M1 and the PMOS tube M3 are in the cut-off state and cannot be closed and turned on, and the core circuit cannot work normally. Therefore, through the startup circuit 101, when power is on, the gate of the NMOS tube M7 is pulled up by the resistor R3, the NMOS tube M7 is closed and turned on, and the gate potential VP1 is pulled down. When the gate potential VP1 is pulled down to make the PMOS tube M4 closed and turned on, the gate potential VN1 is pulled up, and each MOS on the core circuit 102 is turned on, and the core circuit 102 starts to work normally, generating a bandgap reference voltage V bg The voltage levels of VN1 and VP1 before and after power-on are as follows: Figure 3 As shown in the figure, T Vgs4导通 Indicates the moment when the PMOS tube M4 is closed and turned on.

[0036] In one embodiment, the determination signal comparison circuit 20 includes a first comparison circuit 201 and a second comparison circuit 202 .

[0037] The first comparison circuit 201 is connected to the startup circuit 101 and the core circuit 102, and includes at least one switch tube for receiving the potential control voltage and the bandgap reference voltage V bg The component signal V be When the power supply voltage VDD is greater than the turn-on voltage of each of the switch tubes, each of the switch tubes is controlled to be closed and turned on, and a high-level judgment signal is output.

[0038] Preferably, the first comparison circuit is further configured to receive the potential control voltage and the bandgap reference voltage V bg The component signal V be , when the power supply voltage VDD is less than the conduction voltage V gs When the at least one switch tube is controlled to be turned off, a low level judgment signal is output.

[0039] The second comparison circuit 202 is connected to the first comparison circuit 201 and the startup circuit 101, and includes a current source for controlling the current source to maintain the low level state of the judgment signal when the first comparison circuit outputs the low level judgment signal and the startup circuit 101 works normally.

[0040] like Figure 4As shown, the first comparison circuit 201 includes PMOS tube M9, PMOS tube M11, PMOS tube M10, Schmitt trigger I2 and inverter I3. The second comparison circuit 202 includes current source I4, NMOS tube M13, Schmitt trigger I1, PMOS tube M8, NMOS tube M12 and transistor Q5.

[0041] In the first comparison circuit 201, the gate of the PMOS tube M9 is connected to the emitter of the transistor Q2 in the core circuit 102, the source of the PMOS tube M9 is connected to the gate of the PMOS tube M11, and the drain of the PMOS tube M9 is connected to the drain of the NMOS tube M7 in the startup circuit 101; the source of the PMOS tube M11 is connected to the power supply voltage, and the drain of the PMOS tube M11 is connected to the input end of the Schmitt trigger I2; the output end of the Schmitt trigger I2 is connected to the input end of the inverter I3, and the output end of the inverter I3 outputs the judgment signal; the gate and source of the PMOS tube M10 are connected to the power supply voltage VDD, and the drain of the PMOS tube M10 is connected to the gate of the PMOS tube M11.

[0042] In the second comparison circuit 202, the source of the PMOS tube M8 is connected to the power supply voltage VDD, the gate of the PMOS tube M8 is connected to the drain of the NMOS tube M7 in the startup circuit 101, the drain of the PMOS tube M8 is connected to the drain of the NMOS tube M12, the gate of the NMOS tube M12 is connected to the drain of the NMOS tube M6 in the startup circuit 101, the source of the NMOS tube M12 is connected to the emitter of the transistor Q5, and the base and collector of the transistor Q5 are connected to the common ground. The input end of the Schmitt trigger I1 is connected to the drain of the NMOS tube M12, the output end of the Schmitt trigger I1 is connected to the gate of the NMOS tube M13, the drain of the NMOS tube M13 is connected to the input end of the Schmitt trigger I2 in the first comparison circuit 201, and the source of the NMOS tube M13 is connected to the common ground; the current source I4 is connected between the source and drain of the NMOS tube M13.

[0043] Specifically, when the gate of the PMOS tube M9 receives the bandgap reference voltage V bg The component signal V be When the gate of the PMOS tube M9 receives the bandgap reference voltage V bg The component signal V beWhen the PMOS tube M11 is turned off, the inverter I3 outputs the low-level judgment signal. When the NMOS tube M6 is closed and turned on, the NMOS tube M12 is turned off, and the NMOS tube M13 is turned off; the current source I4 pulls down the drain of the NMOS tube M13 to maintain the low-level state of the judgment signal.

[0044] In detail, since the drain voltage VP1 of the NMOS transistor M7 in the startup circuit 101 is low after being turned on and the emitter of the transistor Q2 outputs the effective bandgap reference voltage V bg The component signal V be , at this time the component signal V be is greater than 0V, so the gate of the PMOS tube M9 in the first comparison circuit 201 is affected by the effective component signal V be Control conduction, the source of PMOS tube M9, that is, the gate of PMOS tube M11, generates (V be +V gs9 ) voltage, where V gs9 Indicates the gate-source voltage of the PMOS tube M9. At this time, if the power supply voltage VDD is lower than (V be +V gs9 +V gs11 ), where V gs11 represents the gate-source voltage of the PMOS tube M11. The power supply voltage VDD is not enough to turn on the PMOS tube M11. The drain of the PMOS tube M11 is low. After passing through the Schmitt trigger I2 and the inverter I3, a low-level judgment signal is output, thereby controlling the bandgap reference voltage V bg Not output to the subsequent load module; on the contrary, if the power supply voltage VDD is higher than (V be +V gs9 +V gs11 ), the PMOS tube M11 is turned on, the drain of the PMOS tube M11 is high, and after passing through the Schmitt trigger I2 and the inverter I3, a high-level judgment signal is output, thereby controlling the bandgap reference voltage V bg The output is sent to the load module. The function of the PMOS tube M10 is to maintain the gate of the PMOS tube M11 high when the PMOS tube M9 is in the off state, thereby ensuring that the PMOS tube M11 is in the off state.

[0045] It should be noted that there is a MOS tube in the core circuit 102 that is not turned on, and the component signal V be The size of is close to the ground, the PMOS tube M9 and the PMOS tube M11 are both turned off, the drain of the PMOS tube M11 is low, and a low-level judgment signal is output.

[0046] Through the first comparison circuit, the control judgment signal is greater than V be +Vgs9 +V gs11 When the voltage of the bandgap reference voltage is high, the load module can be properly operated and the functional error of the load module can be avoided. More preferably, the size of the PMOS tube M9 and the PMOS tube M11 can be changed to change the V gs9 +V gs11 The size of V can be changed by changing the gate voltage of the PMOS tube M9. be The size of the power supply voltage required to output a high-level judgment signal is changed by the size of the power supply voltage.

[0047] In detail, when the startup circuit 101 and the core circuit 102 work normally, the bandgap reference voltage V bg After that, since the gate voltage VN1 of the NMOS tube M6 in the start-up circuit 101 is pulled high, the NMOS tube M6 is turned on, and the drain of M6 is low, so the gate of the NMOS tube M12 in the second comparison circuit 202 is pulled low, and the NMOS tube M12 is turned off and cut off. At this time, the drain of the NMOS tube M12 is at a high potential. The input end of the Schmitt trigger I1 is connected to the high potential for rectification and reverse logic processing, and a logic low level signal is output to the gate of the NMOS tube M13 to control the NMOS tube M13 to be turned off and cut off at a low level. After the NMOS tube M13 is turned off, its drain is a potential floating point, which can be any potential, so this point is pulled low by the current source I4 to ensure that the drain potential of the NMOS tube M13 will not affect the input potential of the Schmitt trigger I2 in the first comparison circuit 201, thereby ensuring that the low level state of the judgment signal can be maintained when the first comparison circuit outputs the low level judgment signal.

[0048] More specifically, if Figure 4 As shown, the output judgment circuit of the bandgap reference voltage also includes capacitors C1, C2 and C3, which are used to filter the loop current. The capacitor C1 is connected between the gate of the NMOS tube M12 and the common ground; the capacitor C2 is connected between the input end of the Schmitt trigger I1 and the common ground; and the capacitor C3 is connected between the drain of the NMOS tube M13 and the common ground.

[0049] In one embodiment, a bandgap reference voltage conversion device is provided, the device comprising the output determination circuit of the bandgap reference voltage as described in the above embodiments.

[0050] In one embodiment, an electronic device is provided. The electronic device includes an output judgment circuit for a bandgap reference voltage and a load module as described in the above embodiments. The output judgment circuit for a bandgap reference voltage is connected to the load module.

[0051] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0052] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A bandgap reference voltage output determination circuit, characterized in that: The output judgment circuit comprises: A reference voltage generating circuit, used for generating a bandgap reference voltage according to a power supply voltage at power-on; A judgment signal comparison circuit is connected to the reference voltage generating circuit and includes at least one switch tube, which is used to output a high-level judgment signal when the power supply voltage is greater than the conduction voltage of each of the switch tubes; the high-level judgment signal acts on the reference voltage generating circuit to control the bandgap reference voltage to be output to a load module, and the load module is connected to the reference voltage generating circuit.

2. The output determination circuit of the bandgap reference voltage according to claim 1, characterized in that: The judgment signal comparison circuit is also used to output a low-level judgment signal when the power supply voltage is less than or equal to the conduction voltage of any of the switch tubes; the low-level judgment signal acts on the reference voltage generation circuit to control the bandgap reference voltage not to be output to the load module.

3. The output determination circuit of the bandgap reference voltage according to claim 2, characterized in that: The reference voltage generating circuit comprises: A starting circuit, used for generating a potential control voltage according to the power supply voltage; The core circuit is connected to the startup circuit and includes a plurality of mirror switch tubes for receiving the potential control voltage, stabilizing the gate potential of each mirror switch tube, controlling each mirror switch tube to close and conduct, and generating a bandgap reference voltage.

4. The output determination circuit of the bandgap reference voltage according to claim 3, characterized in that: The judgment signal comparison circuit comprises: The first comparison circuit is connected to the startup circuit and the core circuit, and includes at least one switch tube, which is used to receive the component signals of the potential control voltage and the bandgap reference voltage, and when the power supply voltage is greater than the conduction voltage of each switch tube, controls each switch tube to close and conduct, and outputs a high-level judgment signal.

5. The output determination circuit of the bandgap reference voltage according to claim 4, characterized in that: The first comparison circuit is also used to control at least one of the switching tubes to be turned off and output a low-level judgment signal when the power supply voltage is less than the on-voltage of at least one of the switching tubes based on the component signals of the potential control voltage and the bandgap reference voltage received.

6. The output determination circuit of the bandgap reference voltage according to claim 4, characterized in that: The judgment signal comparison circuit also includes: The second comparison circuit is connected to the first comparison circuit and the startup circuit, and includes a current source for controlling the current source to maintain the low level state of the judgment signal when the first comparison circuit outputs the low level judgment signal and the startup circuit works normally.

7. The output determination circuit of the bandgap reference voltage according to claim 6, characterized in that: The first comparison circuit includes: a PMOS tube M9, a PMOS tube M11, a PMOS tube M10, a Schmitt trigger I2 and an inverter I3. The gate of the PMOS tube M9 is connected to the core circuit, the source of the PMOS tube M9 is connected to the gate of the PMOS tube M11, and the drain of the PMOS tube M9 is connected to the startup circuit; the source of the PMOS tube M11 is connected to the power supply voltage, and the drain of the PMOS tube M11 is connected to the input end of the Schmitt trigger I2; the output end of the Schmitt trigger I2 is connected to the input end of the inverter I3, and the output end of the inverter I3 outputs the judgment signal; the gate and source of the PMOS tube M10 are connected to the power supply voltage, and the drain of the PMOS tube M10 is connected to the gate of the PMOS tube M11; When the gate of the PMOS tube M9 receives the component signal of the bandgap reference voltage and is closed and turned on, the PMOS tube M11 is closed and turned on, and the inverter I3 outputs the high-level judgment signal; When the gate of the PMOS tube M9 receives the component signal of the bandgap reference voltage and is turned off, the PMOS tube M11 is turned off, and the inverter I3 outputs the low-level determination signal.

8. The output determination circuit of the bandgap reference voltage according to claim 7, characterized in that: The second comparison circuit includes a current source I4, an NMOS tube M13, a Schmitt trigger I1, a PMOS tube M8, an NMOS tube M12, and a transistor Q5. The source of the PMOS tube M8 is connected to the power supply voltage, the gate of the PMOS tube M8 is connected to the startup circuit, the drain of the PMOS tube M8 is connected to the drain of the NMOS tube M12, the gate of the NMOS tube M12 is connected to the startup circuit, the source of the NMOS tube M12 is connected to the emitter of the transistor Q5, and the base and collector of the transistor Q5 are connected to a common ground; the input end of the Schmitt trigger I1 is connected to the drain of the NMOS tube M12, the output end of the Schmitt trigger I1 is connected to the gate of the NMOS tube M13, the drain of the NMOS tube M13 is connected to the input end of the Schmitt trigger I2 in the first comparison circuit, and the source of the NMOS tube M13 is connected to a common ground; the current source I4 is connected between the source and the drain of the NMOS tube M13; When the NMOS tube M12 is turned off, the NMOS tube M13 is also turned off; the current source I4 pulls down the drain of the NMOS tube M13 to maintain the low level state of the determination signal.

9. A bandgap reference voltage conversion device, characterized in that: The device comprises the output determination circuit of the bandgap reference voltage according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises an output judgment circuit of a bandgap reference voltage according to any one of claims 1 to 8 and a load module, wherein the output judgment circuit of the bandgap reference voltage is connected to the load module.

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