Chip working mode determination circuit

Abstract

The chip working mode determination circuit provided by the embodiment of the invention comprises a period division module for performing period division on a received initial clock signal to obtain N associated clock signals; the RC discharge module is used for discharging the capacitor when the Nth associated clock signal is changed from the low level to the high level; the function voltage generation module determines a first current according to the first voltage of the capacitor, and determines a second voltage of the function node according to the first current and the external resistor; the comparison module outputs a first level signal to the clock state latch module according to the relation between the second voltage and the reference voltage; and the clock state latch module is used for controlling the clock state latch module to latch the initial clock signal and the N associated clock signals when the first level signal output by the comparison module is a high level, and determining the working mode of the chip according to the latched initial clock signal and N associated clock signals.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the technical field of integrated circuits and related technical fields, and in particular, to a circuit for determining a chip operating mode. Background Art

[0002] In the prior art, the updating and adjustment of the chip working mode is generally carried out by injecting control data into the internal storage unit of the chip through external means to adjust the chip working frequency or working mode, or by using complex processes to deeply intervene in the distributed logic architecture and component working mode inside the chip.

[0003] However, in the prior art, updating and adjusting the chip working mode exposes several problems, such as the operation steps are cumbersome and complicated, and the consistency and timeliness during repeated execution are difficult to be effectively guaranteed. Summary of the invention

[0004] The embodiments described in this article provide a chip working mode determination circuit to solve the problems existing in the prior art.

[0005] According to the content of the present disclosure, a chip working mode determination circuit is provided, including: a cycle division module, an RC discharge module, a functional voltage generation module, a comparison module and a clock state latch module, the functional voltage generation module includes an external resistor, and the RC discharge module includes a first resistor and a capacitor;

[0006] The cycle division module is configured to perform cycle division on the received initial clock signal to obtain N associated clock signals, and send the Nth associated clock signal to the RC discharge module and send the N associated clock signals to the clock state latch module, the clock cycle of the first associated clock signal is twice the clock cycle of the initial clock signal, the clock cycle of the i-th associated clock signal is twice the clock cycle of the i-1th associated clock signal, and i is less than or equal to N;

[0007] The RC discharge module is configured to discharge the capacitor when the Nth associated clock signal changes from a low level to a high level;

[0008] The functional voltage generating module is configured to determine a first current according to the first voltage of the capacitor, and determine a second voltage of the functional node according to the first current and the external resistor;

[0009] The comparison module is configured to output a first level signal to the clock state latch module according to a relationship between the second voltage and a reference voltage;

[0010] The clock state latch module is configured to control the clock state latch module to latch the initial clock signal and N associated clock signals when the first level signal output by the comparison module changes from a low level to a high level.

[0011] In some embodiments of the present disclosure, the period segmentation module includes at least a first period segmentation unit, a second period segmentation unit, and a third period segmentation unit;

[0012] The first cycle division unit is configured to receive an initial clock signal, perform cycle division on the received initial clock signal to obtain a first associated clock signal, and send the first associated clock signal to the clock state latch module;

[0013] The second cycle division unit is configured to receive the first associated clock signal output by the first cycle division unit, perform cycle division on the first associated clock signal to obtain a second associated clock signal, and send the second associated clock signal to the clock state latch module;

[0014] The third cycle division unit is configured to receive the second associated clock signal output by the second cycle division unit, perform cycle division on the second associated clock signal to obtain a third associated clock signal, and send the third associated clock signal to the clock state latch module.

[0015] In some embodiments of the present disclosure, the first period division unit includes a first trigger, the second period division unit includes a second trigger, and the third period division unit includes a third trigger, the clock end of the first trigger receives the initial clock signal, the data input end of the first trigger is electrically connected to the second output end of the first trigger, the first output end of the first trigger is electrically connected to the clock end and the first node of the second trigger, respectively, the data input end of the second trigger is electrically connected to the second output end of the second trigger, the first output end of the second trigger is electrically connected to the clock end and the second node of the third trigger, respectively, the data input end of the third trigger is electrically connected to the second output end of the third trigger, and the first output end of the third trigger is electrically connected to the third node.

[0016] In some embodiments of the present disclosure, the RC discharge module also includes a first pulse generator and a switch, the input end of the first pulse generator receives the third associated clock signal output by the cycle division module, the output end of the first pulse generator outputs a first pulse signal to the control end of the switch, the first end of the switch and the first end of the capacitor are electrically connected to a power supply node, the second end of the switch and the second end of the capacitor are electrically connected to the first end of the first resistor, and the second end of the first resistor is electrically connected to a ground node.

[0017] In some embodiments of the present disclosure, the functional voltage generation module includes a first current determination unit, a current mirror unit and a functional voltage determination unit;

[0018] Wherein, the first current determining unit is configured to collect a first voltage of the capacitor and determine a first current according to the first voltage;

[0019] The current mirror unit is configured to mirror the first current to obtain a second current;

[0020] The functional voltage determination unit is configured to determine a second voltage according to the second current.

[0021] In some embodiments of the present disclosure, the first current determination unit includes a buffer and a second resistor, the current mirror unit includes a first transistor and a second transistor, the first input terminal of the buffer receives the first voltage, the output terminal of the buffer is electrically connected to the second input terminal of the buffer, the first end of the second resistor, the first end of the first transistor, the control end of the first transistor and the control end of the second transistor, respectively, the first power supply terminal of the buffer is electrically connected to the power supply node, the second power supply terminal of the buffer is electrically connected to the ground node, the second end of the first transistor and the second end of the second transistor are electrically connected to the power supply node, the first end of the second transistor is electrically connected to the first end of the external resistor and the functional node, respectively, and the second end of the second resistor and the second end of the external resistor are electrically connected to the ground node.

[0022] In some embodiments of the present disclosure, the comparison module includes a comparator, an inverting input terminal of the comparator receives a reference voltage, a positive input terminal of the comparator receives a second voltage, and an output terminal of the comparator outputs a first level signal.

[0023] In some embodiments of the present disclosure, the clock state latch module includes at least a second pulse generator, a fourth latch, a fifth latch, a sixth latch and a seventh latch, the input end of the second pulse generator receives the first level signal output by the comparison module, the output end of the second pulse generator outputs a second pulse signal to the clock ends of the fourth latch, the fifth latch, the sixth latch and the seventh latch respectively, the data input end of the fourth latch receives the initial clock signal, the data input end of the fifth latch receives the first associated clock signal, the data output end of the sixth latch receives the second associated clock signal, the data input end of the seventh latch receives the third associated clock signal, and the output ends of the fourth latch, the fifth latch, the sixth latch and the seventh latch respectively output first level signals.

[0024] In some embodiments of the present disclosure, a reference voltage generating module is also included;

[0025] The reference voltage generating module is configured to generate a reference voltage;

[0026] The reference voltage generating module includes a fourth resistor and a fifth resistor, the first end of the fourth resistor is electrically connected to the power supply node, the second end of the fourth resistor and the first end of the fifth resistor are electrically connected to the reference voltage node, and the second end of the fifth resistor is electrically connected to the ground node.

[0027] In some embodiments of the present disclosure, N is 3.

[0028] The chip working mode determination circuit provided by the embodiment of the present disclosure includes a period division module, an RC discharge module, a functional voltage generation module, a comparison module and a clock state latch module, wherein the period division module divides the initial clock signal into periods to obtain N associated clock signals, and the Nth associated clock signal output by the period division module controls the charging and discharging of the RC discharge module, the functional voltage generation module determines the second voltage of the functional node by obtaining the first voltage of the capacitor in the RC discharge module, and the comparison module outputs a first level signal to control the clock state latch module to latch the initial clock signal and the N associated clock signals by comparing the relationship between the second voltage and the reference voltage. Since the second voltage of the functional node is determined according to the first current and the external resistor connected to the functional node, when the resistance value of the connected external resistor is different, the determined second voltage is different, and at this time, by comparing the relationship between the second voltage and the reference voltage, the time of outputting the first level signal to the clock state latch module is different, thereby making the initial clock signal and the N associated clock signals latched by the clock state latch module according to the first level signal different, thereby realizing the determination of different working modes of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be noted that the drawings described below only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure, wherein:

[0030] Figure 1 is a schematic diagram of the structure of a chip working mode determination circuit provided by an embodiment of the present disclosure;

[0031] Figure 2 is a structural schematic diagram of another chip working mode determination circuit provided by an embodiment of the present disclosure;

[0032] Figure 3 It is a timing diagram of a chip working mode determination circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0034] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person skilled in the art to which the subject matter of the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the specification and the relevant art, and will not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are joined together directly or through one or more intermediate components.

[0035] In all embodiments of the present disclosure, terms such as “first” and “second” are used only to distinguish one component (or a part of a component) from another component (or another part of a component).

[0036] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0037] Based on the problems existing in the prior art, the present disclosure provides a chip working mode determination circuit. Figure 1 is a schematic diagram of a chip working mode determination circuit provided by an embodiment of the present disclosure, Figure 2 is a schematic diagram of another chip working mode determination circuit provided by an embodiment of the present disclosure, combined with Figure 1 and Figure 2 The chip working mode determination circuit includes: a cycle division module 20, an RC discharge module 20, a functional voltage generation module 30, a comparison module 40 and a clock state latch module 50, wherein the functional voltage generation module 30 includes an external resistor R3, and the RC discharge module 20 includes a first resistor R1 and a capacitor C; wherein the cycle division module 10 is configured to divide the received initial clock signal clk0 into N associated clock signals by cycle division, and convert the Nth associated clock signal ( Figure 2 In an exemplary embodiment, the third associated clock signal clk3 is sent to the RC discharge module 20 and N associated clock signals are sent to the clock state latch module 50, the clock period of the first associated clock signal is twice the clock period of the initial clock signal clk0, and the clock period of the i-th associated clock signal is twice the clock period of the i-1-th associated clock signal; the RC discharge module 20 is configured to discharge the capacitor C when the N-th associated clock signal changes from a low level to a high level; the functional voltage generating module 30 is configured to determine the first current I1 according to the first voltage V1 of the capacitor C, and to generate a first current I1 according to the first current I1 and the external resistor R3 determines the second voltage V2 of the functional node; the comparison module 40 is configured to output a first level signal to the clock state latch module 50 according to the relationship between the second voltage V2 and the reference voltage Vref; the clock state latch module 50 is configured to control the clock state latch module 50 to latch the initial clock signal clk0 and N associated clock signals when the first level signal output by the comparison module 40 changes from a low level to a high level. The latched initial clock signal clk0 and N associated clock signals can be used to determine the working mode of the chip (for example, it can dynamically adjust its internal frequency, working mode and other functional versions during the chip startup phase).

[0038] Specifically, in an exemplary embodiment, the cycle division module 10 receives the initial clock signal clk0, obtains the first associated clock signal clk1, the second associated clock signal clk2 and the third associated clock signal clk3 by performing cycle division on the initial clock signal clk0, and sends the first associated clock signal clk1, the second associated clock signal clk2 and the third associated clock signal clk3 to the clock state latch module 50, and sends the third associated clock signal clk3 to the RC discharge module 20.

[0039] The RC discharge module 20 receives the third associated clock signal clk3 sent by the cycle division module 10, and controls the capacitor C to discharge when the third clock cycle signal clk3 is a rising edge.

[0040] The functional voltage generating module 30 obtains the first current I1 by collecting the first voltage V1 of the capacitor C, obtains the second current I2 by mirroring the first current I1 to the functional node, multiplies the second current I2 by the resistance value of the functional resistor R3 of the functional node, and obtains the second voltage V2 which is input to the functional node.

[0041] The comparison module 40 outputs a first level signal to the clock state latch module by comparing the relationship between the second voltage V2 and the reference voltage Vref. When the second voltage V2 is less than the reference voltage Vref, the comparison module 40 outputs a high level to the clock state latch module 50. When the second voltage V2 is greater than the reference voltage Vref, the comparison module 40 outputs a low level to the clock state latch module.

[0042] The clock state latch module 50 determines whether to latch the initial clock signal clk0, the first associated clock signal clk1, the second associated clock signal clk2 and the third associated clock signal clk3 according to the first level signal output by the comparison module 40. When the first level signal output by the comparison module 40 is at a high level, the clock state latch module 50 latches the initial clock signal clk0, the first associated clock signal clk1, the second associated clock signal clk2 and the third associated clock signal clk3. When the first level signal output by the comparison module 40 is at a low level, the clock state latch module does not latch the initial clock signal clk0, the first associated clock signal clk1, the second associated clock signal clk2 and the third associated clock signal clk3. The working mode of the chip is determined by analyzing the level signals of the latched initial clock signal clk0, the first associated clock signal clk1, the second associated clock signal clk2 and the third associated clock signal clk3, thereby adjusting the working mode of the chip.

[0043] Since the second voltage of the functional node is determined according to the first current and the external resistor connected to the functional node, when the resistance value of the connected external resistor is different, the determined second voltage is different. At this time, by comparing the relationship between the second voltage and the reference voltage, the time for outputting the first level signal to the clock state latch module is different, thereby making the initial clock signal and N associated clock signals latched by the clock state latch module according to the first level signal different, thereby realizing the determination of different working modules of the chip.

[0044] The chip working mode determination circuit provided by the embodiment of the present disclosure includes a period division module, an RC discharge module, a functional voltage generation module, a comparison module and a clock state latch module, wherein the period division module divides the initial clock signal into periods to obtain N associated clock signals, and the Nth associated clock signal output by the period division module controls the charging and discharging of the RC discharge module, the functional voltage generation module determines the second voltage of the functional node by obtaining the first voltage of the capacitor in the RC discharge module, and the comparison module outputs a first level signal to control the clock state latch module to latch the initial clock signal and the N associated clock signals by comparing the relationship between the second voltage and the reference voltage. Since the second voltage of the functional node is determined according to the first current and the external resistor connected to the functional node, when the resistance value of the connected external resistor is different, the determined second voltage is different, and at this time, by comparing the relationship between the second voltage and the reference voltage, the time of outputting the first level signal to the clock state latch module is different, thereby making the initial clock signal and the N associated clock signals latched by the clock state latch module according to the first level signal different, thereby realizing the determination of different working modes of the chip.

[0045] In a specific embodiment, see Figure 2 The cycle division module 10 at least includes a first cycle division unit, a second cycle division unit and a third cycle division unit; wherein the first cycle division unit is configured to receive an initial clock signal, and perform cycle division on the received initial clock signal to obtain a first associated clock signal, and send the first associated clock signal to the clock state latch module; the second cycle division unit is configured to receive a first associated clock signal output by the first cycle division unit, and perform cycle division on the first associated clock signal to obtain a second associated clock signal, and send the second associated clock signal to the clock state latch module; the third cycle division unit is configured to receive a second associated clock signal output by the second cycle division unit, and perform cycle division on the second associated clock signal to obtain a third associated clock signal, and send the third associated clock signal to the clock state latch module.

[0046] Among them, the first period division unit includes a first trigger D1, the second period division unit includes a second trigger D2, and the third period division unit includes a third trigger D3. The clock end of the first trigger D1 receives an initial clock signal, the data input end of the first trigger D1 is electrically connected to the second output end of the first trigger D1, the first output end of the first trigger D1 is electrically connected to the clock end and the first node A1 of the second trigger D2, respectively, the data input end of the second trigger D2 is electrically connected to the second output end of the second trigger, the first output end of the second trigger D2 is electrically connected to the clock end and the second node A2 of the third trigger D3, respectively, the data input end of the third trigger D3 is electrically connected to the second output end of the third trigger D3, and the first output end of the third trigger D3 is electrically connected to the third node A3.

[0047] Combination Figure 2, by setting the cycle division module to at least include a first cycle division unit, a second cycle division unit and a third cycle division unit, the first cycle division unit includes a first trigger D1, the second cycle division unit includes a second trigger D2, and the third cycle division unit includes a third trigger D3, the clock end of the first trigger D1 receives the initial clock signal clk0, and at the rising edge of the initial clock signal clk0, the first output end of the first trigger D1 outputs a high level, and since the clock end of the second trigger D2 is electrically connected to the first output end of the first trigger D1, the clock end of the second trigger D2 receives the first associated clock signal clk1 output by the first output end of the first trigger D1, and the clock period of the first associated clock signal clk1 received by the clock end of the second trigger D2 is twice the clock period of the initial clock signal clk0, that is, the clock period of the first associated clock signal clk1 output by the first output end of the first trigger D1 is twice the clock period of the initial clock signal clk0 received by the clock end of the first trigger D1; Similarly, at the rising edge of the first associated clock signal clk1, the first output terminal of the second flip-flop D2 outputs a high level. Since the clock terminal of the third flip-flop D3 is electrically connected to the first output terminal of the second flip-flop D2, the clock terminal of the third flip-flop D3 receives the second associated clock signal clk2 outputted from the first output terminal of the second flip-flop D2, and the clock cycle of the second associated clock signal clk2 received by the clock terminal of the third flip-flop D3 is twice the clock cycle of the first associated clock signal clk1, that is, the clock cycle of the second associated clock signal clk2 outputted from the first output terminal of the second flip-flop D2 is twice the clock cycle of the first associated clock signal clk1 received by the clock terminal of the second flip-flop D2; at the rising edge of the second associated clock signal clk2, the first output terminal of the third flip-flop D3 outputs a high level, and the clock cycle of the third associated clock signal clk3 outputted from the first output terminal of the third flip-flop D3 is twice the clock cycle of the second associated clock signal clk2 received by the clock terminal of the third flip-flop D3.

[0048] In a specific implementation manner, see Figure 2 The RC discharge module 20 also includes a first pulse generator P1 and a switch K. The input end of the first pulse generator P1 receives the third associated clock signal clk3 output by the cycle division module 10. The output end of the first pulse generator P1 outputs a first pulse signal to the control end of the switch K. The first end of the switch K and the first end of the capacitor C are electrically connected to the power supply node. The second end of the switch K and the second end of the capacitor C are electrically connected to the first end of the first resistor R1. The second end of the first resistor R1 is electrically connected to the ground node.

[0049] Specific, combined Figure 2The RC discharge module includes a first pulse generator P1, a first resistor R1, a capacitor C and a switch K. When the first pulse generator P1 receives the third associated clock signal clk3 output by the cycle division module 10, the first pulse generator P1 outputs a first pulse signal to the control end of the switch K. When the third associated clock signal clk3 output by the cycle division module 10 changes from a low level to a high level, the first pulse generator outputs a high level to the switch K, and keeps the output high level for a preset period of time before changing from a high level to a low level. The switch K closes after receiving the high level, and the capacitor discharges quickly. After receiving the low level, the switch K opens, that is, the switch K is turned on at the rising edge of the first pulse signal, and the capacitor C discharges. The duration of the discharge of the capacitor C is the same as the duration of the high level output by the first pulse generator.

[0050] Among them, the discharge voltage of the capacitor at time t satisfies:

[0051]

[0052] In a specific embodiment, the functional voltage generating module 30 includes a first current determination unit, a current mirror unit and a functional voltage determination unit; wherein the first current determination unit is configured to collect the first voltage of the capacitor and determine the first current based on the first voltage; the current mirror unit is configured to mirror the first current to obtain the second current; the functional voltage determination unit is configured to determine the second voltage based on the second current and the external resistor.

[0053] Among them, the first current determination unit includes a buffer BUF and a second resistor R2, the current mirror unit includes a first transistor M1 and a second transistor M2, the first input end of the buffer BUF receives the first voltage V1, the output end of the buffer BUF is electrically connected to the second input end of the buffer BUF, the first end of the second resistor R2, the first end of the first transistor M1, the control end of the first transistor M1 and the control end of the second transistor M2, respectively, the first power supply end of the buffer BUF is electrically connected to the power supply node, the second power supply end of the buffer BUF is electrically connected to the ground node, the second end of the first transistor M1 and the second end of the second transistor M2 are electrically connected to the power supply node, the first end of the second transistor M2 is electrically connected to the first end of the external resistor R3 and the function node, respectively, and the second end of the second resistor R2 and the second end of the external resistor R3 are electrically connected to the ground node.

[0054] Combination Figure 2The first current determination unit includes a buffer BUF and a second resistor R2. The first current determination unit collects a first voltage V1 of the capacitor during the discharge process of the capacitor. After the first current determination unit collects the first voltage V1 of the capacitor during the discharge process, the first current determination unit determines a first current I1 according to the first voltage V1 and the second resistor, and then mirrors the first current I1 to a functional node through a first transistor M1 and a second transistor M2. According to a mirror ratio of the current mirror unit composed of the first transistor M1 and the second transistor M2, a second current I2 flowing into the functional node is determined, and then the second current I2 is multiplied by an external resistor R3 connected to the functional node to obtain a second voltage V2 of the functional node.

[0055] Wherein, the first voltage satisfies:

[0056]

[0057] The first current satisfies:

[0058]

[0059] The second current satisfies:

[0060]

[0061] The second voltage of the functional node satisfies:

[0062]

[0063] In a specific implementation manner, see Figure 2 The comparison module 40 includes a comparator COMP, an inverting input terminal of the comparator COMP receives a reference voltage Vref, a positive input terminal of the comparator COMP receives a second voltage V2, and an output terminal of the comparator COMP outputs a first level signal.

[0064] Among them, the reference voltage is determined based on the reference voltage generating module. Therefore, the chip working mode determination circuit provided in the embodiment of the present disclosure also includes a reference voltage generating module. The reference voltage generating module includes a fourth resistor R4 and a fifth resistor R5. The first end of the fourth resistor R4 is electrically connected to the power supply node, the second end of the fourth resistor R4 and the first end of the fifth resistor R5 are electrically connected to the reference voltage node, and the second end of the fifth resistor R5 is electrically connected to the ground node.

[0065] By setting a reference voltage generating module, the reference voltage generating module generates a reference voltage, wherein the generated reference voltage satisfies:

[0066]

[0067] After determining the reference voltage Vref and the second voltage V2, by comparing the relationship between the reference voltage Vref and the second voltage V2, a first level signal is output to the clock state latch module 50. Specifically, when the reference voltage Vref is less than the second voltage V2, the comparator COMP outputs a low level. When the reference voltage Vref is greater than the second voltage V2, the comparator COMP outputs a high level. Since the clock state latch module 50 latches the initial clock signal clk0, the first associated clock signal clk1, the second associated clock signal clk2 and the third associated clock signal clk3 at the moment when the comparator COMP outputs a high level, the reference voltage Vref and the second voltage V2 are equal, and the following is obtained:

[0068]

[0069] By solving the above formula, we can get:

[0070]

[0071] That is, by setting the external resistance electrically connected to the functional node to be an exponential law of time t, when the period division module changes linearly, the external resistance of the functional node can change exponentially, and the resistance electrically connected to the functional node can have a wide dynamic range, which is more conducive to the selection and application of the resistor.

[0072] Based on the above embodiments, continue to refer to Figure 2 The clock state latch module 50 at least includes a second pulse generator P2, a fourth latch D4, a fifth latch D5, a sixth latch D6 and a seventh latch D7. The input end of the second pulse generator P2 receives the first level signal output by the comparison module 40. The output end of the second pulse generator P2 outputs the second pulse signal to the clock ends of the fourth latch D4, the fifth latch D5, the sixth latch D6 and the seventh latch D7 respectively. The data input end of the fourth latch D4 receives the initial clock signal clk0, the data input end of the fifth latch D5 receives the first associated clock signal clk1, the data output end of the sixth latch D6 receives the second associated clock signal clk2, the data input end of the seventh latch D7 receives the third associated clock signal clk3, and the output ends of the fourth latch D4, the fifth latch D5, the sixth latch D6 and the seventh latch D7 respectively output second level signals.

[0073] When the comparison module changes from a low level to a high level, the second pulse generator of the clock state latch module will generate a second pulse signal to the clock ends of the fourth latch, the fifth latch, the sixth latch and the seventh latch. Specifically, when the first level signal output by the comparison module changes from a low level to a high level, the second pulse signal generated by the second pulse generator of the clock state latch module will change from a low level to a high level. Since the data input end of the fourth latch is electrically connected to the first node, the data input end of the fourth latch receives the initial clock signal, the data input end of the fifth latch is electrically connected to the second node, and the data input end of the fifth latch receives the first associated clock signal, the data input end of the sixth latch is electrically connected to the third node, and the data input end of the sixth latch receives the second associated clock signal, the data input end of the seventh latch is electrically connected to the fourth node, and the data input end of the seventh latch receives the third associated clock signal. When the clock ends of the fourth latch, the fifth latch, the sixth latch and the seventh latch receive the rising edge of the pulse, the fourth latch will be the first node. The initial clock signal is latched, that is, the fourth latch outputs the second level signal corresponding to the first node when the second pulse generator outputs a rising edge, the fifth latch latches the first associated clock signal of the second node, that is, the fifth latch outputs the second level signal corresponding to the second node when the second pulse generator outputs a rising edge, the sixth latch latches the second associated clock signal of the third node, that is, the sixth latch outputs the second level signal corresponding to the third node when the second pulse generator outputs a rising edge, the seventh latch latches the third associated clock signal of the fourth node, that is, the seventh latch outputs the second level signal corresponding to the fourth node when the second pulse generator outputs a rising edge, and the Figure 3 The second pulse signal generated by the second pulse generator is Figure 3 There is a rising edge at time t=t1, therefore, at time t1, the second level signal output by the fourth latch is high, the second level signal output by the fifth latch is low, the second level signal output by the sixth latch is low, and the second level signal output by the seventh latch is high.

[0074] At this time, the second level signal received by the working mode determination module is high level, low level, low level and high level. By analyzing the second level signal, the working mode of the chip corresponding to the second level signal is determined, and then the working mode of the chip is adjusted.

[0075] By setting the working mode determination module to include a second pulse generator, when the first level signal output by the comparison module changes from a low level to a high level, the second pulse generator outputs a high level to the clock ends of the fourth latch, the fifth latch, the sixth latch and the seventh latch, and keeps the output high level for a preset period of time and then changes from a high level to a low level, thereby avoiding directly electrically connecting the output end of the comparison module with the clock ends of the fourth latch, the fifth latch, the sixth latch and the seventh latch. When there is jitter in the first level signal output by the comparison module, there is an error in the chip working mode determined based on the clock signal latched at the clock ends of the fourth latch, the fifth latch, the sixth latch and the seventh latch.

[0076] It should be noted that, in the embodiment of the present disclosure, the exemplary setting of the cycle division module includes the first latch, the second latch and the third latch, and the corresponding setting of the clock state latch module includes the fourth latch, the fifth latch, the sixth latch and the seventh latch. In other embodiments, when the cycle division module increases a latch correspondingly, the clock state latch module needs to increase a latch correspondingly. When there are many working modes of the chip, the number of latches set in the cycle division module and the clock state latch module can be increased or decreased, thereby ensuring that the working mode of the chip can be determined based on the second level signal latched by the clock state latch module.

[0077] In the embodiment of the present disclosure, the cycle division module can divide the initial clock signal to generate multiple related clock signals according to the ratio change. The lowest frequency related clock signal generated by the cycle division module will be connected to the first pulse generator to control the RC discharge module to restart the discharge process. The discharge voltage V generated by the RC discharge module during the discharge process RC After passing through a buffer, it will generate a discharge current I1 with the second resistor R2. This current can flow into the external resistor in the form of I2 current through the current mirror unit, thereby generating a second voltage of the functional node and comparing it with the reference voltage Vref. When the first level output by the comparison module changes from a low level to a high level, the clock state latch module will latch and output the current states of the initial clock signal and the N related clock signals output by the cycle division module. The initial clock signal latched by the clock state latch module and the current states of the N related clock signals output by the cycle division module are decoded and output, thereby controlling the corresponding functional state of the chip. This feedback mechanism ensures that the chip operating mode determination circuit can accurately adjust the chip's operating mode and performance parameters according to the resistance value of the detected external resistor.

[0078] The technical solution disclosed in the present invention abandons the traditional cumbersome or irreversible adjustment methods and instead adopts a resistance configuration method that is easy to operate, highly repeatable and reliable, thereby simplifying the parameter adjustment steps in the product production and maintenance process, so that it can better adapt to diverse application environments and evolving market demands.

[0079] The embodiment of the present disclosure further provides an electronic chip, which includes a chip operation mode determination circuit according to the embodiment of the present disclosure.

[0080] The embodiments of the present disclosure also provide an electronic device. The electronic device includes an electronic chip according to the embodiments of the present disclosure. The electronic device is, for example, a smart terminal device, such as a tablet computer, a smart phone, etc.

[0081] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0082] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of each step / process mentioned above does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present application. In addition, the serial numbers of the embodiments of the present application mentioned above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0083] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0084] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A chip working mode determination circuit, characterized in that: include: A cycle division module, an RC discharge module, a functional voltage generation module, a comparison module and a clock state latch module, wherein the functional voltage generation module includes an external resistor, and the RC discharge module includes a first resistor and a capacitor; The cycle division module is configured to perform cycle division on the received initial clock signal to obtain N associated clock signals, and send the Nth associated clock signal to the RC discharge module and send the N associated clock signals to the clock state latch module, the clock cycle of the first associated clock signal is twice the clock cycle of the initial clock signal, the clock cycle of the i-th associated clock signal is twice the clock cycle of the i-1th associated clock signal, and i is less than or equal to N; The RC discharge module is configured to discharge the capacitor when the Nth associated clock signal changes from a low level to a high level; The functional voltage generating module is configured to determine a first current according to the first voltage of the capacitor, and determine a second voltage of the functional node according to the first current and the external resistor; The comparison module is configured to output a first level signal to the clock state latch module according to a relationship between the second voltage and a reference voltage; The clock state latch module is configured to latch the initial clock signal and N associated clock signals when the first level signal output by the comparison module changes from a low level to a high level.

2. The circuit according to claim 1, characterized in that The cycle segmentation module at least includes a first cycle segmentation unit, a second cycle segmentation unit and a third cycle segmentation unit; The first cycle division unit is configured to receive an initial clock signal, perform cycle division on the received initial clock signal to obtain a first associated clock signal, and send the first associated clock signal to the clock state latch module; The second cycle division unit is configured to receive the first associated clock signal output by the first cycle division unit, perform cycle division on the first associated clock signal to obtain a second associated clock signal, and send the second associated clock signal to the clock state latch module; The third cycle division unit is configured to receive the second associated clock signal output by the second cycle division unit, perform cycle division on the second associated clock signal to obtain a third associated clock signal, and send the third associated clock signal to the clock state latch module.

3. The circuit according to claim 2, characterized in that The first cycle division unit includes a first trigger, the second cycle division unit includes a second trigger, and the third cycle division unit includes a third trigger. The clock end of the first trigger receives the initial clock signal, the data input end of the first trigger is electrically connected to the second output end of the first trigger, the first output end of the first trigger is electrically connected to the clock end and the first node of the second trigger, respectively, the data input end of the second trigger is electrically connected to the second output end of the second trigger, the first output end of the second trigger is electrically connected to the clock end and the second node of the third trigger, respectively, the data input end of the third trigger is electrically connected to the second output end of the third trigger, and the first output end of the third trigger is electrically connected to the third node.

4. The circuit according to claim 1, characterized in that The RC discharge module also includes a first pulse generator and a switch, wherein the input end of the first pulse generator receives the third associated clock signal output by the cycle division module, the output end of the first pulse generator outputs a first pulse signal to the control end of the switch, the first end of the switch and the first end of the capacitor are electrically connected to a power supply node, the second end of the switch and the second end of the capacitor are electrically connected to the first end of the first resistor, and the second end of the first resistor is electrically connected to a ground node.

5. The circuit according to claim 1, characterized in that The functional voltage generating module comprises a first current determining unit, a current mirror unit and a functional voltage determining unit; Wherein, the first current determining unit is configured to collect a first voltage of the capacitor and determine a first current according to the first voltage; The current mirror unit is configured to mirror the first current to obtain a second current; The functional voltage determination unit is configured to determine a second voltage according to the second current and the external resistor.

6. The circuit according to claim 5, characterized in that The first current determination unit includes a buffer and a second resistor, the current mirror unit includes a first transistor and a second transistor, the first input terminal of the buffer receives the first voltage, the output terminal of the buffer is electrically connected to the second input terminal of the buffer, the first terminal of the second resistor, the first terminal of the first transistor, the control terminal of the first transistor and the control terminal of the second transistor respectively, the first power supply terminal of the buffer is electrically connected to the power supply node, the second power supply terminal of the buffer is electrically connected to the ground node, the second terminal of the first transistor and the second terminal of the second transistor are electrically connected to the power supply node, the first terminal of the second transistor is electrically connected to the first terminal of the external resistor and the function node respectively, and the second terminal of the second resistor and the second terminal of the external resistor are electrically connected to the ground node.

7. The circuit according to claim 1, characterized in that The comparison module comprises a comparator, an inverting input terminal of the comparator receives a reference voltage, a positive input terminal of the comparator receives a second voltage, and an output terminal of the comparator outputs a first level signal.

8. The circuit according to claim 1, characterized in that The clock state latch module at least includes a second pulse generator, a fourth latch, a fifth latch, a sixth latch and a seventh latch, the input end of the second pulse generator receives the first level signal output by the comparison module, the output end of the second pulse generator outputs a second pulse signal to the clock ends of the fourth latch, the fifth latch, the sixth latch and the seventh latch respectively, the data input end of the fourth latch receives the initial clock signal, the data input end of the fifth latch receives the first associated clock signal, the data output end of the sixth latch receives the second associated clock signal, and the data input end of the seventh latch receives the third associated clock signal.

9. The circuit according to claim 1, characterized in that Also includes a reference voltage generation module; The reference voltage generating module is configured to generate a reference voltage; The reference voltage generating module includes a fourth resistor and a fifth resistor, the first end of the fourth resistor is electrically connected to the power supply node, the second end of the fourth resistor and the first end of the fifth resistor are electrically connected to the reference voltage node, and the second end of the fifth resistor is electrically connected to the ground node.

10. The circuit according to claim 1, characterized in that N is 3.

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