Entity unit management method and storage device

Abstract

The invention provides an entity unit management method and a storage device. The method comprises the following steps: determining a programming mode, a verification time point and a classification rule for a first entity unit according to the type of the first entity unit; programming a first entity unit based on the programming mode; verifying the reliability of the first entity unit at the verification time point; and classifying the first entity unit according to the classification rule and the reliability verification result. Therefore, the reliability of the memory module can be improved, and the number of available entity units can be maintained as much as possible.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a physical unit management method and a storage device. Background Art

[0002] During the life cycle of a memory module (e.g., a flash memory module), as usage increases, some physical blocks in the memory module may age faster. Once a physical block ages, the reliability of the physical block will drop significantly (e.g., data stored in the physical block may have more errors).

[0003] Generally speaking, during the production process of memory modules, manufacturers will first perform read and write tests to classify physical blocks with obviously poor reliability as bad blocks in order to improve the overall reliability of the memory module. After the storage device leaves the factory, as the degree of use increases and the use environment changes, some physical blocks are still at risk of aging. Therefore, if specific means are not used to detect and disable physical blocks with aging risks, the overall reliability of the memory module will be significantly reduced (for example, the risk of data loss will be increased). On the other hand, if physical blocks with aging risks are disabled too frequently, some physical blocks that are still available may be misjudged as aged physical blocks, which will lead to a significant decrease in the data storage capacity of the memory module.

[0004] Therefore, how to strike a balance between improving the reliability of the memory module and maintaining the number of available physical blocks as much as possible is a problem that needs to be solved urgently. Summary of the invention

[0005] The present invention provides a physical unit management method and a storage device, which can improve the problems derived from the conventional improper management of physical blocks with aging risks, thereby achieving a balance between improving the reliability of the memory module and maintaining the number of available physical units as much as possible.

[0006] An embodiment of the present invention provides a physical unit management method, which is used for a storage device, wherein the storage device includes a memory module, the memory module includes multiple physical units, and the physical unit management method includes: determining a programming mode, a verification time point and a classification rule for a first physical unit among the multiple physical units according to the type of the first physical unit; programming the first physical unit based on the programming mode; verifying the reliability of the first physical unit at the verification time point; and classifying the first physical unit according to the classification rule and the verification result of the reliability.

[0007] An embodiment of the present invention further provides a storage device, which includes a connection interface, a memory module and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory module includes a plurality of entity units, and the memory controller is used to: determine a programming mode, a verification time point and a classification rule for a first entity unit among the plurality of entity units according to the type of the first entity unit; program the first entity unit based on the programming mode; verify the reliability of the first entity unit at the verification time point; and classify the first entity unit according to the classification rule and the verification result of the reliability.

[0008] Based on the above, the physical unit management method and storage device provided by the embodiment of the present invention can manage the corresponding physical units with different reliability by using appropriate programming modes, verification time points and classification rules. Therefore, the problems derived from the improper management of physical blocks with aging risks in the past can be improved, thereby achieving a balance between improving the reliability of the memory module and maintaining the number of available physical units as much as possible. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0010] Figure 2 is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0011] Figure 3 is a schematic diagram of a management memory module according to an embodiment of the present invention;

[0012] Figure 4 is a schematic diagram of programming modes, verification time points and classification rules corresponding to different types of entity units according to an embodiment of the present invention;

[0013] Figure 5 is a flow chart of a physical unit management method according to an embodiment of the present invention;

[0014] Figure 6 is a flow chart of a physical unit management method according to an embodiment of the present invention;

[0015] Figure 7 is a flow chart of a physical unit management method according to an embodiment of the present invention;

[0016] Figure 8 is a flow chart of a physical unit management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0018] Figure 1 is a schematic diagram of a data storage system according to an embodiment of the present invention. Figure 1 , the data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smart phone, a tablet computer, a notebook computer, a desktop computer, an industrial computer, a game console, a server, or a computer system disposed in a specific carrier (such as a vehicle, an aircraft, or a ship), and the type of the host system 11 is not limited thereto. In addition, the storage device 12 may include a solid state drive, a USB flash drive, a memory card, or other types of non-volatile storage devices.

[0019] The storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect the storage device 12 to the host system 11. For example, the connection interface 121 can support an embedded Multi-Media Card (eMMC), a Universal Flash Storage (UFS), a Peripheral Component Interconnect Express (PCI Express), a Non-Volatile Memory Express (NVM express), a Serial Advanced Technology Attachment (SATA), a Universal Serial Bus (USB), or other types of connection interface standards. Therefore, the storage device 12 can communicate with the host system 11 via the connection interface 121 (e.g., exchange signals, instructions, and / or data).

[0020] The memory module 122 is used to store data. For example, the memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also called threshold voltage). For example, the memory module 122 may include a single level cell (SLC) NAND type flash memory module, a multi level cell (MLC) NAND type flash memory module, a triple level cell (TLC) NAND type flash memory module, a quad level cell (QLC) NAND type flash memory module and / or other memory modules having the same or similar characteristics.

[0021] The memory controller 123 is connected to the connection interface 121 and the memory module 122. The memory controller 123 can be regarded as the control core of the storage device 12 and is used to control the storage device 12. For example, the memory controller 123 can be used to control or manage the entire or partial operation of the storage device 12. For example, the memory controller 123 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSP), programmable controllers, application-specific integrated circuits (ASIC), programmable logic devices (PLD) or other similar devices or combinations of these devices. In one embodiment, the memory controller 123 may include a flash memory controller.

[0022] The memory controller 123 may send a command sequence to the memory module 122 to access the memory module 122. For example, the memory controller 123 may send a write command sequence to the memory module 122 to instruct the memory module 122 to store data in a specific storage unit. For example, the memory controller 123 may send a read command sequence to the memory module 122 to instruct the memory module 122 to read data from a specific storage unit. For example, the memory controller 123 may send an erase command sequence to the memory module 122 to instruct the memory module 122 to erase the data stored in a specific storage unit. In addition, the memory controller 123 may also send other types of command sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations, which are not limited by the present invention. The memory module 122 may receive the command sequence from the memory controller 123 and access the storage unit inside the memory module 122 according to the command sequence.

[0023] Figure 2 FIG. 1 is a schematic diagram of a memory controller according to an embodiment of the present invention. Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22 and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 through the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0024] The memory control circuit 23 is connected to the host interface 21 and the memory interface 22. The memory control circuit 23 may be used to control or manage the whole or part of the operation of the memory controller 123. For example, the memory control circuit 23 may communicate with the host system 11 through the host interface 21 and access the memory module 122 through the memory interface 22. For example, the memory control circuit 23 may include a control circuit such as an embedded controller or a microcontroller. In the following embodiments, the description of the memory control circuit 23 is equivalent to the description of the memory controller 123.

[0025] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuit 23 and used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122.

[0026] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to perform encoding and decoding on the data to ensure the correctness of the data. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check Code (LDPC code), BCH code, Reed-Solomon code (RS code), Exclusive OR (XOR) code, etc. In one embodiment, the memory controller 123 may also include various other types of circuit modules (such as power management circuits, etc.), which are not limited by the present invention.

[0027] Figure 3 FIG. 1 is a schematic diagram of a management memory module according to an embodiment of the present invention. Figures 1 to 3 The memory module 122 includes a plurality of physical units 301 ( 1 ) to 301 (B). Each physical unit includes a plurality of storage cells and is used to store data in a non-volatile manner.

[0028] In one embodiment, a physical unit may include one or more physical erase units. In addition, a physical unit may include multiple sub-physical units. For example, a sub-physical unit may include one or more physical programming units.

[0029] In one embodiment, a physical programming unit may include multiple physical sectors. For example, the data capacity of a physical sector may be 512 bytes (Bytes, B), and a physical programming unit may include 32 physical sectors. However, the data capacity of a physical sector and / or the total number of physical sectors included in a physical programming unit can be adjusted according to practical needs, and the present invention is not limited thereto. In one embodiment, a physical programming unit can be regarded as a physical page. For example, the storage capacity of a physical programming unit may be 16 kilobytes, and the present invention is not limited thereto.

[0030] In one embodiment, a physical programming unit is a minimum unit for synchronously writing data in the memory module 122. For example, when a programming operation (also referred to as a write operation) is performed on a physical programming unit to write data to the physical programming unit, multiple memory cells in the physical programming unit may be synchronously programmed to store corresponding data. For example, when programming a physical programming unit, a write voltage may be applied to the physical programming unit to change the threshold voltage of at least some of the memory cells in the physical programming unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in the memory cell.

[0031] In one embodiment, a physical erase unit may include a plurality of physical programming units. The plurality of physical programming units in a physical erase unit may be erased synchronously. For example, when performing an erase operation on a physical erase unit, an erase voltage may be applied to the plurality of physical programming units in the physical erase unit to change the threshold voltage of at least some of the storage cells in the physical programming units. By performing an erase operation on a physical erase unit, the data stored in the physical erase unit may be cleared.

[0032] In one embodiment, the memory control circuit 23 can logically associate the physical units 301(1)-301(A) and 301(A+1)-301(B) to the data area 31 and the idle area 32, respectively. The physical units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any physical unit in the data area 31 can store valid data and / or invalid data. In addition, the physical units 301(A+1)-301(B) in the idle area 32 do not store data (e.g., valid data).

[0033] In one embodiment, if a physical unit does not store valid data, the physical unit can be associated with the idle area 32. In addition, the physical unit in the idle area 32 can be erased to clear the data in the physical unit. In one embodiment, the physical unit in the idle area 32 is also called an idle physical unit. In one embodiment, the idle area 32 is also called an idle pool.

[0034] In one embodiment, when data is to be stored, the memory control circuit 23 may select one or more physical cells from the idle area 32 and instruct the memory module 122 to store the data in the selected physical cells. After the data is stored in the physical cell, the physical cell may be associated with the data area 31. In other words, one or more physical cells may be used alternately between the data area 31 and the idle area 32.

[0035] In one embodiment, the memory control circuit 23 may configure a plurality of logical units 302(1)-302(C) to map the physical units (i.e., the physical units 301(1)-301(A)) in the data area 31. For example, a logical unit may correspond to a logical block address (LBA) or other logical management units. A logical unit may be mapped to one or more physical units.

[0036] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in the physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that the physical unit does not currently store any valid data.

[0037] In one embodiment, the memory control circuit 23 may record the mapping relationship between the logical unit and the physical unit in at least one management table (also referred to as a logical-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing or erasing according to the information in the management table (i.e., the logical-to-physical mapping table).

[0038] In one embodiment, the memory control circuit 23 may detect the type of at least one physical unit (also referred to as a first physical unit) among the physical units 301(1)-301(A) and 301(A+1)-301(B). For example, the type of the first physical unit is related to the reliability of the first physical unit. For example, physical units of different types may have different reliabilities. Physical units of the same type may have the same or similar reliabilities.

[0039] In one embodiment, the reliability of the first physical unit may be negatively correlated to the bit error rate of the first physical unit. That is, if the reliability of the first physical unit is higher, it means that the bit error rate of the first physical unit may be lower (that is, the data read from the first physical unit may contain relatively less error data). Conversely, if the reliability of the first physical unit is lower, it means that the bit error rate of the first physical unit may be higher (that is, the data read from the first physical unit may contain relatively more error data).

[0040] In one embodiment, the reliability of the first physical unit may be negatively correlated to the usage level of the first physical unit. That is, if the reliability of the first physical unit is higher, it means that the usage level of the first physical unit may be lower (for example, the number of times the first physical unit is programmed, read and / or erased is relatively small). Conversely, if the reliability of the first physical unit is lower, it means that the usage level of the first physical unit may be higher (that is, the number of times the first physical unit is programmed, read and / or erased is relatively large).

[0041] In one embodiment, the memory control circuit 23 may add a tag to the first physical unit according to the type of the first physical unit. The tag may reflect the type of the first physical unit. In one embodiment, the memory control circuit 23 may record the tag corresponding to the first physical unit in the management table. Alternatively, in one embodiment, the memory control circuit 23 may store the tag corresponding to the first physical unit in the first physical unit.

[0042] In one embodiment, according to the type of the first physical unit, the memory control circuit 23 may determine a programming mode, a verification time point, and a classification rule for the first physical unit. After determining the programming mode, the verification time point, and the classification rule for the first physical unit, the memory control circuit 23 may manage, use, and / or operate the first physical unit according to the programming mode, the verification time point, and the classification rule.

[0043] In one embodiment, the programming mode can be used to control the mode adopted when performing programming operations on the first entity unit. The verification time point can be used to control the time point when performing reliability verification on the first entity unit. In addition, the classification rule can be used to control the rule adopted when performing classification (or reclassification) on the first entity unit.

[0044] In one embodiment, if the first physical unit belongs to the first type of physical unit, the memory control circuit 23 can determine that the programming mode, verification time point and classification rule for the first physical unit are respectively a specific programming mode (also called a first programming mode) among multiple programming modes (also called candidate programming modes), a specific verification time point (also called a first verification time point) among multiple verification time points (also called candidate verification time points) and a specific classification rule (also called a first classification rule) among multiple classification rules (also called candidate classification rules).

[0045] In one embodiment, if the first physical unit belongs to the second type of physical unit, the memory control circuit 23 can determine that the programming mode, verification time point and classification rule for the first physical unit are respectively a specific programming mode among the multiple candidate programming modes (also called the second programming mode), a specific verification time point among the multiple candidate verification time points (also called the second verification time point) and a specific classification rule among the multiple candidate classification rules (also called the second classification rule).

[0046] In one embodiment, if the first physical unit belongs to the third type of physical unit, the memory control circuit 23 can determine that the programming mode, verification time point and classification rule for the first physical unit are respectively a specific programming mode among the multiple candidate programming modes (also called the third programming mode), a specific verification time point among the multiple candidate verification time points (also called the third verification time point) and a specific classification rule among the multiple candidate classification rules (also called the third classification rule).

[0047] In one embodiment, the reliability of the first type of physical unit may be higher than the reliability of the second type of physical unit, and the reliability of the second type of physical unit may be higher than the reliability of the third type of physical unit. In one embodiment, if the first physical unit belongs to the first type of physical unit, the second type of physical unit or the third type of physical unit, the memory control circuit 23 may use the first physical unit to store data.

[0048] In one embodiment, the first physical unit may also belong to the fourth type of physical unit. The reliability of the third type of physical unit may be higher than the reliability of the fourth type of physical unit. In one embodiment, the fourth type of physical unit includes a damaged physical unit. In one embodiment, if the first physical unit belongs to the fourth type of physical unit, the memory control circuit 23 may no longer use the first physical unit to store data. That is, in one embodiment, if the first physical unit is determined to belong to the fourth type of physical unit, the first physical unit will no longer be used.

[0049] In one embodiment, if the first physical unit belongs to the first type of physical unit, the second type of physical unit, or the third type of physical unit, the memory control circuit 23 may map at least one logical unit to the first physical unit. Thereafter, the memory control circuit 23 may access the first physical unit according to the at least one logical unit. However, in one embodiment, if the first physical unit belongs to the fourth type of physical unit, the memory control circuit 23 may not map any logical unit to the first physical unit. Thus, the first physical unit can be prevented from being accidentally accessed.

[0050] In one embodiment, the multiple candidate programming modes may include a single-level programming mode and a multi-level programming mode. In one embodiment, the single-level programming mode includes an SLC mode (also called a virtual SLC mode). Based on the single-level programming mode, a storage cell in a physical unit may be programmed to store p bits. For example, p may be "1". In one embodiment, the multi-level programming mode may include an MLC mode, a TLC mode, a QLC mode, or other types of multi-level programming modes. Based on the multi-level programming mode, a storage cell in a physical unit may be programmed to store q bits. For example, q may be "2", "3", "4", or other integers greater than "1".

[0051] In one embodiment, the multiple candidate verification time points may include a first time point and a second time point. The first time point is within the period of performing a regular read operation on the first physical unit. For example, the first time point may refer to any time point within the period of performing a regular read operation on the first physical unit. For example, the regular read operation may be performed according to an instruction (such as a read instruction) from the host system 11. Alternatively, the regular read operation may also be performed according to a data sorting operation performed on the memory module 122. For example, the data sorting operation may include a garbage collection (GC) operation, a wear leveling (WL) operation, or other operations involving data movement within the memory module 122. In addition, the second time point is after the first physical unit is filled. For example, the second time point may refer to any time point after the first physical unit is filled. In addition, the multiple candidate classification rules can be used to classify different types of physical units.

[0052] In one embodiment, after determining the programming mode for the first entity unit, the memory control circuit 23 may program the first entity unit based on the programming mode. For example, if the first entity unit belongs to the first type of entity unit, the memory control circuit 23 may program the first entity unit based on the first programming mode. If the first entity unit belongs to the second type of entity unit, the memory control circuit 23 may program the first entity unit based on the second programming mode. Alternatively, if the first entity unit belongs to the third type of entity unit, the memory control circuit 23 may program the first entity unit based on the third programming mode.

[0053] In one embodiment, the first programming mode includes a single-level programming mode and a multi-level programming mode, and / or the second programming mode also includes a single-level programming mode and a multi-level programming mode. For example, the memory control circuit 23 may determine, according to demand, whether to program the first physical unit belonging to the first type of physical unit or the second type of physical unit based on one of the single-level programming mode and the multi-level programming mode.

[0054] In one embodiment, the third programming mode can only be a single-stage programming mode. For example, for the first physical unit belonging to the third type of physical unit, the memory control circuit 23 can program the first physical unit based on the single-stage programming mode, but cannot program the first physical unit based on the multi-stage programming mode. Therefore, even if the reliability of the first physical unit belonging to the third type of physical unit is relatively low, there is still an opportunity to maintain the normal use of the first physical unit by strictly controlling the programming mode for the first physical unit.

[0055] In one embodiment, after determining the verification time point for the first physical unit, at the verification time point, the memory control circuit 23 may verify the reliability of the first physical unit. For example, in the operation of verifying the reliability of the first physical unit, the memory control circuit 23 may read data (also referred to as first data) from the first physical unit. Then, the decoding circuit 25 decodes the first data based on at least one of a plurality of decoding modes (also referred to as candidate decoding modes). For example, the decoding circuit 25 may decode the first data based on at least one of the plurality of decoding modes according to a preset order until the first data is successfully decoded (i.e., all errors in the first data are corrected) or it is determined that the first data cannot be successfully decoded (i.e., all errors in the first data cannot be corrected). Then, the memory control circuit 23 may confirm the reliability of the first physical unit based on the decoding result of the first data.

[0056] In one embodiment, the first verification time point is the first time point, the second verification time point is the second time point, and / or the third verification time point is the second time point.

[0057] For example, for a first physical unit belonging to the first category of physical units, the memory control circuit 23 can integrate the timing of verifying the reliability of the first physical unit (i.e., the first time point) into the regular read operation for the first physical unit, without the need to additionally verify the reliability of the first physical unit at a second time point (i.e., after the first physical unit is fully written).

[0058] However, for the first physical unit belonging to the second type physical unit or the third type physical unit, the memory control circuit 23 needs to verify the reliability of the first physical unit each time the first physical unit is filled. Therefore, by performing additional reliability verification on the physical unit each time a physical unit with relatively low reliability (i.e., the second type physical unit or the third type physical unit) is filled, it can be ensured as much as possible that the current classification results for each physical unit are correct.

[0059] In one embodiment, after determining the classification rule for the first physical unit and the verification result of the reliability of the first physical unit, the memory control circuit 23 may classify the first physical unit according to the classification rule and the verification result of the reliability. It should be noted that the classification may mean maintaining or changing the previous classification result of the first physical unit. In particular, for different types of first physical units, the memory control circuit 23 may use the most appropriate classification rule to classify the first physical unit.

[0060] Figure 4 Schematic diagram of programming modes, verification time points and classification rules corresponding to different types of entity units according to an embodiment of the present invention. Figure 4, referring to the table data 41, according to the type of the first physical unit, the memory control circuit 23 can manage, use and / or operate the first physical unit according to the appropriate programming mode, verification time point and classification rule.

[0061] For example, for the first physical unit belonging to the first type of physical unit, the memory control circuit 23 can set the programming mode, verification time point and classification rule corresponding to the first physical unit to "SLC (i.e., single-level programming mode) / xLC (i.e., multi-level programming mode)", "T(1) (i.e., the first time point)" and "R(1) (i.e., the first grouping rule)" respectively.

[0062] For the first physical unit belonging to the second type of physical unit, the memory control circuit 23 can set the programming mode, verification time point and classification rule corresponding to the first physical unit to "SLC / xLC", "T(2) (i.e., the second time point)" and "R(2) (i.e., the second grouping rule)" respectively.

[0063] For the first physical cell belonging to the third category of physical cells, the memory control circuit 23 may set the programming mode, verification time point and classification rule corresponding to the first physical cell to "SLC", "T(2)" and "R(3) (i.e., the third grouping rule)", respectively. In addition, for the first physical cell belonging to the fourth category of physical cells, the memory control circuit 23 may set the first physical cell to no longer be used.

[0064] By using the method proposed in the example of this application, different usage strategies are set for different categories of physical units, which can achieve the purpose of improving the stability and security of data storage. By setting different usage modes throughout the life cycle of the storage device, the stability of the data of the storage device can be ensured when it is near the end of its life cycle.

[0065] It should be noted that Figure 4 The management strategies for different types of entity units presented in the table data 41 are only examples and are not intended to limit the present invention. In one embodiment, the information in each column of the table data 41 can be adjusted according to practical needs, and the present invention is not limited thereto.

[0066] In one embodiment, when the first physical cell belongs to the first type of physical cell, the memory control circuit 23 may classify the first physical cell according to the first classification rule and the verification result of the reliability of the first physical cell at the first verification time point.

[0067] For example, if the verification result of the reliability of the first physical cell shows that the first data is successfully decoded based on a specific decoding mode (also referred to as the first decoding mode) among the plurality of decoding modes, the memory control circuit 23 may maintain the first physical cell as a first type physical cell.

[0068] If the verification result of the reliability of the first physical cell shows that the first data is successfully decoded based on another decoding mode (also referred to as the second decoding mode) among the plurality of decoding modes, the memory control circuit 23 may classify the first physical cell as a second type of physical cell.

[0069] In addition, if the verification result of the reliability of the first physical cell shows that the first data cannot be successfully decoded (in any decoding mode), the memory control circuit 23 may classify the first physical cell as a third type of physical cell.

[0070] It should be noted that the second decoding mode is triggered after the first decoding mode fails. For example, in the process of decoding the first data by the decoding circuit 25, the decoding circuit 25 may first decode the first data based on the first decoding mode. If the first data cannot be successfully decoded based on the first decoding mode, the second decoding mode may be triggered. Then, the decoding circuit 25 may decode the first data based on the second decoding mode. In addition, the error correction capability of the second decoding mode may be higher than the error correction capability of the first decoding mode.

[0071] In one embodiment, the first decoding mode may include a plurality of decoding modes (also referred to as sub-decoding modes). For example, the plurality of sub-decoding modes may include a normal decoding mode (also referred to as a first sub-decoding mode), a retry mode (also referred to as a second sub-decoding mode), and a soft bit decoding mode (also referred to as a third sub-decoding mode).

[0072] In one embodiment, the conventional decoding mode refers to a basic decoding mode in which the decoding circuit 25 performs a decoding operation on the first data for the first time after reading the first data from the first physical unit. The retry mode refers to an advanced decoding mode that attempts to reduce the error bits in the read first data by adjusting the read voltage level for the first physical unit and repeatedly reading the first physical unit after determining that the first data cannot be decoded based on the conventional decoding mode. The soft bit decoding mode refers to a more advanced decoding mode that improves the decoding success rate by applying more read voltage levels to the first physical unit to read additional auxiliary decoding data (also called soft bits) and adjusting some decoding parameters (such as Log Likelihood Ratio (LLR)) after determining that the first data cannot be decoded based on the retry mode.

[0073] In one embodiment, based on the first decoding mode, the decoding circuit 25 may sequentially decode the first data through the first sub-decoding mode, the second sub-decoding mode and the third sub-decoding mode until the first data is successfully decoded or it is determined that the first decoding mode cannot successfully decode the first data.

[0074] In one embodiment, the time required to decode the first data based on the first sub-decoding mode is less than the time required to decode the first data based on the second sub-decoding mode, and the time required to decode the first data based on the second sub-decoding mode is less than the time required to decode the first data based on the third sub-decoding mode. Correspondingly, the error correction capability of the second sub-decoding mode may be higher than the error correction capability of the first sub-decoding mode, and the error correction capability of the third sub-decoding mode may be higher than the error correction capability of the second sub-decoding mode.

[0075] In one embodiment, the second decoding mode may include a group decoding mode. For example, assuming that the first data to be decoded is read from the first physical programming unit in the first physical unit, in the group decoding mode, the data stored in other physical programming units in the first physical unit (or other physical units) can be used together to decode the first data. In one embodiment, the second decoding mode is also called a disk array (RAID) decoding mode.

[0076] It should be noted that the first decoding mode, each sub-decoding mode in the first decoding mode and the second decoding mode mentioned in the above embodiment are only examples and are not intended to limit the present invention. In one embodiment, any decoding mode and any sub-decoding mode can be adjusted according to practical needs, and the present invention is not limited thereto.

[0077] In one embodiment, when the first physical unit belongs to the second type of physical unit, the memory control circuit 23 may classify the first physical unit according to the second classification rule and the verification result of the reliability of the first physical unit at the second verification time point. For example, if the verification result of the reliability of the first physical unit reflects that the first data is successfully decoded based on a specific sub-decoding mode (e.g., the first sub-decoding mode) in the first decoding mode, the memory control circuit 23 may classify the first physical unit as the first type of physical unit. If the verification result of the reliability of the first physical unit reflects that the first data is successfully decoded based on another sub-decoding mode (e.g., the second sub-decoding mode) in the first decoding mode, the memory control circuit 23 may maintain the first physical unit as the second type of physical unit. In addition, if the verification result of the reliability of the first physical unit reflects that the first data cannot be successfully decoded (by the second sub-decoding mode or other sub-decoding modes), the memory control circuit 23 may classify the first physical unit as the third type of physical unit.

[0078] In one embodiment, when the first physical unit belongs to the third type of physical unit, the memory control circuit 23 may classify the first physical unit according to the third classification rule and the verification result of the reliability of the first physical unit at the third verification time point. For example, if the verification result of the reliability of the first physical unit reflects that the first data can be successfully decoded, the memory control circuit 23 may maintain the first physical unit as the third type of physical unit. However, if the verification result of the reliability of the first physical unit reflects that the first data cannot be successfully decoded, the memory control circuit 23 may classify the first physical unit as the fourth type of physical unit.

[0079] It should be noted that once the first physical unit is classified as the fourth type physical unit, the first physical unit can no longer be used. For example, the memory control circuit 23 can lock the first physical unit belonging to the fourth type physical unit so that the first physical unit can no longer be used.

[0080] In one embodiment, the memory control circuit 23 may also monitor whether the usage level of the first physical unit meets the preset condition at any time point. If the usage level of the first physical unit meets the preset condition, the memory control circuit 23 may classify the first physical unit into one of the second type of physical unit, the third type of physical unit and the fourth type of physical unit, depending on the current setting and / or demand.

[0081] In one embodiment, the memory control circuit 23 may obtain a wear assessment value corresponding to the first physical unit. This wear assessment value may reflect the degree of use of the first physical unit. For example, this wear assessment value may be positively correlated with the degree of use of the first physical unit. That is, if this wear assessment value is larger, it means that the degree of use of the first physical unit is higher. For example, the memory control circuit 23 may determine the wear assessment value corresponding to the first physical unit based on the programming count, read count, erase count and / or bit error rate assessment value corresponding to the first physical unit. The programming count may reflect the number of times the first physical unit is programmed. The read count may reflect the number of times the first physical unit is read. The erase count may reflect the number of times the first physical unit is erased. The bit error rate assessment value may reflect the bit error rate of the first physical unit. In addition, the wear assessment value corresponding to the first physical unit may also be determined with reference to other parameters, which is not limited by the present invention.

[0082] In one embodiment, the memory control circuit 23 may compare the wear evaluation value corresponding to the first physical unit with a critical value. If the wear evaluation value is greater than the critical value, the memory control circuit 23 may determine that the usage level of the first physical unit meets the preset condition. However, if the wear evaluation value is not greater than (e.g., less than or equal to) the critical value, the memory control circuit 23 may determine that the usage level of the first physical unit does not meet the preset condition.

[0083] In one embodiment, the memory control circuit 23 may monitor whether each programming and / or erasing of the first physical unit is successful. If a certain programming or erasing of the first physical unit fails, the memory control circuit 23 may classify the first physical unit into one of the second type physical unit, the third type physical unit and the fourth type physical unit, depending on the current setting and / or demand.

[0084] Figure 5 is a flow chart of a physical unit management method according to an embodiment of the present invention. Figure 5 In step S501, a programming mode, a verification time point, and a classification rule for the first entity unit are determined according to the type of the first entity unit. In step S502, the first entity unit is programmed based on the programming mode. In step S503, the reliability of the first entity unit is verified at the verification time point. In step S504, the first entity unit is classified according to the classification rule and the verification result of the reliability.

[0085] Figure 6 is a flow chart of a physical unit management method according to an embodiment of the present invention. Figure 6 As shown, the specific steps include:

[0086] In step S601, it is determined that the first entity element belongs to a first type of entity element.

[0087] In step S602 , it is determined whether the first data can be successfully decoded based on a first decoding mode among a plurality of decoding modes.

[0088] If the first data can be successfully decoded based on the first decoding mode, in step S603 , the first physical unit is maintained as a first-type physical unit.

[0089] If the first data cannot be successfully decoded based on the first decoding mode, in step S604 , it is determined whether the first data can be successfully decoded based on a second decoding mode among the plurality of decoding modes.

[0090] If the first data can be successfully decoded based on the second decoding mode, in step S605 , the first physical unit is classified as a second type of physical unit.

[0091] If the first data cannot be decoded successfully, in step S606 , the first physical unit is classified as a third type of physical unit.

[0092] Figure 7 is a flow chart of a physical unit management method according to an embodiment of the present invention. Figure 7 As shown, the specific steps include:

[0093] In step S701, it is determined whether the first entity element belongs to the second type of entity element.

[0094] In step S702 , it is determined whether the first data can be successfully decoded based on the first sub-decoding mode in the first decoding mode.

[0095] If the first data can be successfully decoded based on the first sub-decoding mode, in step S703 , the first physical unit is reclassified as a first type of physical unit.

[0096] If the first data cannot be successfully decoded based on the first sub-decoding mode, in step S704, it is determined whether the first data can be successfully decoded based on the second sub-decoding mode in the first decoding mode.

[0097] If the first data can be successfully decoded based on the second sub-decoding mode, in step S705 , the first physical unit is maintained as a second-type physical unit.

[0098] If the first data cannot be successfully decoded, in step S706 , the first physical unit is classified as a third type of physical unit.

[0099] Figure 8 is a flow chart of a physical unit management method according to an embodiment of the present invention. Figure 8 As shown, the specific steps include:

[0100] In step S801, it is determined that the first entity element belongs to the third type of entity element.

[0101] In step S802, it is determined whether the first data can be successfully decoded.

[0102] If the first data can be decoded successfully, in step S803 , the first physical unit is maintained as a third type physical unit.

[0103] If the first data cannot be successfully decoded, in step S804 , the first physical unit is classified as a fourth type of physical unit.

[0104] However, Figures 5 to 8 The steps in the above are described in detail, so I will not repeat them here. It is worth noting that Figures 5 to 8 Each step in the above process can be implemented as multiple program codes or circuits, and the present invention is not limited thereto. Figures 5 to 8 The method can be used in conjunction with the above exemplary embodiments or can be used alone, and the present invention is not limited thereto.

[0105] In summary, the physical unit management method and storage device provided by the embodiment of the present invention can manage the corresponding physical units with different reliability by using appropriate programming modes, verification time points and classification rules. In particular, for the physical units with relatively low reliability (i.e., the second type of physical units and the third type of physical units), in addition to limiting them to use only programming modes with higher reliability, an additional procedure for verifying the reliability of the physical units after the physical units are fully written is added. In this way, the problems derived from the improper management of physical blocks with aging risks in the past can be improved, and a balance can be achieved between improving the reliability of the memory module and maintaining the number of available physical units as much as possible.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A physical unit management method, characterized in that: For use in a storage device, wherein the storage device comprises a memory module, the memory module comprises a plurality of physical units, and the physical unit management method comprises: Determining, according to the type of a first entity unit among the plurality of entity units, a programming mode, a verification time point, and a classification rule for the first entity unit; Based on the programming mode, programming the first entity unit; At the verification time point, verifying the reliability of the first entity unit; and The first entity unit is classified according to the classification rule and the reliability verification result.

2. The physical unit management method according to claim 1, wherein the programming mode includes multiple candidate programming modes, each of the candidate programming modes includes a single-level programming mode and / or a multi-level programming mode, and the verification time point includes one of a first time point and a second time point, the first time point is during a period of performing a normal read operation on the first physical unit, and the second time point is after the first physical unit is fully written.

3. The entity unit management method according to claim 1, wherein the step of determining the programming mode, the verification time point and the classification rule for the first entity unit according to the type of the first entity unit among the plurality of entity units comprises: If the first entity unit belongs to the first type of entity unit, determining that the programming mode, the verification time point and the classification rule for the first entity unit are respectively a first programming mode among a plurality of candidate programming modes, a first verification time point among a plurality of candidate verification time points and a first classification rule among a plurality of candidate classification rules; If the first entity unit belongs to the second type of entity unit, determining that the programming mode, the verification time point and the classification rule for the first entity unit are respectively the second programming mode among the multiple candidate programming modes, the second verification time point among the multiple candidate verification time points and the second classification rule among the multiple candidate classification rules; as well as If the first entity unit belongs to the third type of entity unit, the programming mode, the verification time point and the classification rule for the first entity unit are respectively determined to be a third programming mode among the multiple candidate programming modes, a third verification time point among the multiple candidate verification time points and a third classification rule among the multiple candidate classification rules, The reliability of the first type of entity units is higher than the reliability of the second type of entity units, and the reliability of the second type of entity units is higher than the reliability of the third type of entity units.

4. The physical unit management method according to claim 3, wherein the first programming mode includes a single-level programming mode and a multi-level programming mode, the second programming mode includes the single-level programming mode and the multi-level programming mode, and the third programming mode is the single-level programming mode.

5. The physical unit management method according to claim 3, wherein the first verification time point is the first time point, the second verification time point is the second time point, the third verification time point is the second time point, the first time point is during a period of performing a normal read operation on the first physical unit, and the second time point is after the first physical unit is fully written.

6. The physical unit management method according to claim 1, wherein the step of verifying the reliability of the first physical unit comprises: Reading first data from the first physical unit; as well as The first data is decoded based on at least one of a plurality of decoding modes until the first data is successfully decoded or it is determined that the first data cannot be successfully decoded.

7. The entity unit management method according to claim 6, wherein when the first entity unit belongs to a first type of entity unit, the step of classifying the first entity unit according to the classification rule and the verification result of the reliability comprises: If the first data is successfully decoded based on a first decoding mode among the plurality of decoding modes, maintaining the first physical unit as the first type of physical unit; if the first data is successfully decoded based on a second decoding mode among the plurality of decoding modes, classifying the first physical unit as a second type of physical unit, wherein the second decoding mode is triggered after the first decoding mode fails, and an error correction capability of the second decoding mode is higher than an error correction capability of the first decoding mode; as well as If the first data cannot be successfully decoded, the first physical unit is classified as a third type of physical unit.

8. The entity unit management method according to claim 6, wherein when the first entity unit belongs to the second type of entity unit, the step of classifying the first entity unit according to the classification rule and the verification result of the reliability comprises: If the first data is successfully decoded based on a first sub-decoding mode in a first decoding mode among the plurality of decoding modes, classifying the first physical unit as a first type of physical unit; If the first data is successfully decoded based on a second sub-decoding mode in the first decoding mode, maintaining the first physical unit as the second type of physical unit, wherein the second sub-decoding mode is triggered after the first sub-decoding mode fails, and an error correction capability of the second sub-decoding mode is higher than an error correction capability of the first sub-decoding mode; and If the first data cannot be successfully decoded, the first physical unit is classified as a third type of physical unit.

9. The entity unit management method according to claim 6, wherein when the first entity unit belongs to the third type of entity unit, the step of classifying the first entity unit according to the classification rule and the verification result of the reliability comprises: If the first data can be successfully decoded, maintaining the first physical unit as the third type physical unit; as well as If the first data cannot be successfully decoded, the first physical unit is classified as a fourth-type physical unit, wherein the fourth-type physical unit is no longer used.

10. The physical unit management method according to claim 1, further comprising: monitoring whether the usage degree of the first entity unit meets the preset conditions; Monitoring whether programming and / or erasing of the first physical unit is successful; as well as If the usage level of the first physical unit meets the preset condition, or the programming or erasing of the first physical unit fails, the first physical unit is classified into one of a second type physical unit, a third type physical unit, and a fourth type physical unit.

11. A storage device, characterized in that: include: A connection interface for connecting to a host system; Memory module; as well as a memory controller connected to the connection interface and the memory module, The memory module includes a plurality of physical units, and the memory controller is used to: Determining, according to the type of a first entity unit among the plurality of entity units, a programming mode, a verification time point, and a classification rule for the first entity unit; Based on the programming mode, programming the first entity unit; At the verification time point, verifying the reliability of the first entity unit; as well as The first entity unit is classified according to the classification rule and the reliability verification result.

12. The storage device according to claim 11, wherein the programming mode comprises one of a single-level programming mode and a multi-level programming mode, the verification time point comprises one of a first time point and a second time point, the first time point is during a period of performing a normal read operation on the first physical unit, and the second time point is after the first physical unit is fully written.

13. The storage device according to claim 11, wherein the memory controller determines the programming mode, the verification time point, and the classification rule for the first physical unit according to the type of the first physical unit among the plurality of physical units, comprising: If the first entity unit belongs to the first type of entity unit, determining that the programming mode, the verification time point and the classification rule for the first entity unit are respectively a first programming mode among a plurality of candidate programming modes, a first verification time point among a plurality of candidate verification time points and a first classification rule among a plurality of candidate classification rules; If the first entity unit belongs to the second type of entity unit, determining that the programming mode, the verification time point and the classification rule for the first entity unit are respectively the second programming mode among the multiple candidate programming modes, the second verification time point among the multiple candidate verification time points and the second classification rule among the multiple candidate classification rules; as well as If the first entity unit belongs to the third type of entity unit, the programming mode, the verification time point and the classification rule for the first entity unit are respectively determined to be a third programming mode among the multiple candidate programming modes, a third verification time point among the multiple candidate verification time points and a third classification rule among the multiple candidate classification rules, The reliability of the first type of entity units is higher than the reliability of the second type of entity units, and the reliability of the second type of entity units is higher than the reliability of the third type of entity units. 14 . The storage device according to claim 13 , wherein the first programming mode includes a single-level programming mode and a multi-level programming mode, the second programming mode includes the single-level programming mode and the multi-level programming mode, and the third programming mode is the single-level programming mode.

15. The storage device according to claim 13, wherein the first verification time point is a first time point, the second verification time point is a second time point, the third verification time point is the second time point, the first time point is during a period of performing a normal read operation on the first physical unit, and the second time point is after the first physical unit is fully written.

16. The storage device according to claim 11, wherein the operation of the memory controller verifying the reliability of the first physical unit comprises: Reading first data from the first physical unit; as well as The first data is decoded based on at least one of a plurality of decoding modes until the first data is successfully decoded or it is determined that the first data cannot be successfully decoded.

17. The storage device according to claim 16, wherein when the first physical unit belongs to a first type of physical unit, the memory controller classifies the first physical unit according to the classification rule and the verification result of the reliability, comprising: If the first data is successfully decoded based on a first decoding mode among the plurality of decoding modes, maintaining the first physical unit as the first type of physical unit; if the first data is successfully decoded based on a second decoding mode among the plurality of decoding modes, classifying the first physical unit as a second type of physical unit, wherein the second decoding mode is triggered after the first decoding mode fails, and an error correction capability of the second decoding mode is higher than an error correction capability of the first decoding mode; as well as If the first data cannot be successfully decoded, the first physical unit is classified as a third type of physical unit.

18. The storage device according to claim 16, wherein when the first physical unit belongs to the second type of physical unit, the memory controller classifies the first physical unit according to the classification rule and the verification result of the reliability, comprising: If the first data is successfully decoded based on a first sub-decoding mode in a first decoding mode among the plurality of decoding modes, classifying the first physical unit as a first type of physical unit; If the first data is successfully decoded based on a second sub-decoding mode in the first decoding mode, maintaining the first physical unit as the second type of physical unit, wherein the second sub-decoding mode is triggered after the first sub-decoding mode fails, and an error correction capability of the second sub-decoding mode is higher than an error correction capability of the first sub-decoding mode; and If the first data cannot be successfully decoded, the first physical unit is classified as a third type of physical unit.

19. The storage device according to claim 16, wherein when the first physical unit belongs to the third type of physical unit, the memory controller classifies the first physical unit according to the classification rule and the verification result of the reliability, comprising: If the first data can be successfully decoded, maintaining the first physical unit as the third type physical unit; as well as If the first data cannot be successfully decoded, the first physical unit is classified as a fourth-type physical unit, wherein the fourth-type physical unit is no longer used.

20. The storage device according to claim 11, wherein the memory controller is further configured to: monitoring whether the usage degree of the first entity unit meets the preset conditions; monitoring whether programming and / or erasing of the first physical unit is successful; and If the usage level of the first physical unit meets the preset condition or the programming or erasing of the first physical unit fails, the first physical unit is classified into one of a second type physical unit, a third type physical unit and a fourth type physical unit.

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