Pci interface module and pci bus control data transmission method

Abstract

The invention relates to a pci interface module and a pci bus control data transmission method. Power-on reset is carried out through a reset management module; the external CPU issues a configuration space read-write command and transmits the configuration space read-write command to the configuration management module through a pci configuration space time sequence processing module of the transmission engine module; an external cpu issues a register read-write command through a pci register read-write time sequence processing module of the transmission engine module and transmits the register read-write command to an address decoding module, the address decoding module judges that a receiver is a dma data transmission time sequence processing module in the transmission engine module, the dma data transmission time sequence processing module receives the register read-write command, an external pci device applies for a pci bus, and the dma data transmission time sequence processing module transmits the dma data transmission time sequence processing module to an address decoding module; and data transmission is carried out. The method does not depend on an ip core developed by any special manufacturer or an interface chip produced by a third-party manufacturer.

Description

Technical Field

[0001] The invention relates to the technical field of human-computer interaction, in particular to a PCI interface module and a method for realizing PCI bus control data transmission by utilizing the PCI interface module. Background Art

[0002] In the field of communications, the PCI bus is widely used due to its high transmission rate and low power consumption. However, due to the complexity of the PCI protocol, the development is difficult and the time cycle is long. Therefore, in the relatively relaxed international environment of chip exports, the control of the PCI bus will use IP cores developed by dedicated manufacturers or interface chips produced by third-party manufacturers. Both methods have their own advantages and disadvantages. Generally, dedicated IP cores are highly integrated in FPGA chips, but they are expensive. Dedicated interface chips occupy too many hardware resources; and both methods have the problem of poor code flexibility and portability, and logic and hardware resources are relatively wasted under limited requirements. And logic and hardware resources are relatively wasted under limited requirements. The most critical problem is that many domestic FPGA software have not developed PCI IP under the environment of localized software and hardware research and development, and there are not many domestic PCI hardware chip selections, which increases many restrictions on the development of the PCI bus. Summary of the invention

[0003] The present invention aims to solve the above problems and proposes a PCI interface module that does not develop the entire PCI protocol but meets the transmission requirements under the PCI 33M clock, and a method for implementing PCI bus control data transmission using the PCI interface module, thereby reducing the waste of logic resources, having high code portability and being compatible with all FPGA software.

[0004] The technical solution of the present invention is.

[0005] (I) The present invention proposes a PCI interface module.

[0006] A PCI interface module comprises a transmission engine module and a configuration management module, an address decoding module, a register access module and a FIFO respectively connected to the transmission engine module; further comprises a reset management module, the reset management module is respectively connected to the configuration management module, the address decoding module, the register access module and the transmission engine module; the transmission engine module is also connected to an external PCI bus and then to an external PCI device; the address decoding module is also connected to the register access module; the FIFO comprises an input FIFO and an output FIFO; the input FIFO and the output FIFO are both connected to the transmission engine module; The transmission engine module includes a PCI configuration space timing processing module, a PCI register read and write timing processing module and a DMA data transmission timing processing module; the PCI configuration space timing processing module is connected to the configuration management module, the PCI register read and write timing processing module is connected to the address decoding module, and one end of the DMA data transmission timing processing module is connected to the register access module and the other end is connected to the FIFO; When the transmission timing of the PCI register read / write timing processing module is the DWORD timing of PCI memory writing, after transmitting a DWORD size of data, the PCI bus needs to be re-applied after the PCI bus is released. During this period, the PCI bus does not perform any other processing until the external PCI device and the external CPU complete the data interaction; When the transmission timing of the DMA data transmission timing processing module is the multi-byte timing of PCI memory writing, three timings of PCI retry, DisConnect without data terminate or target abort are introduced and processed in coordination; when an interruption occurs between the PCI bus and the external PCI device, the external PCI device needs to re-apply for the PCI bus to continue transmission until the data interaction between the external PCI device and the external CPU is completed.

[0007] (II) The present invention provides a method for controlling data transmission via a PCI bus.

[0008] A method for controlling data transmission via a PCI bus, using the PCI interface module as described above, the specific method is as follows: Power-on reset is performed through the reset management module; The external CPU sends the configuration space read and write commands, which are transmitted to the configuration management module through the PCI configuration space timing processing module of the transmission engine module. The configuration management module implements the configuration of each configuration space on the PCI bus. The external CPU sends register read and write commands to the address decoding module through the PCI register read and write timing processing module of the transmission engine module. The address decoding module determines whether the receiver is the user function module in the register access module or the DMA data transmission timing processing module in the transmission engine module, and sends the register read and write commands to the receiver accordingly, and reads back the processing status of the receiver. If the DMA data transmission timing processing module in the transmission engine module receives the register read and write command, the external PCI device applies for the PCI bus, that is, data transmission is performed until the external PCI device and the external CPU complete the data exchange.

[0009] The specific process of implementing the configuration of each configuration space on the PCI bus is as follows: the external CPU transmits and issues configuration space read and write commands to the PCI configuration space timing processing module of the transmission engine module, and the configuration space read and write commands include the 16bite-2G address space applied by the external PCI device to the external CPU; the transmission engine module receives the configuration space read and write commands, the PCI configuration space timing processing module parses the configuration space read and write address, read and write enable and configuration data and passes them to the configuration management module, and the configuration management module implements the configuration of each configuration space on the PCI bus through the transmission engine module.

[0010] It also includes: the external CPU sends a register read and write command to the PCI register read and write timing processing module of the transmission engine module, adopts the DWORD timing of PCI memory writing and PCI memory reading, the external CPU controls the main control signal of the external CPU to be effective according to the timing requirements, when it is a register write command, the PCI bus address, command code and data are placed on the PCI bus, when it is a register read command, the PCI bus address, command code and data are placed on the PCI bus; The PCI register read / write timing processing module of the transmission engine module receives the register read / write command, parses the read / write address and write data, and transmits them to the address decoding module; the address decoding module determines whether the receiver is the user function module in the register access module or the DMA data transmission timing processing module in the transmission engine module according to the read / write address, and generates the corresponding enable signal accordingly; The address decoding module transmits the read-write address, write data and enable signal to the register access module, and the register access module stores and identifies the read-write address and enable signal; if the external CPU sends a register write command to the transmission engine module, the write data will be transmitted to the user function module or the DMA data transmission timing processing module accordingly and used as the corresponding control signal. If it is a register read command, the feedback data of the control signal corresponding to the user function module will be transmitted via the register access module to the address decoding module and then to the PCI register read-write timing processing module of the transmission engine module, and then placed on the PCI bus by the external PCI device for reading by the host computer.

[0011] It also includes: the address decoding module uses the highest 2 bits in the address bus to perform decoding operations; when the highest 2 bits in the address bus = 2'b00, the access address of the address decoding module is mapped to the DMA data transmission timing processing module in the transmission engine module; otherwise, the access address of the address decoding module is mapped to the user function module in the register access module.

[0012] Among them, if the receiving party is a user function module, it is necessary to read back the processing status of the user function module, and the processing status is returned to the external CPU via the register access module, the transmission engine module and the PCI bus in sequence; if the receiving party is a DMA data transmission timing processing module, then the external PCI device applies for the PCI bus, and the external PCI device controls the main control signal of the external PCI device to be valid according to the timing requirements, and places the PCI bus address, command code and data on the PCI bus, and starts data transmission until the external PCI device and the external CPU complete the data interaction.

[0013] It also includes: if the data interaction direction is from an external PCI device to an external CPU, the input FIFO obtains the data cache from the user module and transmits it to the external CPU via the transmission engine module and the PCI bus in sequence; if the data interaction direction is from an external CPU to an external PCI device, the data of the external CPU is transmitted to the output FIFO cache via the PCI bus and the transmission engine module in sequence and then transmitted to the user module.

[0014] The technical effects of the present invention are: The present invention does not rely on any IP core developed by a dedicated manufacturer or an interface chip produced by a third-party manufacturer, and can adapt to bus requirements of different speeds under a PCI 33M clock, with a transmission rate of up to 80M / s. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a module connection diagram of the PCI interface module of the present invention. DETAILED DESCRIPTION

[0016] Example 1 A PCI interface module comprises a transmission engine module and a configuration management module, an address decoding module, a register access module and a FIFO respectively connected to the transmission engine module; further comprises a reset management module, the reset management module is respectively connected to the configuration management module, the address decoding module, the register access module and the transmission engine module; the transmission engine module is also connected to an external PCI bus and then to an external PCI device; the address decoding module is also connected to the register access module; the FIFO comprises an input FIFO and an output FIFO; the input FIFO and the output FIFO are both connected to the transmission engine module; The transmission engine module includes a PCI configuration space timing processing module, a PCI register read and write timing processing module and a DMA data transmission timing processing module; the PCI configuration space timing processing module is connected to the configuration management module, the PCI register read and write timing processing module is connected to the address decoding module, and one end of the DMA data transmission timing processing module is connected to the register access module and the other end is connected to the FIFO; When the transmission timing of the PCI register read / write timing processing module is the DWORD timing of PCI memory writing, after transmitting a DWORD size of data, the PCI bus needs to be re-applied after the PCI bus is released. During this period, the PCI bus does not perform any other processing until the external PCI device and the external CPU complete the data interaction; When the transmission timing of the DMA data transmission timing processing module is the multi-byte timing of PCI memory writing, three timings of PCI retry, DisConnect without data terminate or target abort are introduced and processed in coordination; when an interruption occurs between the PCI bus and the external PCI device, the external PCI device needs to re-apply for the PCI bus to continue transmission until the data interaction between the external PCI device and the external CPU is completed.

[0017] The language of the PCI interface module is Verilog.

[0018] Among them, the clock signal and reset signal of the reset management module come from the external pxi backplane 33m clock and pci reset, which serve as the main clock and power-on reset of each module of the pci interface module.

[0019] The configuration management module is used to define and implement various functional registers in the configuration space, and use the transmission engine module to parse the configuration space read and write addresses and read and write enables to implement the power-on initialization configuration of each configuration space on the PCI bus; the configuration space of the PCI bus is 256 bytes; in the technical solution, the configuration space is simplified, and only the main configuration registers are configured, and other registers are not processed; for example, only the Vendor ID, Device ID, Command, Status, Revision ID, Class Code, HeaderType, Base Address, Interrupt Line and Interrupt Pin and other related registers need to be configured. The functions of these registers include identifying the device ID number, device control, device status recording, marking the purpose of the PCI device, single / multi-function device selection, obtaining the PCI address to access the device, and interrupt related signals.

[0020] Among them, the register access module implements write latching and read acquisition of relevant control signals according to the read / write addresses and read / write data sent by the address decoding module, and returns the current operation status to the transmission engine module.

[0021] Among them, the address decoding module determines whether the address it accesses is for the DMA data transmission module in the transmission engine module or the user function module in the register access module according to the read and write address parsed by the transmission engine module, and generates a corresponding enable signal accordingly.

[0022] The specific implementation process of this embodiment is as follows: Power-on reset is performed through the reset management module; The external CPU sends the configuration space read and write commands, which are transmitted to the configuration management module through the PCI configuration space timing processing module of the transmission engine module. The configuration management module implements the configuration of each configuration space on the PCI bus. The external CPU sends register read and write commands to the address decoding module through the PCI register read and write timing processing module of the transmission engine module. The address decoding module determines whether the receiver is the user function module in the register access module or the DMA data transmission timing processing module in the transmission engine module, and sends the register read and write commands to the receiver accordingly, and reads back the processing status of the receiver. If the DMA data transmission timing processing module in the transmission engine module receives the register read and write command, the external PCI device applies for the PCI bus, that is, data transmission is performed until the external PCI device and the external CPU complete the data exchange.

[0023] Example 2 On the basis of Example 1, it also includes: The specific process of implementing the configuration of each configuration space on the PCI bus is as follows: the external CPU transmits and issues a configuration space read and write command to the PCI configuration space timing processing module of the transmission engine module, the configuration space read and write command includes a 16bite-2G address space applied for by the external PCI device to the external CPU; the transmission engine module receives the configuration space read and write command, the PCI configuration space timing processing module parses the configuration space read and write address, read and write enable and configuration data and transmits them to the configuration management module, and the configuration management module implements the configuration of each configuration space on the PCI bus through the transmission engine module.

[0024] Example 3 On the basis of Example 2, the invention further includes: The external CPU sends register read and write commands to the PCI register read and write timing processing module of the transmission engine module, using the DWORD timing of PCI memory writing and PCI memory reading. The external CPU controls the main control signal of the external CPU to be effective according to the timing requirements. When it is a register write command, the PCI bus address, command code and data are placed on the PCI bus. When it is a register read command, the PCI bus address, command code and data are placed on the PCI bus. The PCI register read / write timing processing module of the transmission engine module receives the register read / write command, parses the read / write address and write data, and transmits them to the address decoding module; the address decoding module determines whether the receiver is the user function module in the register access module or the DMA data transmission timing processing module in the transmission engine module according to the read / write address, and generates the corresponding enable signal accordingly; The address decoding module transmits the read-write address, write data and enable signal to the register access module, and the register access module stores and identifies the read-write address and enable signal; if the external CPU sends a register write command to the transmission engine module, the write data will be transmitted to the user function module or the DMA data transmission timing processing module accordingly and used as the corresponding control signal. If it is a register read command, the feedback data of the control signal corresponding to the user function module will be transmitted via the register access module to the address decoding module and then to the PCI register read-write timing processing module of the transmission engine module, and then placed on the PCI bus by the external PCI device for reading by the host computer.

[0025] Example 4 On the basis of Example 3, the invention further includes: The address decoding module uses the highest 2 bits in the address bus for decoding operations; when the highest 2 bits in the address bus = 2'b00, the access address of the address decoding module is mapped to the DMA data transmission timing processing module in the transmission engine module; otherwise, the access address of the address decoding module is mapped to the user function module in the register access module.

[0026] If the receiving party is a user function module, it is necessary to read back the processing status of the user function module, and the processing status is returned to the external CPU via the register access module, the transmission engine module and the PCI bus in sequence; If the receiving party is a DMA data transmission timing processing module, the external PCI device then applies for the PCI bus, the external PCI device controls the main control signal of the external PCI device to be valid according to the timing requirements, and places the PCI bus address, command code and data on the PCI bus, and starts data transmission until the external PCI device and the external CPU complete data interaction.

[0027] For example: the external PCI device selects 4M address space; For this, the address decoding module uses the 22-bit address bus [21: 0] to access the address space of the external PCI device, and uses [21:20] for decoding operations: when [21:20]=2'b00, the address decoding module access address is mapped to the DMA data transmission timing processing module in the transmission engine module; when [21:20]≠2'b00, the address decoding module access address is mapped to the user function module in the register access module.

[0028] Example 5 On the basis of Example 4, the invention further comprises: If the data exchange direction is from external PCI device to external CPU, the data buffer from the user module is obtained by inputting FIFO and then transmitted to the external CPU via the transmission engine module and PCI bus in sequence; If the data exchange direction is from the external CPU to the external PCI device, the data of the external CPU is sequentially transmitted to the output FIFO buffer via the PCI bus and the transmission engine module and then transmitted to the user module.

[0029] Specific experimental case - taking the external PCI device to transmit data to the external CPU as an example (write) (1) Initial preparation: Power-on reset is performed through the reset management module; The specific process of implementing the configuration of each configuration space on the PCI bus is as follows: the external CPU transmits and issues a configuration space read and write command to the PCI configuration space timing processing module of the transmission engine module, and the configuration space read and write command includes a 4M address space requested by the external PCI device to the external CPU; the transmission engine module receives the configuration space read and write command, the PCI configuration space timing processing module parses the configuration space read and write address, read and write enable and configuration data and transmits them to the configuration management module, and the configuration management module implements the configuration of each configuration space on the PCI bus through the transmission engine module; (2) Determine the recipient: The external CPU sends register read and write commands to the PCI register read and write timing processing module of the transmission engine module; The PCI register read / write timing processing module of the transmission engine module receives the register read / write command, parses the read / write address and write data, and transmits them to the address decoding module; The address decoding module uses the 22-bit address bus [21: 0] to access the address space of the external PCI device, and uses [21:20] for decoding operations: when [21:20] = 2'b00, the address decoding module access address is mapped to the DMA data transmission timing processing module in the transmission engine module; (3) Data transmission: The address decoding module transmits the read / write address, write data and enable signal to the register access module, which stores and identifies the read / write address and enable signal, and transmits the write data to the DMA data transmission timing processing module as the corresponding control signal; The DMA data transmission timing processing module receives the control signal. Then the external PCI device applies for the PCI bus. The external PCI device controls the main control signal of the external PCI device to be valid according to the timing requirements, and places the PCI bus address, command code and data on the PCI bus to start data transmission until the data interaction between the external PCI device and the external CPU is completed.

[0030] If the transmission mode of the DMA data transmission timing processing module is the DWORD timing of PCI memory writing, after transmitting a DWORD size of data, the PCI bus must be re-applied after releasing the PCI bus. During this period, the PCI bus does not perform any other processing until the external PCI device and the external CPU complete the data exchange.

[0031] If the transmission mode is multi-byte timing of PCI memory writing, it is found in practice that during the transmission of multi-byte timing, the PCI slave device will start the PCI bus to disconnect the PCI slave device due to factors such as the PCI bus being extremely busy, the PCI bus arbitration priority or the address reaching the memory boundary. Therefore, this process will introduce and should cooperate with the processing of three timings: PCI retry, DisConnect without data terminate, or targetabort. In case of these situations, the PCI master device will disconnect the PCI bus in time and reconnect after 1-2 clocks until all data are transmitted to the external CPU.

[0032] If the external CPU transmits data to the external PCI device, the external CPU places the PCI bus address, command code and data on the PCI bus to start data transmission until the external CPU completes the data transmission to the external PCI device.

Claims

1. A PCI interface module, characterized in that: It includes a transmission engine module and a configuration management module, an address decoding module, a register access module and a fifo respectively connected to the transmission engine module; it also includes a reset management module, the reset management module is respectively connected to the configuration management module, the address decoding module, the register access module and the transmission engine module; the transmission engine module is also connected to an external PCI bus and then connected to an external PCI device; the address decoding module is also connected to the register access module; the fifo includes an input fifo and an output fifo; the input fifo and the output fifo are both connected to the transmission engine module; The transmission engine module includes a PCI configuration space timing processing module, a PCI register read and write timing processing module and a DMA data transmission timing processing module; the PCI configuration space timing processing module is connected to the configuration management module, the PCI register read and write timing processing module is connected to the address decoding module, and one end of the DMA data transmission timing processing module is connected to the register access module and the other end is connected to the FIFO.

2. The PCI interface module according to claim 1, characterized in that: Also includes: When the transmission timing of the PCI register read and write timing processing module is the DWORD timing of PCI memory writing, after transmitting a DWORD size of data, the PCI bus needs to be re-applied after releasing the PCI bus. During this period, the PCI bus does not perform any other processing until the external PCI device and the external CPU complete the data interaction.

3. The PCI interface module according to claim 2, characterized in that: Also includes: When the transmission timing of the DMA data transmission timing processing module is the multi-byte timing of PCI memory writing, three timings of PCI retry, DisConnect without data terminate or target abort are introduced and processed in coordination; when an interruption occurs between the PCI bus and the external PCI device, the external PCI device needs to re-apply for the PCI bus to continue transmission until the data interaction between the external PCI device and the external CPU is completed.

4. A PCI bus control data transmission method, characterized in that: Using the PCI interface module as described in claim 3, the specific method is as follows: Power-on reset is performed through the reset management module; The external CPU sends the configuration space read and write commands, which are transmitted to the configuration management module through the PCI configuration space timing processing module of the transmission engine module. The configuration management module implements the configuration of each configuration space on the PCI bus. The external CPU sends register read and write commands to the address decoding module through the PCI register read and write timing processing module of the transmission engine module. The address decoding module determines whether the receiver is the user function module in the register access module or the DMA data transmission timing processing module in the transmission engine module, and sends the register read and write commands to the receiver accordingly, and reads back the processing status of the receiver. If the DMA data transmission timing processing module in the transmission engine module receives the register read and write command, the external PCI device applies for the PCI bus, that is, data transmission is performed until the external PCI device and the external CPU complete the data exchange.

5. The PCI bus controlled data transmission method according to claim 4, characterized in that: The specific process of implementing the configuration of each configuration space on the PCI bus is as follows: the external CPU transmits and issues a configuration space read and write command to the PCI configuration space timing processing module of the transmission engine module, the configuration space read and write command includes a 16bite-2G address space applied for by the external PCI device to the external CPU; the transmission engine module receives the configuration space read and write command, the PCI configuration space timing processing module parses the configuration space read and write address, read and write enable and configuration data and transmits them to the configuration management module, and the configuration management module implements the configuration of each configuration space on the PCI bus through the transmission engine module.

6. The PCI bus controlled data transmission method according to claim 5, characterized in that: Also includes: The external CPU sends register read and write commands to the PCI register read and write timing processing module of the transmission engine module, using the DWORD timing of PCI memory writing and PCI memory reading. The external CPU controls the main control signal of the external CPU to be effective according to the timing requirements. When it is a register write command, the PCI bus address, command code and data are placed on the PCI bus. When it is a register read command, the PCI bus address, command code and data are placed on the PCI bus. The PCI register read and write timing processing module of the transmission engine module receives the register read and write commands, parses the read and write addresses and write data, and transmits them to the address decoding module; The address decoding module determines whether the receiver is the user function module in the register access module or the DMA data transmission timing processing module in the transmission engine module according to the read / write address, and generates a corresponding enable signal accordingly; The address decoding module transmits the read-write address, write data and enable signal to the register access module, and the register access module stores and identifies the read-write address and enable signal; if the external CPU sends a register write command to the transmission engine module, the write data will be transmitted to the user function module or the DMA data transmission timing processing module accordingly and used as the corresponding control signal. If it is a register read command, the feedback data of the control signal corresponding to the user function module will be transmitted via the register access module to the address decoding module and then to the PCI register read-write timing processing module of the transmission engine module, and then placed on the PCI bus by the external PCI device for reading by the host computer.

7. The PCI bus controlled data transmission method according to claim 4, characterized in that: Also includes: The address decoding module uses the highest 2 bits in the address bus to perform decoding operations; when the highest 2 bits in the address bus = 2'b00, the access address of the address decoding module is mapped to the DMA data transmission timing processing module in the transmission engine module; Otherwise, the access address of the address decoding module is mapped to the user function module in the register access module.

8. The PCI bus controlled data transmission method according to claim 5, characterized in that: If the receiving party is a user function module, it is necessary to read back the processing status of the user function module, and the processing status is returned to the external CPU via the register access module, the transmission engine module and the PCI bus in sequence; If the receiving party is a DMA data transmission timing processing module, the external PCI device then applies for the PCI bus, the external PCI device controls the main control signal of the external PCI device to be valid according to the timing requirements, and places the PCI bus address, command code and data on the PCI bus, and starts data transmission until the external PCI device and the external CPU complete data interaction.

9. The PCI bus controlled data transmission method according to claim 6, characterized in that: Also includes: If the data exchange direction is from external PCI device to external CPU, the data buffer from the user module is obtained by inputting FIFO and then transmitted to the external CPU via the transmission engine module and PCI bus in sequence; If the data exchange direction is from the external CPU to the external PCI device, the data of the external CPU is sequentially transmitted to the output FIFO buffer via the PCI bus and the transmission engine module and then transmitted to the user module.

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