Time sequence sign-off method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention discloses a time sequence sign-off method and device, electronic equipment and a storage medium, relates to the technical field of integrated circuits, and can perform effective time sequence sign-off on a three-dimensional integrated chip. The method comprises the steps that an alternative sign-off strategy set of a chip to be signed off is generated, the chip to be signed off is obtained through three-dimensional integration of at least two crystal grains, the alternative sign-off strategy set comprises at least one alternative sign-off strategy, and each alternative sign-off strategy comprises a time sequence standard deviation calculation model adopted by each crystal grain in the chip to be signed off; for each alternative sign-off strategy, determining a corresponding chip sign-off scene number and a corresponding chip standard deviation under the alternative sign-off strategy according to a time sequence standard deviation calculation model adopted by each crystal grain in the alternative sign-off strategy; selecting one alternative sign-off strategy from the alternative sign-off strategy set as a target strategy according to the chip sign-off scene number corresponding to each alternative sign-off strategy and the chip standard deviation corresponding to each alternative sign-off strategy; and performing time sequence sign-off on the to-be-sign-off chip according to the target strategy.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a timing sign-off method and device, electronic equipment, and storage medium. Background Art

[0002] Before a chip is commissioned to be processed by a wafer fab, it needs to undergo a timing sign-off. Timing sign-off refers to checking the timing of the chip design to ensure that the chip can work properly under different PVT (Process Voltage Temperature) scenarios.

[0003] For 2D (two-dimensional) chips, there are already relatively mature standards for how to perform timing signoff. However, for 2.5D, 3D and other three-dimensional integrated chips, since the chip is three-dimensionally integrated from at least two dies, there is no clear signoff standard for how to perform timing signoff on such chips. Summary of the invention

[0004] In view of this, the embodiments of the present invention provide a timing sign-off method and apparatus, an electronic device, and a storage medium, which can effectively perform timing sign-off on a three-dimensional integrated chip while ensuring the time required for timing sign-off and the timing margin.

[0005] In a first aspect, an embodiment of the present invention provides a timing sign-off method, comprising: generating a set of candidate sign-off strategies for a chip to be signed off, the chip to be signed off being obtained by three-dimensional integration of at least two crystal grains, the set of candidate sign-off strategies comprising at least one candidate sign-off strategy, wherein each of the candidate sign-off strategies comprises a timing standard deviation calculation model adopted by each crystal grain in the chip to be signed off; the timing standard deviation calculation model adopted by each crystal grain is selected from the optional models corresponding to the crystal grain, there is at least one multi-model crystal grain in the chip to be signed off, and the number of the optional models corresponding to the multi-model crystal grain is greater than 1; for each of the candidate sign-off strategies, According to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy, the number of chip sign-off scenarios and the corresponding chip standard deviation under the alternative sign-off strategy are determined, wherein the number of chip sign-off scenarios is the number of sign-off scenarios that need to be processed when performing timing sign-off on the chip to be signed off; the chip standard deviation is the standard deviation of the timing parameters of the chip to be signed off; according to the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each of the alternative sign-off strategies, one of the alternative sign-off strategies is selected from the set of alternative sign-off strategies as the target strategy; and timing sign-off is performed on the chip to be signed off according to the target strategy.

[0006] In one embodiment, generating a set of alternative sign-off strategies for the chip to be signed off includes: respectively obtaining the number of grains included in the chip to be signed off and the optional models corresponding to the timing standard deviation calculation model of each grain; determining the number of alternative sign-off strategies included in the set of alternative sign-off strategies to be generated, and the timing standard deviation calculation model adopted by each grain under each alternative sign-off strategy in the set of alternative sign-off strategies to be generated according to the number of grains included in the chip to be signed off and the optional models corresponding to the timing standard deviation calculation model of each grain; generating the set of alternative sign-off strategies according to the number of alternative sign-off strategies included in the set of alternative sign-off strategies to be generated, and the timing standard deviation calculation model adopted by each grain under each alternative sign-off strategy in the set of alternative sign-off strategies to be generated.

[0007] In one implementation, the number of candidate sign-off strategies included in the candidate sign-off strategy set is equal to the product of the number of selectable models corresponding to the timing standard deviation calculation model of each die in the chip to be signed off multiplied by each other.

[0008] In one embodiment, the optional models corresponding to the multi-model grain include: a first model and a second model, wherein the first model includes calculating the total standard deviation of the timing parameters of the grain, and the second model includes respectively calculating the global standard deviation and the local standard deviation of the timing parameters of the grain.

[0009] In one embodiment, for each of the alternative sign-off strategies, according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy, determining the number of chip sign-off scenarios and the corresponding chip standard deviation under the alternative sign-off strategy includes: determining the grain standard deviation of each of the grains under the alternative sign-off strategy according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy; determining the grain standard deviation of each of the grains according to a preset functional relationship between the grain standard deviation and the chip standard deviation, and determining the number of chip standard deviations of each of the grains according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy; ... The chip standard deviation corresponding to the alternative sign-off strategy is determined by the grain standard deviation; for each of the grains, if the timing standard deviation calculation model adopted by the grain is the first model, the number of grain sign-off scenarios corresponding to the grain is determined to be the first number of scenarios; if the timing standard deviation calculation model adopted by the grain is the second model, the number of grain sign-off scenarios corresponding to the grain is determined to be the second number of scenarios; the number of grain sign-off scenarios corresponding to each grain in the chip to be signed off is multiplied to obtain the number of chip sign-off scenarios corresponding to the alternative sign-off strategy.

[0010] In one embodiment, the determining, according to the timing standard deviation calculation model adopted by each of the grains in each of the alternative sign-off strategies, the grain standard deviation of each of the grains under the alternative sign-off strategy includes: determining, under each of the alternative sign-off strategies, the first grain adopting the first model and the second grain adopting the second model in the chip to be signed off; for each of the alternative sign-off strategies, determining, according to the first model, the total standard deviation corresponding to each of the first grains, and determining, according to the second model, the global standard deviation and the local standard deviation corresponding to each of the second grains; determining, according to the grain standard deviation and the chip The preset functional relationship between the standard deviations and the grain standard deviations of each of the grains, determining the chip standard deviation corresponding to the alternative sign-off strategy includes: for each of the alternative sign-off strategies, determining the first standard deviation of the chip to be signed off according to the sum of the global standard deviations corresponding to the second grains, and determining the second standard deviation of the chip to be signed off according to the sum of the squares of the total standard deviations corresponding to the first grains and the sum of the squares of the local standard deviations corresponding to the second grains; determining the chip standard deviation corresponding to the chip to be signed off under the alternative sign-off strategy according to the first standard deviation and the second standard deviation.

[0011] In one embodiment, determining the first standard deviation of the chip to be signed based on the sum of the global standard deviations corresponding to each of the second grains includes: the first standard deviation is equal to each of the global standard deviations multiplied by the first coefficient corresponding to each, and the products are summed, wherein the first coefficient is a multiple of the global standard deviation corresponding to each grain specified in the sign-off condition of the chip to be signed, and the multiple of the global standard deviation is used to limit the fluctuation range of the global deviation of each grain allowed when the chip to be signed is passed.

[0012] In one embodiment, determining the second standard deviation of the chip to be signed off based on the sum of the squares of the total standard deviations corresponding to each of the first grains and the sum of the squares of the local standard deviations corresponding to each of the second grains includes: the second standard deviation is equal to the sum of the squares of the products of each of the total standard deviations and the second coefficients corresponding to each of the two grains, plus the sum of the squares of the products of each of the local standard deviations and the second coefficients corresponding to each of the two grains, and taking the arithmetic square root of the sum obtained, wherein the second coefficient is a multiple of the local standard deviation or the total standard deviation corresponding to each grain specified in the sign-off pass condition of the chip to be signed off, and the local standard deviation or the multiple of the total standard deviation is used to limit the fluctuation range of the local deviation or the total deviation of each grain allowed when the chip to be signed off is passed.

[0013] In one embodiment, determining the second standard deviation of the chip to be signed off based on the sum of the squares of the total standard deviation corresponding to each of the first grains and the sum of the squares of the local standard deviations corresponding to each of the second grains includes: determining the number of register levels included in the target path to be signed off in each of the second grains; when the number of register levels is greater than a preset threshold, adjusting the local standard deviation corresponding to the second grain where the target path is located to obtain a local adjusted standard deviation; determining the second standard deviation of the target path in the chip to be signed off based on the sum of the squares of the total standard deviation corresponding to each of the first grains and the sum of the squares of the local adjusted standard deviations corresponding to each of the second grains.

[0014] In one implementation, the first number of scenes includes 1, and the second number of scenes includes 3.

[0015] In one embodiment, selecting one of the alternative sign-off strategies as the target strategy from the set of alternative sign-off strategies according to the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each of the alternative sign-off strategies includes: selecting one of the alternative sign-off strategies as the target strategy from the set of alternative sign-off strategies according to the sign-off requirement of the chip to be signed-off, the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each of the alternative sign-off strategies, wherein the sign-off requirement includes at least one of the following: a requirement for a design margin of the chip to be signed-off, a requirement for a sign-off progress of the chip to be signed-off, the requirement for the design margin of the chip to be signed-off is related to the chip standard deviation, and the requirement for the sign-off progress of the chip to be signed-off is related to the number of chip sign-off scenarios.

[0016] In one embodiment, after the chip to be signed off is timing signed off according to the target strategy, the method further includes: testing the three-dimensional integrated chip manufactured after the timing sign-off; adjusting the functional relationship between the chip standard deviation and the grain standard deviation of each of the grains according to the test results, wherein the grain standard deviation of each of the grains is related to the timing standard deviation calculation model adopted by the grain.

[0017] In a second aspect, an embodiment of the present invention further provides a timing sign-off device, comprising: a generating unit, configured to generate a set of alternative sign-off strategies for a chip to be signed off, wherein the chip to be signed off is obtained by three-dimensional integration of at least two crystal grains, and the set of alternative sign-off strategies includes at least one alternative sign-off strategy, wherein each of the alternative sign-off strategies includes a timing standard deviation calculation model adopted by each crystal grain in the chip to be signed off; the timing standard deviation calculation model adopted by each crystal grain is selected from the optional models corresponding to the crystal grain, and there is at least one multi-model crystal grain in the chip to be signed off, and the number of the optional models corresponding to the multi-model crystal grain is greater than 1; a determining unit, configured to determine, for each of the alternative sign-off strategies, , according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy, determine the number of chip sign-off scenarios and the corresponding chip standard deviation under the alternative sign-off strategy, wherein the number of chip sign-off scenarios is the number of sign-off scenarios that need to be processed when performing timing sign-off on the chip to be signed; the chip standard deviation is the standard deviation of the timing parameters of the chip to be signed; a selection unit is used to select one of the alternative sign-off strategies from the set of alternative sign-off strategies as a target strategy according to the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each of the alternative sign-off strategies; a sign-off unit is used to perform timing sign-off on the chip to be signed according to the target strategy.

[0018] In one embodiment, the generation unit includes: an acquisition module, which is used to respectively acquire the number of grains included in the chip to be signed off and the various optional models corresponding to the timing standard deviation calculation model of each grain; a first determination module, which is used to determine the number of alternative sign-off strategies included in the set of alternative sign-off strategies to be generated, and the timing standard deviation calculation model adopted by each grain under each alternative sign-off strategy in the set of alternative sign-off strategies to be generated, according to the number of grains included in the chip to be signed off and the various optional models corresponding to the timing standard deviation calculation model of each grain; a generation module, which is used to generate the set of alternative sign-off strategies according to the number of alternative sign-off strategies included in the set of alternative sign-off strategies to be generated, and the timing standard deviation calculation model adopted by each grain under each alternative sign-off strategy in the set of alternative sign-off strategies to be generated.

[0019] In one implementation, the number of candidate sign-off strategies included in the candidate sign-off strategy set is equal to the product of the number of selectable models corresponding to the timing standard deviation calculation model of each die in the chip to be signed off multiplied by each other.

[0020] In one embodiment, the optional models corresponding to the multi-model grain include: a first model and a second model, wherein the first model includes calculating the total standard deviation of the timing parameters of the grain, and the second model includes respectively calculating the global standard deviation and the local standard deviation of the timing parameters of the grain.

[0021] In one embodiment, the determination unit includes: a second determination module, which is used to determine the grain standard deviation of each grain under each alternative sign-off strategy according to the timing standard deviation calculation model adopted by each grain in the alternative sign-off strategy; a third determination module, which is used to determine the chip standard deviation corresponding to the alternative sign-off strategy according to a preset functional relationship between the grain standard deviation and the chip standard deviation, and the grain standard deviation of each grain; a fourth determination module, which is used to determine, for each grain among the grains, if the timing standard deviation calculation model adopted by the grain is the first model, the number of grain sign-off scenarios corresponding to the grain is the first scenario number, and if the timing standard deviation calculation model adopted by the grain is the second model, the number of grain sign-off scenarios corresponding to the grain is the second scenario number; a multiplication module, which is used to multiply the grain sign-off scenario numbers corresponding to each grain in the chip to be signed off, to obtain the chip sign-off scenario number corresponding to the alternative sign-off strategy.

[0022] In one embodiment, the second determination module includes: a first determination submodule, used to determine, under each of the alternative sign-off strategies, first grains using the first model and second grains using the second model in the chip to be signed off; a second determination submodule, used to determine, for each of the alternative sign-off strategies, the total standard deviation corresponding to each of the first grains according to the first model, and to determine, according to the second model, the global standard deviation and the local standard deviation corresponding to each of the second grains; the third determination module includes: a fourth determination submodule, used to determine, for each of the alternative sign-off strategies, the first standard deviation of the chip to be signed off according to the sum of the global standard deviations corresponding to the second grains, and to determine the second standard deviation of the chip to be signed off according to the sum of the squares of the total standard deviations corresponding to the first grains and the sum of the squares of the local standard deviations corresponding to the second grains; and a fifth determination submodule, used to determine, according to the first standard deviation and the second standard deviation, the chip standard deviation corresponding to the chip to be signed off under the alternative sign-off strategy.

[0023] In one embodiment, the fourth determination submodule is specifically used to: determine that the first standard deviation is equal to the multiplication of each global standard deviation and the first coefficient corresponding to each, and then sum the products, wherein the first coefficient is a multiple of the global standard deviation corresponding to each grain specified in the sign-off pass conditions of the chip to be signed, and the multiple of the global standard deviation is used to limit the fluctuation range of the global deviation of each grain allowed when the chip to be signed is passed.

[0024] In one embodiment, the fourth determination submodule is specifically used to: determine that the second standard deviation is equal to the sum of the squares of the products of each of the total standard deviations and the corresponding second coefficients, plus the sum of the squares of the products of each of the local standard deviations and the corresponding second coefficients, and calculate the arithmetic square root of the sum, wherein the second coefficient is a multiple of the local standard deviation or the total standard deviation corresponding to each grain specified in the sign-off pass conditions of the chip to be signed, and the local standard deviation or the multiple of the total standard deviation is used to limit the fluctuation range of the local deviation or the total deviation of each grain allowed when the chip to be signed is passed.

[0025] In one embodiment, the fourth determination submodule is specifically used to: determine the number of register levels included in the target path to be signed off in each of the second grains; when the number of register levels is greater than a preset threshold, adjust the local standard deviation corresponding to the second grain where the target path is located to obtain a local adjusted standard deviation; determine the second standard deviation of the target path in the chip to be signed off based on the sum of the squares of the total standard deviation corresponding to each of the first grains and the sum of the squares of the local adjusted standard deviations corresponding to each of the second grains.

[0026] In one implementation, the first number of scenes includes 1, and the second number of scenes includes 3.

[0027] In one embodiment, the selection unit is specifically used to select one of the alternative sign-off strategies from the set of alternative sign-off strategies as the target strategy based on the sign-off requirement of the chip to be signed off, the number of chip sign-off scenarios corresponding to each of the alternative sign-off strategies, and the corresponding chip standard deviation, wherein the sign-off requirement includes at least one of the following: a requirement for the design margin of the chip to be signed off, a requirement for the sign-off progress of the chip to be signed off, the requirement for the design margin of the chip to be signed off is related to the chip standard deviation, and the requirement for the sign-off progress of the chip to be signed off is related to the number of chip sign-off scenarios.

[0028] In one embodiment, the device also includes: a testing unit, which is used to test the three-dimensional integrated chip manufactured after the timing sign-off is performed on the chip to be signed off according to the target strategy; an adjustment unit, which is used to adjust the functional relationship between the chip standard deviation and the grain standard deviation of each of the grains according to the test results of the testing unit, wherein the grain standard deviation of each of the grains is related to the timing standard deviation calculation model adopted by the grain.

[0029] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement any one of the timing sign-off methods provided in the embodiments of the present invention.

[0030] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement any timing sign-off method provided by an embodiment of the present invention.

[0031] The timing sign-off method and device, electronic device, and storage medium provided by the embodiments of the present invention can generate a set of alternative sign-off strategies for a chip to be signed off, wherein the set of alternative sign-off strategies includes at least one alternative sign-off strategy. For each of the alternative sign-off strategies, the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to the alternative sign-off strategy are determined according to the timing standard deviation calculation model adopted by each grain in the alternative sign-off strategy. Then, according to the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each alternative sign-off strategy, one of the alternative sign-off strategies is selected from the set of alternative sign-off strategies as the target strategy, and the timing sign-off of the chip to be signed off is performed according to the target strategy. Since the chip to be signed off is obtained by integrating at least two grains, a model combination corresponding to such a grain combination of the chip to be signed off, i.e., an alternative sign-off strategy, can be determined according to the timing standard deviation calculation model adopted by each grain in the chip to be signed off. Furthermore, since the timing standard deviation calculation model adopted by each grain is selected from the optional models corresponding to the grain, and there is at least one multi-model grain in the chip to be signed, and the number of the optional models corresponding to the multi-model grain is greater than 1, due to the existence of the multi-model grain and the timing standard deviation calculation models of each grain can be arranged and combined, it is possible to form multiple alternative sign-off strategies for the chip to be signed, thereby forming an alternative sign-off strategy set, so as to provide a basis for the selection of the target strategy. Furthermore, the number of chip signoff scenarios and the corresponding chip standard deviation under each alternative signoff strategy can be determined based on the timing standard deviation calculation model adopted by each die in the alternative signoff strategy. The number of chip signoff scenarios will involve the time required for signoff, and the chip standard deviation will involve the chip timing margin allowed for signoff. Therefore, the number of chip signoff scenarios and the chip standard deviation are used as considerations for the chip signoff strategy. A suitable target strategy is selected from the set of alternative signoff strategies. The target strategy is used to signoff the three-dimensional integrated chip. This allows the three-dimensional integrated chip to be effectively signed off on timing while ensuring the time required for timing signoff and the timing margin. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A flow chart of a timing sign-off method provided by an embodiment of the present invention; Figure 2 A detailed flow chart of a timing sign-off method provided by an embodiment of the present invention; Figure 3 A schematic diagram of the structure of a timing sign-off device provided by an embodiment of the present invention; Figure 4 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] In a first aspect, an embodiment of the present invention provides a timing sign-off method, which can effectively perform timing sign-off on a three-dimensional integrated chip while ensuring the time required for timing sign-off and the timing margin.

[0037] like Figure 1 As shown, an embodiment of the present invention provides a timing sign-off method, comprising: S11, generating a set of candidate sign-off strategies for a chip to be signed off, wherein the chip to be signed off is obtained by three-dimensional integration of at least two dies, and the set of candidate sign-off strategies includes at least one candidate sign-off strategy, wherein each of the candidate sign-off strategies includes a timing standard deviation calculation model adopted by each dies in the chip to be signed off, and the timing standard deviation calculation model adopted by each dies is selected from the optional models corresponding to the dies, and there is at least one multi-model dies in the chip to be signed off, and the number of the optional models corresponding to the multi-model dies is greater than 1; In an embodiment of the present invention, the chip to be signed is a chip that needs to be signed for timing. The chip to be signed is obtained by three-dimensional integration of at least two crystals, that is, the chip to be signed may include at least two crystals, and the at least two crystals may be integrated together in a three-dimensional manner. Here, three-dimensional integration may include integration in non-planar manners such as 2.5D, 3D, and 3.5D. For example, three-dimensional integration can be achieved through silicon vias (TSV), interposers, hybrid bonding, and the like.

[0038] The candidate sign-off strategy set is a set formed by multiple different candidate sign-off strategies, and the candidate sign-off strategy is an optional strategy for how to perform timing sign-off on the chip to be signed. Each candidate sign-off strategy can include a timing standard deviation calculation model used by each die in the chip to be signed. In one embodiment of the present invention, various candidate sign-off strategies for the chip to be signed can be exhaustively enumerated to obtain a candidate sign-off strategy set.

[0039] The timing standard deviation calculation model used by each die may refer to how the standard deviation of each die is determined. Here, the standard deviation of each die may include the standard deviation of any timing parameter in the target path that needs to be signed off on the timing in the die, such as the standard deviation of the arrival time, the standard deviation of the hold time, etc. Using different timing standard deviation calculation models, the calculated standard deviation is also different. For example, in one example, the calculation model of the standard deviation of a die may be to determine the standard deviation of a die with respect to a timing parameter of the die by calculating the total standard deviation of the die, and in another example, the calculation model of the standard deviation of a die may be to determine the standard deviation of a die with respect to a timing parameter of the die by respectively calculating the global standard deviation and the local standard deviation of the die.

[0040] Since the chip to be signed off is obtained by three-dimensional integration of multiple dies, and each die has its own timing standard deviation calculation model, the alternative sign-off strategy of the chip to be signed off is related to the timing standard deviation calculation model adopted by each die in the chip to be signed off. For example, if the timing standard deviation calculation model adopted by at least one die in two alternative sign-off strategies is different, then the two alternative sign-off strategies are different. If the timing standard deviation calculation models adopted by all dies in the two alternative sign-off strategies are the same, then the two alternative sign-off strategies are the same and can be merged into one alternative sign-off strategy.

[0041] In each die of the chip to be signed off, the number of optional models corresponding to each die can be the same or different, wherein the number of optional models corresponding to a multi-model die is greater than 1. For example, in one example, the chip to be signed off includes three dies A, B, and C, wherein the number of optional models corresponding to die A is 1, the number of optional models corresponding to die B is 2, and the number of optional models corresponding to die C is also 2, then both die B and die C are multi-model die. Each optional model corresponding to a multi-model die can form an alternative sign-off strategy together with an optional model of other dies. For example, the alternative sign-off strategy R1 may include the optional model a of die A, the optional model b1 of die B, and the optional model c1 of die C; the alternative sign-off strategy R2 may include the optional model a of die A, the optional model b1 of die B, and the optional model c2 of die C; the alternative sign-off strategy R3 may include the optional model a of die A, the optional model b2 of die B, and the optional model c1 of die C; the alternative sign-off strategy R4 may include the optional model a of die A, the optional model b2 of die B, and the optional model c2 of die C. Among them, the alternative sign-off strategies R1, R2, R3, and R4 can form an alternative sign-off strategy set.

[0042] That is to say, for an alternative sign-off strategy, the timing standard deviation calculation model used by each die is determined, but the number of optional models corresponding to the timing standard deviation calculation model can be multiple.

[0043] S12, for each of the alternative sign-off strategies, according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy, determine the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to the alternative sign-off strategy, wherein the number of chip sign-off scenarios is the number of sign-off scenarios that need to be processed when performing timing sign-off on the chip to be signed; the chip standard deviation is the standard deviation of the timing parameters of the chip to be signed; In an embodiment of the present invention, the timing standard deviation calculation model used by each die in the chip to be signed off will affect the number of chip sign-off scenarios and the chip standard deviation. That is to say, if the timing standard deviation calculation model used by the die is different, the number of chip sign-off scenarios and the chip standard deviation will be different when the chip is signed off. Among them, the number of chip sign-off scenarios is the number of sign-off scenarios that need to be processed when the timing sign-off of the chip to be signed off is performed. For example, in one example, 3 sign-off scenarios need to be processed when signing off the chip to be signed off, and in another example, 9 sign-off scenarios need to be processed when signing off the chip to be signed off. The number of chip sign-off scenarios may be related to the number of process corners that each die in the chip to be signed off may be in when signing off, which will be described in detail later. The chip standard deviation is the standard deviation of the chip to be signed off. It should be noted that in an embodiment of the present invention, the chip standard deviation is different from the die standard deviation, and the die standard deviation refers to the standard deviation of each die. The chip is a three-dimensional structure formed by the integration of multiple die, so the chip standard deviation refers to the standard deviation of the entire three-dimensional structure formed by the integration of multiple die. In an embodiment of the present invention, the die standard deviation of each die under each candidate sign-off strategy can be calculated according to the aforementioned timing standard deviation calculation model, and then the chip standard deviation of the chip to be signed off under the sign-off strategy can be determined according to the die standard deviation of each die.

[0044] S13, selecting one of the candidate sign-off strategies from the candidate sign-off strategy set as a target strategy according to the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each of the candidate sign-off strategies; Because the number of chip sign-off scenarios and the chip standard deviation will be different under different alternative sign-off strategies, and the number of chip sign-off scenarios and the chip standard deviation are issues of greater concern in chip sign-off, therefore, in an embodiment of the present invention, an alternative sign-off strategy can be selected from the set of alternative sign-off strategies as the target strategy based on the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each alternative sign-off strategy.

[0045] S14, performing timing sign-off on the chip to be signed off according to the target strategy.

[0046] After obtaining the target strategy, in this step, the target strategy can be applied to perform timing signoff on the chip to be signed off.

[0047] The timing sign-off method provided by the embodiment of the present invention can generate a set of alternative sign-off strategies for a chip to be signed off, wherein the set of alternative sign-off strategies includes at least one alternative sign-off strategy. For each of the alternative sign-off strategies, the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to the alternative sign-off strategy are determined according to the timing standard deviation calculation model adopted by each grain in the alternative sign-off strategy. Then, according to the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each alternative sign-off strategy, one of the alternative sign-off strategies is selected from the set of alternative sign-off strategies as the target strategy, and the timing sign-off of the chip to be signed off is performed according to the target strategy. Since the chip to be signed off is obtained by integrating at least two grains, a model combination corresponding to such a grain combination of the chip to be signed off, i.e., an alternative sign-off strategy, can be determined according to the timing standard deviation calculation model adopted by each grain in the chip to be signed off. Furthermore, since the timing standard deviation calculation model adopted by each grain is selected from the optional models corresponding to the grain, and there is at least one multi-model grain in the chip to be signed, and the number of the optional models corresponding to the multi-model grain is greater than 1, due to the existence of the multi-model grain and the timing standard deviation calculation models of each grain can be arranged and combined, it is possible to form multiple alternative sign-off strategies for the chip to be signed, thereby forming an alternative sign-off strategy set, so as to provide a basis for the selection of the target strategy. Furthermore, the number of chip signoff scenarios and the corresponding chip standard deviation under each alternative signoff strategy can be determined based on the timing standard deviation calculation model adopted by each die in the alternative signoff strategy. The number of chip signoff scenarios will involve the time required for signoff, and the chip standard deviation will involve the chip timing margin allowed for signoff. Therefore, the number of chip signoff scenarios and the chip standard deviation are used as considerations for the chip signoff strategy. A suitable target strategy is selected from the set of alternative signoff strategies. The target strategy is used to signoff the three-dimensional integrated chip. This allows the three-dimensional integrated chip to be effectively signed off on timing while ensuring the time required for timing signoff and the timing margin.

[0048] Specifically, in one embodiment of the present invention, in step S11, each alternative sign-off strategy in the generated set of alternative sign-off strategies may include a timing standard deviation calculation model adopted by each die in the chip to be signed off. The timing standard deviation calculation model adopted by each die may be selected from the optional models corresponding to the die. Optionally, if the number of optional models corresponding to the die is 1, the optional model may be selected; if the number of optional models corresponding to the die is multiple, one of the optional models may be selected in one alternative sign-off strategy, and another optional model may be selected in another alternative sign-off strategy, and so on.

[0049] In one embodiment, step S11 of generating a set of alternative sign-off strategies for the chip to be signed off may include: respectively obtaining the number of grains included in the chip to be signed off and the respective optional models corresponding to the timing standard deviation calculation model of each grain; determining the number of the alternative sign-off strategies included in the set of alternative sign-off strategies and the timing standard deviation calculation model adopted by each grain under each alternative sign-off strategy in the set of alternative sign-off strategies according to the number of grains included in the chip to be signed off and the respective optional models corresponding to the timing standard deviation calculation model of each grain; generating the set of alternative sign-off strategies according to the number of the alternative sign-off strategies included in the set of alternative sign-off strategies and the timing standard deviation calculation model adopted by each grain under each alternative sign-off strategy in the set of alternative sign-off strategies.

[0050] In an example, the number of candidate sign-off strategies included in the candidate sign-off strategy set may be equal to the product of the number of selectable models corresponding to the timing standard deviation calculation model of each die in the chip to be signed off multiplied by each other.

[0051] For example, in one embodiment of the present invention, the number of dies included in the chip to be signed off is 3, namely, die1, die2, and die3, wherein the optional model corresponding to the timing standard deviation calculation model of die1 is ModelA, that is, the number of optional models is 1, the optional models corresponding to the timing standard deviation calculation model of die2 are ModelB1 and ModelB2, that is, the number of optional models is 2, and the optional model corresponding to the timing standard deviation calculation model of die3 is ModelC, that is, the number of optional models is 1. It can be determined that the number of alternative sign-off strategies included in the alternative sign-off strategy set is equal to 1×2×1=2, that is, the number of alternative sign-off strategies included in the alternative sign-off strategy set is 2, that is to say, the alternative sign-off strategy set includes 2 alternative sign-off strategies. By the same token, in another embodiment of the present invention, the chip to be signed off includes 3 grains, wherein the number of optional models corresponding to the timing standard deviation calculation model of each grain is 2, then the number of alternative sign-off strategies included in the alternative sign-off strategy set of the chip to be signed off is equal to 2×2×2=8.

[0052] In an embodiment of the present invention, among the multiple dies included in the chip to be signed, there is at least one multi-model die, and the number of optional models corresponding to the multi-model die may be at least 2. Based on this, in one embodiment, the optional models corresponding to the multi-model die may include: a first model and a second model, wherein the first model may include calculating the total standard deviation of the timing parameters of the die, and the second model may include respectively calculating the global standard deviation and the local standard deviation of the timing parameters of the die. The total standard deviation of the timing parameters of the die refers to the overall standard deviation of the same timing parameters of the same devices at different positions, such as the overall standard deviation of the arrival time of each inverter A. The global standard deviation of the timing parameters of the die refers to the standard deviation of the same timing parameters of the same devices between die and die, between wafers and wafers, and between batches, and the local standard deviation refers to the standard deviation of the same timing parameters of the same devices at different positions in the same die.

[0053] For 2D grains, as the process continues to develop, in some cases, the first model for calculating the total standard deviation can be improved to a second model that calculates the global standard deviation and the local standard deviation separately, so that the standard deviation estimation of the grain is more accurate and the pessimism of the sign-off is effectively reduced. However, in the case where the chip to be signed is a three-dimensional integrated chip, it is not clear whether the use of the second model to calculate the standard deviation of each grain will reduce the overall pessimism of the chip to be signed, and there is no unified standard for how to calculate the chip standard deviation of the chip to be signed. In addition, although calculating the global standard deviation and the local standard deviation separately can effectively reduce the pessimism in the sign-off of 2D grains, it may take longer to perform timing sign-off, because calculating the global standard deviation and the local standard deviation separately may result in the need to process more sign-off scenarios.

[0054] In view of this, in one embodiment of the present invention, for each of the alternative sign-off strategies, in step S12, according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy, the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to the alternative sign-off strategy are determined. In a specific implementation, for each of the alternative sign-off strategies, according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy, determining the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to the alternative sign-off strategy may include: determining the grain standard deviation of each die under the alternative sign-off strategy according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy; determining the grain standard deviation of each die according to a preset functional relationship between the grain standard deviation and the chip standard deviation, and the grain standard deviation of each die; determining the number of chip standard deviation corresponding to the alternative sign-off strategy according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy ... The chip standard deviation is determined according to the alternative sign-off strategy; for each of the grains, if the timing standard deviation calculation model adopted by the grain is the first model, the number of grain sign-off scenarios corresponding to the grain is determined to be the first number of scenarios; if the timing standard deviation calculation model adopted by the grain is the second model, the number of grain sign-off scenarios corresponding to the grain is determined to be the second number of scenarios; the number of grain sign-off scenarios corresponding to each grain in the chip to be signed off is multiplied to obtain the number of chip sign-off scenarios corresponding to the alternative sign-off strategy.

[0055] The following is a detailed introduction to the number of chip signoff scenarios and the chip standard deviation. First, we will introduce how to determine the number of chip signoff scenarios.

[0056] Optionally, in an embodiment of the present invention, the specific number of the first scenario number corresponding to the first model and the second scenario number corresponding to the second model are not limited. In one example, since the first model is to calculate the total standard deviation of the die, the model is relatively simple, and the corresponding number of the first scenario is also small, and the second model is to calculate the global standard deviation and local standard deviation of the die respectively, the model is relatively complex, and the corresponding number of the second scenario is also large, that is, the number of the first scenario can be less than the number of the second scenario. Exemplarily, in one embodiment of the present invention, the number of the first scenario may include 1, and the number of the second scenario may include 3. For example, the typical value of the standard deviation of the die (that is, the die is in the TT process angle) can be used to calculate the total standard deviation, so the corresponding number of die sign-off scenarios (that is, the first scenario number) is 1; for another example, the local standard deviations corresponding to the above process angles can be superimposed under the FFG (fast N fast P global) process angle, the TTG (typical N typical P global) process angle, and the SSG (slow N slow P global) process angle, so the corresponding number of die sign-off scenarios (that is, the second scenario number) is 3.

[0057] In this way, for each alternative sign-off strategy, each die in the chip to be signed off has its own timing standard deviation calculation model, such as the first model or the second model. Since different timing standard deviation calculation models have different numbers of die sign-off scenarios (such as 1 or 3), the number of die sign-off scenarios corresponding to each die in the chip to be signed off is multiplied to obtain the number of chip sign-off scenarios corresponding to the alternative sign-off strategy. For example, in one example, the chip to be signed off includes 3 dies, each of which uses the second model as its own timing standard deviation calculation model. Under the second model, since each die has 3 die sign-off scenarios, the 3 die sign-off scenarios can be arranged and combined to generate 3×3×3=27 different chip sign-off scenarios. That is to say, in this case, if the chip to be signed off is signed off, 27 chip sign-off scenarios need to be processed. In another example, the chip to be signed off includes three dies, each of which uses the first model as its own timing standard deviation calculation model. Under the first model, since each die has only one die sign-off scenario, the die sign-off scenarios of the three dies can be arranged and combined to generate 1×1×1=1 sign-off scenario.

[0058] For example, in one embodiment of the present invention, the chip to be signed off includes two dies, and the corresponding chip sign-off scenarios under each candidate sign-off strategy can be shown in Table 1. In the column "Chip Sign-off Scenario Examples", the left side of the short dash "-" represents the process angle used by die1, and the right side represents the process angle used by die2. For example, TT-FF means that die1 is at the TT process angle, and die2 is at the FF process angle.

[0059]

[0060] It can be seen from the above embodiments that the timing standard deviation calculation model used by each die in the chip to be signed off will affect the number of chip sign-off scenarios of the chip to be signed off. It is understandable that the larger the number of chip sign-off scenarios, the more time and resources are required to perform timing sign-off under the same conditions.

[0061] The following is a detailed introduction on how to determine the chip standard deviation.

[0062] In an embodiment of the present invention, the grain standard deviation of each grain under each alternative sign-off strategy can be determined according to the timing standard deviation calculation model adopted by each grain in the alternative sign-off strategy; it can be understood that if the same grain adopts different timing standard deviation calculation models, the obtained grain standard deviation will be different. In one embodiment, there can be a preset functional relationship between the grain standard deviation and the chip standard deviation. After the grain standard deviation is obtained according to the timing standard deviation calculation model adopted by each grain, the corresponding chip standard deviation can be obtained using the grain standard deviation and the preset functional relationship.

[0063] Specifically, in one embodiment of the present invention, determining the grain standard deviation of each grain under each of the alternative sign-off strategies according to the timing standard deviation calculation model adopted by each grain in the alternative sign-off strategy may include: determining the first grain adopting the first model and the second grain adopting the second model in the chip to be signed off under each of the alternative sign-off strategies; for each alternative sign-off strategy, determining the total standard deviation corresponding to each of the first grains according to the first model, and determining the global standard deviation and the local standard deviation corresponding to each of the second grains according to the second model; based on this, determining the total standard deviation corresponding to each of the first grains according to the first model and the local standard deviation corresponding to each of the second grains according to the second model; based on the total standard deviation and the local standard deviation of the grains according to the timing standard deviation and the local standard deviation of the grains; determining the total standard deviation corresponding to each of the first grains according to the first model and the local standard deviation of the grains according to the local standard deviation; determining the total standard deviation corresponding to each of the first grains according to the second model; determining the total standard deviation corresponding to each of the first grains according to the local standard deviation and the local standard deviation of the grains according to the local standard deviation ... According to a preset functional relationship between the chip standard deviations and the respective grain standard deviations of the respective grains, determining the chip standard deviation corresponding to the alternative sign-off strategy may include: for each alternative sign-off strategy, determining a first standard deviation of the chip to be signed off according to the sum of the global standard deviations corresponding to the second grains, and determining a second standard deviation of the chip to be signed off according to the sum of the squares of the total standard deviations corresponding to the first grains and the sum of the squares of the local standard deviations corresponding to the second grains; and determining the chip standard deviation corresponding to the chip to be signed off under the alternative sign-off strategy according to the first standard deviation and the second standard deviation.

[0064] That is to say, for the first model, the grain standard deviation of the first grain may specifically include the total standard deviation, and for the second model, the grain standard deviation of the second grain may specifically include the global standard deviation and the local standard deviation. When calculating the chip standard deviation of the chip to be signed, on the one hand, the global standard deviations corresponding to each grain may be added together to determine the first standard deviation (the calculation of the global standard deviation involves the second grain), and on the other hand, the square sum of the total standard deviation or the local standard deviation corresponding to each grain may be calculated to determine the second standard deviation, and then the chip standard deviation may be further determined based on the first standard deviation and the second standard deviation (the calculation of the total standard deviation involves the first grain, and the calculation of the local standard deviation involves the second grain).

[0065] In one example, determining the first standard deviation of the chip to be signed based on the sum of the global standard deviations corresponding to each of the second grains may specifically include: the first standard deviation is equal to the multiplication of each of the global standard deviations by the first coefficient corresponding to each of the global standard deviations, and the products are summed, wherein the first coefficient is a multiple of the global standard deviation corresponding to each grain specified in the sign-off condition of the chip to be signed, and the multiple of the global standard deviation is used to limit the fluctuation range of the global deviation of each grain allowed when the chip to be signed is signed. The first coefficient may be a positive real number, such as a positive integer. Optionally, the first coefficients corresponding to the global standard deviations may be equal or unequal, and the embodiment of the present invention does not limit this. Exemplarily, in one embodiment of the present invention, the first coefficients corresponding to the global standard deviations may be, for example, 3, indicating that when the chip to be signed is signed, the global deviation of each grain of the chip to be signed fluctuates within 3 times the global standard deviation. In another embodiment of the present invention, the first coefficient corresponding to the global standard deviation of grain A is 3, indicating that when the chip to be signed is approved, the global deviation of grain A of the chip to be signed fluctuates within 3 times of the global standard deviation; the first coefficient corresponding to the global standard deviation of grain B is 5, indicating that when the chip to be signed is approved, the global deviation of grain B of the chip to be signed fluctuates within 5 times of the global standard deviation.

[0066] In another example, determining the second standard deviation of the chip to be signed based on the square sum of the total standard deviation corresponding to each of the first die and the square sum of the local standard deviation corresponding to each of the second die may specifically include: the second standard deviation is equal to the square sum of the products of each of the total standard deviations and the second coefficients corresponding to each of the two, plus the square sum of the products of each of the local standard deviations and the second coefficients corresponding to each of the two, and the square root of the sum is calculated, wherein the second coefficient is a multiple of the local standard deviation or the total standard deviation corresponding to each of the die specified in the sign-off pass condition of the chip to be signed, and the multiple of the local standard deviation or the total standard deviation is used to limit the fluctuation range of the local deviation or the total deviation of each of the die allowed when the chip to be signed is passed. The second coefficient may be a positive real number, such as a positive integer. Optionally, the second coefficients corresponding to the local standard deviations or the total standard deviations may be equal or unequal, and the embodiments of the present invention are not limited to this. Exemplarily, each second coefficient may be, for example, 6, indicating that when the chip to be approved is approved, the local deviation of each die of the chip to be approved fluctuates within 6 times the local standard deviation, or the total deviation of each die of the chip to be approved fluctuates within 6 times the total standard deviation. Exemplarily, the second coefficient of die A may be 3, and the second coefficient of die B may be 6, indicating that when the chip to be approved is approved, the local deviation of die A of the chip to be approved fluctuates within 3 times the local standard deviation, the total deviation of die A of the chip to be approved fluctuates within 3 times the total standard deviation, the local deviation of die B of the chip to be approved fluctuates within 6 times the local standard deviation, and the total deviation of die B of the chip to be approved fluctuates within 6 times the total standard deviation.

[0067] Further, based on the above first standard deviation and second standard deviation, it can be obtained that chip standard deviation = first standard deviation + second standard deviation; Exemplarily, in one embodiment of the present invention, the chip standard deviation σchip has the following relationship: σchip=σ1+σ2 (1) Among them, σ1 is the first standard deviation, which is equal to the global standard deviation corresponding to each second grain multiplied by the first coefficient corresponding to each grain, and the products are summed up; σ2 is the second standard deviation, which is equal to the square sum of the products of the total standard deviation corresponding to each first grain and the second coefficient corresponding to each grain, plus the square sum of the products of the local standard deviation of each second grain and the second coefficient corresponding to each grain, and the arithmetic square root of the sum is calculated.

[0068] For example, in one embodiment of the present invention, the chips to be signed include dieA1, dieA2, and dieA3, wherein dieA1 uses the first model to calculate the total standard deviation σA1total; dieA2 and dieA3 both use the second model to calculate the global standard deviation σA2global, σA3global, and the local standard deviation σA2local, σA3local, respectively. Then the chip standard deviation σchip can be expressed as: σchip=M×σA2global+M×σA3global+((N×σA1total) 2 +(N×σA2local) 2 +(N×σA3local) 2 ) 0.5 (2) Wherein, M is the first coefficient and N is the second coefficient.

[0069] For example, in one embodiment of the present invention, the chip to be signed off includes three dies, and the die process parameters of each die can be shown in Table 2. Then, according to formula (1), when all the dies adopt the first model and all the dies adopt the second model, the calculated chip standard deviation can be: All grains adopt the first model: σchip=σ1+σ2=0+ =7.3 All grains use the second model: σchip=3×1+3×1+3×1+ =14.2

[0070] It can be seen that the chip standard deviation 14.2 calculated by all the grains using the second model is larger than the chip standard deviation 7.3 calculated by all the grains using the first model, indicating that calculating the chip standard deviation by using the second model for all the grains may not be a suitable strategy, and there is a certain degree of over-design. It should be noted that here, only the cases where all three grains use the first model or all use the second model to calculate the chip standard deviation are listed, but the embodiments of the present invention are not limited to this. Similarly, the chip standard deviations calculated by using the first model for some grains and the second model for other grains can be calculated separately.

[0071] Combined with the number of chip sign-off scenarios in the foregoing text, illustratively, in one embodiment of the present invention, an example of the number of chip sign-off scenarios and chip standard deviations corresponding to different candidate sign-off strategies may be shown in Table 3.

[0072]

[0073] The above embodiment describes how to calculate the first standard deviation and the second standard deviation, and how to use the first standard deviation and the second standard deviation to obtain the chip standard deviation σchip of the chip to be signed. However, the embodiments of the present invention are not limited thereto. In other embodiments of the present invention, the first standard deviation and the second standard deviation may also be determined in other ways.

[0074] For example, in one embodiment of the present invention, determining the second standard deviation of the chip to be signed off according to the sum of squares of the total standard deviation corresponding to each of the first dies and the sum of squares of the local standard deviation corresponding to each of the second dies may specifically include: determining the number of register levels included in the target path to be signed off in each of the second dies; when the number of register levels is greater than a preset threshold, adjusting the local standard deviation corresponding to the second dies where the target path is located to obtain a local adjusted standard deviation; determining the second standard deviation of the target path in the chip to be signed off according to the sum of squares of the total standard deviation corresponding to each of the first dies and the sum of squares of the local adjusted standard deviation corresponding to each of the second dies. Exemplarily, in one example, the adjusted local adjusted standard deviation may be smaller than the local standard deviation before adjustment, for example, the local standard deviation before adjustment may be 1.5, and the adjusted local adjusted standard deviation may be 1.

[0075] In an embodiment of the present invention, the number of preset thresholds can be set and adjusted as needed. In one example, the preset threshold can be between 50 and 500, for example, 80. When calculating the second standard deviation, if the number of register levels included in the target path in the second grain is greater than the preset threshold, that is, if the number of register levels included in the target path of the second grain is large enough, the local standard deviation corresponding to the second grain can be adjusted, for example, the preset ratio can be reduced to obtain the local adjusted standard deviation, and the local adjusted standard deviation is further used to determine the second standard deviation of the target path in the chip to be signed. Here, since the number of register levels included in the target path is large enough, the probability that all registers are in the same extreme process condition is very low, that is, the probability that the local standard deviation of the grain is an extreme value is very low. Therefore, when calculating the second standard deviation, the local standard deviation can be appropriately reduced to obtain a smaller local adjusted standard deviation, so that the second standard deviation and the chip standard deviation can be more accurate.

[0076] For example, a chip to be signed includes three dies, and the die process parameters of each die can be shown in Table 4. Since the number of register levels of the target path is 100, which is greater than the preset threshold (the preset threshold is, for example, 80 levels), when calculating the chip standard deviation, the local adjustment standard deviation 1 can be used instead of the local standard deviation 2. In the case where all the dies adopt the first model or all the dies adopt the second model, the chip standard deviation calculated according to formula (1) can be: All grains adopt the first model: σchip=0+ =23.2 All grains use the second model: σchip=3×1+3×1+3×1+ =14.2=19.4

[0077] After obtaining the number of chip sign-off scenarios and the corresponding chip standard deviation under each alternative sign-off strategy in step S12, in step S13, one of the alternative sign-off strategies can be selected from the set of alternative sign-off strategies as the target strategy according to the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each of the alternative sign-off strategies. In one embodiment of the present invention, selecting one of the alternative sign-off strategies from the set of alternative sign-off strategies as the target strategy according to the number of chip sign-off scenarios corresponding to each of the alternative sign-off strategies and the corresponding chip standard deviation may specifically include: selecting one of the alternative sign-off strategies from the set of alternative sign-off strategies as the target strategy according to the sign-off requirement of the chip to be signed off, the number of chip sign-off scenarios corresponding to each of the alternative sign-off strategies and the corresponding chip standard deviation, wherein the sign-off requirement includes at least one of the following: a requirement for a design margin of the chip to be signed off and a requirement for a sign-off progress of the chip to be signed off, the requirement for the design margin of the chip to be signed off may be related to the chip standard deviation, and the requirement for the sign-off progress of the chip to be signed off may be related to the number of chip sign-off scenarios.

[0078] Specifically, the larger the chip standard deviation, the larger the design margin that needs to be reserved in order to meet the timing requirements, and the smaller the chip standard deviation, the smaller the design margin that needs to be reserved. The more chip sign-off scenarios there are, the longer it takes to perform the timing sign-off, and the fewer chip sign-off scenarios there are, the shorter it takes to perform the timing sign-off. Based on this, if the design margin of the chip to be signed is small in the sign-off requirements, when selecting the target strategy, an alternative sign-off strategy with a smaller chip standard deviation can be selected. If the sign-off progress of the chip to be signed is more urgent in the sign-off requirements, when selecting the target strategy, an alternative sign-off strategy with a smaller number of chip sign-off scenarios can be selected. If the design margin of the chip to be signed is small and the sign-off progress of the chip to be signed is more urgent in the sign-off requirements, when selecting the target strategy, a compromise solution that takes both into account can be selected. Therefore, in an embodiment of the present invention, when performing the timing sign-off on the chip to be signed, various sign-off requirements can be comprehensively considered, and the target strategy can be flexibly selected according to various sign-off requirements, and the scope of application is relatively wide.

[0079] After the target strategy is selected, the chip to be signed off can be subjected to timing sign-off according to the selected target strategy in step S14, thereby achieving effective timing sign-off of the stereo chip.

[0080] Furthermore, in one embodiment of the present invention, after step S14 performs timing sign-off on the chip to be signed according to the target strategy, the timing sign-off method provided by the embodiment of the present invention may also include: testing the three-dimensional integrated chip manufactured after the timing sign-off; adjusting the functional relationship between the chip standard deviation and the grain standard deviation of each of the grains according to the test results, wherein the grain standard deviation of each of the grains is related to the timing standard deviation calculation model adopted by the grain.

[0081] Specifically, if after testing the three-dimensional integrated chip manufactured after the timing sign-off, it is found that there is a large gap between the test results and the sign-off results, for example, many parameter items that passed the sign-off did not pass the actual test, then the functional relationship between the chip standard deviation and the grain standard deviation of each grain can be adjusted according to the test results, so as to make the timing sign-off result more accurate. Exemplarily, in one example, at least one of the following methods can be adjusted: a method of obtaining a first standard deviation from a grain standard deviation, a method of obtaining a second standard deviation from a grain standard deviation, a method of obtaining a chip standard deviation from a first standard deviation and a second standard deviation, etc.

[0082] The timing sign-off method provided by the embodiment of the present invention is described in detail below through a specific embodiment.

[0083] like Figure 2 As shown, the timing sign-off method provided by the embodiment of the present invention may include the following steps: S201 , respectively obtaining the number of dies included in the chip to be signed and each optional model corresponding to the timing standard deviation calculation model of each die.

[0084] S202. Determine the number of alternative sign-off strategies included in the set of alternative sign-off strategies to be generated, and the timing standard deviation calculation model adopted by each die under each alternative sign-off strategy in the set of alternative sign-off strategies, according to the number of die included in the chip to be signed off and the optional models corresponding to the timing standard deviation calculation model of each die.

[0085] S203 , generating a candidate sign-off strategy set according to the number of candidate sign-off strategies included in the candidate sign-off strategy set to be generated and the timing standard deviation calculation model used by each die under each candidate sign-off strategy in the candidate sign-off strategy set to be generated.

[0086] S204 , determining a first die using the first model and a second die using the second model in the chip to be signed off under each candidate sign-off strategy in the candidate sign-off strategy set.

[0087] S205 . For each candidate sign-off strategy, determine a total standard deviation corresponding to each first die according to the first model, and determine a global standard deviation and a local standard deviation corresponding to each second die according to the second model.

[0088] S206. For each candidate sign-off strategy, determine the first standard deviation of the chip to be signed off according to the sum of the global standard deviations corresponding to the second grains, and determine the second standard deviation of the chip to be signed off according to the sum of the squares of the total standard deviations corresponding to the first grains and the sum of the squares of the local standard deviations corresponding to the second grains.

[0089] S207 . Determine the chip standard deviation corresponding to the chip to be signed off under the candidate sign-off strategy according to the first standard deviation and the second standard deviation.

[0090] S208 . Select an alternative sign-off strategy from the set of alternative sign-off strategies as a target strategy according to the sign-off requirement of the chip to be signed off, the number of chip sign-off scenarios corresponding to each alternative sign-off strategy, and the corresponding chip standard deviation.

[0091] S209 , performing timing sign-off on the chip to be signed off according to the target strategy.

[0092] S210 , testing the three-dimensional integrated chip manufactured after the timing sign-off.

[0093] S211 . Adjust the functional relationship between the chip standard deviation and the grain standard deviation of each grain according to the test result, wherein the grain standard deviation of each grain is related to the timing standard deviation calculation model adopted by the grain.

[0094] For example, at least one of the following methods may be adjusted: a method of obtaining a first standard deviation from a grain standard deviation, a method of obtaining a second standard deviation from a grain standard deviation, and a method of obtaining a chip standard deviation from a first standard deviation and a second standard deviation.

[0095] In a second aspect, an embodiment of the present invention provides a timing sign-off apparatus, which can effectively perform timing sign-off on a three-dimensional integrated chip while ensuring the time required for timing sign-off and the timing margin.

[0096] like Figure 3 As shown, an embodiment of the present invention further provides a timing sign-off device, comprising: A generating unit 31 is used to generate a set of candidate sign-off strategies for a chip to be signed off, wherein the chip to be signed off is obtained by three-dimensional integration of at least two crystal grains, and the set of candidate sign-off strategies includes at least one candidate sign-off strategy, wherein each of the candidate sign-off strategies includes a timing standard deviation calculation model adopted by each crystal grain in the chip to be signed off; the timing standard deviation calculation model adopted by each crystal grain is selected from the optional models corresponding to the crystal grain, and there is at least one multi-model crystal grain in the chip to be signed off, and the number of the optional models corresponding to the multi-model crystal grain is greater than 1; The determining unit 32 is configured to determine, for each of the alternative sign-off strategies, the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to the alternative sign-off strategy according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy, wherein the number of chip sign-off scenarios is the number of sign-off scenarios that need to be processed when performing timing sign-off on the chip to be signed; and the chip standard deviation is the standard deviation of the timing parameters of the chip to be signed; A selection unit 33, configured to select one of the candidate sign-off strategies from the candidate sign-off strategy set as a target strategy according to the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each of the candidate sign-off strategies; The sign-off unit 34 is configured to perform a timing sign-off on the chip to be signed off according to the target strategy.

[0097] The timing sign-off device provided by the embodiment of the present invention can generate a set of alternative sign-off strategies for a chip to be signed off, wherein the set of alternative sign-off strategies includes at least one alternative sign-off strategy. For each of the alternative sign-off strategies, the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to the alternative sign-off strategy are determined according to the timing standard deviation calculation model adopted by each grain in the alternative sign-off strategy. Then, according to the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each alternative sign-off strategy, one of the alternative sign-off strategies is selected from the set of alternative sign-off strategies as the target strategy, and the timing sign-off of the chip to be signed off is performed according to the target strategy. Since the chip to be signed off is obtained by integrating at least two grains, a model combination corresponding to such a grain combination of the chip to be signed off, i.e., an alternative sign-off strategy, can be determined according to the timing standard deviation calculation model adopted by each grain in the chip to be signed off. Furthermore, since the timing standard deviation calculation model adopted by each grain is selected from the optional models corresponding to the grain, and there is at least one multi-model grain in the chip to be signed, and the number of the optional models corresponding to the multi-model grain is greater than 1, due to the existence of the multi-model grain and the timing standard deviation calculation models of each grain can be arranged and combined, it is possible to form multiple alternative sign-off strategies for the chip to be signed, thereby forming an alternative sign-off strategy set, so as to provide a basis for the selection of the target strategy. Furthermore, the number of chip signoff scenarios and the corresponding chip standard deviation under each alternative signoff strategy can be determined based on the timing standard deviation calculation model adopted by each die in the alternative signoff strategy. The number of chip signoff scenarios will involve the time required for signoff, and the chip standard deviation will involve the chip timing margin allowed for signoff. Therefore, the number of chip signoff scenarios and the chip standard deviation are used as considerations for the chip signoff strategy. A suitable target strategy is selected from the set of alternative signoff strategies. The target strategy is used to signoff the three-dimensional integrated chip. This allows the three-dimensional integrated chip to be effectively signed off on timing while ensuring the time required for timing signoff and the timing margin.

[0098] In one embodiment, the generation unit 31 may include: an acquisition module, used to respectively acquire the number of grains included in the chip to be signed off and the various optional models corresponding to the timing standard deviation calculation model of each grain; a first determination module, used to determine the number of alternative sign-off strategies included in the set of alternative sign-off strategies to be generated, and the timing standard deviation calculation model adopted by each grain under each alternative sign-off strategy in the set of alternative sign-off strategies to be generated, according to the number of grains included in the chip to be signed off and the various optional models corresponding to the timing standard deviation calculation model of each grain; a generation module, used to generate the set of alternative sign-off strategies according to the number of alternative sign-off strategies included in the set of alternative sign-off strategies to be generated, and the timing standard deviation calculation model adopted by each grain under each alternative sign-off strategy in the set of alternative sign-off strategies to be generated.

[0099] In one implementation, the number of candidate sign-off strategies included in the candidate sign-off strategy set is equal to the product of the number of selectable models corresponding to the timing standard deviation calculation model of each die in the chip to be signed off multiplied by each other.

[0100] In one embodiment, the optional models corresponding to the multi-model grain include: a first model and a second model, wherein the first model includes calculating the total standard deviation of the timing parameters of the grain, and the second model includes respectively calculating the global standard deviation and the local standard deviation of the timing parameters of the grain.

[0101] In one embodiment, the determination unit 32 may include: a second determination module, configured to determine the grain standard deviation of each grain under each of the alternative sign-off strategies according to the timing standard deviation calculation model adopted by each grain in the alternative sign-off strategy; a third determination module, configured to determine the chip standard deviation corresponding to the alternative sign-off strategy according to a preset functional relationship between the grain standard deviation and the chip standard deviation and the grain standard deviation of each grain; a fourth determination module, configured to determine, for each of the grains, if the timing standard deviation calculation model adopted by the grain is the first model, the number of grain sign-off scenarios corresponding to the grain is the first scenario number, and if the timing standard deviation calculation model adopted by the grain is the second model, the number of grain sign-off scenarios corresponding to the grain is the second scenario number; and a multiplication module, configured to multiply the grain sign-off scenario numbers corresponding to each grain in the chip to be signed off to obtain the chip sign-off scenario number corresponding to the alternative sign-off strategy.

[0102] In one embodiment, the second determination module includes: a first determination submodule, used to determine, under each of the alternative sign-off strategies, first grains using the first model and second grains using the second model in the chip to be signed off; a second determination submodule, used to determine, for each of the alternative sign-off strategies, the total standard deviation corresponding to each of the first grains according to the first model, and to determine, according to the second model, the global standard deviation and the local standard deviation corresponding to each of the second grains; the third determination module includes: a fourth determination submodule, used to determine, for each of the alternative sign-off strategies, the first standard deviation of the chip to be signed off according to the sum of the global standard deviations corresponding to the second grains, and to determine the second standard deviation of the chip to be signed off according to the sum of the squares of the total standard deviations corresponding to the first grains and the sum of the squares of the local standard deviations corresponding to the second grains; and a fifth determination submodule, used to determine, according to the first standard deviation and the second standard deviation, the chip standard deviation corresponding to the chip to be signed off under the alternative sign-off strategy.

[0103] In one embodiment, the fourth determination submodule is specifically used to: determine that the first standard deviation is equal to the multiplication of each global standard deviation and the first coefficient corresponding to each, and then sum the products, wherein the first coefficient is a multiple of the global standard deviation corresponding to each grain specified in the sign-off pass conditions of the chip to be signed, and the multiple of the global standard deviation is used to limit the fluctuation range of the global deviation of each grain allowed when the chip to be signed is passed.

[0104] In one embodiment, the fourth determination submodule is specifically used to: determine that the second standard deviation is equal to the sum of the squares of the products of each of the total standard deviations and the corresponding second coefficients, plus the sum of the squares of the products of each of the local standard deviations and the corresponding second coefficients, and calculate the arithmetic square root of the sum, wherein the second coefficient is a multiple of the local standard deviation or the total standard deviation corresponding to each grain specified in the sign-off pass conditions of the chip to be signed, and the local standard deviation or the multiple of the total standard deviation is used to limit the fluctuation range of the local deviation or the total deviation of each grain allowed when the chip to be signed is passed.

[0105] In one embodiment, the fourth determination submodule is specifically used to: determine the number of register levels included in the target path to be signed off in each of the second grains; when the number of register levels is greater than a preset threshold, adjust the local standard deviation corresponding to the second grain where the target path is located to obtain a local adjusted standard deviation; determine the second standard deviation of the target path in the chip to be signed off based on the sum of the squares of the total standard deviation corresponding to each of the first grains and the sum of the squares of the local adjusted standard deviations corresponding to each of the second grains.

[0106] In one implementation, the first number of scenes includes 1, and the second number of scenes includes 3.

[0107] In one embodiment, the selection unit 33 is specifically used to select one of the alternative sign-off strategies from the set of alternative sign-off strategies as the target strategy according to the sign-off requirement of the chip to be signed off, the number of chip sign-off scenarios corresponding to each of the alternative sign-off strategies, and the corresponding chip standard deviation, wherein the sign-off requirement includes at least one of the following: a requirement for the design margin of the chip to be signed off, a requirement for the sign-off progress of the chip to be signed off, the requirement for the design margin of the chip to be signed off is related to the chip standard deviation, and the requirement for the sign-off progress of the chip to be signed off is related to the number of chip sign-off scenarios.

[0108] In one embodiment, the device also includes: a testing unit, which is used to test the three-dimensional integrated chip manufactured after the timing sign-off is performed on the chip to be signed off according to the target strategy; an adjustment unit, which is used to adjust the functional relationship between the chip standard deviation and the grain standard deviation of each of the grains according to the test results of the testing unit, wherein the grain standard deviation of each of the grains is related to the timing standard deviation calculation model adopted by the grain.

[0109] In a third aspect, an embodiment of the present invention further provides an electronic device capable of performing effective timing sign-off on a three-dimensional integrated chip while ensuring the time required for timing sign-off and the timing margin.

[0110] like Figure 4 As shown, the electronic device provided by the embodiment of the present invention may include: a processor 51 and a memory 52, wherein the processor 51 is electrically connected to the memory 52; the memory 52 is used to store executable program codes; the processor 51 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 52, so as to implement any one of the timing sign-off methods provided by the embodiment of the present invention.

[0111] The specific execution process of the above steps by the processor 51 and the steps further executed by the processor 51 by running the executable program code can be found in the description of the above embodiment, which will not be repeated here.

[0112] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more processors to implement any one of the timing sign-off methods provided in the aforementioned embodiments, thereby also achieving the corresponding technical effects, which have been described in detail above and will not be repeated here.

[0113] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0114] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0115] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0116] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0117] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0118] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A timing sign-off method, characterized in that: include: Generate a set of candidate sign-off strategies for a chip to be signed off, wherein the chip to be signed off is obtained by three-dimensional integration of at least two dies, and the set of candidate sign-off strategies includes at least one candidate sign-off strategy, wherein each of the candidate sign-off strategies includes a timing standard deviation calculation model adopted by each dies in the chip to be signed off; the timing standard deviation calculation model adopted by each dies is selected from the optional models corresponding to the dies, and there is at least one multi-model dies in the chip to be signed off, and the number of the optional models corresponding to the multi-model dies is greater than 1; For each of the alternative sign-off strategies, according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy, determine the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to the alternative sign-off strategy, wherein the number of chip sign-off scenarios is the number of sign-off scenarios that need to be processed when performing timing sign-off on the chip to be signed; the chip standard deviation is the standard deviation of the timing parameters of the chip to be signed; According to the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each of the candidate sign-off strategies, selecting one of the candidate sign-off strategies from the set of candidate sign-off strategies as a target strategy; Performing timing sign-off on the chip to be signed off according to the target strategy.

2. The method according to claim 1, characterized in that The generating of a set of candidate sign-off strategies for a chip to be signed off comprises: Respectively obtaining the number of dies included in the chip to be signed and each of the optional models corresponding to the timing standard deviation calculation model of each die; Determine, according to the number of dies included in the chip to be signed off and the optional models corresponding to the timing standard deviation calculation model of each die, the number of the alternative sign-off strategies included in the set of alternative sign-off strategies to be generated, and the timing standard deviation calculation model adopted by each of the dies under each of the alternative sign-off strategies in the set of alternative sign-off strategies to be generated; The candidate sign-off strategy set is generated according to the number of the candidate sign-off strategies included in the candidate sign-off strategy set to be generated and the timing standard deviation calculation model adopted by each of the die under each of the candidate sign-off strategies in the candidate sign-off strategy set to be generated.

3. The method according to claim 2, characterized in that The number of the candidate sign-off strategies included in the candidate sign-off strategy set is equal to the product obtained by multiplying the number of selectable models corresponding to the timing standard deviation calculation model of each die in the chip to be signed off.

4. The method according to claim 1, characterized in that: The optional models corresponding to the multi-model grain include: a first model and a second model, wherein the first model includes calculating the total standard deviation of the timing parameters of the grain, and the second model includes respectively calculating the global standard deviation and the local standard deviation of the timing parameters of the grain.

5. The method according to claim 4, characterized in that For each of the alternative sign-off strategies, determining the number of chip sign-off scenarios and the corresponding chip standard deviation under the alternative sign-off strategy according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy includes: Determine, according to a timing standard deviation calculation model used by each die in each of the alternative sign-off strategies, a die standard deviation of each of the die under the alternative sign-off strategy; Determine the chip standard deviation corresponding to the candidate sign-off strategy according to a preset functional relationship between the die standard deviation and the chip standard deviation and the die standard deviation of each die; For each of the die, if the timing standard deviation calculation model adopted by the die is the first model, the number of die sign-off scenarios corresponding to the die is determined to be the first number of scenarios; if the timing standard deviation calculation model adopted by the die is the second model, the number of die sign-off scenarios corresponding to the die is determined to be the second number of scenarios; The number of chip sign-off scenarios corresponding to each chip in the chip to be signed off is multiplied to obtain the number of chip sign-off scenarios corresponding to the alternative sign-off strategy.

6. The method according to claim 5, characterized in that Determining the die standard deviation of each die under each of the alternative sign-off strategies according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy includes: Determine, under each of the candidate sign-off strategies, a first die using the first model and a second die using the second model in the chip to be signed off; For each of the candidate sign-off strategies, determine the total standard deviation corresponding to each of the first die according to the first model, and determine the global standard deviation and the local standard deviation corresponding to each of the second die according to the second model; The determining the chip standard deviation corresponding to the candidate sign-off strategy according to the preset functional relationship between the die standard deviation and the chip standard deviation and the die standard deviation of each die includes: For each of the candidate sign-off strategies, determine a first standard deviation of the chip to be signed off according to the sum of the global standard deviations corresponding to the second dies, and determine a second standard deviation of the chip to be signed off according to the sum of the squares of the total standard deviations corresponding to the first dies and the sum of the squares of the local standard deviations corresponding to the second dies; The chip standard deviation corresponding to the chip to be signed off under the alternative sign-off strategy is determined according to the first standard deviation and the second standard deviation.

7. The method according to claim 6, characterized in that Determining the first standard deviation of the chip to be signed off according to the sum of the global standard deviations corresponding to each of the second dies includes: The first standard deviation is equal to the multiplication of each global standard deviation and the corresponding first coefficient, and the products are summed, wherein the first coefficient is a multiple of the global standard deviation corresponding to each grain specified in the sign-off pass conditions of the chip to be signed, and the multiple of the global standard deviation is used to limit the fluctuation range of the global deviation of each grain allowed when the chip to be signed is passed.

8. The method according to claim 6, characterized in that The determining the second standard deviation of the chip to be signed off according to the sum of squares of the total standard deviation corresponding to each of the first dies and the sum of squares of the local standard deviation corresponding to each of the second dies comprises: The second standard deviation is equal to the square sum of the products of each of the total standard deviations and the corresponding second coefficients, plus the square sum of the products of each of the local standard deviations and the corresponding second coefficients, and the arithmetic square root of the sum is obtained, wherein the second coefficient is the multiple of the local standard deviation or the total standard deviation corresponding to each grain specified in the sign-off pass conditions of the chip to be signed, and the local standard deviation or the multiple of the total standard deviation is used to limit the fluctuation range of the local deviation or the total deviation of each grain allowed when the chip to be signed is passed.

9. The method according to any one of claims 6 to 8, characterized in that The determining the second standard deviation of the chip to be signed off according to the sum of squares of the total standard deviation corresponding to each of the first dies and the sum of squares of the local standard deviation corresponding to each of the second dies comprises: Determining the number of register levels included in the target path to be signed off in each of the second dies; When the number of register levels is greater than a preset threshold, adjusting the local standard deviation corresponding to the second die where the target path is located to obtain a local adjusted standard deviation; The second standard deviation of the target path in the chip to be signed off is determined according to the sum of squares of the total standard deviation corresponding to each of the first dies and the sum of squares of the local adjustment standard deviation corresponding to each of the second dies.

10. The method according to claim 5, characterized in that The first number of scenes includes 1, and the second number of scenes includes 3.

11. The method according to any one of claims 1 to 8, characterized in that The selecting one of the candidate sign-off strategies as the target strategy from the candidate sign-off strategy set according to the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each of the candidate sign-off strategies comprises: According to the sign-off requirement of the chip to be signed off, the number of chip sign-off scenarios corresponding to each of the alternative sign-off strategies, and the corresponding chip standard deviation, one of the alternative sign-off strategies is selected from the set of alternative sign-off strategies as the target strategy, wherein the sign-off requirement includes at least one of the following: a requirement for a design margin of the chip to be signed off, a requirement for a sign-off progress of the chip to be signed off, the requirement for the design margin of the chip to be signed off is related to the chip standard deviation, and the requirement for the sign-off progress of the chip to be signed off is related to the number of chip sign-off scenarios.

12. The method according to any one of claims 1 to 8, characterized in that After performing timing sign-off on the chip to be signed off according to the target strategy, the method further includes: Test the 3D integrated chip manufactured after timing sign-off; The functional relationship between the chip standard deviation and the grain standard deviation of each of the grains is adjusted according to the test results, wherein the grain standard deviation of each of the grains is related to the timing standard deviation calculation model adopted by the grain.

13. A timing sign-off device, characterized in that: include: a generating unit, configured to generate a set of candidate sign-off strategies for a chip to be signed off, wherein the chip to be signed off is obtained by three-dimensional integration of at least two crystal grains, and the set of candidate sign-off strategies includes at least one candidate sign-off strategy, wherein each of the candidate sign-off strategies includes a timing standard deviation calculation model adopted by each crystal grain in the chip to be signed off; the timing standard deviation calculation model adopted by each crystal grain is selected from the optional models corresponding to the crystal grain, and there is at least one multi-model crystal grain in the chip to be signed off, and the number of the optional models corresponding to the multi-model crystal grain is greater than 1; A determination unit is used to determine, for each of the alternative sign-off strategies, the number of chip sign-off scenarios and the corresponding chip standard deviation under the alternative sign-off strategy according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy, wherein the number of chip sign-off scenarios is the number of sign-off scenarios that need to be processed when performing timing sign-off on the chip to be signed; the chip standard deviation is the standard deviation of the timing parameters of the chip to be signed; A selection unit, configured to select one of the candidate sign-off strategies from the candidate sign-off strategy set as a target strategy according to the number of chip sign-off scenarios and the corresponding chip standard deviation corresponding to each of the candidate sign-off strategies; A sign-off unit is used to perform a timing sign-off on the chip to be signed off according to the target strategy.

14. The device according to claim 13, characterized in that The generating unit comprises: An acquisition module, used to respectively acquire the number of dies included in the chip to be signed and each of the optional models corresponding to the timing standard deviation calculation model of each die; A first determination module is used to determine the number of the alternative sign-off strategies included in the set of alternative sign-off strategies to be generated, and the timing standard deviation calculation model adopted by each of the die under each of the alternative sign-off strategies in the set of alternative sign-off strategies to be generated, according to the number of the die included in the chip to be signed off and the optional models corresponding to the timing standard deviation calculation model of each die; A generating module is used to generate the set of alternative sign-off strategies according to the number of the alternative sign-off strategies included in the set of alternative sign-off strategies to be generated and the timing standard deviation calculation model adopted by each of the die under each of the alternative sign-off strategies in the set of alternative sign-off strategies to be generated.

15. The device according to claim 14, characterized in that The number of the candidate sign-off strategies included in the candidate sign-off strategy set is equal to the product obtained by multiplying the number of selectable models corresponding to the timing standard deviation calculation model of each die in the chip to be signed off.

16. The device according to claim 13, characterized in that The optional models corresponding to the multi-model grain include: a first model and a second model, wherein the first model includes calculating the total standard deviation of the timing parameters of the grain, and the second model includes respectively calculating the global standard deviation and the local standard deviation of the timing parameters of the grain.

17. The device according to claim 16, characterized in that The determining unit comprises: A second determination module is used to determine the die standard deviation of each die under each of the alternative sign-off strategies according to the timing standard deviation calculation model adopted by each die in the alternative sign-off strategy; A third determination module, configured to determine the chip standard deviation corresponding to the candidate sign-off strategy according to a preset functional relationship between the die standard deviation and the chip standard deviation and the die standard deviation of each die; a fourth determining module, configured to, for each of the dies, determine, if the timing standard deviation calculation model adopted by the die is the first model, that the number of die sign-off scenarios corresponding to the die is the first number of scenarios; and if the timing standard deviation calculation model adopted by the die is the second model, determine, if the timing standard deviation calculation model adopted by the die is the second model, that the number of die sign-off scenarios corresponding to the die is the second number of scenarios; The multiplication module is used to multiply the number of chip sign-off scenarios corresponding to each chip in the chip to be signed off, so as to obtain the number of chip sign-off scenarios corresponding to the alternative sign-off strategy.

18. The device according to claim 17, characterized in that The second determining module comprises: A first determination submodule is used to determine, under each of the candidate sign-off strategies, a first die using the first model and a second die using the second model in the chip to be signed off; a second determination submodule, configured to determine, for each of the candidate sign-off strategies, the total standard deviation corresponding to each of the first die according to the first model, and determine, according to the second model, the global standard deviation and the local standard deviation corresponding to each of the second die; The third determination module comprises: a fourth determination submodule, configured to determine, for each of the candidate sign-off strategies, a first standard deviation of the chip to be signed off according to the sum of the global standard deviations corresponding to the second grains, and to determine a second standard deviation of the chip to be signed off according to the sum of the squares of the total standard deviations corresponding to the first grains and the sum of the squares of the local standard deviations corresponding to the second grains; The fifth determining submodule is configured to determine the chip standard deviation corresponding to the chip to be signed off under the alternative sign-off strategy according to the first standard deviation and the second standard deviation.

19. The device according to claim 18, characterized in that The fourth determining submodule is specifically used for: Determine that the first standard deviation is equal to each of the global standard deviations multiplied by the first coefficient corresponding to each, and then sum the products, wherein the first coefficient is a multiple of the global standard deviation corresponding to each grain specified in the sign-off pass condition of the chip to be signed, and the multiple of the global standard deviation is used to limit the fluctuation range of the global deviation of each grain allowed when the chip to be signed is passed.

20. The device according to claim 18, characterized in that The fourth determining submodule is specifically used for: Determine that the second standard deviation is equal to the sum of the squares of the products of the total standard deviations and the second coefficients corresponding to them, plus the sum of the squares of the products of the local standard deviations and the second coefficients corresponding to them, and calculate the arithmetic square root of the sum, wherein the second coefficient is a multiple of the local standard deviation or the total standard deviation corresponding to each die specified in the sign-off pass condition of the chip to be signed off, and the local standard deviation or the multiple of the total standard deviation is used to limit the fluctuation range of the local deviation or the total deviation of each die allowed when the chip to be signed off is passed.

21. The device according to any one of claims 18 to 20, characterized in that The fourth determining submodule is specifically used for: Determining the number of register levels included in the target path to be signed off in each of the second dies; When the number of register levels is greater than a preset threshold, adjusting the local standard deviation corresponding to the second die where the target path is located to obtain a local adjusted standard deviation; The second standard deviation of the target path in the chip to be signed off is determined according to the sum of squares of the total standard deviation corresponding to each of the first dies and the sum of squares of the local adjustment standard deviation corresponding to each of the second dies.

22. The device according to claim 17, characterized in that The first number of scenes includes 1, and the second number of scenes includes 3.

23. The device according to any one of claims 13 to 20, characterized in that The selection unit is specifically configured to select one of the alternative sign-off strategies from the set of alternative sign-off strategies as the target strategy according to the sign-off requirement of the chip to be signed off, the number of chip sign-off scenarios corresponding to each of the alternative sign-off strategies, and the corresponding chip standard deviation, wherein the sign-off requirement includes at least one of the following: a requirement for a design margin of the chip to be signed off, a requirement for a sign-off progress of the chip to be signed off, the requirement for the design margin of the chip to be signed off is related to the chip standard deviation, and the requirement for the sign-off progress of the chip to be signed off is related to the number of chip sign-off scenarios.

24. The device according to any one of claims 13 to 20, characterized in that Also includes: A testing unit, configured to test the three-dimensional integrated chip manufactured after the timing sign-off is performed on the chip to be signed off according to the target strategy; An adjustment unit is used to adjust the functional relationship between the chip standard deviation and the grain standard deviation of each grain according to the test result of the test unit, wherein the grain standard deviation of each grain is related to the timing standard deviation calculation model adopted by the grain.

25. An electronic device, characterized in that: The electronic device includes: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the timing sign-off method described in any one of claims 1 to 12.

26. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the timing signoff method according to any one of claims 1 to 12.

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