Logic comprehensive optimization method based on control signal, storage medium and electronic equipment

By performing control signal-based optimization processing on multiple branch statements in FPGA logical synthesis, a special multiple selector unit is generated, which solves the problem of high consumption of logical comprehensive resources in multiple branch statements, and improves the utilization rate of logical resources and Timing performance.

CN119180248AActive Publication Date: 2024-12-24EHIWAY MICROELECTRONIC SCI & TECH (SUZHOU) CO LTD
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Patent Information

Application Number
CN202411688044.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-11-25
Publication Date
2024-12-24
Estimated Expiration
2044-11-25

AI Technical Summary

Technical Problem

When processing multiple branch statements, the existing FPGA logic synthesis technology generates a large number of multiple selectors and gate circuit units, resulting in increased resource consumption and area, and lacks effective optimization methods.

Method used

By syntax analysis of the circuit code, parallel multiplexer units are extracted, their input and output signals are obtained, and their input and output signals are split and combined according to the control signal and input signal bit widths are generated to generate a special multiplexer unit to reduce logical resources consumption and unit number.

Benefits of technology

It effectively reduces the number of units after logical synthesis of multiple branch statements, improves the utilization rate and timing performance of logical resources, and reduces the area of ​​FPGA layout.

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Abstract

The invention provides a logic comprehensive optimization method based on a control signal, a storage medium and electronic equipment, and the method comprises the steps: traversing a multiplexer unit, and obtaining the signal bit width of the input S end of the multiplexer unit; if the bit width is greater than or equal to N, traversing each bit value of an input S-end signal, obtaining an ith sigb [i], a selection signal value sv and a control signal, and storing a key value pair (sv, sigb [i]) into a mapping set; performing expansion operation and combination operation on the mapping set to generate a plurality of N-bit combination signals, taking the lowest two bits of control signals as selection signals to generate a 1-in-N multiplexer unit muxN, and collecting muxN output signals as input B end signals of the current multiplexer unit; the lowest two bits of the control signal are removed, and the bit width is updated. According to the invention, the optimization effect of logic synthesis of the multiplexer unit can be improved, and the consumption of logic resources and the number of units after logic synthesis are reduced.
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Citation Information

Patent Citations

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