Memory device and operating method of memory device

Abstract

The invention relates to a memory device and an operating method of the memory device. An operating method of a memory device may include performing a pre-program operation on select transistors included in strings, where each string includes a first source select transistor, a second source select transistor, a plurality of memory cells, and a drain select transistor that are sequentially coupled; and performing an erase operation and a fine program operation on at least one of the select transistors.

Description

Technical Field

[0001] The present technology relates to a memory device, and more particularly, to a nonvolatile memory device. Background Art

[0002] An electronic device includes many electronic components. Among these electronic components, a computer system may include many electronic components composed of semiconductors. Among the semiconductor devices constituting the computer system, a host device such as a processor or a memory controller may perform data communication with a memory device. The memory device may include a plurality of memory cells, which may be designated by word lines and bit lines, and may store data.

[0003] The memory device may include a selection transistor for selecting a memory cell. The selection transistor may be constructed similarly to the memory cell. Therefore, the selection transistor may be controlled similarly to the memory cell. In order to correctly select the desired memory cell, a solution for finely controlling the selection transistor may be required. Summary of the invention

[0004] In an embodiment, a method for operating a memory device may include the following steps: performing a pre-programming operation on selection transistors included in strings, wherein each string includes a first source selection transistor, a second source selection transistor, a plurality of memory cells, and a drain selection transistor connected in sequence; and performing an erase operation and a fine programming operation on at least one of the selection transistors.

[0005] In an embodiment, an operating method of a memory device may include the following steps: performing a first pre-programming operation on selection transistors included in strings, wherein each string includes a plurality of memory cells connected between the selection transistors; and sequentially performing an erase operation, a second pre-programming operation, a slow transistor masking operation, and a fine programming operation on a target selection transistor among the selection transistors included in the string.

[0006] In an embodiment, a memory device may include: a memory block including a plurality of strings, each string including a first source selection transistor, a second source selection transistor, a plurality of memory cells, and a drain selection transistor connected in sequence; a control circuit configured to perform a pre-programming operation on the selection transistors included in the string, and configured to perform an erase operation and a fine programming operation on at least one of the selection transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating a memory device according to an embodiment.

[0008] Figure 2 It is shown Figure 1 The circuit diagram of the memory block is shown.

[0009] Figure 3 is a diagram showing a string coupled to a bit line according to an embodiment.

[0010] Figure 4 is a flowchart illustrating a method of forming a threshold voltage distribution of a selection transistor according to an embodiment.

[0011] Figure 5 is a flowchart illustrating a method of performing a pre-programming operation on a source selection transistor according to an embodiment.

[0012] Figure 6 It shows that when according to Figure 5 FIG. 1 is a diagram showing changes in the threshold voltage distribution of the source select transistor when a pre-programming operation is performed on the source select transistor during a process of performing a pre-programming operation on the source select transistor.

[0013] Figure 7 is a flowchart illustrating a method of performing a pre-programming operation on a source selection transistor according to an embodiment.

[0014] Figure 8 It shows that when according to Figure 7 FIG. 1 is a diagram showing changes in the threshold voltage distribution of the source select transistor when a pre-programming operation is performed on the source select transistor during a process of performing a pre-programming operation on the source select transistor.

[0015] Fig. 9 is a flowchart illustrating a method of performing a pre-programming operation on a drain selection transistor according to an embodiment.

[0016] Fig.10 It shows that when according to Fig. 9 FIG. 1 is a diagram showing changes in the threshold voltage distribution of the drain select transistor when a pre-programming operation is performed on the drain select transistor during a process of performing a pre-programming operation on the drain select transistor.

[0017] Fig.11 is a flowchart illustrating a method of performing an erase operation and a fine program operation on a drain selection transistor according to an embodiment.

[0018] Fig.12 It shows that when according to Fig.11 FIG. 1 is a diagram showing changes in threshold voltage distribution of drain select transistors when an erase operation and a fine program operation are performed on the drain select transistors during a process of performing an erase operation and a fine program operation on the drain select transistors.

[0019] Fig.13 is a flowchart illustrating a method of forming a threshold voltage distribution of a selection transistor according to an embodiment.

[0020] Fig.14 is a flowchart illustrating a method of performing an erase operation and a fine program operation on a second source selection transistor according to an embodiment.

[0021] Fig.15 It shows that when according to Fig.14 FIG. 1 is a diagram showing changes in the threshold voltage distribution of the source select transistor when an erase operation and a fine program operation are performed on the second source select transistor during a process of performing an erase operation and a fine program operation on the second source select transistor.

[0022] Fig.16 is a flowchart illustrating a method of forming a threshold voltage distribution of a selection transistor according to an embodiment.

[0023] Fig.17 is a diagram used to describe a slow transistor.

[0024] Fig.18 is a flowchart illustrating a method of forming a threshold voltage distribution of a selection transistor according to an embodiment.

[0025] Fig.19 is a flowchart illustrating a method of performing an erase operation, a second pre-program operation, a slow transistor masking operation, and a fine program operation on a drain selection transistor according to an embodiment.

[0026] Fig. 20 is a graph showing changes in threshold voltage distribution of a drain select transistor when an erase operation, a second pre-program operation, a slow transistor masking operation, and a fine program operation are performed on the drain select transistor according to an embodiment.

[0027] Fig.21 is a flowchart illustrating a method of performing an erase operation, a second pre-program operation, a slow transistor masking operation, and a fine program operation on a second source select transistor according to an embodiment. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings.

[0029] Figure 1 is a block diagram showing a memory device 10 according to an embodiment.

[0030] Reference Figure 1 , the memory device may operate under the control of an external device (eg, a controller). The operation of the memory device may include a read operation, a write operation, an erase operation, and the like.

[0031] The memory device may include various types of memory, such as NAND flash memory, 3D NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), or spin transfer torque random access memory (STT-RAM).

[0032] The memory device 10 may include a data storage area 11 and a control circuit 12. The data storage area 11 may include a plurality of memory blocks MB1 to MBk.

[0033] Figure 2 It is shown Figure 1 The circuit diagram of the memory block MB1 is shown in FIG. Figure 1 Each of the memory blocks MB1 to MBk can be connected to Figure 2 The memory block MB1 shown is constructed similarly.

[0034] Reference Figure 2 , the memory block MB1 may include strings ST11 to ST1m and ST21 to ST2m. Each of the strings ST11 to ST1m and ST21 to ST2m may extend in a vertical direction (ie, a Z direction). m strings may be arranged in a row direction (ie, an X direction) within the memory block MB1. Figure 2 Two strings arranged in the column direction (ie, the Y direction) are shown, but this is for convenience of description. Three or more strings may be arranged in the column direction (ie, the Y direction).

[0035] The strings ST11 to ST1m and ST21 to ST2m may be constructed identically. For example, the string ST11 may include a source selection transistor SST, memory cells MC1 to MCn, and a drain selection transistor DST connected in series between a source line SL and a bit line BL1. The source of the source selection transistor SST may be connected to the source line SL. The drain of the drain selection transistor DST may be connected to the bit line BL1. The memory cells MC1 to MCn may be connected in series between the source selection transistor SST and the drain selection transistor DST. According to an embodiment, the strings ST11 to ST1m and ST21 to ST2m may each include a plurality of drain selection transistors connected in series in series. According to an embodiment, the strings ST11 to ST1m and ST21 to ST2m may each include a plurality of source selection transistors connected in series in series in series.

[0036] The gates of the source select transistors of the strings arranged in the same row may be coupled to the same source select line. For example, the gates of the source select transistors of the strings ST11 to ST1m in the first row may be coupled to the source select line SSL1. For example, the gates of the source select transistors of the strings ST21 to ST2m in the second row may be coupled to the source select line SSL2. In another embodiment, the source select transistors of the strings ST11 to ST1m and ST21 to ST2m may be commonly coupled to one source select line.

[0037] The gates of the drain selection transistors of the strings arranged in the same row may be coupled to the same drain selection line. For example, the gates of the drain selection transistors of the strings ST11 to ST1m in the first row may be coupled to the drain selection line DSL1. For example, the gates of the drain selection transistors of the strings ST21 to ST2m in the second row may be coupled to the drain selection line DSL2.

[0038] Strings arranged in the same column may be coupled to the same bit line. For example, strings ST11 and ST21 in the first column may be coupled to the bit line BL1. For example, strings ST1m and ST2m in the mth column may be coupled to the bit line BLm.

[0039] The gates of the memory cells at the same position in the vertical direction (i.e., the same height in the Z direction) may be connected to the same word line. For example, in the strings ST11 to ST1m and ST21 to ST2m, the memory cells at the same position in the direction perpendicular to the memory cell MC1 (i.e., on the same XY plane) may be connected to the word line WL1.

[0040] Memory cells connected to the same word line in the same row among the memory cells may constitute a memory region. For example, memory cells connected to the word line WL1 in the first row may constitute a memory region MR11. For example, memory cells connected to the word line WL1 in the second row may constitute a memory region MR12. For example, memory cells connected to the word line WL2 in the first row may constitute a memory region MR21. Each word line may be connected to a plurality of memory regions according to the number of rows. Memory cells constituting one memory region may be programmed simultaneously.

[0041] Figure 3 is a diagram showing strings ST1 to ST8 coupled to a bit line BL according to an embodiment. Figure 3 The numbers of components shown may be examples.

[0042] Reference Figure 3, the bit line BL may be connected to the strings ST1 to ST8. The strings ST1 to ST8 may be similarly constructed. The string ST1 is described as an example. The string ST1 may include a first source selection transistor SST1, a second source selection transistor SST2, one or more memory cells MC, and a drain selection transistor DST, which are sequentially connected between the source line SL and the bit line BL. The first source selection transistor SST1 may be closer to the source line SL than the second source selection transistor SST2. The first source selection transistor SST1 may connect the second source selection transistor SST2 to the source line SL. The second source selection transistor SST2 may be closer to the memory cell MC than the first source selection transistor SST1. The second source selection transistor SST2 may connect the memory cell MC adjacent to the second source selection transistor SST2 to the first source selection transistor SST1. In string ST1, the first source select transistor SST1 may be connected to the first source select line SSL11, the second source select transistor SST2 may be connected to the second source select line SSL12, the memory cells MC may be respectively connected to one or more word lines WL, and the drain select transistor DST may be connected to the drain select line DSL1.

[0043] The strings ST1 to ST8 may be grouped into string groups STG1 to STG4, each of which includes two strings. The two strings included in each of the string groups STG1 to STG4 may share a first source selection line and a second source selection line. For example, the first source selection transistor SST1 included in the string group STG1 may be commonly connected to the first source selection line SSL11. The second source selection transistor SST2 included in the string group STG1 may be commonly connected to the second source selection line SSL12.

[0044] Similar to the programming operation for the memory cell, a programming operation may be performed on the selection transistor (i.e., the first source selection transistor SST1, the second source selection transistor SST2, or the drain selection transistor DST). For example, when a programming voltage is applied to the drain selection line DSL1, a charge may be injected into the floating gate of the drain selection transistor DST, and the threshold voltage of the drain selection transistor DST may be increased. In this case, when a voltage higher than the threshold voltage of the drain selection transistor DST is applied to the drain selection line DSL1, the drain selection transistor DST may be turned on and the string ST1 may be connected to the bit line BL. In addition, when a voltage lower than the threshold voltage of the drain selection transistor DST is applied to the drain selection line DSL1, the drain selection transistor DST may be turned off and the string ST1 may not be connected to the bit line BL. Therefore, in order to correctly select and access the memory cell MC, it is necessary to fully control the turning on and off of the selection transistor. To this end, it may be important to form a threshold voltage distribution of the selection transistor within a predetermined range through the programming operation of the selection transistor.

[0045] The bit line BL may correspond to Figure 2 Each of the bit lines BL1 to BLm shown. Therefore, in the memory block MB1, the string ST1 connected to the bit lines BL1 to BLm may include a drain selection transistor DST commonly connected to the drain selection line DSL1. Similarly, in the memory block MB1, the string ST2 connected to the bit lines BL1 to BLm may include a drain selection transistor DST commonly connected to the drain selection line DSL2. Other selection transistors included in the memory block MB1 may be similarly constructed. Hereinafter, a method of performing a programming operation on a selection transistor in units of memory blocks in order to form a threshold voltage distribution of the selection transistor according to an embodiment will be described.

[0046] Return to reference Figure 1 The control circuit 12 can perform a pre-programming operation on the selection transistors (i.e., the first source selection transistor SST1, the second source selection transistor SST2, and the drain selection transistor DST) included in the string of the storage block, and can perform an erase operation and a fine programming operation on at least one selection transistor included in the string of the storage block.

[0047] Specifically, the pre-programming operation for the source selection transistor may include: a whole programming operation, which applies a programming voltage to all source selection transistors included in the string for a predetermined count while incrementally increasing the programming voltage; and an additional programming operation, which further applies the programming voltage to the second source selection transistor included in the string. In the additional programming operation, the programming voltage may not be applied to the first source selection transistor included in the string of the memory block.

[0048] More specifically, additional programming operations for the source selection transistor may include: a-1) an operation of applying a programming voltage to the second source selection transistor; a-2) an operation of verifying the threshold voltage of a target second source selection transistor among the second source selection transistors by using a first verification voltage; and a-3) an operation of repeating operations a-1) and a-2) while incrementally increasing the programming voltage until the pass count of the target second source selection transistor is greater than the reference pass count.

[0049] In addition, additional programming operations for the source selection transistor may also include: a-4) determining a new target second source selection transistor until the pass count is greater than the reference pass count; a-5) verifying the threshold voltage of the new target second source selection transistor by using a first verification voltage; and a-6) repeatedly performing operations a-1) and a-2) on the new target second source selection transistor while incrementally increasing the programming voltage until the pass count of the new target second source selection transistor is greater than the reference pass count.

[0050] A pre-programming operation for a drain selection transistor may include: b-1) an operation of applying a programming voltage to a target drain selection transistor included in a string; b-2) an operation of verifying a threshold voltage of the target drain selection transistor by using a first verification voltage; and b-3) an operation of repeating operations b-1) and b-2) while incrementally increasing the programming voltage until a failure count of the target drain selection transistor is less than a reference failure count.

[0051] In addition, the pre-programming operation for the drain selection transistor may also include: b-4) determining an operation of a new target drain selection transistor when the failure count is less than a reference failure count; and b-5) repeatedly performing operations b-1) and b-2) on the new target drain selection transistor while incrementally increasing the programming voltage until the failure count for the new target drain selection transistor is less than the reference failure count.

[0052] The erase operation and fine programming operation for the drain selection transistor may include: c-1) an operation of performing an erase operation on a target drain selection transistor included in a string; c-2) an operation of applying a programming voltage to the target drain selection transistor; c-3) an operation of verifying a threshold voltage of the target drain selection transistor by using a second verification voltage; c-4) an operation of controlling programming of a pass transistor among the target drain selection transistors so that programming is prohibited; and c-5) an operation of repeating operations c-2), c-3) and c-4) while incrementally increasing the programming voltage until a failure count for the target drain selection transistor is less than a reference failure count.

[0053] In addition, the erase operation and fine programming operation for the drain selection transistor may also include: c-6) determining a new target drain selection transistor until the failure count is less than a reference failure count; c-7) performing an erase operation on the new target drain selection transistor; and c-8) repeatedly performing operations c-2), c-3) and c-4) on the new target drain selection transistor while incrementally increasing the programming voltage until the failure count for the new target drain selection transistor is less than a reference failure count.

[0054] The erase operation and fine programming operation for the source selection transistor may include: d-1) an operation of performing an erase operation on a target second source selection transistor among the second source selection transistors included in the string; d-2) an operation of applying a programming voltage to the target second source selection transistor; d-3) an operation of verifying the threshold voltage of the target second source selection transistor by using a second verification voltage; d-4) an operation of controlling the programming of a pass transistor among the target second source selection transistor so that programming is prohibited; and d-5) an operation of repeating operations d-2), d-3) and d-4) while incrementally increasing the programming voltage until the failure count for the target second source selection transistor is less than a reference failure count.

[0055] In addition, the erase operation and fine programming operation for the source selection transistor may also include: d-6) an operation of determining a new target second source selection transistor when the failure count is less than a reference failure count; d-7) an operation of performing an erase operation on the new target second source selection transistor; and d-8) an operation of repeatedly performing operations d-2), d-3) and d-4) on the new target second source selection transistor while incrementally increasing the programming voltage until the failure count for the new target second source selection transistor is less than the reference failure count.

[0056] According to an embodiment, the control circuit 12 may perform a pre-programming operation (i.e., a first pre-programming operation) on the selection transistors included in the string of the memory block, and may sequentially perform an erase operation, a second pre-programming operation, a slow transistor masking operation, and a fine programming operation on a target selection transistor among the selection transistors. According to an embodiment, the selection transistor may be one of three types (i.e., a first source selection transistor SST1, a second source selection transistor SST2, and a drain selection transistor DST) included in the string of the memory block.

[0057] Specifically, the second pre-program operation may include an operation of applying a program voltage to the target selection transistor a predetermined number of times while incrementally increasing the program voltage.

[0058] The slow transistor masking operation may include: an operation of verifying a threshold voltage of a target selection transistor by using a third verification voltage; and an operation of masking a slow transistor among the target selection transistors using a pass transistor.

[0059] The fine programming operation may include: e-1) an operation of applying a programming voltage to a target selection transistor; e-2) an operation of verifying a threshold voltage of the target selection transistor by using a second verification voltage; e-3) an operation of controlling programming for a pass transistor among the target selection transistors so that programming is prohibited; and e-4) an operation of repeating operations e-1), e-2) and e-3) while incrementally increasing the programming voltage until a fail count for the target selection transistor is less than a reference fail count. In this case, the pass transistor may include a selection transistor among the target selection transistors whose threshold voltage is lower than the third verification voltage and a selection transistor whose threshold voltage is higher than the second verification voltage.

[0060] When the fail count is less than the reference fail count, the control circuit 12 may perform an operation of determining a new target selection transistor, and may further sequentially perform an erase operation, a second pre-program operation, a slow transistor masking operation, and a fine program operation on the new target selection transistor.

[0061] Figure 4 is a flowchart illustrating a method of forming a threshold voltage distribution of a selection transistor according to an embodiment.

[0062] Reference Figure 4 In operation S401 , the control circuit 12 may perform a pre-programming operation on source selection transistors SST included in a memory block, ie, first and second source selection transistors SST1 and SST2 .

[0063] In operation S402 , the control circuit 12 may perform a pre-programming operation on the drain selection transistor DST.

[0064] In operation S403 , the control circuit 12 may perform an erase operation and a fine program operation on the drain selection transistor DST.

[0065] Figure 5 is a flowchart illustrating a method of performing a pre-programming operation on a source selection transistor SST according to an embodiment. Figure 5 The process can be Figure 4 Detailed implementation of operation S401. Figure 6 It shows that when according to Figure 5 FIG. 1 is a graph showing changes in threshold voltage distribution of source selection transistors SST when a pre-programming operation is performed on source selection transistors SST during a process of performing a pre-programming operation on source selection transistors SST. Hereinafter, in the graph of threshold voltage distribution, the horizontal axis Vt may mean threshold voltage, and the vertical axis may mean the number of selection transistors.

[0066] Before performing the pre-programming operation, the source selection transistor SST may be formed Figure 6The initial threshold voltage distribution 61 may indicate the state of the source select transistor SST just after the memory device has been produced.

[0067] Reference Figure 5 In operations S501 to S504, the control circuit 12 may perform a whole program operation of applying a program voltage to all source selection transistors SST of the memory block a predetermined number of times while incrementally increasing the program voltage. The source selection transistor SST may be formed after operations S501 to S504 have been performed. Figure 6 The intermediate threshold voltage distribution 62 is shifted upward from the initial threshold voltage distribution 61.

[0068] Specifically, in operation S501 , the control circuit 12 may set a program loop count to 1.

[0069] In operation S502 , the control circuit 12 may simultaneously apply a program voltage to all source selection transistors SST of a memory block.

[0070] In operation S503, the control circuit 12 may determine whether the program loop count is greater than the reference loop count. When the program loop count is greater than the reference loop count, the process may proceed to operation S506. When the program loop count is less than or equal to the reference loop count, the process may proceed to operation S504.

[0071] In operation S504 , the control circuit 12 may increase the program voltage by a predetermined increment.

[0072] In operation S505 , the control circuit 12 may increase the program loop count by 1. The process may proceed to operation S502 .

[0073] In operations S506 to S512, the control circuit 12 may perform an additional programming operation of further applying a programming voltage to the second source selection transistor SST2 to raise the threshold voltage of the second source selection transistor SST2 to be closer to the first SST verification voltage VF_SST1. At this time, the programming voltage may not be applied to the first source selection transistor SST1. As a result, after operations S506 to S512 have been performed, the second source selection transistor SST2 may form Figure 664. Even if operations S506 to S512 have been performed, the first source selection transistor SST1 may form a threshold voltage distribution 63 similar to the intermediate threshold voltage distribution 62. The threshold voltage distribution 63 may be placed in a threshold voltage range lower than the threshold voltage distribution 64. Therefore, the first source selection transistor SST1 may be turned off in response to a voltage lower than the threshold voltage distribution 63, and may be turned on in response to a voltage higher than the threshold voltage distribution 63. That is, each of the first source selection transistors SST1 may be maintained to have a lower threshold voltage than each of the second source selection transistors SST2 to facilitate the turn-off of the first source selection transistor SST1, because the first source selection transistor SST1 is adjacent to the source line SL. The second source selection transistor SST2 may be turned off in response to a voltage lower than the threshold voltage distribution 64, and may be turned on in response to a voltage higher than the threshold voltage distribution 64.

[0074] Specifically, in operation S506, the control circuit 12 may set the target index to 1. According to an embodiment, the target index may be a string index corresponding to each of the strings ST1 to ST8. In this case, hereinafter, the target second source select transistor SST2 may be a second source select transistor SST2 of a string corresponding to the target index among the strings ST1 to ST8 connected to the first bit line BL1 to the mth bit line BLm. For example, when the target index is 1, the target second source select transistor SST2 may be a second source select transistor SST2 of a string ST1 connected to the first bit line BL1 to the mth bit line BLm, respectively, and the second source select transistor SST2 is commonly connected to the second source select line SSL12. According to an embodiment, the target index may be a string group index corresponding to each of the string groups STG1 to STG4. In this case, hereinafter, the target second source select transistor SST2 may be a second source select transistor SST2 of a string group corresponding to the target index among the string groups STG1 to STG4 connected to the first bit line BL1 to the mth bit line BLm.

[0075] In operation S507, the control circuit 12 may simultaneously apply a program voltage to all second source selection transistors SST2 of the memory block. In other words, operation S507 may be performed on all second source selection transistors SST2 of the memory block except the target second source selection transistor SST2.

[0076] In operation S508, the control circuit 12 may use Figure 6The first SST verification voltage VF_SST1 in the control circuit 12 is used to verify the threshold voltage of the target second source selection transistor SST2, and the read values ​​corresponding to the first bit line BL1 to the mth bit line BLm can be generated respectively. Specifically, the control circuit 12 can apply the first SST verification voltage VF_SST1 to the second source selection line connected to the target second source selection transistor SST2. The control circuit 12 can detect the state (i.e., current or voltage) of the first bit line BL1 to the mth bit line BLm derived by the target second source selection transistor SST2 in response to the first SST verification voltage VF_SST1, and can generate the detected values ​​as the read values ​​corresponding to the first bit line BL1 to the mth bit line BLm.

[0077] In operation S509, the control circuit 12 may determine whether the pass count is greater than the reference pass count. The control circuit 12 may determine the pass count based on the read value. The pass count may be the number of first values ​​(e.g., 0) among the read values. The pass count may be the number of second source select transistors SST2 whose threshold voltage among the target second source select transistors SST2 is higher than the first SST verification voltage VF_SST1. When the pass count is greater than the reference pass count, the pre-programming operation of the target second source select transistor SST2 may be terminated, and the process may proceed to operation S511. When the pass count is less than or equal to the reference pass count, the process may proceed to operation S510.

[0078] In operation S510, the control circuit 12 may increase the program voltage by a predetermined increment. In addition, the process may proceed to operation S507.

[0079] In operation S511, the control circuit 12 may determine whether the target index is the same as the reference index. When the target index is a string index, the reference index may be the number of strings ST1 to ST8 respectively connected to the bit line BL (i.e., 8). When the target index is a string group index, the reference index may be the number of string groups STG1 to STG4 respectively connected to the bit line BL (i.e., 4). When the target index is the same as the reference index, the process may terminate. When the target index is not the same as the reference index, the process may proceed to operation S512.

[0080] In operation S512, the control circuit 12 may increase the target index by 1. In addition, the process may proceed to operation S508, and the control circuit 12 may perform a pre-programming operation on the target second source selection transistor SST2 of the subsequent string. That is, the control circuit 12 may determine the second source selection transistor SST2 of the subsequent string as a new target second source selection transistor SST2, and may perform a pre-programming operation on the new target second source selection transistor SST2.

[0081] As a result of the above operation, only some (at least one) of the second source selection transistors SST2 may have a threshold voltage higher than the first SST verification voltage VF_SST1, and the threshold voltage of each second source selection transistor SST2 may not be excessively higher than the first SST verification voltage VF_SST1. As a result, the conduction of the source selection transistors SST coupled to the selected string may be effectively controlled so that the selected string may be fully coupled to the source line SL.

[0082] Figure 7 is a flowchart illustrating a method of performing a pre-programming operation on a source selection transistor SST according to an embodiment. Figure 7 The flowchart can be Figure 4 Detailed implementation of operation S401 in . Figure 8 It shows that when according to Figure 7 1 is a diagram showing changes in the threshold voltage distribution of the source select transistor SST when a pre-programming operation is performed on the source select transistor SST during a process of performing a pre-programming operation on the source select transistor SST.

[0083] Before performing the pre-programming operation, the source selection transistor SST may be formed Figure 8 The initial threshold voltage distribution 81.

[0084] In operations S701 to S707, the control circuit 12 may apply a programming voltage only to the second source selection transistor SST2 to increase the threshold voltage of the second source selection transistor SST2 to be closer to the first SST verification voltage VF_SST1. At this time, the programming voltage may not be applied to the first source selection transistor SST1. Operations S701 to S707 may be performed in accordance with Figure 5 Operations S506 to S512 in are performed in a similar manner.

[0085] In operations S708 to S714, the control circuit 12 may apply a programming voltage only to the first source selection transistor SST1 to increase the threshold voltage of the first source selection transistor SST1 to be closer to the first SST verification voltage VF_SST1. At this time, the programming voltage may not be applied to the second source selection transistor SST2. In addition to performing a pre-programming operation on the first source selection transistor SST1 instead of the second source selection transistor SST2, operations S708 to S714 may be performed in accordance with Figure 5 According to an embodiment, operations S708 to S714 may be performed earlier than operations S701 to S707.

[0086] After operations S701 to S714 have been performed, the source selection transistor SST may be formed. Figure 8Therefore, the source selection transistor SST may be turned off in response to a voltage lower than the threshold voltage distribution 82, and may be turned on in response to a voltage higher than the threshold voltage distribution 82.

[0087] Fig. 9 is a flowchart illustrating a method of performing a pre-programming operation on a drain selection transistor DST according to an embodiment. Fig. 9 The process can be Figure 4 Detailed implementation of operation S402 in . Fig.10 It shows that when according to Fig. 9 1 is a diagram showing changes in the threshold voltage distribution of the drain select transistor DST when a pre-programming operation is performed on the drain select transistor DST during a process of performing a pre-programming operation on the drain select transistor DST.

[0088] Before performing a pre-programming operation, the drain select transistor DST may be formed Fig.10 An initial threshold voltage distribution 101 is provided.

[0089] Reference Fig. 9 In operations S901 to S907, the control circuit 12 may apply a programming voltage to the target drain selection transistor DST to raise the threshold voltage of the target drain selection transistor DST to be closer to the first DST verification voltage VF_DST1. After operations S1201 to S1207 have been performed, the target drain selection transistor DST may be formed. Fig.10 Therefore, the target drain selection transistor DST may be turned off in response to a voltage lower than the threshold voltage distribution 102, and may be turned on in response to a voltage higher than the threshold voltage distribution 102.

[0090] Specifically, in operation S901, the control circuit 12 may set the target index to 1. The target index may be a string index. Therefore, hereinafter, the target drain selection transistor DST may be a drain selection transistor DST of a string corresponding to the target index among the strings ST1 to ST8 connected to the first bit line BL1 to the mth bit line BLm. For example, when the target index is 1, the target drain selection transistor DST may be a drain selection transistor DST of the string ST1 connected to the first bit line BL1 to the mth bit line BLm, respectively, and the drain selection transistors DST are commonly connected to the drain selection line DSL1.

[0091] In operation S902, the control circuit 12 may apply a program voltage to a drain selection line coupled to the target drain selection transistor DST. At this time, the program voltage may not be applied to the remaining drain selection transistors DST except the target drain selection transistor DST.

[0092] In operation S903, the control circuit 12 can use Fig.10The control circuit 12 may verify the threshold voltage of the target drain selection transistor DST by using the first DST verification voltage VF_DST1 in the control circuit 12, and may generate read values ​​corresponding to the first bit line BL1 to the mth bit line BLm, respectively. Specifically, the control circuit 12 may apply the first DST verification voltage VF_DST1 to the drain selection line connected to the target drain selection transistor DST. The control circuit 12 may detect the state (i.e., current or voltage) of the first bit line BL1 to the mth bit line BLm derived by the target drain selection transistor DST in response to the first DST verification voltage VF_DST1, and may generate the detected values ​​as read values ​​corresponding to the first bit line BL1 to the mth bit line BLm, respectively.

[0093] In operation S904, the control circuit 12 may determine whether the fail count is less than the reference fail count. The control circuit 12 may determine the fail count based on the read value. The fail count may be the number of second values ​​(e.g., 1) among the read values. The fail count may be the number of drain select transistors DST whose threshold voltage among the target drain select transistors DST is lower than the first DST verification voltage VF_DST1. When the fail count is less than the reference fail count, the pre-programming operation for the target drain select transistor DST may be terminated, and the process may proceed to operation S906. When the fail count is equal to or greater than the reference fail count, the process may proceed to operation S905.

[0094] In operation S905, the control circuit 12 may increase the program voltage by a predetermined increment. In addition, the process may proceed to operation S902.

[0095] In operation S906, the control circuit 12 may determine whether the target index is the same as the reference index. When the target index is a string index, the reference index may be the number of strings ST1 to ST8 respectively connected to the bit line BL (i.e., 8). When the target index is the same as the reference index, the process may terminate. When the target index is not the same as the reference index, the process may proceed to operation S907.

[0096] In operation S907 , the control circuit 12 may increase the target index by 1. Furthermore, the process may proceed to operation S902 , and the control circuit 12 may perform a pre-programming operation on the target drain select transistor DST of the subsequent string.

[0097] As a result of the above operation, only some (at least one) of the target drain selection transistors DST may have a threshold voltage lower than the first DST verification voltage VF_DST1. As a result, the cutoff of the drain selection transistors DST connected to the unselected string can be effectively controlled so that the unselected string is not connected to the bit line BL.

[0098] Fig.11is a flowchart illustrating a method of performing an erase operation and a fine program operation on a drain select transistor DST according to an embodiment. Fig.11 The flowchart can be Figure 4 Detailed implementation of operation S403 in . Fig.12 It shows that when according to Fig.11 FIG. 1 is a diagram showing changes in the threshold voltage distribution of the drain select transistor DST when an erase operation and a fine program operation are performed on the drain select transistor DST.

[0099] Reference Fig.12 , after performing the pre-programming operation and before performing the erase operation, the drain selection transistor DST can be as shown in FIG. Fig.10 The threshold voltage distribution 102 is formed.

[0100] Reference Fig.11 In operations S1101 to S1109, the control circuit 12 may perform an erase operation and a fine program operation on the drain selection transistor DST so that the drain selection transistor DST forms Fig.12 The narrow threshold voltage distribution 122 of the drain select transistor 124 is shown in FIG. 1. As a result, the turning on and off of the drain select transistor 124 can be finely controlled.

[0101] Specifically, in operation S1101 , the control circuit 12 may set the target index to 1.

[0102] In operation S1102, the control circuit 12 may perform an erase operation on the target drain select transistor DST. After the erase operation has been performed, the target drain select transistor DST may form Fig.12 The threshold voltage distribution 121.

[0103] In operation S1103, the control circuit 12 may apply a program voltage to a drain selection line coupled to the target drain selection transistor DST. At this time, the program voltage may not be applied to the remaining drain selection transistors DST except the target drain selection transistor DST.

[0104] In operation S1104, the control circuit 12 may verify the threshold voltage of the target drain selection transistor DST by using the second DST verification voltage VF_DST2, and may generate read values ​​corresponding to the first to m-th bit lines BL1 to BLm, respectively. The second DST verification voltage VF_DST2 used in the fine programming operation may be the same as or different from the first SST verification voltage VF_SST1 used in the pre-programming operation.

[0105] In operation S1105, the control circuit 12 may control programming for the pass transistor to be inhibited based on the read value. The pass transistor may be a drain select transistor DST corresponding to the read value having a first value (e.g., 0) among the target drain select transistors DST. The pass transistor may be a drain select transistor DST having a threshold voltage higher than the second DST verification voltage VF_DST2 among the target drain select transistors DST.

[0106] In operation S1106, the control circuit 12 may determine whether the fail count is less than the reference fail count. The control circuit 12 may determine the fail count based on the read value. The fail count may be the number of second values ​​(e.g., 1) among the read values. The fail count may be the number of drain select transistors DST whose threshold voltage among the target drain select transistors DST is lower than the second DST verification voltage VF_DST2. When the fail count is less than the reference fail count, the fine programming operation for the target drain select transistor DST may be terminated, and the process may proceed to operation S1108. At this point, the drain select transistor DST that has not yet performed the erase operation and the fine programming operation may still form the threshold voltage distribution 102. When the fail count is equal to or greater than the reference fail count, the process may proceed to operation S1107.

[0107] In operation S1107, the control circuit 12 may increase the programming voltage by a predetermined increment. In addition, the process may proceed to operation S1103. In this case, in operation S1103, when the programming voltage is applied to the target drain selection transistor DST again, the control circuit 12 may control the pass transistor by applying a program inhibition voltage having a high level to the bit line connected to the pass transistor so that the pass transistor is not affected by the programming voltage. Therefore, the threshold voltage of each target drain selection transistor DST may be prevented from rising to excessively higher than the second DST verification voltage VF_DST2.

[0108] In operation S1108, the control circuit 12 may determine whether the target index is the same as the reference index. When the target index is the same as the reference index, the process may terminate. When the target index is not the same as the reference index, the process may proceed to operation S1109.

[0109] In operation S1109, the control circuit 12 may increase the target index by 1. In addition, the process may proceed to operation S1102, and the control circuit 12 may perform an erase operation and a fine program operation on the target drain select transistor DST of the subsequent string. That is, the control circuit 12 may determine the drain select transistor DST of the subsequent string as a new target drain select transistor DST, and may perform an erase operation and a fine program operation on the new target drain select transistor DST.

[0110] After performing an erase operation on the target drain select transistor DST, the target drain select transistor DST may form a threshold voltage distribution 121. At this time, the drain select transistor DST on which the erase operation has not been performed may still form a threshold voltage distribution 102, and may be turned off in response to a voltage lower than the threshold voltage distribution 102. Therefore, an erase operation and a fine program operation for the target drain select transistor DST may be effectively performed without being affected by the drain select transistor DST on which the erase operation and the fine program operation have not been performed.

[0111] Fig.13 is a flowchart illustrating a method of forming a threshold voltage distribution of a selection transistor according to an embodiment.

[0112] Reference Fig.13 In operation S1301, the control circuit 12 may perform a pre-programming operation on the source selection transistor SST. Operation S1301 may be performed in accordance with Figure 4 The operation S401 is performed in a similar manner.

[0113] In operation S1302, the control circuit 12 may perform a pre-programming operation on the drain selection transistor DST. Operation S1302 may be performed in accordance with Figure 4 According to an embodiment, operation S1302 may be performed earlier than operation S1301.

[0114] In operation S1303, the control circuit 12 may perform an erase operation and a fine programming operation on the selected source selection transistor SST. The selected source selection transistor SST may be a second source selection transistor SST2 in addition to the first source selection transistor SST1. According to an embodiment, when three or more source selection transistors are connected in series to each string, the selected source selection transistor may be the source selection transistor closest to the memory cell MC in each string.

[0115] Fig.14 is a flowchart illustrating a method of performing an erase operation and a fine program operation on the second source select transistor SST2 according to an embodiment. Fig.14 The flowchart can be Fig.13 Detailed implementation of operation S1303 in . Fig.15 It shows that when according to Fig.14 2 is a diagram showing changes in the threshold voltage distribution of the source select transistor SST when an erase operation and a fine program operation are performed on the second source select transistor SST2.

[0116] Reference Fig.15 , after the pre-programming operation has been performed and before the erase operation is performed, as shown in Figure 6As described, the first source select transistor SST1 may form a threshold voltage distribution 63 , and the second source select transistor SST2 may form a threshold voltage distribution 64 .

[0117] Reference Fig.14 In operations S1401 to S1409, the control circuit 12 may perform an erase operation and a fine programming operation on the second source selection transistor SST2 so that the second source selection transistor SST2 forms Fig.15 As a result, the turn-on and turn-off of the second source selection transistor SST2 can be finely controlled. The first source selection transistor SST1 can maintain the threshold voltage distribution 63. In addition to performing an erase operation and a fine programming operation on the second source selection transistor SST2 instead of the drain selection transistor DST, and using the second SST verification voltage VF_SST2 instead of the second DST verification voltage VF_DST2, operations S1401 to S1409 can be performed in accordance with Fig.11 Operations S1101 to S1109 are performed in a similar manner.

[0118] Specifically, in operation S1401, the control circuit 12 may set the target index to 1. According to an embodiment, the target index may be a string index. In this case, hereinafter, the target second source select transistor SST2 may be a second source select transistor SST2 of a string corresponding to the target index among the strings ST1 to ST8 connected to the first bit line BL1 to the mth bit line BLm. According to an embodiment, the target index may be a string group index. In this case, hereinafter, the target second source select transistor SST2 may be a second source select transistor SST2 of a string group STG1 to STG4 corresponding to the target index among the string groups STG1 to STG4 connected to the first bit line BL1 to the mth bit line BLm.

[0119] In operation S1402, the control circuit 12 may perform an erase operation on the target second source selection transistor SST2. After the erase operation has been performed, the target second source selection transistor SST2 may form Fig.15 The threshold voltage distribution 151.

[0120] In operation S1403, the control circuit 12 may apply a program voltage to a second source selection line coupled to the target second source selection transistor SST2. At this time, the program voltage may not be applied to the remaining second source selection transistors SST2 except the target second source selection transistor SST2.

[0121] In operation S1404, the control circuit 12 may verify the threshold voltage of the target second source selection transistor SST2 by using the second SST verification voltage VF_SST2, and may generate read values ​​corresponding to the first to m-th bit lines BL1 to BLm, respectively. The second SST verification voltage VF_SST2 used in the fine programming operation may be the same as or different from the first SST verification voltage VF_SST1 used in the pre-programming operation.

[0122] In operation S1405, the control circuit 12 may control programming for the pass transistor to be inhibited based on the read value. The pass transistor may be a second source select transistor SST2 corresponding to the read value having a first value (e.g., 0) among the target second source select transistors SST2. The pass transistor may be a second source select transistor SST2 having a threshold voltage higher than the second SST verification voltage VF_SST2 among the target second source select transistors SST2.

[0123] In operation S1406, the control circuit 12 may determine whether the fail count is less than the reference fail count. The control circuit 12 may determine the fail count based on the read value. The fail count may be the number of second values ​​(e.g., 1) among the read values. The fail count may be the number of second source select transistors SST2 whose threshold voltage among the target second source select transistors SST2 is lower than the second SST verification voltage VF_SST2. When the fail count is less than the reference fail count, the fine programming operation for the target second source select transistor SST2 may be terminated, and the process may proceed to operation S1408. At this point, the second source select transistor SST2, which has not yet performed the erase operation and the fine programming operation, may still form a threshold voltage distribution 64. When the fail count is equal to or greater than the reference fail count, the process may proceed to operation S1407.

[0124] In operation S1407, the control circuit 12 may increase the programming voltage by a predetermined increment. In addition, the process may proceed to operation S1403. In this case, in operation S1403, when the programming voltage is applied to the target second source selection transistor SST2 again, the control circuit 12 may control the pass transistor to be unaffected by the programming voltage by applying a program inhibition voltage having a high level to the bit line connected to the pass transistor. Therefore, the threshold voltage of each target second source selection transistor SST2 may be prevented from rising to excessively higher than the second SST verification voltage VF_SST2.

[0125] In operation S1408, the control circuit 12 may determine whether the target index is the same as the reference index. When the target index is the same as the reference index, the process may terminate. When the target index is not the same as the reference index, the process may proceed to operation S1409.

[0126] In operation S1409, the control circuit 12 may increase the target index by 1. In addition, the process may proceed to operation S1402, and the control circuit 12 may perform an erase operation and a fine program operation on the target second source selection transistor SST2 of the subsequent string. That is, the control circuit 12 may determine the second source selection transistor SST2 of the next string as a new target second source selection transistor SST2, and may perform an erase operation and a fine program operation on the new target second source selection transistor SST2.

[0127] As a result, programming for the pass transistors may be inhibited, and only some (at least one) of the target second source selection transistors SST2 have a threshold voltage lower than the second SST verification voltage VF_SST2. Fig.15 A narrow threshold voltage distribution 152 is provided.

[0128] If the source select transistor SST is formed Figure 6 If a fine programming operation is performed immediately while the initial threshold voltage distribution 61 is being formed, the cut-off of the source selection transistor SST may not be correctly controlled. Therefore, it may be difficult to correctly perform the erase operation and the fine programming operation only on the target second source selection transistor SST2. However, while the erase operation in operation S1402 and the fine programming operation in operations S1403 to S1407 are performed on the target second source selection transistor SST2, the second source selection transistor SST2, which has not yet performed the erase operation and the fine programming operation, has a high threshold voltage while forming the threshold voltage distribution 64. Therefore, the second source selection transistor SST2 can certainly be cut off in response to a voltage lower than the threshold voltage distribution 64. Similarly, the first source selection transistor SST1 connected to the second source selection transistor SST2, which has not yet performed the erase operation and the fine programming operation, can be cut off in response to a voltage lower than the threshold voltage distribution 63 because the first source selection transistor SST1 has formed the threshold voltage distribution 63. Therefore, an erase operation and a fine program operation with respect to the target second source select transistor SST2 may be efficiently performed without being affected by the second source select transistor SST2 on which the erase operation and the fine program operation have not been performed.

[0129] Fig.16 is a flowchart illustrating a method of forming a threshold voltage distribution of a selection transistor according to an embodiment.

[0130] Reference Fig.16 In operation S1601, the control circuit 12 may perform a pre-programming operation on the source selection transistor SST. Operation S1601 may be performed in accordance with Figure 4 The operation S401 is performed in a similar manner.

[0131] In operation S1602, the control circuit 12 may perform a pre-programming operation on the drain selection transistor DST. Operation S1602 may be performed in accordance with Figure 4 According to an embodiment, operation S1602 may be performed earlier than operation S1601.

[0132] In operation S1603, the control circuit 12 may perform an erase operation and a fine program operation on the drain selection transistor DST. Operation S1603 may be performed in accordance with Figure 4 Operation S403 is performed in a similar manner.

[0133] In operation S1604, the control circuit 12 may perform an erase operation and a fine program operation on the selected source selection transistor SST. Operation S1604 may be performed in accordance with Fig.13 The operation S1604 may be performed in a similar manner to the operation S1303. According to an embodiment, the operation S1604 may be performed earlier than the operation S1603.

[0134] Fig.17 is a diagram used to describe a slow transistor.

[0135] Reference Fig.17 For example, when a fine programming operation is performed on the drain selection transistor DST, since the threshold voltage of the slow transistor 173 rarely rises even if a programming voltage is applied to the slow transistor 173, the threshold voltage of the slow transistor 173 may form a long-tail distribution. Therefore, although a normal transistor other than the slow transistor 173 forms a narrow threshold voltage distribution 171 as a pass transistor, the slow transistor 173 does not satisfy the threshold voltage distribution 171. Fig.11 The failure count condition in operation S1106 may be repeated unnecessarily. Fig.11 Operation S1107.

[0136] In this case, there is a problem in that the pass transistor may also be indirectly affected by the program voltage, and the threshold voltage distribution 172 having a wider voltage range than the threshold voltage distribution 171 may be formed.

[0137] Fig.18 is a flowchart illustrating a method of forming a threshold voltage distribution of a selection transistor according to an embodiment.

[0138] Reference Fig.18 In operation S1801, the control circuit 12 may perform a pre-programming operation on the source selection transistor SST. Operation S1801 may be performed in accordance with Figure 4 The operation S401 is performed in a similar manner.

[0139] In operation S1802, the control circuit 12 may perform a pre-programming operation on the drain selection transistor DST. Operation S1802 may be performed in accordance with Figure 4 According to an embodiment, operation S1802 may be performed earlier than operation S1801.

[0140] In operation S1803 , the control circuit 12 may perform an erase operation, a second pre-program operation, a slow transistor masking operation, and a fine program operation on the drain selection transistor DST.

[0141] In operation S1804, the control circuit 12 may perform an erase operation, a second pre-program operation, a slow transistor masking operation, and a fine program operation on the selected source selection transistor SST. According to an embodiment, operation S1804 may be performed earlier than operation S1803.

[0142] According to an embodiment, any one of operations S1803 and S1804 may be omitted.

[0143] Fig.19 is a flowchart illustrating a method of performing an erase operation, a second pre-program operation, a slow transistor masking operation, and a fine program operation on a drain select transistor DST according to an embodiment. Fig.19 The flowchart can be Fig.18 Detailed implementation of operation S1803. Fig. 20 It shows that when according to Fig.19 1 is a diagram showing changes in the threshold voltage distribution of the drain select transistor DST when an erase operation, a second pre-program operation, a slow transistor masking operation, and a fine program operation are performed on the drain select transistor DST.

[0144] Reference Fig. 20 , before performing an erase operation after a pre-programming operation has been performed, the drain select transistor DST may be as shown in FIG. Fig.10 The threshold voltage distribution 102 is formed.

[0145] Reference Fig.19 In operations S1901 to S1916, the control circuit 12 may perform an erase operation, a second pre-programming operation, a slow transistor masking operation, and a fine programming operation on the drain selection transistor DST so that the drain selection transistor DST forms Fig. 20 As a result, the on and off of the drain selection transistor DST can be finely controlled. In particular, the control circuit 12 can utilize the transistor masking through the second pre-programming operation and the slow transistor masking operation to achieve the desired effect. Fig. 20 The slow transistor 203 is used to prevent unnecessary application of the programming voltage.

[0146] Specifically, in operation S1901, the control circuit 12 may set the target index to 1. The target index may be a string index.

[0147] In operation S1902, the control circuit 12 may perform an erase operation on the target drain selection transistor DST. After the erase operation has been performed, the target drain selection transistor DST may form Fig. 20 The threshold voltage distribution 201.

[0148] In operations S1903 to S1907, the control circuit 12 may perform a second pre-programming operation on the target drain selection transistor DST. After the second pre-programming operation has been performed, the target drain selection transistor DST may form Fig. 20 The intermediate threshold voltage distribution 202 of FIG. 202 may be performed to slightly increase the threshold voltage of the target drain select transistor DST so as to determine a slow transistor.

[0149] Specifically, in operation S1903 , the control circuit 12 may set the program loop count to 1.

[0150] In operation S1904, the control circuit 12 may apply a program voltage to a drain selection line coupled to the target drain selection transistor DST. At this time, the program voltage may not be applied to the remaining drain selection transistors DST except the target drain selection transistor DST.

[0151] In operation S1905, the control circuit 12 may determine whether the program loop count is greater than the reference loop count. When the program loop count is greater than the reference loop count, the process may proceed to operation S1908. When the program loop count is less than or equal to the reference loop count, the process may proceed to operation S1906.

[0152] In operation S1906, the control circuit 12 may increase the program voltage by a predetermined increment.

[0153] In operation S1907, the control circuit 12 may increase the program loop count by 1. The process may proceed to operation S1904.

[0154] In operations S1908 to S1909 , the control circuit 12 may perform a slow transistor masking operation on the target drain selection transistor DST.

[0155] Specifically, in operation S1908 , the control circuit 12 may verify the threshold voltage of the target drain selection transistor DST by using the third DST verification voltage VF_DST3 , and may generate read values ​​corresponding to the first to m-th bit lines BL1 to BLm, respectively.

[0156] In operation S1909, the control circuit 12 may mask the slow transistor with a pass transistor. The slow transistor may be a drain selection transistor DST corresponding to a read value having a second value (e.g., 1) among the target drain selection transistors DST. The slow transistor may be a drain selection transistor DST having a threshold voltage lower than a third DST verification voltage VF_DST3 among the target drain selection transistors DST. Masking the slow transistor with a pass transistor may mean that the slow transistor is treated as a pass transistor.

[0157] In operations S1910 to S1914, the control circuit 12 may perform a fine programming operation on the target drain selection transistor DST. After the fine programming operation has been performed, the target drain selection transistor DST may form Fig. 20 The threshold voltage distribution 204 of FIG. 104 may be formed by the drain selection transistors DST that have not yet performed the erase operation, the second pre-programming operation, the slow transistor masking operation, and the fine programming operation.

[0158] Operations S1910 to S1916 may be performed in accordance with Fig.11 Since the slow transistors are also masked with the pass transistors in operation S1909, the pass transistors may include the drain select transistors DST having a threshold voltage higher than the second DST verification voltage VF_DST2 and the drain select transistors DST having a threshold voltage lower than the third DST verification voltage VF_DST3 among the target drain select transistors DST in operation S1912.

[0159] According to an embodiment, when two or more drain select transistors are connected in series to each string, the operation that has been performed on the drain select transistor DST in the present disclosure may be similarly applied to each drain select transistor.

[0160] Fig.21 is a flowchart illustrating a method of performing an erase operation, a second pre-program operation, a slow transistor masking operation, and a fine program operation on the second source select transistor SST2 according to an embodiment. Fig.21 The flowchart can be Fig.18 Detailed implementation of operation S1804 in .

[0161] In addition to performing the erase operation, the second pre-programming operation, the slow transistor masking operation, and the fine programming operation on the second source selection transistor SST2 instead of the drain selection transistor DST, and using the third SST verification voltage VF_SST3 instead of the third DST verification voltage VF_DST3, operations S2101 to S2116 may be performed in accordance with Fig.19 Operations S1901 to S1916 are performed in a similar manner.

[0162] According to an embodiment, when three or more source select transistors are connected in series to each string, the operation that has been performed on the second source select transistor SST2 in the present disclosure may be similarly applied to a source select transistor closest to the memory cell MC among the three or more source select transistors.

[0163] The memory device and the method of operating the memory device according to the embodiments may effectively form a threshold voltage distribution of a selection transistor.

[0164] The above description is only a description of the technical spirit of the present technology. Without departing from the basic characteristics of the present technology, those skilled in the art can change and modify the present technology in various ways. Therefore, the disclosed embodiments should not be interpreted as limiting the technical spirit of the present technology, but should be interpreted as describing the technical spirit of the present technology. The technical spirit of the present technology is not limited by the implementation method. The protection scope of the present technology should be interpreted based on the following claims, and all technical spirits within the equivalent scope of the present technology should be interpreted as included in the scope of rights of the present technology.

[0165] CROSS-REFERENCE TO RELATED APPLICATIONS

[0166] This application claims priority to Korean Patent Application No. 10-2023-0080557, filed on Jun. 22, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A method for operating a memory device, the method comprising the following steps: performing a pre-programming operation on selection transistors included in strings, wherein each of the strings includes a first source selection transistor, a second source selection transistor, a plurality of memory cells, and a drain selection transistor that are sequentially connected; and An erase operation and a fine program operation are performed on at least one of the selection transistors.

2. The operating method according to claim 1, wherein: The steps of performing the pre-programming operation include: performing an entire program operation of applying a program voltage to all source selection transistors included in the string a predetermined number of times while incrementally increasing the program voltage; and An additional program operation of further applying the program voltage to a second source select transistor included in the string is performed, wherein, in the additional program operation, the program voltage is not applied to a first source select transistor included in the string.

3. The operating method according to claim 2, wherein: The steps of performing the additional programming operation include: A first process of applying the programming voltage to the second source selection transistor; a second process of verifying a threshold voltage of a target second source selection transistor among the second source selection transistors by using a first verification voltage; and A third process of repeating the first process and the second process while incrementally increasing the programming voltage until a pass count for the target second source selection transistor is greater than a reference pass count.

4. The operating method according to claim 3, wherein: The step of performing the additional programming operation further includes: a fourth process, when the pass count is greater than the reference pass count, determining a new target second source selection transistor; a fifth process of verifying a threshold voltage of the new target second source selection transistor by using the first verification voltage; and A sixth process of repeatedly performing the first process and the second process on the new target second source selection transistor while incrementally increasing the programming voltage until a pass count for the new target second source selection transistor is greater than the reference pass count.

5. The operating method according to claim 1, wherein: The steps of performing the pre-programming operation include: A first process of applying a program voltage to a target drain selection transistor included in the string; a second process of verifying a threshold voltage of the target drain selection transistor by using a first verification voltage; and A third process of repeating the first process and the second process while incrementally increasing the program voltage until a fail count for the target drain selection transistor is smaller than a reference fail count.

6. The operating method according to claim 5, wherein: The step of performing the pre-programming operation further includes: a fourth process, when the fail count is less than the reference fail count, determining a new target drain selection transistor; and A fifth process of repeatedly performing the first process and the second process on the new target drain selection transistor while incrementally increasing the programming voltage until the fail count for the new target drain selection transistor is smaller than the reference fail count.

7. The operating method according to claim 1, wherein: The steps of performing the erase operation and the fine programming operation include: a first process of performing the erase operation on a target drain selection transistor included in the string; a second process of applying a programming voltage to the target drain selection transistor; a third process of verifying a threshold voltage of the target drain selection transistor by using a second verification voltage; a fourth process of controlling programming for a pass transistor among the target drain selection transistors so that the programming is inhibited; and A fifth process of repeating the second process, the third process, and the fourth process while incrementally increasing the program voltage until a fail count for the target drain selection transistor is smaller than a reference fail count.

8. The operating method according to claim 7, wherein: The step of performing the erase operation and the fine programming operation further includes: A sixth process, when the failure count is less than the reference failure count, determining a new target drain selection transistor; a seventh process of performing the erase operation on the new target drain selection transistor; and An eighth process of repeatedly performing the second process, the third process, and the fourth process on the new target drain selection transistor while incrementally increasing the programming voltage until a fail count for the new target drain selection transistor is smaller than the reference fail count.

9. The operating method according to claim 1, wherein: The steps of performing the erase operation and the fine programming operation include: a first process of performing the erase operation on a target second source select transistor among the second source select transistors included in the string; A second process of applying a programming voltage to the target second source selection transistor; a third process of verifying a threshold voltage of the target second source selection transistor by using a second verification voltage; a fourth process of controlling programming for a pass transistor among the target second source selection transistors so that the programming is inhibited; and A fifth process of repeating the second process, the third process, and the fourth process while incrementally increasing the program voltage until a fail count for the target second source selection transistor is smaller than a reference fail count.

10. The operating method according to claim 9, wherein: The step of performing the erase operation and the fine programming operation further includes: A sixth process, when the failure count is less than the reference failure count, determining a new target second source selection transistor; a seventh process of performing the erase operation on the new target second source selection transistor; and An eighth process of repeatedly performing the second process, the third process, and the fourth process on the new target second source selection transistor while incrementally increasing the programming voltage until a fail count for the new target second source selection transistor is less than the reference fail count.

11. A method for operating a memory device, the method comprising the following steps: performing a first pre-programming operation on selection transistors included in strings, wherein each of the strings includes a plurality of memory cells coupled between the selection transistors; and An erase operation, a second pre-program operation, a slow transistor masking operation, and a fine program operation are sequentially performed on a target selection transistor among the selection transistors included in the string.

12. The operating method according to claim 11, wherein: The step of performing the second pre-program operation includes applying a program voltage to the target selection transistor a predetermined number of times while incrementally increasing the program voltage.

13. The operating method according to claim 12, wherein: The steps of performing the slow transistor masking operation include: verifying a threshold voltage of the target selection transistor by using a third verification voltage; and A slow transistor among the target selection transistors is masked using a pass transistor.

14. The operating method according to claim 13, wherein: The steps of performing the fine programming operation include: A first process is to apply the programming voltage to the target selection transistor; a second process of verifying a threshold voltage of the target selection transistor by using a second verification voltage; a third process of controlling programming for the pass transistor among the target selection transistors so that the programming is inhibited; and A fourth process of repeating the first process, the second process, and the third process while incrementally increasing the program voltage until a fail count for the target selection transistor is smaller than a reference fail count.

15. The operating method according to claim 14, wherein: The pass transistors include a selection transistor having a threshold voltage lower than the third verification voltage among the target selection transistors and a selection transistor having a threshold voltage higher than the second verification voltage among the target selection transistors.

16. The operating method according to claim 14, further comprising the following steps: When the fail count is less than the reference fail count, determining a new target selection transistor; as well as The erase operation, the second pre-program operation, the slow transistor masking operation, and the fine program operation are sequentially performed on the new target selection transistor.

17. A memory device, the memory device comprising: A memory block, the memory block comprising a plurality of strings, each string comprising a first source selection transistor, a second source selection transistor, a plurality of memory cells and a drain selection transistor connected in sequence; as well as A control circuit performs a pre-program operation on the selection transistors included in the string and performs an erase operation and a fine program operation on at least one of the selection transistors.

18. The memory device of claim 17, wherein: The pre-programming operation includes: performing a first programming operation so that all of the source selection transistors included in the string form an intermediate threshold voltage distribution shifted upward from an initial threshold voltage distribution; performing a second programming operation so that the second source select transistors included in the string form a first threshold voltage distribution shifted upward from the intermediate threshold voltage distribution, wherein the first source select transistors included in the string maintain the intermediate threshold voltage distribution; and A third program operation is performed so that the drain selection transistors included in the string form a second threshold voltage distribution shifted upward from the initial threshold voltage distribution.

19. The memory device of claim 18, wherein: The erase operation and the fine program operation include: performing the erase operation so that the target drain selection transistors included in the string corresponding to the target index form an erase threshold voltage distribution; performing the fine programming operation so that the target drain select transistor forms a third threshold voltage distribution shifted upward from the erase threshold voltage distribution, wherein a voltage range of the third threshold voltage distribution is narrower than a voltage range of the second threshold voltage distribution; and The erase operation and the fine program operation are repeatedly performed on a new target drain select transistor included in a string corresponding to a new target index.

20. The memory device of claim 18, wherein: The erase operation and the fine program operation include: performing the erase operation so that the target second source selection transistor included in the string corresponding to the target index forms an erase threshold voltage distribution; performing the fine programming operation so that the target second source select transistor forms a fourth threshold voltage distribution shifted upward from the erase threshold voltage distribution, wherein a voltage range of the fourth threshold voltage distribution is narrower than a voltage range of the first threshold voltage distribution; and The erase operation and the fine program operation are repeatedly performed on a new target second source select transistor included in a string corresponding to a new target index.

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