Memory device and method of operating memory device

Abstract

The invention relates to a memory device and a method of operating the memory device. The memory device includes: a memory cell array including a plurality of memory cell strings and coupled between a plurality of bit lines and a plurality of word lines, the plurality of bit lines being commonly coupled to a common source line; and a control section suitable for: pre-charging the bit line to a first level during a read operation for a selected memory cell coupled to a selected word line among the plurality of word lines, and pre-charging the bit line to a second level during a verify operation for a program operation of the selected memory cell, wherein the second level is lower than the first level by a set level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0081017, filed on June 23, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to a semiconductor memory device, and more particularly, to a memory device that efficiently performs a bit line precharge operation and a method of operating the memory device. Background Art

[0004] A memory system is a storage device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. Memory systems are classified into volatile memory devices and non-volatile memory devices. A volatile memory device is a memory device that loses stored data when the power is interrupted. Representative examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), etc. A non-volatile memory device is a memory device that retains stored data even if the power is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. Flash memory is mainly classified into NOR type memory and NAND type memory.

[0005] A programming operation may be performed on a plurality of memory cells included in a nonvolatile memory device by repeating a programming loop including a voltage application operation and a verification operation. Here, the voltage application operation may be an operation of changing a threshold voltage of a memory cell selected as a programming target when a programming pulse having a gradually increasing voltage is applied to a word line to which the memory cell selected as a programming target is connected.

[0006] Furthermore, the verification operation may be an operation of checking whether a threshold voltage level of a memory cell selected as a programming target reaches a target voltage level.

[0007] Furthermore, the read operation of the plurality of memory cells included in the nonvolatile memory device may be an operation of sensing whether a threshold voltage level of a memory cell selected as a read target reaches a read voltage level. Summary of the invention

[0008] Embodiments of the present invention relate to a memory device capable of changing a bit line precharge level according to whether a requested operation is a verification operation included in a program operation or a read operation, and a method of operating the memory device.

[0009] The technical problems that the embodiments of the present invention hope to solve are not limited to the above-mentioned technical problems. Those skilled in the art to which the present invention belongs can clearly understand other technical problems not mentioned above through the following description.

[0010] According to an embodiment of the present invention, a memory device may include: a memory cell array, including a plurality of memory cells connected in series and in parallel between a plurality of bit lines and a plurality of word lines, the plurality of bit lines being commonly connected to a common source line; and a control unit, adapted to: precharge the bit line to a first level during a read operation of a selected memory cell connected to a selected word line among the plurality of word lines; and precharge the bit line to a second level during a verification operation of a programming operation of the selected memory cell, wherein the second level is set lower than the first level.

[0011] According to another embodiment of the present invention, a method for operating a memory device includes a memory cell array, the memory cell array includes multiple memory cell strings connected in parallel between multiple bit lines and multiple word lines, the method may include: precharging the bit line to a first level during a read operation for a selected memory cell included in a cell string connected to a selected word line among the multiple word lines; and precharging the bit line to a second level during a verification operation of a programming operation for the selected memory cell, wherein the second level is set lower than the first level.

[0012] According to another embodiment of the present invention, a method for operating a memory device may include: during a verification operation in a programming operation for a row of memory cells, reducing a precharge level of a bit line by a certain amount from a precharge level of a read operation on the row of memory cells; increasing the amount when the row is set closer to a common source line and / or when the number of programming loops increases during the programming operation; and increasing the level of a verification voltage applied to the row in proportion to the amount. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present invention.

[0014] Figure 2A and Figure 2B The embodiment according to the present invention is shown Figure 1 The structure of a memory cell array among the constituent elements of the memory device shown.

[0015] FIG. 3A to FIG. 3CThe embodiment according to the present invention is shown Figure 1 The difference between the bit line precharge voltage level of a read operation and the bit line precharge voltage level of a verify operation in the memory device is shown.

[0016] Figure 4 is shown in the embodiment according to the present invention Figure 1 FIG. 1 is a diagram illustrating an operation of changing a difference between a bit line precharge voltage level of a read operation and a bit line precharge voltage level of a verify operation according to a physical position of a word line selected as a program target in a memory device.

[0017] Figure 5 is shown in the embodiment according to the present invention Figure 1 FIG. 1 is a graph showing an operation of changing a difference between a bit line precharge voltage level of a read operation and a bit line precharge voltage level of a verify operation according to the number of repetitions of a program loop in a memory device.

[0018] Figure 6 is shown in the embodiment according to the present invention Figure 1 FIG. 1 is a graph showing an operation of adjusting a level of a verification voltage in a verification operation according to an operation of changing a difference between a bit line precharge voltage level of a read operation and a bit line precharge voltage level of a verification operation in a memory device shown.

[0019] Figure 7 is a diagram showing an embodiment of the present invention Figure 1 A block diagram of an example of a control unit among constituent elements of a memory device shown.

[0020] Figure 8 The present invention is described in detail according to an embodiment of the present invention. Figure 1 Flowchart showing the sequence of read and program operations performed in a memory device. DETAILED DESCRIPTION

[0021] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any disclosed embodiment.

[0022] In the present disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “embodiment,” “another embodiment,” “some embodiments,” “multiple embodiments,” “other embodiments,” “alternative embodiments,” etc.) are intended to indicate that any such features are included in one or more embodiments of the present disclosure, but may or may not be combined in the same embodiment.

[0023] In this disclosure, the terms "comprises," "comprising," "includes," and "including" are open ended. As used in the appended claims, these terms specify the presence of the elements stated and do not preclude the presence or addition of one or more other elements. The terms in the claims do not preclude the device from including additional components (e.g., interface units, circuits, etc.).

[0024] In the present disclosure, various units, circuits, or other components may be described or claimed to be "configured to" perform one or more tasks. In this case, "configured to" is used to represent a structure by indicating that the block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Therefore, even when a particular block / unit / circuit / component is not currently operating (e.g., not turned on or activated), it can be said that the block / unit / circuit / component is configured to perform a task. The blocks / units / circuit / components used with the "configured to" statement include hardware, such as circuits, memories storing executable program instructions to implement operations, etc. In addition, "configured to" may include general structures (e.g., general circuits) manipulated by software and / or firmware (e.g., FPGAs or general processors running software) to operate in a manner that can perform related tasks. "Configured to" may also include adjusting a manufacturing process (e.g., semiconductor manufacturing equipment) to manufacture a device (e.g., an integrated circuit) suitable for implementing or performing one or more tasks.

[0025] As used in this disclosure, the term "circuit" or "logic" refers to all of the following: (a) hardware circuit implementations only (e.g., implementations only in analog and / or digital circuits), and (b) combinations of circuits and software (and / or firmware), such as, as applicable: (i) a combination of processors, or (ii) portions of processors / software (including digital signal processors, software, and memory) that work together to enable a device such as a mobile phone or server to perform various functions, and (c) circuits, such as a microprocessor or portion of a microprocessor, that require software or firmware to operate even if the software or firmware is not physically present. This definition of "circuit" or "logic" applies to all uses of the term in this application, including all uses in any claims. As another example, as used in this application, the term "circuit" or "logic" also covers implementations of only a processor (or multiple processors) or a portion of a processor and a processor (or multiple processors) with accompanying software and / or firmware. The term "circuit" or "logic" also covers, for example, integrated circuits of storage devices, where applicable to a particular claim element.

[0026] As used herein, the terms "first", "second", "third", etc. are used as markers for nouns preceding the terms and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms "first" and "second" do not necessarily mean that the first value must be written before the second value. Further, although these terms may be used herein to identify various components, these components are not limited by these terms. These terms are used to distinguish one component from another component having the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0027] In addition, the term "based on" is used to describe one or more factors that affect the determination. The term does not exclude other factors that may affect the determination. That is, the determination may be based only on these factors, or at least in part on these factors. For example, the phrase "determine A based on B." In this case, B is a factor that affects the determination of A, but this phrase does not exclude that the determination of A is also based on C. In other cases, A may be determined based only on B.

[0028] In this document, an item of data, a data item or a data entry or an entry of data may be a bit sequence. For example, a data item may include the contents of a file, a portion of a file, a page in a memory, an object in an object-oriented program, a digital message, a digital scanned image, a portion of a video or audio signal, metadata, or any other entity that may be represented by a bit sequence. According to an embodiment, a data item may include a discrete object. According to another embodiment, a data item may include an information unit within a transmission data packet between two different components.

[0029] Figure 1 is a block diagram illustrating a memory device according to an embodiment of the present invention.

[0030] Figure 2A and Figure 2B The embodiment according to the present invention is shown Figure 1 The structure of a memory cell array among the constituent elements of the memory device shown.

[0031] FIG. 3A to FIG. 3C The embodiment according to the present invention is shown Figure 1 The difference between the bit line precharge voltage level of a read operation and the bit line precharge voltage level of a verify operation in the memory device is shown.

[0032] Reference Figure 1 as well as Figure 2A and Figure 2B , the memory device 150 according to an embodiment of the present disclosure may include a memory cell array 201 and a control section 202 .

[0033] The memory cell array 201 may include a plurality of memory blocks BLK<1:z>. Each of the memory blocks BLK<1:one of z> may include a plurality of memory cells (not shown). One memory block may include a plurality of pages.

[0034] A storage block can be understood as a group of nonvolatile memory cells that remove data together through an erase operation. Each <1: one of z> in a storage block BLK may include a page (not shown), and from a logical point of view, nonvolatile memory cells that store data together during a programming operation or output data together during a read operation are grouped in a page. For example, a storage block may include multiple pages. A page may include multiple nonvolatile memory cells.

[0035] From a physical perspective different from a logical perspective (eg, a program operation or a read operation), one memory block may include a plurality of word lines WL<1:n>. One word line may include a plurality of nonvolatile memory cells.

[0036] In this case, according to the number of bits that can be stored or represented in one nonvolatile memory cell, one word line can correspond to at least one page. For example, when a nonvolatile memory cell is a single-layer cell (SLC) storing one data bit, one word line can correspond to one page. When a nonvolatile memory cell is a double-layer cell (DLC) storing two data bits, one word line can correspond to two pages. When a nonvolatile memory cell is a triple-layer cell (TLC) storing three data bits, one word line can correspond to three pages. When a nonvolatile memory cell is a quad-layer cell (QLC) storing four data bits, one word line can correspond to four pages. In this way, when a nonvolatile memory cell is a multi-layer cell storing five or more data bits, one word line can correspond to five or more pages.

[0037] Each of the memory blocks BLK <1: one of z> may include a 3D structure. For example, each of the memory blocks BLK <1: one of z> may include a plurality of memory cells stacked on a substrate. Therefore, each of the memory blocks may be arranged along the +X direction, the +Y direction, and the +Z direction.

[0038] More specifically, each of the memory blocks may include a plurality of memory cells connected between a plurality of word lines WL<1:n> arranged along the Z direction, a plurality of bit lines BL<1:m> arranged along the X direction, and a plurality of memory cell strings CS<11′:1m′, 21′:2m′> arranged along the X and Y directions.

[0039] Herein, each of the plurality of memory cell strings CS<11′:1m′, 21′:2m′> may include at least one source select transistor SST and first to nth memory cells MC<1:n> and at least one drain select transistor DST.

[0040] Herein, each of the selection transistors SST and DST and the memory cells MC<1:n> may have a similar structure. According to an embodiment of the present invention, each of the selection transistors SST and DST and the memory cells MC<1:n> may include a channel layer, a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer. According to another embodiment of the present invention, a pillar for providing a channel layer may be provided in each cell string. According to another embodiment of the present invention, a pillar for providing at least one of a channel layer, a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer may be provided in each cell string.

[0041] The source selection transistor SST included in each of the memory cell strings CS<11′:1m′, 21′:2m′> may be coupled between the common source line CSL and the memory cells MC<1:n>.

[0042] According to an embodiment of the present invention, the source selection transistors of the cell strings arranged in the same row can be connected to the source selection line extending in the row direction, and the source selection transistors of the cell strings arranged in different rows can be connected to different source selection lines. In the figure, the source selection transistor of each of the cell strings CS<11':1m'> of the first row can be connected to the first source selection line SSL1. In addition, the source selection transistor of each of the cell strings CS<21':2m'> of the second row can be connected to the second source selection line SSL2.

[0043] According to another embodiment of the present invention, unlike what is shown in the drawing, source selection transistors of cell strings CS<11′:1m′> and CS<21′:2m′> may be commonly connected to one source selection line.

[0044] First to nth memory cells MC<1:n> included in each of the memory cell strings CS<11′:1m′, 21′:2m′> may be coupled between a source select transistor SST and a drain select transistor DST.

[0045] The drain selection transistor DST included in each of the memory cell strings CS<11':1m', 21':2m'> may be connected between the corresponding bit line and the memory cell MC<1:n>. The cell strings arranged in the row direction may be connected to the drain selection line extending in the row direction. The drain selection transistor of the cell string CS<11':1m'> of the first row may be connected to the first drain selection line DSL1. The drain selection transistor of the cell string CS<21':2m'> of the second row may be connected to the second drain selection line DSL2.

[0046] Cell strings arranged in a column direction may be coupled to bit lines extending in the column direction. In the figure, cell strings CS11' and CS21' of a first column may be coupled to a first bit line BL1. Cell strings CS1m' and CS2m' of an mth column may be coupled to an mth bit line BLm.

[0047] The memory cells connected to the word lines in the cell strings arranged along the row direction may form one physical page. For example, the memory cells connected to the first word line WL1 in the cell string CS<11':1m'> of the first row may form one physical page. For another example, the memory cells connected to the first word line WL1 in the cell string CS<21':2m'> of the second row may form another physical page. The cell strings arranged along one row direction may be selected by selecting one of the drain selection lines DSL1 and DSL2. One physical page of the selected cell string may be selected by selecting one of the word lines WL<1:n>.

[0048] According to an embodiment of the present invention, at least one of the first to nth memory cells MC<1:n> can be used as a dummy memory cell. For example, at least one or more dummy memory cells can be set to reduce the electric field between the source selection transistor SST and the memory cell MC<1:n>. In addition, at least one or more dummy memory cells can be set to reduce the electric field between the drain selection transistor DST and the memory cell MC<1:n>. When more dummy memory cells are set, the size of the memory block can be increased, but the operational reliability of the memory block is improved. When fewer dummy memory cells are set, the size of the memory block BLKa can be reduced, but the operational reliability of the memory block BLKa may be reduced.

[0049] In order to effectively control at least one or more dummy memory cells, each of the dummy memory cells may have a desired threshold voltage. Before or after an erase operation is performed on a storage block, a programming operation may be performed on all or part of the dummy memory cells. When an erase operation is performed after a programming operation, each of the dummy memory cells may have a desired threshold voltage by controlling a voltage applied to a dummy word line coupled to the dummy memory cell.

[0050] The control section 202 may control a read operation of reading data stored (programmed) in a selected region of the memory cell array 201. The control section 202 may perform a read operation on a selected memory cell (hereinafter referred to as a "read cell") included in a selected cell string of the cell string CS<11':1m', 21':2m'>. The selected memory cell may be connected to a word line selected as a read target among a plurality of word lines WL<1:n>.

[0051] More specifically, refer to Figure 3A The read operation READ OPERATION may include a bit line precharge operation BITLINE PRECHARGE, an evaluation operation EVALUATION, and a sensing operation SENSING.

[0052] Herein, the bit line precharge operation BIT LINE PRECHARGE may be an operation of applying a precharge voltage to the bit line BL<1:m>. In the bit line precharge operation BIT LINE PRECHARGE, a voltage level of the bit line BL<1:m> may be raised to a level of the precharge voltage.

[0053] In particular, the control section 202 according to the embodiment of the present invention may apply a precharge voltage having a first level to the bit line BL<1:m> in the bit line precharge operation BIT LINE PRECHARGE included in the read operation READ OPERATION. The control section 202 according to the embodiment of the present invention may precharge the bit line BL<1:m> to the first level in the bit line precharge operation BIT LINE PRECHARGE included in the read operation READ OPERATION (see Figure 1 10).

[0054] In addition, the evaluation operation EVALUATION may be an operation of applying the state of the read cell to the bit line BL<1:m>. For example, since the read cell has a threshold voltage level lower than the read voltage level, the level of the bit line corresponding to the read cell turned on in the evaluation operation EVALUATION may drop from the level of the precharge voltage applied by the bit line precharge operation BIT LINEPRECHARGE to the level of the ground voltage. For another example, since the read cell has a threshold voltage level higher than the read voltage level, the level of the bit line corresponding to the read cell turned off in the evaluation operation EVALUATION may remain unchanged at the level of the precharge voltage applied by the bit line precharge operation BIT LINE PRECHARGE.

[0055] Furthermore, the sensing operation SENSING may be an operation of sensing data corresponding to a state of a read unit applied to a bit line BL<1:m> through the evaluation operation EVALUATION and storing the sensed data in a page buffer.

[0056] In summary, during the read operation READ OPERATION, the control unit 202 according to the embodiment of the present invention can perform the evaluation operation EVALUATION and the sensing operation SENSING on the bit line BL<1:m> precharged to the first level by the bit line precharge operation BIT LINE PRECHARGE (see Figure 1 20 in the above).

[0057] In addition, the control section 202 may control a programming operation of programming data into a selected area of ​​the memory cell array 201. The control section 202 may perform a programming operation on a selected memory cell (hereinafter referred to as a "programming cell") included in a selected cell string of the cell string CS<11':1m', 21':2m'>. The selected memory cell may be connected to a word line (hereinafter referred to as a "programming word line") selected as a programming target among a plurality of word lines WL<1:n>. Here, the programming cell may have one programming state among a plurality of programming states through a programming operation.

[0058] According to an embodiment of the present invention, a single-layer cell SLC storing one data bit may have two programming states distinguished based on one threshold voltage level. A multi-layer cell MLC storing two data bits may have four programming states distinguished based on three threshold voltage levels. A three-layer cell TLC storing three data bits may have eight programming states distinguished based on seven threshold voltage levels. A four-layer cell QLC storing four data bits may have sixteen programming states distinguished based on fifteen threshold voltage levels.

[0059] Reference Figure 3B and Figure 1 The programming operation may include a plurality of programming loops PL1 to PL7. The control unit 202 may program the programming unit to have one programming state among a plurality of programming states by repeatedly running the plurality of programming loops PL1 to PL7 one by one in a predetermined order until the programming operation is completed (see Figure 1 30). Herein, if the program operation is not successful within a predetermined number of program loops, the control section 202 may determine the program operation as a failure.

[0060] According to an embodiment of the present invention, Figure 3B In the embodiment, when the seventh program loop PL7 among the program loops PL1 to PL7 is completed, the program operation is successfully performed. Figure 3BIn the embodiment, when the seventh program loop PL7 among the program loops PL1 to PL7 is completed, the program cells have the target program states.

[0061] Herein, each of the programming loops PL1 to PL7 may include: a voltage application operation VIO for changing a threshold voltage level of a programming cell by applying a programming pulse PGM<1:7> to a programming word line; and a verification operation VER for verifying which programming state the programming cell is in by applying a verification voltage VRY<1:7> corresponding to a target level to the programming word line.

[0062] In addition, whenever each of the programming loops PL1 to PL7 is executed, the potential level of the programming pulse may be increased. When each of the programming loops PL1 to PL7 is repeatedly executed, the programming operation may increase the level of the programming voltage according to an incremental step pulse programming (ISPP) method. In this case, the number of times the programming voltage used in each of the programming loops PL1 to PL7 is applied, the level of the programming voltage, and the duration for which the programming voltage is applied may be determined in a variety of forms.

[0063] Furthermore, the verification operation VERIFY OPERATION included in each of the program loops PL1 to PL7 may include a bit line precharge operation BIT LINE PRECHARGE, an evaluation operation EVALUATION, and a sensing operation SENSING.

[0064] Herein, the bit line precharge operation BIT LINE PRECHARGE may be an operation of applying a precharge voltage to the bit line BL<1:m>. During a program operation, the bit line precharge operation BIT LINE PRECHARGE included in the verify operation VER may be substantially the same operation as the bit line precharge operation BIT LINE PRECHARGE included in the above-described read operation READ OPERATION.

[0065] However, further reference Figure 3CDuring the programming operation, the control section 202 according to the embodiment of the present invention may apply a precharge voltage having a second level LV2 lower than the first level LV1 by a set level PDLV to the bit line BL<1:m> in the bit line precharge operation BIT LINE PRECHARGE included in the verification operation VER. The control section 202 according to the embodiment of the present invention may precharge the bit line BL<1:m> to the first level LV1 in the bit line precharge operation BIT LINE PRECHARGE included in the read operation READ OPERATION, but during the programming operation, the bit line BL<1:m> may be precharged to a second level LV2 lower than the first level LV1 by a set level PDLV in the bit line precharge operation BIT LINE PRECHARGE included in the verification operation VER (see Figure 1 40).

[0066] In addition, the evaluation operation EVALUATION may be an operation of applying the state of the programming cell to the bit line BL<1:m>. For example, since the programming cell has a threshold voltage level lower than the level of the verification voltage VRY<1:7>, the level of the bit line corresponding to the programming cell turned on in the evaluation operation EVALUATION may drop from the level of the precharge voltage applied by the bit line precharge operation BITLINE PRECHARGE to the level of the ground voltage. For another example, since the programming cell has a threshold voltage level higher than the level of the verification voltage VRY<1:7>, the level of the bit line corresponding to the programming cell turned off in the evaluation operation EVALUATION may remain unchanged at the level of the precharge voltage applied by the bit line precharge operation BIT LINE PRECHARGE.

[0067] Furthermore, the sensing operation SENSING may be an operation of sensing data corresponding to the state of a program cell applied to the bit line BL<1:m> through the evaluation operation EVALUATION and storing the sensed data in the page buffer.

[0068] In summary, during the verification operation VER of the programming operation, the control unit 202 according to the embodiment of the present invention may perform an evaluation operation and a sensing operation on the bit line BL<1:m> precharged to the second level LV2 by the bit line precharge operation BIT LINE PRECHARGE (see Figure 1 of 50).

[0069] In addition, the control unit 202 according to the embodiment of the present invention may adjust the setting level PDLV indicating the voltage level difference between the first level LV1 and the second level LV2 (see Figure 141 and 42 in). During a program operation for a program cell, the control section 202 may adjust a set level PDLV indicating a level difference between a precharge voltage of a first level LV1 used in a bit line precharge operation BIT LINE PRECHARGE of a read operation READ OPERATION for a read cell and a precharge voltage of a second level LV2 used in a bit line precharge operation BIT LINE PRECHARGE of a verify operation VER.

[0070] Furthermore, the control section 202 according to an embodiment of the present invention may adjust the level of the verification voltage VRY<1:7> applied to the program word line in the verification operation VER in response to the adjustment setting level PDLV (see Figure 1 51 in). The control section 202 may increase the level of the verification voltage VRY<1:7> applied to the program word line during the verification operation VER in proportion to the increase of the set level PDLV.

[0071] In the following we will refer to Figures 4 to 6 Describe in more specific details.

[0072] Figure 4 is shown in the embodiment according to the present invention Figure 1 FIG. 1 is a diagram illustrating an operation of changing a difference between a bit line precharge voltage level of a read operation and a bit line precharge voltage level of a verify operation according to a physical position of a word line selected as a program target in a memory device.

[0073] Reference Figure 4 and Figure 1 According to an embodiment of the present invention, the control unit 202 can adjust the setting level PDLV (see FIG. 1 ) representing the voltage level difference between the first level LV1 and the second level LV2 according to the physical position of the programming word line. Figure 1 41). In this case, the physical position of the programming word line may refer to how close the programming word line is physically to the common source line CSL.

[0074] According to the embodiments of the present invention, it can be seen that Figure 2B The first word line WL1 among the word lines WL<1:n> shown in FIG. 1 is a word line that is physically closer to the common source line CSL than the second word line WL2. Figure 4 As shown, the control section 202 may set the setting level PDLV corresponding to selecting the first word line WL1 as the programming word line to be relatively greater than the setting level PDLV corresponding to selecting the second word line WL2 as the programming word line. That is, when the selected word line is located closer to the common source line CSL, the control section 202 may adjust the setting level PDLV by increasing the setting level PDLV.

[0075] According to another embodiment of the present invention, Figure 2B As shown in FIG. 1 , it can be seen that the (n-1)th word line WLn-1 among the word lines WL<1:n> is physically closer to the common source line CSL than the nth word line. Figure 4 As shown, the control section 202 may set the setting level PDLV corresponding to selecting the (n-1)th word line WLn-1 as the programming word line to be relatively greater than the setting level PDLV corresponding to selecting the nth word line WLn as the programming word line.

[0076] In summary, when the control section 202 selects a word line physically closer to the common source line CSL as a programming word line, the setting level PDLV indicating the voltage level difference between the first level LV1 and the second level LV2 may increase.

[0077] Figure 5 is shown in the embodiment according to the present invention Figure 1 FIG. 1 is a graph showing an operation of changing a difference between a bit line precharge voltage level of a read operation and a bit line precharge voltage level of a verify operation according to the number of repetitions of a program loop in a memory device.

[0078] Reference Figure 5 and Figure 1 , the control section 202 according to the embodiment of the present invention may adjust the setting level PDLV (see FIG. 1 ) indicating the voltage level difference between the first level LV1 and the second level LV2 according to which programming loop among the plurality of programming loops PL1 to PL7 included in the programming operation is included in the bit line precharge operation BIT LINE PRECHARGE of the verification operation VER. Figure 1 42 in FIG. 4). The control unit 202 adjusts the setting level PDLV (see FIG. 42 ) representing the voltage level difference between the first level LV1 and the second level LV2 according to the number of repetitions of the programming loop. Figure 1 42).

[0079] According to an embodiment of the present invention, Figure 5 As shown, the control section 202 may set the setting level PDLV in the bit line precharge operation BIT LINE PRECHARGE of the verification operation VER included in the first programming loop PL1 among the programming loops PL1 to PL7 to be relatively greater than the setting level PDLV in the bit line precharge operation BIT LINE PRECHARGE of the verification operation VER included in the second programming loop PL2. That is, the control section 202 may further adjust the setting level PDLV according to the number of repetitions of the programming loop.

[0080] According to another embodiment of the present invention, Figure 5 As shown, the control unit 202 can set the set level PDLV in the bit line precharge operation BIT LINE PRECHARGE of the verification operation VER included in the third programming loop PL3 among the programming loops PL1 to PL7 to be relatively greater than the set level PDLV in the bit line precharge operation BIT LINE PRECHARGE of the verification operation VER included in the fourth programming loop PL4.

[0081] In summary, the control section 202 may increase the setting level PDLV indicating the voltage level difference between the first level LV1 and the second level LV2 in proportion to the increase in the number of repetitions of the program loop.

[0082] Figure 6 is shown in the embodiment according to the present invention Figure 1 FIG. 1 is a graph showing an operation of adjusting a level of a verification voltage in a verification operation according to an operation of changing a difference between a bit line precharge voltage level of a read operation and a bit line precharge voltage level of a verification operation in a memory device shown.

[0083] Reference Figure 6 and Figure 1 , the control section 202 according to an embodiment of the present invention may adjust the level of the verification voltage VRY<1:7> applied to the programming word line in the verification operation VER in response to the adjustment of the setting level PDLV indicating the voltage level difference between the first level LV1 and the second level LV2 (see Figure 1 51 in the figure). The control unit 202 may respond to the Figure 4 and Figure 5 The adjustment of the set level PDLV set in the methods 41 and 42 described in , adjusts the level of the verification voltage VRY<1:7> applied to the program word line in the verification operation VER.

[0084] According to an embodiment of the present invention, Figure 6 As shown, the control unit 202 may increase the level of the verification voltage VRY<1:7> by "a" in proportion to the increase of the setting level PDLV indicating the voltage level difference between the first level LV1 and the second level LV2 by "b". Herein, "a" as the level increment of the verification voltage VRY<1:7> may refer to the additional increase of the level of the verification voltage VRY<1:7> corresponding to the target level of the programming cell by "a".

[0085] For example, when the target level of the programming cell in the verification operation VER is "k", the level of the verification voltage VRY<1:7> used to verify this may be "k'. When the target level of the programming cell in the verification operation VER is "k" and the set level PDLV is increased by "b", the control unit 202 may change the level of the verification voltage VRY<1:7> to "k+a" increased from "k" by "a", and use this level in the verification operation VER.

[0086] For another example, when the target level of the programming unit is "k" and the setting level PDLV is increased by "3b" (i.e., three times "b"), in the verification operation VER, the control unit 202 can change the level of the verification voltage VRY<1:7> to "k+3a", i.e., increased from "k" to three times "a", and use this level in the verification operation VER.

[0087] In addition, "a" which is an increment of the level of the verification voltage VRY<1:7> and "b" which is an increment of the level of the setting level PDLV may have different values. The value of "a", that is, the increment of the level of the verification voltage VRY<1:7>, and the value of "b", that is, the increment of the level of the setting level PDLV, may be defined by a designer as a preset ratio.

[0088] In summary, the control section 202 may increase the level of the verification voltage VRY<1:7> in proportion to the increase in the level of the setting level PDLV which is the voltage level difference between the first level LV1 and the second level LV2 .

[0089] Figure 7 is a diagram showing an embodiment of the present invention Figure 1 A block diagram of an example of a control unit among constituent elements of a memory device shown.

[0090] Reference Figure 7 , the memory device 150 may include a memory cell array 201 and a control section 202. The control section 202 may include a control circuit unit 309 and a control logic unit 304. The control circuit unit 309 may include a page buffer unit 302, a check unit 303, a data input / output circuit 305, a voltage supply circuit 306, and an address decoder 307. The control circuit unit 309 may include an operation check unit 311, a precharge control unit 312, a positioning unit 313, and a program operation unit 314.

[0091] The memory cell array 201 may include a plurality of memory blocks MEMORY BLOCK<1:6>. The plurality of memory blocks MEMORY BLOCK<1:6> may be connected to the address decoder 307 through row lines RL. The plurality of memory blocks MEMORY BLOCK<1:6> may be connected to the page buffer unit 302 through bit lines BL1 to BLm. Each of the memory blocks MEMORY BLOCK<1:6> may include a plurality of memory cells.

[0092] Reference Figure 7 and Figure 2B , the row line RL may include at least one source selection line SSL1 , SSL2 , a plurality of word lines (WL<1:n>) and at least one drain selection line (DSL1 , DSL2 ).

[0093] The control circuit unit 309 may be configured to perform a program operation, a read operation, or an erase operation on a selected area of ​​the memory cell array 201. The control circuit unit 309 may drive the memory cell array 201. For example, the control circuit unit 309 may apply various operation voltages to the row lines RL and the bit lines BL1 to BLm, or discharge the applied voltages. The control circuit unit 309 may perform a program operation on a programming unit in response to the control of the control logic unit 304. In particular, the control circuit unit 309 may perform an overwrite-type program operation in addition to performing a normal program operation on the programming unit in response to the control of the control logic unit 304.

[0094] The address decoder 307 included in the control circuit unit 309 may be connected to the memory cell array 201 through the row lines RL.

[0095] The address decoder 307 may be configured to operate in response to the control of the control logic unit 304. The address decoder 307 may receive the address RADD from the control logic unit 304.

[0096] The address decoder 307 may be configured to decode the block address in the received address RADD. The address decoder 307 may select at least one memory block among the memory blocks MEMORY BLOCK<1:6> according to the decoded block address. The address decoder 307 may be configured to decode the row address in the received address RADD. The address decoder 307 may select at least one word line among the word lines of the selected memory block according to the decoded row address. The address decoder 307 may apply the operating voltage Vop supplied from the voltage supply circuit 306 to the selected word line.

[0097] The voltage supply circuit 306 in the control circuit unit 309 may be configured to generate a plurality of operation voltages Vop by using an external power supply voltage. The voltage supply circuit 306 may operate in response to the control of the control logic unit 304 .

[0098] In an embodiment, the voltage supply circuit 306 may regulate an external power supply voltage and generate an internal power supply voltage.

[0099] In an embodiment, the voltage supply circuit 306 may generate a plurality of operating voltages Vop by using an external power supply voltage or an internal power supply voltage.

[0100] The voltage supply circuit 306 may include a plurality of pumping capacitors receiving an internal power supply voltage to generate a plurality of operating voltages Vop having various voltage levels, and generates the plurality of operating voltages Vop by selectively activating the plurality of pumping capacitors in response to control of the control logic unit 304 .

[0101] The generated operation voltage Vop may be provided to the memory cell array 201 through the address decoder 307. For example, the voltage supply circuit 306 may adjust a level and a supply time of each operation voltage Vop in response to the operation signal OP_SIG.

[0102] Further references Figure 3B , the voltage supply circuit 306 may generate a programming voltage PGM<1:7>, a pass voltage, a verification voltage VRY<1:7>, a read voltage, an erase voltage, etc. as an operation voltage VOP, and supply the generated operation voltage VOP to the address decoder 307. For example, during a programming operation, the voltage supply circuit 306 may generate a programming voltage, a pass voltage, and a verification voltage as an operation voltage VOP in response to an operation signal OP_SIG, and supply the generated operation voltage VOP to the address decoder 307. In this case, the programming voltage may be a voltage supplied to a programming word line, and the pass voltage may be a voltage supplied to a word line that is not selected as a programming target. The voltage supply circuit 306 may control the supply time of each operation voltage VOP according to the operation signal OP_SIG. For example, the voltage supply circuit 306 may adjust the output time of the programming voltage, the pass voltage, and the verification voltage according to the operation signal OP_SIG, and output the voltage according to the adjusted output time.

[0103] The page buffer unit 302 may include a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm may be connected to the memory cell array 201 through a plurality of bit lines BL1 to BLm, respectively. The plurality of page buffers PB1 to PBm may operate in response to control of the control logic unit 304 .

[0104] The plurality of page buffers PB1 to PBm may communicate data DATA with the data input / output circuit 305. During a program operation, the plurality of page buffers PB1 to PBm may receive data DATA to be stored through the data input / output circuit 305 and the data lines DL.

[0105] After the program operation starts, the plurality of page buffers PB1 to PBm may store data DATA received from the outside through the data input / output circuit 305, and may transmit a program enable voltage or a program inhibit voltage to the bit lines BL1 to BLm in response to the stored data DATA. For example, the program enable voltage may be 0V, and the program inhibit voltage may be a power supply voltage.

[0106] After the read operation starts, multiple page buffers PB1 to PBm can sense data DATA based on the voltage or current of bit lines BL1 to BLm and can send the sensed data DATA to the data input / output circuit 305 through the data line DL, where the voltage or current is determined based on the threshold voltage of the memory cell of the selected page.

[0107] After the erase operation starts, the plurality of page buffers PB1 to PBm may float the bit lines BL1 to BLm, or may apply a voltage of 0V to the bit lines BL1 to BLm.

[0108] The data input / output circuit 305 may include a plurality of input / output buffers (not shown) receiving data DATA input thereto. During a program operation, the data input / output circuit 305 may receive data DATA to be stored from the outside. During a read operation, the data input / output circuit 305 may output data DATA transmitted from a plurality of page buffers PB1 to PBm included in the page buffer unit 302 to the outside.

[0109] The inspection unit 303 of the control circuit unit 309 may generate a reference current in response to a verification reference signal VRYBIT generated by the control logic unit 304 after the read operation or the verification operation starts, may compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated according to the reference current, and may output a pass signal PASS or a fail signal FAIL to the control logic unit 304. For example, when the level of the sensing voltage VPB is higher than or equal to the level of the reference voltage, the inspection unit 303 may output a pass signal PASS to the control logic unit 304. When the level of the sensing voltage VPB is lower than the level of the reference voltage, the inspection unit 303 may output a fail signal FAIL to the control logic unit 304.

[0110] The control logic unit 304 may be connected to the address decoder 307, the voltage supply circuit 306, the page buffer unit 302, the data input / output circuit 305, and the check unit 303 included in the control circuit unit 309. The control logic unit 304 may be configured to control the overall operation of the memory device 150. The control logic unit 304 may operate in response to a command CMD from an external device.

[0111] The control logic unit 304 may control the control circuit unit 309 by generating various signals in response to the command CMD and the address ADDR. For example, the control logic unit 304 may generate an operation signal OP_SIG, an address RADD, a read and write control signal PBSIGNALS, and a verification reference signal VRYBIT in response to the command CMD and the address ADDR. The control logic unit 304 may output the operation signal OP_SIG to the voltage supply circuit 306, may output the address RADD to the address decoder 307, may output the read and write control signal PBSIGNALS to the page buffer unit 302, and may output the verification reference signal VRYBIT to the inspection unit 303. In addition, the control logic unit 304 may determine whether the verification operation passes or fails in response to a pass signal or a fail signal PASS / FAIL output by the inspection unit 303.

[0112] More specifically, the operation checking unit 311 included in the control logic unit 304 may check what operation is requested externally in response to the command CMD applied from the outside.

[0113] According to an embodiment of the present invention, the operation checking unit 311 may confirm that the externally requested operation is a read operation in response to a command CMD applied from the outside In this case, the operation checking unit 311 may generate a first output signal RD corresponding to the read operation.

[0114] According to another embodiment of the present invention, the operation checking unit 311 may confirm that the externally requested operation is the verification operation VER included in the program operation in response to the command CMD applied from the outside. In this case, the operation checking unit 311 may generate a second output signal VR corresponding to the verification operation VER.

[0115] In addition, the precharge control unit 312 included in the control logic unit 304 may precharge the bit line BL<1:m> to one of a first level LV1 and a second level LV2 lower than the first level LV1 by a set level PDLV in response to the output signals RD and VR of the operation check unit 311. Under the control of the operation check unit 311, the precharge control unit 312 may control the operation of the control circuit unit 309 to apply a precharge voltage having one of the first level LV1 and the second level LV2 lower than the first level LV1 by a set level PDLV to the bit line BL<1:m> in a verification operation VER included in a programming operation.

[0116] According to an embodiment of the present invention, in response to the first output signal RD corresponding to the read operation generated in the operation checking unit 311, the precharge control unit 312 can control the operation of the control circuit unit 309 to apply the precharge voltage having the first level LV1 to the bit line BL<1:m>.

[0117] According to another embodiment of the present invention, in response to the operation check unit 311 generating a second output signal VR corresponding to the verification operation VER included in the programming operation, the pre-charge control unit 312 can control the operation of the control circuit unit 309 to apply a pre-charge voltage of a second level LV2 having a set level PDLV lower than the first level LV1 to the bit line BL<1:m>.

[0118] In addition, in response to the address ADDR applied from the outside, the positioning unit 313 included in the control circuit unit 309 can detect the memory cell on which the externally requested operation is to be performed, that is, the memory cell selected based on the selected word line and the selected memory cell string in the memory cell array 201. Since the selected memory cell can be detected by the positioning unit 313, the physical position of the selected word line can also be detected. The positioning unit 313 can check the degree to which the physical position of the selected word line is away from the common source line, and generate a third output signal POC corresponding to the inspection result.

[0119] When the precharge control unit 312 precharges the bit line BL<1:m> to the second level in response to the operation check unit 311 generating the second output signal VR, the precharge control unit 312 may adjust a set level PDLV corresponding to a level difference between the first level LV1 and the second level LV2 in response to the third output signal POC generated by the positioning unit 313 .

[0120] According to an embodiment of the present invention, the positioning unit 313 may determine that the physical position of the first word line WL1 among the word lines WL<1:n> is relatively closer to the common source line than the physical position of the second word line WL2, and may generate the third output signal POC to control the precharge control unit 312, so that as a result of the inspection result, the set level PDLV adjusted by the precharge control unit 312 in response to the first word line WL1 being selected as the selected word line is relatively greater than the set level PDLV adjusted by the precharge control unit 312 in response to the second word line WL2 being selected as the selected word line. That is, when the selected word line is located closer to the common source line CSL, the precharge control unit 312 may adjust the set level PDLV by increasing the set level PDLV.

[0121] According to another embodiment of the present invention, the positioning unit 313 can determine that the physical position of the (n-1)th word line WLn-1 among the word lines WL<1:n> is relatively closer to the common source line than the physical position of the nth word line WLn, and can generate a third output signal POC to control the pre-charging control unit 312, so that as a result of the inspection result, the set level PDLV adjusted by the pre-charging control unit 312 in response to the (n-1)th word line WLn-1 being selected as the selected word line is relatively greater than the set level PDLV adjusted by the pre-charging control unit 312 in response to the nth word line WLn being selected as the selected word line.

[0122] The program operation unit 314 included in the control circuit unit 309 may repeatedly perform the program loops PL1 to PL7 including the voltage applying operation VIO and the verification operation VER until the program operation on the program unit is successfully performed. Herein, the program operation unit 314 may generate information PLi indicating which program loop is being repeated among the program loops PL1 to PL7 repeated for the program unit, and transmit the generated information PLi to the precharge control unit 312. When the precharge control unit 312 precharges the bit line BL<1:m> to the second level in response to the operation check unit 311 generating the second output signal VR, the precharge control unit 312 may adjust the set level PDLV corresponding to the level difference between the first level LV1 and the second level LV2 in response to the program loop information PLi transmitted from the program operation unit 314.

[0123] According to an embodiment of the present invention, the precharge control unit 312 may increase the set level PDLV corresponding to the level difference between the first level LV1 and the second level LV2 in proportion to the increase in the number of repetitions of the program loop transmitted from the program operation unit 314. That is, the precharge control unit 312 may further adjust the set level PDLV according to the number of repetitions of the program loop.

[0124] Then, the precharge control unit 312 may generate information LTi indicating the extent to which the set level PDLV corresponding to the level difference between the first level LV1 and the second level LV2 is adjusted, and transmit the generated information LTi to the program operation unit 314. The program operation unit 314 may adjust the level of the verification voltage VRY<1:7> applied to the program word line during the verification operation VER of the program operation in response to the level adjustment information LTi of the set level PDLV transmitted from the precharge control unit 312.

[0125] According to an embodiment of the present invention, the program operation unit 314 may increase the level of the verification voltage VRY<1:7> applied to the program word line in the verification operation VER of the program operation in proportion to the increase of the set level PDLV transferred from the precharge control unit 312 .

[0126] Figure 8 The present invention is described in the embodiment of the present invention Figure 1 Flowchart showing the sequence of read and program operations performed in a memory device.

[0127] Reference Figure 8 , in operation S10, an operation requested for a selected memory cell of the memory cell array 201 may be detected in response to a command CMD and an address ADDR applied from the outside.

[0128] When the detected operation is a read operation (“READ” in operation S10 ), the bit line BL< 1 :m> may be precharged to a first level LV1 in operation S20 .

[0129] In operation S30 , a read operation including an evaluation operation EVALUATION and a sensing operation SENSING may be performed on the bit line BL<1:m> precharged to the first level through operation S20 .

[0130] When the detected operation is a program operation (“PROGRAM” in operation S10 ), in operation S40 , a voltage applying operation VIO included in a first program loop PL1 among program loops PL1 to PL7 may be performed.

[0131] After operation S40, in operation S50, the bit line BL<1:m> may be precharged to a second level LV2 lower than the first level LV1 by a set level PDLV. When operation S50 is performed, the set level PDLV may be adjusted according to the physical position of the program word line. In addition, when operation S50 is performed, the set level PDLV may be adjusted according to the number of repetitions of the program loop.

[0132] In operation S60 , a verification operation VER including an evaluation operation and a sensing operation may be performed. When operation S60 is performed, a level of a verification voltage VRY<1:7> applied to a program word line may be adjusted in proportion to the set level PDLV adjusted in operation S50 .

[0133] After operation S60, in operation S70, it may be checked whether the programming operation is successful. When the programming operation is successfully performed in operation S70 ("Yes" in operation S70), it may be determined that the programming operation is successful, and then the programming operation is terminated. When the programming operation is unsuccessful in operation S70 ("No" in operation S70), in operation S80, the count value of the programming loop may be increased. Herein, when the programming operation is unsuccessful in the first programming loop PL1, the count value of the programming loop may be increased from the first programming loop PL1 to the second programming loop PL2 through operation S80.

[0134] After operation S80, in operation S90, it may be checked whether the count value of the program loop is the maximum program loop count value. When the count value of the program loop is the maximum program loop count value in operation S90 ("Yes" in operation S90), it may be determined that the program operation fails and then the program operation is terminated.

[0135] In operation S90, when the count value of the program loop is less than the maximum program loop count value ('No' in operation S90), operations S40, S50, S60, S70, S80, and S90 may be sequentially performed again.

[0136] According to an embodiment of the present invention, a level of a precharge voltage used in a bit line precharge operation of a verification operation included in a program operation may be set to be lower by a set level than a level of a precharge voltage used in a bit line precharge operation of a read operation.

[0137] In addition, according to an embodiment of the present invention, a set level may be adjusted according to a physical location of a word line selected as a programming target.

[0138] In addition, according to an embodiment of the present invention, the set level may be adjusted according to the number of repetitions of the program loop.

[0139] Therefore, the reliability of the programming operation can be improved.

[0140] Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined in the appended claims. In addition, these embodiments may be combined to form additional embodiments.

Claims

1. A memory device, comprising: a memory cell array including a plurality of memory cell strings and coupled between a plurality of bit lines and a plurality of word lines, the plurality of bit lines being commonly coupled to a common source line; as well as Control Department: During a read operation for a selected memory cell coupled to a selected word line among the plurality of word lines, a bit line is precharged to a first level, and precharging the bit line to a second level during a verification operation of a program operation for the selected memory cell, The second level is lower than the first level by a set level.

2. The memory device according to claim 1, wherein: The control section further adjusts the setting level according to a physical position of the selected word line during the verification operation.

3. The memory device according to claim 2, wherein: The control section adjusts the setting level by increasing the setting level when the selected word line is located closer to the common source line.

4. The memory device according to claim 2, wherein: The control section further performs the programming operation by repeatedly performing a programming loop including a voltage applying operation and the verification operation until the programming operation is successfully performed, and The control unit further adjusts the setting level according to the number of repetitions of the programming loop.

5. The memory device according to claim 4, wherein: The control section adjusts the set level by increasing the set level in proportion to the number of repetitions.

6. The memory device according to claim 4, wherein: The control section further increases a level of a verification voltage applied to the selected word line during the verification operation in proportion to an increase in the set level.

7. The memory device according to claim 1, wherein: The control section includes a precharge control unit that precharges the bit line to one of the first level and the second level.

8. The memory device according to claim 7, wherein: The precharge control unit precharges the bit line to the first level during the read operation, and precharges the bit line to the second level during the verify operation.

9. The memory device according to claim 8, wherein: The control section further includes a positioning unit that detects a physical position of the selected word line, and The precharge control unit further adjusts the set level according to the physical location during the verification operation.

10. The memory device according to claim 9, wherein: The precharge control unit adjusts the set level by increasing the set level when the selected word line is located closer to the common source line.

11. The memory device according to claim 9, wherein: The control unit further includes a program operation unit that performs the program operation by repeatedly performing a program loop including a voltage applying operation and the verification operation until the program operation is successfully performed, and The precharge control unit further adjusts the setting level according to the number of repetitions of the programming loop.

12. The memory device according to claim 11, wherein: The precharge control unit adjusts the set level by increasing the set level in proportion to the number of repetitions.

13. The memory device according to claim 11, wherein: The program operation unit further increases a level of a verification voltage applied to the selected word line during the verification operation in proportion to an increase in the set level.

14. A method of operating a memory device, the memory device comprising a memory cell array, the memory cell array comprising a plurality of memory cell strings and coupled between a plurality of bit lines and a plurality of word lines, the plurality of bit lines being commonly coupled to a common source line, the method comprising: precharging a bit line to a first level during a read operation for a selected memory cell included in a cell string coupled to a selected word line among the plurality of word lines; as well as precharging the bit line to a second level during a verification operation of a program operation for the selected memory cell, The second level is lower than the first level by a set level.

15. The method according to claim 14, further comprising: During the verification operation, the set level is adjusted according to a physical location of the selected word line.

16. The method according to claim 15, wherein: The adjusting includes increasing the setting level when the selected word line is located closer to the common source line.

17. The method according to claim 15, further comprising: The program operation is performed by repeatedly performing a program loop including a voltage applying operation and the verification operation until the program operation is successfully performed, and in, The setting level is further adjusted according to the number of repetitions of the programming loop.

18. The method according to claim 17, wherein: The adjusting includes increasing the set level in proportion to the number of repetitions.

19. The method according to claim 17, further comprising: A level of a verification voltage applied to the selected word line during the verification operation is increased in proportion to an increase in the set level.

20. A method for operating a memory device, comprising: During a verification operation in a programming operation on a row of memory cells, lowering a precharge level of a bit line by a certain amount from a precharge level of a read operation on the row of memory cells; During the programming operation, the amount is increased as the row of memory cells is placed closer to a common source line and / or as the number of programming loops increases; and A level of a verification voltage applied to the row of memory cells is increased in proportion to the amount.

Images