Storage and calculation integration method, storage device and storage system

Abstract

The invention relates to a storage and calculation integration method, a storage device and a storage system. In a flash memory, a memory transistor array is used as a carrier of a weight matrix of a neural network, and a single-row memory transistor is used as a carrier of an offset value of the neural network. The size of the weight of any transistor in the memory transistor array can be adjusted by using its threshold voltage so as to configure its weight matrix for the neural network. Input data of the neural network are transmitted to the series bit lines of the storage transistor array, and bias data of the neural network are transmitted to the bias bit lines where the single-row storage transistors are located. Output data of the neural network is retrieved from a series of source lines of the memory transistor array, and a single row of memory transistors is configured with a bias transistor in any row of the memory transistor array, wherein the bias transistor and any row share the same source line. The threshold voltages of the single-row storage transistors are adjusted to tend to the same state, so that different bias values are prevented from being used by the same network level in the neural network.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of data storage, and more specifically, to a method, storage device and storage system suitable for storage and computing integration in the field of data storage. Background Art

[0002] In traditional computing devices, computing and storage are separated. The computing part, such as the processor, and the storage part, such as the hard disk or memory, each focus on their own fields, and the two basically do not interfere with each other. In order to improve computing speed and computing power, some manufacturers integrate the processor and memory closer in layout, such as shortening the lines between them and bringing them closer to each other in circuit board layout design; or directly merging the packaging process in the packaging stage.

[0003] In recent years, convolutional neural networks (CNNs) have been widely used in the field of image processing. As the network scale continues to expand and the model parameters continue to grow, there may be millions of parameter reading and calculation operations in a calculation cycle of the convolutional neural network CNN, and these parameters need to be moved between the processor and the memory. Hardware with separated storage and computing will face the problem of storage walls and is not suitable as a carrier for edge computing, such as computing near the device end. The hardware of the storage-computing integrated architecture advocates the merger of computing units and storage units, which can greatly break through the limitations of the storage wall. The industry also believes that floating gate flash memory (FLASH), which has a relatively mature semiconductor manufacturing process, is very suitable as a medium for realizing storage and computing integration, and cooperates to complete the deployment and computing of convolutional neural networks CNN on edge devices, or as a computing accelerator.

[0004] Storage and computing integrate storage and computing organically, and based on its huge potential to improve energy efficiency, it is expected to become an advanced computing architecture solution in the computing power era. However, there are also doubts: how to map the memory to the neural network and how to configure the neural network with dynamically adjustable weight matrices and bias values ​​are key issues that must be dealt with in-memory computing. For example, unreasonable configuration of bias values ​​usually results in the inability of neural network-based perceptrons to generate separation planes. This is an urgent problem to be solved in neural network classification processing. For memory, how to cooperate with the network to configure bias values ​​is a major problem. Summary of the invention

[0005] The present application relates to a method suitable for storage and computing integration, which is characterized by comprising:

[0006] In a flash memory, a storage transistor array is used as a carrier of a weight matrix of a neural network and a single-column storage transistor is used as a carrier of a bias value of the neural network. The weight of any transistor in the storage transistor array is adjusted using its threshold voltage, thereby configuring a weight matrix for the neural network.

[0007] Setting the input data of the neural network to be transmitted to a series of bit lines of the storage transistor array and setting the bias data of the neural network to be transmitted to the bias bit line where the single column storage transistor is located;

[0008] The output data of the neural network is set to be captured from a series of source lines of a memory transistor array, wherein each row of the memory transistor array is provided with a bias transistor sharing the same source line with the row;

[0009] By adjusting the threshold voltages of the storage transistors in the single column to be close to each other, it is avoided that a same network layer in the neural network uses different bias values.

[0010] In the above method, the original input data of the neural network is converted into an input quantity in the form of a voltage value, which is transmitted to a series of bit lines of the storage transistor array based on the input quantity sorted into a vector; and the original bias data of the neural network is converted into an input quantity in the form of a voltage value and transmitted to the bias bit line.

[0011] In the above method, the output data of the neural network is represented by the output current of the storage transistor array, the output current of a series of source lines of the storage transistor array is regarded as the output quantity of the storage transistor array sorted into a vector; and the current value of the bias transistor configured on any source line is merged into the output current of any source line, thereby serving as a bias value in the output quantity of any source line.

[0012] In the above method, the way of adjusting the weight of any transistor in the storage transistor array includes changing its floating gate injection charge; the weight size of any transistor at the location of the storage transistor array is adjusted by changing the floating gate injection charge of the transistor.

[0013] In the above method, when setting the bias value for the network level of the neural network, the way of adjusting the bias value of any bias transistor in the single-column storage transistor at least includes changing the charge injected into its floating gate; and adjusting the size of a bias value corresponding to the position of any bias transistor in the single-column storage transistor by changing the floating gate charge of the bias transistor.

[0014] In the above method, when setting the bias value for the network level of the neural network, the method of adjusting the bias value of any bias transistor in the single-column storage transistor at least includes changing the bias data transmitted to the single-column storage transistor; and adjusting the bias value corresponding to the position of any bias transistor in the single-column storage transistor by changing the bias data.

[0015] The above method, in which the threshold voltages of the respective single-column storage transistors are adjusted to a similar mode, at least includes: after the weight matrix of the neural network is configured, synchronously resetting the floating gate charges of the respective single-column storage transistors (such as programming the weight matrix first and programming the floating gate charges of the single-column storage transistors later).

[0016] The present application relates to a storage device suitable for storage and computing integration, characterized in that it includes:

[0017] Flash memory having an array of memory transistors and a single column of memory transistors presented in columns;

[0018] The storage transistor array is regarded as the carrier of the weight matrix of the neural network. The weight of any transistor in the storage transistor array is adjusted by using its threshold voltage, thereby configuring the weight matrix for the neural network.

[0019] A single row of memory transistors is considered as a carrier of bias values ​​for the neural network;

[0020] Setting the input data of the neural network to be transmitted to a series of bit lines of the storage transistor array and setting the bias data of the neural network to be transmitted to the bias bit line where the single column storage transistor is located;

[0021] The output data of the neural network is set to be captured from a series of source lines of a memory transistor array, wherein each row of the memory transistor array is provided with a bias transistor sharing the same source line with the row;

[0022] For the single-column storage transistors, the difference between the bias values ​​of the single-column storage transistors is reduced by adjusting the threshold voltages of the single-column storage transistors to be close to each other.

[0023] The above storage device is suitable for storage and computing integration, the original input data of the neural network is converted into an input quantity in the form of a voltage value, and is transmitted to a series of bit lines of the storage transistor array based on the input quantity sorted into a vector, wherein the original bias data of the neural network is converted into an input quantity in the form of a voltage value and transmitted to the bias bit line; and

[0024] The output data of the neural network is represented by the output current of the storage transistor array. The output current of a series of source lines of the storage transistor array is regarded as the output quantity of the storage transistor array sorted into a vector, wherein the current value of the bias transistor configured on any source line is merged into the output current of any source line, thereby serving as a bias value in the output quantity of any source line.

[0025] The above-mentioned storage device is suitable for integrated storage and computing. The method of adjusting the weight of any transistor in the storage transistor array includes changing its floating gate injection charge; the weight size of any transistor at the position of the storage transistor array is adjusted by changing the floating gate injection charge of the transistor.

[0026] The above-mentioned storage device suitable for integrated storage and computing, when setting the bias value for the network level of the neural network, the method of adjusting the bias value of any bias transistor in the single-column storage transistor at least includes changing the charge injected into its floating gate; by changing the floating gate charge of the bias transistor, the size of a bias value corresponding to the position of any bias transistor in the single-column storage transistor is adjusted.

[0027] The above-mentioned storage device suitable for integrated storage and computing, when setting the bias value for the network level of the neural network, the method of adjusting the bias value of any bias transistor in the single-column storage transistor at least includes changing the bias data transmitted to the single-column storage transistor; and adjusting the bias value size corresponding to the position of any bias transistor in the single-column storage transistor by changing the bias data.

[0028] The above-mentioned storage device suitable for integrated storage and computing, adjusting the threshold voltages of the respective single-column storage transistors to a similar mode includes: after the weight matrix of the neural network is configured, synchronously resetting the floating gate charges of the respective single-column storage transistors.

[0029] The present application relates to a storage system suitable for storage and computing integration, characterized in that it includes:

[0030] Flash memory having an array of memory transistors and a single column of memory transistors presented in columns;

[0031] A neural network, which is attached to a flash memory, uses a storage transistor array as a carrier of a weight matrix of the neural network and uses a single-row storage transistor as a carrier of a bias value of the neural network, and the size of the weight of any transistor in the storage transistor array is adjusted using its threshold voltage, thereby configuring the weight matrix for the neural network;

[0032] Setting the input data of the neural network to be transmitted to a series of bit lines of the storage transistor array and setting the bias data of the neural network to be transmitted to the bias bit line where the single column storage transistor is located;

[0033] The output data of the neural network is set to be captured from a series of source lines of a memory transistor array, wherein each row of the memory transistor array is provided with a bias transistor sharing the same source line with the row;

[0034] By adjusting the threshold voltages of the storage transistors in the single column to be close to each other, it is avoided that a same network layer in the neural network uses different bias values.

[0035] The above-mentioned storage system is suitable for integrated storage and computing. The method of adjusting the weight of any transistor in the storage transistor array at least includes changing its floating gate injection charge; the weight size of any transistor at the position of the storage transistor array is adjusted by changing the floating gate injection charge of the transistor.

[0036] The above-mentioned storage system is suitable for integrated storage and computing. When setting the bias value for the network level of the neural network, the method of adjusting the bias value of any bias transistor in the single-column storage transistor at least includes changing the charge injected into its floating gate; by changing the floating gate charge of the bias transistor, the size of a bias value corresponding to the position of any bias transistor in the single-column storage transistor is adjusted.

[0037] The above-mentioned storage system suitable for integrated storage and computing, when setting the bias value for the network level of the neural network, the method of adjusting the bias value of any bias transistor in the single-column storage transistor at least includes changing the bias data transmitted to the single-column storage transistor; and adjusting the bias value size corresponding to the position of any bias transistor in the single-column storage transistor by changing the bias data.

[0038] The above-mentioned storage system suitable for integrated storage and computing, adjusting the threshold voltages of the respective single-column storage transistors to a similar mode includes: after the weight matrix of the neural network is configured, synchronously resetting the floating gate charges of the respective single-column storage transistors.

[0039] Based on the foregoing, one of the biggest advantages of the present application is that the core parameters of the neural network, such as weights and biases, are enabled to the storage tube, thereby attaching the neural network to the memory. The weight matrix of the neural network is directly mapped to the storage transistor array and the transistor threshold voltage can be adjusted to dynamically configure the weight matrix of the neural network to adapt to the weight matrix (weight matrix) of the neural network. Update, such as matching back propagation. And synchronously map other extremely important bias values ​​(bias unit) or intercept terms of the neural network directly to a single column of storage transistors or a column of storage transistors in the storage transistor array, so as to adapt the bias value for the memory-based neural network and prevent neural networks such as perceptrons from being unable to find a suitable discrimination plane for classification.

[0040] Based on the above, the second biggest advantage of this application is that it adopts a non-von Neumann architecture to solve the problems of compilation wall, storage wall, and power consumption wall under the traditional von Neumann architecture. One convenient aspect of compilation is to realize the programming of weights and bias values ​​by adjusting the threshold voltage of the transistor. This solution only needs to configure the voltage or current of the three terminals of the transistor at the transistor to realize the weight and bias compilation. Considering that the compilation compatible with the information such as voltage and current is performed on the traditional memory, there is no obstacle in implementing the relevant compilation of this part. Moreover, unlike the traditional solution, it is not required to perform data exchange between the memory and the processor and the subsequent storage wall. Data storage and data calculation, especially the accumulation and bias of the product, occur inside the memory, solving the problem of storage wall. Since the specific implementation of the neural network is based on the premise that there is no need to implement a large amount of data transfer between the memory and the processor, and since most of the energy consumption of the power consumption wall is generated during the data transfer process, such as the data transfer power consumption is more than a thousand times the computing power consumption, it also solves the high energy consumption problem of neural networks and their artificial intelligence application scenarios.

[0041] Based on the foregoing, the third biggest advantage of this application is to promote a substantial doubling of computing power. By adopting storage-computing integrated technology, the weight part of a large number of multiplication and addition calculations involved in AI calculations can be stored in storage units, and the bias or intercept operations involved in the AI ​​calculation function relationship are also stored in the storage unit. They can be modified on the existing transistor circuit part of the storage unit, so as to facilitate the operation of data calculation and processing while updating parameters, and complete neural networks such as convolution operations in storage. Convolution operations with a large number of multiplications and additions are the core components of deep learning, so in-memory computing and in-memory logic are very suitable for deep neural network applications in the direction of artificial intelligence and big data technologies based on AI. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to make the above purposes, features and advantages more understandable, the following text will explain the specific implementation methods in detail in conjunction with the drawings. After reading the following description and referring to the following drawings, the features and advantages of the present application will become apparent.

[0043] Figure 1 It is to select some storage tubes as weight carriers and select some storage tubes as bias carriers.

[0044] Figure 2 The input data to the neural network comes from a series of bit lines in the storage transistor array.

[0045] Figure 3 It is to transmit the bias data of the neural network to the bias bit line where the single column storage transistor is located.

[0046] Figure 4The weight value of the transistor in the transistor array is adjusted by changing the charge injected into the floating gate.

[0047] Figure 5 It is the relationship between the weight matrix and bias value of the neural network in the local level of the neural network.

[0048] Figure 6 It is the unreasonable bias value that causes the neural network-based perceptron to be unable to produce a separation plane.

[0049] Figure 7 The method is to adjust the threshold voltages of the biased single-column storage transistors to be similar.

[0050] Figure 8 It is the unreasonable bias value that causes the neural network-based perceptron to be unable to produce a separation plane. DETAILED DESCRIPTION

[0051] The technical solutions disclosed in the present application will be clearly and completely described below in conjunction with specific embodiments. However, the embodiments described are only embodiments used for narrative explanation in the present application and are not all embodiments. Based on these embodiments, technicians in this field should realize that any solution obtained without creative work falls within the scope of protection of the present application.

[0052] See also Figure 1 , the flash memory uses at least two storage transistor areas: region 0 is mainly used to map to the weight matrix of the neural network, and region 1 is mainly used to map to the bias value of the neural network. Since each element in the weight matrix has a one-to-one correspondence with each storage transistor in region 0, this application temporarily refers to the storage transistors in region 0 where the elements are placed as an array, and region 1 as a single-column storage transistor. This is a way to classify the many storage transistors in the flash memory.

[0053] See also Figure 1For the two storage transistor areas in the flash memory: region 0 is still used to map to the weight matrix of the neural network, and region 1 is still used to map to the bias value of the neural network, but they belong to the same storage transistor array, but the functions of the two are different. Therefore, in another way of classification, all the storage transistors in region 0 and region 1 can be called an array, and a sub-array in this array is used as the carrier of the weight matrix of the neural network, and a single-column storage transistor in this array is used as the carrier of the bias value of the neural network. The location of the sub-array corresponding to the weight is region 0, and the location of the sub-array corresponding to the bias value carrier is region 1. This is another way to classify the memory.

[0054] See also Figure 1 Regardless of the classification method, it can be expressed as: using a storage transistor array such as region0 in a flash memory as a carrier of the weight matrix of the neural network and using the aforementioned single-column storage transistor such as region1 as a carrier of the bias value of the neural network.

[0055] See also Figure 1 , the figure shows the circuit of an existing general-purpose NOR flash memory, and its working principle is that a floating gate (Floating Gate) for storing charges such as electrons can be formed between the source S and the drain D of the storage transistor, that is, on the semiconductor where current is conducted in one direction, and the floating gate is wrapped with a layer of silicon oxide film insulator. Above the floating gate is a selection / control gate (Control Gate) that controls the conduction current between the source and the drain. The charges on the floating gate, such as electrons, will not disappear due to power failure, so flash memory is a non-volatile memory. The write operation, such as applying a positive voltage to the control electrode, allows charges such as electrons to pass through the insulating layer into the floating gate. The erase operation is just the opposite, such as applying a positive voltage to the substrate to separate electrons from the floating gate to achieve erasure. The data operation of flash memory belongs to the prior art, and it will not be described separately in this article. The read, write or erase operations of flash memory in the prior art can be applied to the flash memory of this application.

[0056] See also Figure 1 The weight of any transistor in the storage transistor array, such as region 0, is adjusted using its threshold voltage to configure a weight matrix for the neural network.

[0057] See also Figure 1, the input data of the neural network is set to be transmitted to the series bit lines of the storage transistor array such as region0, and the bias data of the neural network is transmitted to the bias bit lines of the single column storage transistor such as region1. The so-called series bit lines are shown as B1, B2, B3...BN in the figure. The bias bit lines are shown as B_Bias in the figure.

[0058] See also Figure 1 , describes flash memory in array form: the gate of each row of transistors is connected to a common word line and the drain of each column of transistors is connected to a common bit line and the source of each column of transistors is connected to a common source line.

[0059] See also Figure 1 , with respect to the row word line example, the gates of the first row transistors are connected to the word line G1 and the gates of the second row transistors are connected to the word line G2, and the gates of the Mth row transistors are connected to the word line GM. More omitted rows are not repeatedly shown in the figure. The total of M rows of transistors is regarded as the row element of the matrix M×N.

[0060] See also Figure 1 , regarding the row source line example, the source of each transistor in the first row is connected to the source line S1, the source of each transistor in the second row is connected to the source line S2, and the source of each transistor in the Mth row is connected to the source line SM. More omitted rows are not repeatedly shown in the figure. A single column storage transistor such as region1 is configured with a bias transistor that shares a source line with any row in any row of the storage transistor array such as region0.

[0061] See also Figure 1 , regarding the single-column storage tube, the single-column storage transistor in the first row of the storage transistor array may be configured with a bias transistor sharing the source line S1 with the first row, and its gate is connected to G1, its drain is connected to B_Bias, and its source is connected to S1. The same can be deduced in the single-column storage tube, and the single-column storage transistor in the second row of the storage transistor array may be configured with a bias transistor sharing the source line S2 with the second row, and its gate is connected to G2, its drain is connected to B_Bias, and its source is connected to S2. The same can be deduced in the single-column storage tube, and the single-column storage transistor in the Mth row of the storage transistor array may be configured with a bias transistor sharing the source line SM with the Mth row, and its gate is connected to GM, its drain is connected to B_Bias, and its source is connected to SM.

[0062] See also Figure 1 For the example of column bit lines, the drains of the first column transistors are connected to the bit line B1, the drains of the second column transistors are connected to the bit line B2, and the drains of the Nth column transistors are connected to the bit line BN. More omitted columns are not shown repeatedly in the figure. The total N columns of transistors are regarded as column elements of the matrix M×N.

[0063] See also Figure 1Regarding the column bit line example, the drain of each transistor in a single column of memory transistors, such as region1, is connected to a bit line B_Bias (the bit line B_Bias is called a bias bit line).

[0064] See also Figure 1 The original function of the flash memory shown in the figure is to store code elements 1 or 0. In other words, the flash memory has no special use in traditional computers, servers or other similar electronic devices. However, the present application no longer regards the flash memory as a storage space that only stores code elements 1 or 0, but advocates changing the circuit architecture of the flash memory to a computing unit that can participate in artificial intelligence, and the underlying physical structure of the flash memory remains almost unchanged.

[0065] See also Figure 1 , set to capture the output data of the neural network from the series source lines B1-BN of the storage transistor array, such as region0. As mentioned above, a single-column storage transistor in any row of the storage transistor array (in this case, for example, the Qth row) can be configured with a bias transistor that shares the same source line SQ as the row, and the gate of the bias transistor is connected to the bit line GQ, the drain is connected to B_Bias, and the source is connected to the source line SQ. 1≤Q≤M.

[0066] See also Figure 1 In an optional embodiment, by adjusting the threshold voltages of the storage transistors in a single column, such as region 1, to be close to each other, that is, the threshold voltages of the storage transistors in different rows 1-M in the single column are set to be close to each other. In an optional embodiment, it is possible to avoid using different bias values ​​for the same network level in the neural network, which will be described in detail below. The positive integers Q and M are both greater than 1.

[0067] See also Figure 2 , using flash memory-based computing units to replace traditional computers is because there are several major drawbacks in the operation phase of computers executing neural networks: reading and writing data from the memory outside the processor, the data transfer time is hundreds or thousands of times the operation time, the power consumption of the whole process is about 60%-90%, the energy efficiency is very low, and the incidental storage wall problem has become a major obstacle to data computing applications. In particular, the biggest challenge for accelerating deep learning in neural networks is the frequent movement of data between computing units and storage units. Although multi-core CPUs or multi-core GPUs are used to improve computing power, in the post-Moore era, storage bandwidth restricts the effective bandwidth of computing systems and makes the overall computing power growth difficult. Running weight calculations of neural networks or running inference calculations of neural networks on traditional computers is time-consuming and power-consuming, which is one of the most prominent manifestations of this drawback.

[0068] See also Figure 2 , the neural network has encountered a bottleneck in its development due to the introduction of a large number of parameters. Each output neuron of the fully connected layer is connected to all input neurons. According to the assumptions in the figure: if the number of input neurons is N and the number of output neurons is M, then there are at least approximately N×M weights or M biases that need to be trained and calculated. For each output neuron of the convolutional layer, there are usually input neurons within the coverage of the convolution kernel connected to it, and the convolution kernel used for all outputs is the same. Although local connections and weight sharing reduce the parameters of the convolutional layer, a large amount of calculations still need to be performed under the conditions of large-size image input and deep neural networks. The reading and calculation of large amounts of data face the memory bottleneck and computing bottleneck of the network. The power consumption and latency of neural networks have risen sharply, limiting the application of neural networks.

[0069] See also Figure 2 In the design, bit lines B1-BN are used as input and source lines S1-SM are used as output. Figure 1 The flash memory is regarded as the physical carrier that can realize the neural network NET.

[0070] See also Figure 3 In order to explain the specific implementation process, we first design a matrix Ma_wei as follows.

[0071]

[0072] See also Figure 2 , the input of bit lines B1-BN is represented by the vector Ma_in=[B1, B2...BN]. For the convenience of mathematical expression, the input of bit line B1 needs to be mapped to X1, the input of bit line B2 needs to be mapped to X2, the input of bit line B3 needs to be mapped to X3, and the input of bit line BN needs to be mapped to X N .

[0073] See also Figure 2 , the output of source line S1-SM is represented by vector Ma_out = [S1, S2...SM]. For the convenience of mathematical expression, the output of source line S1 needs to be mapped to Y1, the output of source line S2 needs to be mapped to Y2, the output of source line S3 needs to be mapped to Y3, ..., the output of source line SM needs to be mapped to Y M .

[0074] See also Figure 2 The purpose of the flash memory is to perform the computing function of the neural network NET. The specific computing process is expressed by the following formula. In fact, this process is also a detailed example of simulating the flash memory as a computing unit or a quasi-computing unit. M etc. as representatives to illustrate this spirit.

[0075] Y1=X1*W11 +X2*W 12 +X3*W 13 +…X N *W 1N

[0076] Y2=X1*W 21 +X2*W 22 +X3*W 23 +…X N *W 2N

[0077] Y M =X1*W M1 +X2*W M2 +X3*W M3 +…X N *W MN

[0078] See also Figure 2 In order to solve the aforementioned bottlenecks, the non-von Neumann architecture shown in the figure can provide greater computing power and higher energy efficiency in specific fields, and can surpass existing ASIC computing chips. In-memory computing and in-memory logic, that is, the integrated storage and computing technology directly uses the memory for data processing or calculation, which can completely eliminate the bottleneck of the von Neumann computing architecture.

[0079] See also Figure 2 A more intuitive expression is to use vector-matrix multiplication to show the aforementioned complex operation. The vector-matrix expression flash memory performs local data processing of the neural network NET as follows.

[0080]

[0081] See also Figure 2 If we define X1 to X N is the input layer of the neural network NET, then Y1 to Y N The corresponding layer is the output layer of the neural network NET. Figure 1 The flash memory completes the entire vector operation from the input layer to the output layer, and this operation is very different from the operation of the traditional von Neumann computer, because its operation only needs to measure the respective signal quantities from the source lines S1-SM, and the single multiplication and addition do not need to be implemented one by one. The final operation result can be fully reflected from the signal quantities of the source lines S1-SM at one time. So it is called quasi-computing. The operation of the traditional von Neumann computer must implement all multiplications and additions one by one, which is the biggest difference between the two.

[0082] See also Figure 2, the neural network NET based on flash memory is suitable for the field of image processing. Assume that data such as pictures or videos with pixel values ​​or grayscale values ​​(artificial intelligence, autonomous driving, face recognition, target detection) are input into the neural network NET based on flash memory, and the image Gr_in is taken as an example below.

[0083] See also Figure 2 , the pixels in the image Gr_in are divided into multiple rows and columns, and the pixel corresponding to the address of the 0th pixel is defined as g1, the pixel corresponding to the address of the 1st pixel is defined as g2, the pixel corresponding to the address of the 2nd pixel is defined as g3, and so on. The pixel corresponding to the last pixel address is gn. According to the arrangement rule and address regulations of the pixel matrix, the gray value of any pixel can be obtained by the image obtained by shooting. Allow the gray value or pixel value of n pixels (belonging to the image Gr_in) to be coupled to the X1 to X N Of course, the grayscale value or pixel value can also be normalized or similar image data processing can be performed.

[0084] See also Figure 2 , one issue worth noting is that the input quantity format of the bit lines B1-BN should conform to the inherent characteristics of the flash memory, that is, the input value of the bit lines B1-BN is not directly equivalent to the pixel value g1-gn. Therefore, in an optional embodiment, the pixel values ​​g1-gn are converted from digital to analog by a DAC device such as a digital-to-analog converter packaged together with the flash memory, and the analog quantities corresponding to the pixel values ​​g1-gn are then input to the bit lines B1-BN. The DAC (Digital to Analog Converter) device can also be directly integrated with the flash memory on the same semiconductor chip during the wafer manufacturing stage. At this point, the data contained in the image Gr_in can be smoothly coupled with the flash memory. Another important factor is that the final storage location or space of the image Gr_in must usually be various types of memory. Then the storage location of the image Gr_in and the location where the matrix operation is performed are the same flash memory. The outstanding advantage of this inherent characteristic can be revealed. The processor CPU or GPU will no longer need to read data from the memory to itself to perform matrix operations. The storage and calculation actions are all implemented in the memory. The concerns about reading and writing data from the processor to the memory, the time cost of data transportation, etc. mentioned in the previous article will no longer exist.

[0085] See also Figure 2 There is an important problem that has not been solved: In order to explain the specific implementation process of the neural network, the previous article specially designed the matrix Ma_wei involved in the network calculation. However, how to map the M*N vector matrix Ma_wei to the transistors in the flash memory? Figure 1 The M×N elements shown still present concerns that need to be resolved.

[0086] See also Figure 3 , regarding the relationship between pixel values ​​g1-gn and bit lines B1-BN, pixel value g1 is converted into voltage value V1 through DAC digital-to-analog conversion, pixel value g2 is converted into voltage value V2 through digital-to-analog conversion, pixel value g3 is converted into voltage value V3 through digital-to-analog conversion, and so on, pixel value gn is converted into voltage value VN through digital-to-analog conversion. According to the interface correspondence shown in the figure, voltage value V1 is connected to bit line B1, voltage value V2 is connected to bit line B2, voltage value V3 is connected to bit line B3, and so on, voltage value VN is connected to bit line BN. According to the rule, the larger the pixel value, the larger the converted bit line voltage value, and the smaller the pixel value, the lower the converted bit line voltage value. Furthermore, the number of transistor layouts, that is, the size of the matrix M×N, should have a corresponding relationship with the pixel size of the image Gr_in.

[0087] See also Figure 3 , with respect to the matrix Ma_wei, the gates of the transistors in the first row are connected to the word line G1, the gates of the transistors in the second row are connected to the word line G2, and the gates of the transistors in the Mth row are connected to the word line GM. The weights generated by the transistors in the first row of the weight matrix are recorded as W 11 , W 12 , W 13 , ...W 1N The second row of transistors in the weight matrix have their own weights, which are recorded as W. 21 , W 22 , W 23 , ...W 2N The weights generated by the Mth row of transistors in the weight matrix are recorded as W. M1 , W M2 , W M3 , ...W MN . So far, each transistor is configured with a corresponding weight value that contributes to the matrix Ma_wei involved in the network calculation. Traditional transistors themselves do not have features associated with weights, especially flash memory and neural networks have no direct relevance, so how to map weights to transistors is another key problem that needs to be solved.

[0088] See also Figure 3, the total of M rows and N columns of transistors are regarded as M×N matrix elements. The definition of each weight value in the matrix Ma_wei is the basis for realizing the neural network NET. The figure shows that the source current of each row of transistors flows to the common source line of the row of transistors, and the figure shows that the drain of each column of transistors is connected to the common bit line of the column of transistors. This layout of transistors will provide a feasible solution for how to define the weights of transistors. For example, the source current convergence characteristics of each row of transistors correspond to the multiplication and accumulation calculation algorithm of the vector matrix multiplication mentioned above.

[0089] See also Figure 3 To explain how to map weights to transistors, let’s first introduce the relationship between the current and threshold of the storage transistor and the applied voltage: The threshold voltage of the gate is V TH ; The process parameter K of the storage transistor related to the process is μCW / L, where W / L is the aspect ratio of the transistor. For a storage transistor with a certain manufacturing process and a certain size, the process parameter K is almost a constant; the voltage between the gate and the source is V GS and the voltage V between the transistor drain and source DS Can satisfy K(V GS -V TH )V DS = I. When the current I flowing through the transistor operates in the linear region or the triode region, if the current I of a single transistor performs multiplication and the output currents I of a row of transistors perform accumulation, this is equivalent to the multiplication and accumulation calculation of the matrix multiplication.

[0090] See also Figure 3 , for the first row of transistors (gate coupled to G1): the current I1 of the first transistor is approximately K(V GS1 -V TH1 )V DS1 =I1, according to the same current formula, the current I2 of the second transistor is calculated to be approximately K(V GS2 -V TH2 )V DS2 =I2, Nth transistor current K(V GSN -V THN )V DSN =IN. The voltage between the gate and source of the first transistor is V GS1 The voltage between the drain and source is V DS1 , the threshold voltage is V TH1 , the voltage between the gate and source of the second transistor is V GS2 The voltage between the drain and source is V DS2 , the threshold voltage is V TH2 , the voltage between the gate and source of the Nth transistor is V GSNThe voltage between the drain and source is V DSN , the threshold voltage is V THN .

[0091] See also Figure 3 For the first row of transistors (gate coupled to G1): the source currents of the first transistor to the Nth transistor all flow to the common source line S1 of the transistors in the row, and the current of the source line S1 is recorded as IS1.

[0092] IS1=I1+I2+I3+…IN+IB1

[0093] See also Figure 3 , for the first row of transistors (gate coupled to G1): if W is defined at the location of the first transistor 11 With K(V GS1 -V TH1 ) are proportional or equal, and V1 and V DS1 If the current I1 flowing through the first transistor is proportional or equal, the current I1 can be expressed as I1 = W 11 × V1. If W is defined at the location of the second transistor 12 With K(V GS2 -V TH2 ) are proportional or equal, and V2 and V DS2 If the current I2 flowing through the second transistor is proportional or equal, the current I2 can be expressed as I2 = W 12 × V2. If W is defined at the location of the third transistor 13 With K(V GS3 -V TH3 ) are proportional or equal, and V3 and V DS3 If the current I3 flowing through the third transistor is proportional or equal, the current I3 can be expressed as I3 = W 13 ×V3. If W is defined at the location of the Nth transistor 1N With K(V GSN -V THN ) are proportional or equal, and VN and V DSN If they are proportional or equal, the current IN flowing through the aforementioned Nth transistor can be expressed as IN = W 1N ×VN or a multiple of the product.

[0094] See also Figure 3, for the first row of transistors (gate coupled to G1): the current of source line S1 is recorded as IS1, which can be expressed as follows after the conversion of the formula (Y1=IS1 can also be defined). The prerequisite is that the source current of the first row of transistors has the characteristic of converging, which corresponds to the multiplication and accumulation calculation algorithm of vector-matrix multiplication. Therefore, it is one of the main factors that flash memory can replace some functions of traditional CPU or GPU.

[0095] IS1=Y1=W 11 *V1+W 12 *V2+W 13 *V3+…W 1N *VN+IB1

[0096] See also Figure 3 , for the second row of transistors (gate coupled to G2): the current of the source line S2 is denoted as IS2 and can be expressed in the following way after conversion of the formula (Y2=IS2 can also be defined).

[0097] IS2=Y2=W 21 *V1+W 22 *V2+W 23 *V3+…W 2N *VN+IB2

[0098] See also Figure 3 , for the Mth row of transistors (gate coupled to GM): the current of the source line SM is recorded as ISM, which can be expressed as follows after the conversion of the formula (Y can also be defined M =ISM).

[0099] ISM=Y M =W M1 *V1+W M2 *V2+W M3 *V3+…W MN *VN+IBM

[0100] See also Figure 3 , as defined above, X1 to X N As the input layer of the neural network NET, define Y1 to Y N The corresponding is the output layer of the neural network NET. So far, the first row of transistors in the flash memory has completed a vector operation Y1 from the input layer to the output layer, and the result of Y1 can be directly calculated at one time by sensing the current of the source line S1 of the first row of transistors, without having to calculate W separately. 11 ×V1 or W 12 ×V2 or W 1N×VN, etc., belong to the class calculation under the non-von Neumann architecture. The calculation result is not obtained through numerical calculation, but through current sensing. Similarly, the second row of transistors in the flash memory completes a vector operation Y2 from the input layer to the output layer, the third row of transistors in the flash memory completes a vector operation Y3 from the input layer to the output layer, and the Mth row of transistors in the flash memory completes a vector operation Y from the input layer to the output layer. M In an optional embodiment, the current IS1-ISM is converted from analog to digital by an ADC device such as an analog-to-digital converter packaged together with the flash memory, and the digital quantities corresponding to the current values ​​are suitable for various electronic devices. The ADC (Analog to Digital Converter) device can also be directly integrated with the flash memory on the same semiconductor chip during the wafer manufacturing stage.

[0101] See also Figure 3 One of the tasks performed by the transistor array of the flash memory is to construct the matrix Ma_wei, and each element in the matrix corresponds to the weight matrix of the neural network NET.

[0102] See also Figure 3 , the matrix Ma_wei takes the neural network NET input layer Lay1 / hidden layer Lay2 as an example. When the input data is input to the input layer Lay1, there is a matrix Ma_wei between the input layer Lay1 and the hidden layer Lay2, and the input data is converted into voltage V1-VN to give to the input layer Lay1, then the output obtained by the hidden layer Lay2 is equivalent to the input data obtained by performing matrix operations by the weight matrix Ma_wei. The voltage signal is the type of input and the output data is the current value signal. The weight matrix Ma_wei affects the input voltage signal and thus affects the amplitude of the output current value. This is also the general process of realizing artificial intelligence operations through NOR Flash memory.

[0103] See also Figure 2 For the first row of transistors (gate coupled to G1): the current I1 of the first transistor should be superimposed with a bias value or intercept term Bias1 represented by addition 101 based on the bias, the current I2 of the second transistor should be superimposed with the bias value or intercept term Bias1 represented by addition 101 based on the bias, and the current I3 of the third transistor should be superimposed with the bias value or intercept term Bias1 represented by addition 101 based on the bias. The current IN of the Nth transistor should be superimposed with the bias value or intercept term Bias1 represented by addition 101 based on the bias. That is, the current IS1 of the source line S1.

[0104] See also Figure 3Regarding the bias, take the neural network NET input layer Lay1 / hidden layer Lay2 as an example. This network level should use the same bias value Bias1. That is, when each input node or neuron of the input layer Lay1 is used to calculate each hidden node or neuron of the subsequent hidden layer Lay2, different input nodes or neurons of the input layer Lay1 network level should use the same bias value Bias1. Otherwise, it is not logical.

[0105] See also Figure 3 For other biases, take the neural network NET hidden layer Lay2 / output layer Lay3 as an example. This network level should use the same bias value Bias2. That is, when each hidden node or neuron of the hidden layer Lay2 is used to calculate each output node or neuron of the subsequent output layer Lay3, different input nodes or neurons of the hidden layer Lay2 network level should use the same bias value Bias2 (note that the matrix corresponding to Bias2 is not repeated).

[0106] See also Figure 3 , for the first row of transistors (gate coupled to G1): the gate of the single-column storage transistor region1 located in the so-called first row, i.e., the first bias transistor, is coupled to G1, and the source current of the first bias transistor in the first row flows to the common source line S1 of the transistors in the row, and the source current of the first bias transistor is recorded as IB1.

[0107] See also Figure 3 , for the first row of transistors (gate coupled to G1): the current IB1, i.e. the first bias transistor current, is calculated as K(V GSB1 -V THB1 )V DSB1 = IB1. The voltage between the gate and source of the first bias transistor in the current IB1 relationship is V GSB1 The voltage between the drain and source is V DSB1 , the threshold voltage is V THB1 .

[0108] See also Figure 3 Regarding the relationship between bias data and bias bit line B_Bias: the bias data is converted into voltage value VB through DAC digital-to-analog conversion, and the voltage value VB is connected and input to bias bit line B_Bias. The bias data of a neural network is different from the input data of a neural network: the bias data is mainly a parameter for bias modulation of the result after the input data participates in the convolution operation. For example, the output data IS1 includes the parameter for bias modulation of the result after the input data V1-VN participates in the convolution operation, namely the bias data IB1.

[0109] See also Figure 3, for the first row of transistors (gate coupled to G1): the single column storage transistor region1 is located at the transistor of the first row, i.e., the first bias transistor. If B is defined IB1 With K(V GSB1 -V THB1 ) are proportional or equal, and VB and V DSB1 If the current IB1 flowing through the first bias transistor is proportional or equal, it can be expressed as IB1 = B IB1 ×VB or a multiple of the product.

[0110] See also Figure 3 , for the second row of transistors (gate coupled to G2): the gate of the single-column storage transistor region1 located in the so-called second row, i.e., the second bias transistor, is coupled to G2, and the source current of the second bias transistor in the second row flows to the common source line S2 of the transistors in the row, and the source current of the second bias transistor is recorded as IB2.

[0111] See also Figure 3 , for the second row of transistors (gate coupled to G2): the current IB2, i.e. the second bias transistor current, is calculated as K(V GSB2 -V THB2 )V DSB2 = IB2. The voltage between the gate and source of the second bias transistor in the current IB1 relationship is V GSB2 The voltage between the drain and source is V DSB2 , the threshold voltage is V THB2 .

[0112] See also Figure 3 Regarding the relationship between bias data and bias bit line B_Bias: the bias data is converted into voltage value VB through DAC digital-to-analog conversion, and the voltage value VB is connected and input to bias bit line B_Bias. The bias data of the neural network is different from the input data of the neural network: the bias data is mainly a parameter for bias modulation of the result after the input data participates in the convolution operation. For example, the output data IS2 includes the parameter for bias modulation of the result after the input data V1-VN participates in the convolution operation, namely the bias data IB2.

[0113] See also Figure 3 , for the second row of transistors (gate coupled to G2): the single column storage transistor region1 is located at the second row of transistors, i.e., the second bias transistor, if B is defined IB2 With K(V GSB2 -V THB2 ) are proportional or equal, and VB and V DSB2 If the current IB2 flowing through the second bias transistor is proportional or equal, it can be expressed as IB2 = BIB2 ×VB or a multiple of the product.

[0114] See also Figure 3 , for the Mth row of transistors (gate coupling GM): the single column storage transistor region1 is located in the Mth row of transistors, that is, the gate coupling GM of the Mth bias transistor, the source current of the Mth bias transistor in the Mth row flows to the common source line SM of the row of transistors, and the source current of the Mth bias transistor is IBM.

[0115] See also Figure 3 , for the Mth row of transistors (gate coupling GM): the current IBM, i.e. the current of the Mth bias transistor, is calculated and recorded as K(V GSBM -V THBM )V DSBM = IBM. In the current IBM relationship, the voltage between the gate and source of the Mth bias transistor is V GSBM The voltage between the drain and source is V DSBM , the threshold voltage is V THBM .

[0116] See also Figure 3 Regarding the relationship between bias data and bias bit line B_Bias: the bias data is converted into voltage value VB through DAC digital-to-analog conversion, and the voltage value VB is connected and input to the bias bit line B_Bias. The bias data of the neural network is different from the input data of the neural network: the bias data is mainly a parameter for bias modulation of the result after the input data participates in the convolution operation. For example, the output data ISM includes the parameter for bias modulation of the result after the input data V1-VN participates in the convolution operation, namely the bias data IBM.

[0117] See also Figure 3 , for the Mth row of transistors (gate coupling GM): the single column storage transistor region1 is located at the Mth row of transistors, i.e., the Mth bias transistor, and defines B IBM With K(V GSBM -V THBM ) are proportional or equal, and VB and V DSBM If they are proportional or equal, the current IBM flowing through the Mth bias transistor can be expressed as IBM = B IBM ×VB or a multiple of the product.

[0118] See also Figure 3In an optional embodiment, the original input data of the neural network NET is converted into input quantities in the form of voltage values, such as V1, V2, V3...VN, so as to be respectively transmitted to a series of bit lines B1-BN of the storage transistor array based on the input quantities sorted into a vector Ma_in, that is, Ma_in=[B1=V1, B2=V2...BN=VN].

[0119] See also Figure 3 In an optional embodiment, the original bias data of the neural network NET is converted into an input quantity in the form of a voltage value, such as VB, and transmitted to the bias bit line B_Bias.

[0120] See also Figure 3 In an optional embodiment, the output data of the neural network NET is represented by the output current of the storage transistor array, such as IS1, IS2...ISM, and the output current of the source lines S1-SM of the storage transistor array is regarded as the output quantity of the storage transistor array sorted into a vector, that is, Ma_out=[S1=IS1, S2=IS2...SM=ISM].

[0121] See also Figure 3 In an optional embodiment, the current value of a bias transistor configured on any source line is merged into the output current of any source line, thereby serving as a bias value in the output quantity of any source line.

[0122] See also Figure 3 In an optional embodiment, the current value IB1 of the bias transistor configured on the source line S1 is merged into the output current IS1 of the source line S1 as a bias value Bias1 in the output quantity of the source line S1.

[0123] See also Figure 3 In an optional embodiment, the current value IB2 of the bias transistor configured on the source line S2 is merged into the output current IS2 of the source line S2 as a bias value Bias1 in the output quantity of the source line S2.

[0124] See also Figure 3 In an optional embodiment, the current value IBM of the bias transistor configured on the source line SM is merged into the output current ISM of the source line SM as a bias value Bias1 in the output quantity of the source line SM.

[0125] See also Figure 3In addition to being used for AI computing, flash memory can also be used for other computing applications such as brain-like chips. It represents a future mainstream big data computing chip architecture, and can also be used as a core computing module for low-energy supercomputing centers. For example, NOR FLASH in-memory computing can support about 300M of deep learning weight parameters in a single chip, and can perform calculations without additional memory.

[0126] See also Figure 3 Compared with other types of general-purpose computing, flash memory has several important characteristics described below for neural network NET computing, which are also its own advantages.

[0127] See also Figure 3 First, the calculation process of the neural network NET based on flash memory is simple and allows a large amount of parallelism. The calculation of the neural network NET no longer uses the branch prediction and speculative execution mechanisms of the CPU used in general computing to run efficiently. This feature allows the flash memory hardware accelerator for the neural network NET to reduce or break away from the use of CPU or GPU as much as possible, thereby performing low-cost and high-efficiency calculations.

[0128] See also Figure 3 , Secondly, the calculations performed by the neural network NET consist of only a few single operations, such as matrix multiplication and vector operations, the application of convolution kernels, and other linear algebra operations. This makes the neural network NET accelerator similar to the GPU, using a large number of simple computing units to cope with the complex data operations that the industry needs to perform.

[0129] See also Figure 3 ,Thirdly, the neural network NET itself shows a great sparsity feature, and a large number of its parameters and calculation results are very small, or even close to zero. Utilizing the sparsity feature can make the operation reasonably use the data to skip the calculation of multiplying by zero, thereby improving the overall calculation speed, especially matrix operations.

[0130] See also Figure 3Fourthly, the neural network NET allows for low-precision calculations such as low-bit precision. For example, for most artificial intelligence applications, 8-bit or 4-bit (meaning a small transistor array) fixed-point numbers can be used for quantization without losing recognition accuracy. Low-precision fixed-point numbers can be used for calculations based on artificial intelligence application scenarios to increase reasoning speed and reduce power consumption. Power loss is a point worth emphasizing. Traditional CPUs / GPUs generate a lot of heat during model training and reasoning stages, and most of the power is lost in the heat dissipation of the processor. The class calculation of this application completely avoids the processor's accumulation process for monocular multiplication and multiplication results, and reduces unnecessary data transfer between the processor and the memory, reducing energy consumption to 1 / 10 to 1 / 100 of the original.

[0131] See also Figure 3 For example, the size of intelligent voice models is usually hundreds of KB to several megabytes, and the size of image inference models on the end side is usually between several megabytes and tens of megabytes. The storage space of conventional NOR FLASH on the market can easily handle models of this size. Therefore, even the NOR FLASH in-memory computing chip of a handheld terminal is sufficient to meet the needs of most AI scenarios. Under the premise of optimizing the NOR FLASH structure, such as the series-parallel or cascade connection of many flash memories, it is almost comparable to all artificial intelligence application scenarios that can be achieved by GPUs.

[0132] See also Figure 4 , the previous article focuses on weights such as W 11 and transistor parameters such as K(V GS1 -V TH1 ) is explained. In the neural network NET, weights are information that needs to be adjusted and updated at any time, so the part that deserves detailed explanation also includes how to adaptively modify transistor parameters (or weights). In particular, neural networks include back propagation, and the core of back propagation is the update and iteration of weights. Obviously, the local calculation of flash memory is different from the weight iteration of traditional processors.

[0133] See also Figure 4 , the threshold voltage of the transistor is V TH , if the threshold voltage is changed, then it is equivalent to K(V GS -V TH ) is changed, which is equivalent to changing K(V GS -V TH ) is proportional to the weight value, so changing the threshold voltage V THIt is an optional method. The writing and erasing of flash memory data is performed by manipulating the charge inside the floating gate related to the control gate, such as charge release and tunneling. For example, in the writing method, NOR Flash uses hot electron injection. By increasing the voltage of the control gate during writing, such as injecting charge from the source to the floating gate, the change in the charge amount of the floating gate can change K (V GS -V TH ). For example, in the erasing method, NOR Flash uses the tunnel effect to remove the charge in the floating gate, for example, the voltage applied to the control gate is a negative voltage.

[0134] See also Figure 4 Taking the transistors in the Mth row (the gate is coupled to the word line GM) as an example, in the erase operation of programming PG0, the transistors determined by the bit line BN (with a weight of W) can be cleared. MN ) floating gate charge, so its threshold voltage is reduced and the weight W MN The erase of programming PG0 is typically performed by applying a negative voltage to the word line GM to cause the floating gate charge of the transistor to generate a quantum tunnel effect and enter the substrate where the transistor is located. According to the requirements of the weight value modification mentioned above, in contrast, in the write action of programming PG1, for example, a transistor determined by the bit line BN (with a weight of W) can be injected. MN ) floating gate charge, in this case, so the threshold voltage of the transistor is increased and the weight W MN Furthermore, in the write operation of programming PG2, the transistor (weight W) determined by the bit line BN is continuously injected. MN ) floating gate charge, programming PG2 is a fine-tuning compared to programming PG1, so the threshold voltage of the transistor continues to increase and the weight W MN The voltage of charge injection programming PG1 is much higher than that of fine-tuning programming PG1. The small voltage scale of programming PG2 is to avoid over-adjustment of weight. In fact, charge injection programming can adopt more injection times than those in the figure, so that the weight W MN Not only can the multi-value requirement of the weight matrix Ma_wei be met, but also the high-precision requirement of the weight value can be met. The execution of multiple cycles of the erase programming action and the charge injection programming action as shown in the figure represents the iteration of the weight.

[0135] See also Figure 4In an optional embodiment, the method for performing in-memory calculations includes: using a storage transistor array as a carrier of a weight matrix of a neural network NET in a flash memory, setting the input data of the neural network to be transmitted to a series of bit lines B1-BN of the storage transistor array, and also setting the output data of the neural network NET to be captured from a series of source lines S1-SM of the storage transistor array. The weight of any transistor in the storage transistor array is adjusted by its threshold voltage, thereby dynamically configuring the weight matrix of the neural network. For example, a transistor T determined by the bit line B1 and the source line S1 11 :Transistor T 11 The weight of the transistor T is adjusted by its threshold voltage. 21 :Transistor T 21 The weight of the transistor T is adjusted by its threshold voltage. 31 :Transistor T 31 The weight of the transistor T is adjusted by its threshold voltage. The bit line B1 and the source line SM determine M1 :Transistor T M1 The weight of any transistor is adjusted by its threshold voltage. Therefore, the weight of any transistor is adjusted by its threshold voltage, thereby dynamically configuring the weight matrix of the neural network. N and M are positive integers. For example, the transistor T determined by the bit line BN and the source line SM MN :Transistor T MN The weight is adjusted by its threshold voltage, the charge on the floating gate, etc.

[0136] See also Figure 4 , the threshold voltage of the bias transistor is V THBM , if the threshold voltage is changed, then it is equivalent to K(V GSBM -V THBM ) is changed, which is equivalent to changing K(V GSBM -V THBM ) and changes the threshold voltage V THBM is an optional way to change the bias value Bias1.

[0137] See also Figure 4, and the relationship between the bias data and the bias bit line B_Bias: the bias data is converted into a voltage value VB by DAC digital-to-analog conversion, and the voltage value VB is connected and input to the bias bit line B_Bias. If the bias data is changed, it is equivalent to changing the voltage VB supply of the bias bit line B_Bias, which is equivalent to changing the bias value associated with the voltage value VB. Changing the bias data such as VB is an optional way to change the bias value Bias1.

[0138] See also Figure 4 In an optional embodiment, the method of adjusting the weight of any transistor in the storage transistor array, such as region0, includes changing its floating gate injection charge, and adjusting the weight size of any transistor at the location of the storage transistor array by changing the floating gate injection charge of the transistor.

[0139] See also Figure 3 In an optional embodiment, when setting bias values ​​such as Bias1 or Bias2 for network levels such as Lay1 or Lay2 of the network NET, a method for adjusting the bias value of a single-column storage transistor such as any bias transistor in region1 at least includes changing the charge injected into its floating gate; by changing the floating gate charge of the bias transistor, the bias value corresponding to the position of the single-column storage transistor such as any bias transistor in region1 is adjusted.

[0140] See also Figure 3 In an optional embodiment, when setting bias values ​​such as Bias1 or Bias2 for network levels such as Lay1 or Lay2 of the network NET, a method for adjusting the bias value of a single-column storage transistor such as any bias transistor in region1 at least includes changing bias data such as VB transmitted to the single-column storage transistor such as region1; therefore, the bias value such as Bias1 or Bias2 corresponding to the position of any bias transistor in the single-column storage transistor such as region1 is adjusted by changing the bias data.

[0141] See also Figure 3 In an optional embodiment, the original input data of the neural network NET is converted into an input quantity in the form of a voltage value, and is transmitted to a series of bit lines of the storage transistor array based on the input quantity sorted into a vector. The original input data includes data types such as pixel values ​​or grayscale values ​​of an image or video, and the original input data is converted into input quantities V1, V2, V3...VN in the form of voltage values ​​as shown in the figure. The voltage value V1 is input to the bit line B1, the voltage value V2 is similarly input to the bit line B2, the voltage value V3 is input to the bit line B3, and the voltage value VN is input to the bit line BN.

[0142] See also Figure 3The input is represented by a vector Ma_in=[B1=V1, B2=V2...BN=VN]. The input quantity [V1, V2...VN] is sent to a series of bit lines B1-BN of the array (transistor arrays) based on the input quantity [V1, V2...VN] sorted into a vector.

[0143] See also Figure 3 In an optional embodiment, the output data of the neural network NET is represented by the output current of the storage transistor array, and the output current of a series of source lines of the storage transistor array is regarded as the output quantity of the storage transistor array sorted into a vector. For example, the output currents of the series of source lines S1-SM of the storage transistor array are respectively recorded as IS1, IS2, ... ISM. The output current IS1 of the source line S1 can be converted into a digital quantity through an ADC analog-to-digital conversion, and the output current ISM of the similar source line SM can be converted into a digital quantity through an ADC analog-to-digital conversion. The output data of the network NET is represented by the output currents IS1, IS2, ... ISM of the storage transistor array.

[0144] See also Figure 3 In an optional embodiment, the output current of the series source lines S1-SM of the storage transistor array is regarded as the output quantity [IS1, IS2, ... ISM] of the storage transistor array arranged into a vector Ma_out. The output of the neural network can also be considered to be represented by the vector Ma_out = [S1 = IS1, S2 = IS2, ... SM = ISM].

[0145] See also Figure 3 In an alternative embodiment, the regulating transistor (T MN ) weights include changing the floating gate injection charge (such as changing T MN The floating gate charge of the transistor is changed to adjust the weight of any transistor at the position (such as the position determined by BN / SM) in the memory transistor array. For example, the weight of T MN The weight W MN The same method can also be used to adjust the bias value of the bias transistor.

[0146] See also Figure 3 In an optional embodiment, during the back propagation phase of the neural network NET, the weight matrix of the neural network is dynamically configured by resetting the weights at various locations in the storage transistor array. The various locations in the array mentioned here include each location where the bit lines B1-BN and the source lines S1-SM intersect each other. In fact, the various locations mentioned also represent the row and column indexes of each element in the weight matrix. For example, in the weight matrix W MNThe row and column index of this element is determined by or corresponds to the position of the bit line BN / source line SM. In the back propagation algorithm, the neural network needs to repeatedly iterate the size value of each element in the weight matrix until it meets the requirements.

[0147] See also Figure 3 In an optional embodiment, the input data of the neural network is transmitted to a series of bit lines of the storage transistor array and the output data of the neural network is captured from a series of source lines of the storage transistor array: the source of each row of storage transistors in the transistor array is connected and regarded as a source line output end of one output data of the neural network, and the drain of each column of storage transistors in the transistor array is connected and regarded as a bit line input end of one input data of the neural network. In addition, the gate of each row of storage transistors in the storage transistor array is connected and coupled to a word line.

[0148] See also Figure 3 So far, the present application has preferably mapped the memory to the neural network NET and has preferably configured the neural network NET with a dynamically adjustable weight matrix and bias value, and has achieved the established goal of the present application. The weight and bias values ​​can be set and reasonably configured as needed. Achieve the purpose stated in this article.

[0149] See also Figure 2 In an optional embodiment, a digital-to-analog converter DAC is configured at each of the bit lines B1-BN of the storage transistor array, and the digital-to-analog converter DAC is used to convert the input data of the neural network NET into a voltage value that matches the input signal pattern of the bit line (for example, the bit line requires a voltage signal as an input quantity).

[0150] See also Figure 2 In an optional embodiment, an analog-to-digital converter ADC is configured at each of the source lines S1-SM of the storage transistor array. The analog-to-digital converter ADC is used to convert the output signal in the output current format at the source line into output data that is compatible with the digital output quantity of the neural network NET. For example, the analog-to-digital converter configured at the source line SM is used to convert the output signal in the output current ISM format at the source line SM into output data that is compatible with the digital output quantity of the neural network. The digital quantity (digital) of current is different from the analog quantity (analog). The analog-to-digital converter configured at the source line S1 is used to convert the output signal in the output current IS1 format at the source line S1 into output data that is compatible with the digital output quantity of the neural network. The same is true for the others S2 to SM-1.

[0151] See also Figure 3In this application, the input data or output data of the neural network mapped to the storage transistor array can be the data of a certain layer (input layer / hidden layer / output layer, etc.) of the neural network. In other words, the storage transistor array is allowed to be only a local sub-network structure of the neural network. Alternatively, the neural network can use multiple storage transistor arrays as shown in the figure to perform a series-parallel cascade combination of the front and rear stages, and multiple storage transistor arrays are combined into a local sub-network structure of the neural network or into the entire network structure.

[0152] See also Figure 5 , storage and computing are integrated to organically integrate storage and computing, and based on its huge potential for improving energy efficiency, it is expected to become an advanced computing architecture solution in the computing era. However, there are doubts: unreasonable configuration of bias values ​​usually leads to the inability of neural network-based perceptrons to generate separation planes. This is an urgent problem to be solved in neural network classification processing, and how to configure bias values ​​in conjunction with neural networks is a major problem for memory.

[0153] See also Figure 5 , taking the operation from input layer Lay1 to hidden layer Lay2 as an example, it is ideal for the same network layer in the neural network to use the same bias value: for example Figure 3 It is ideal to use the same bias value Bias1 for the input layer Lay1 in the network layer. For example Figure 3 It is ideal to use the same bias value Bias2 for the hidden layer Lay2 in the network layer. And so on.

[0154] See also Figure 5 , because neural networks are based on transistors inside memory, Figure 4 In addition to the differences in wafer fab manufacturing processes, the biggest difference in bias transistors in different rows of a single-column storage transistor, such as region 1, that generates an intercept term, actually comes from the charge modulation problem of other weight transistors in the same row. This ultimately leads to different bias values ​​for bias transistors in different rows of a single-column storage transistor.

[0155] See also Figure 5 Assuming that the bias value of the first bias transistor in the first row of a single column storage transistor such as region1 is Bias1_1, the source line S1 includes the bias value Bias1_1.

[0156] See also Figure 5 Assuming that the bias value of the second bias transistor in the second row of a single column storage transistor such as region1 is Bias1_2, the source line S2 includes the bias value Bias1_2.

[0157] See also Figure 5 Assuming that the bias value of a single column storage transistor such as region1 located at the position of the Mth bias transistor in the Mth row is Bias1_B, the source line SB includes the bias value Bias1_M.

[0158] See also Figure 5 As mentioned above, for example Figure 3 It is ideal to use the same bias value Bias1 for the input layer Lay1 in the network layer, but the bias values ​​Bias1_1, Bias1_2...Bias1_M of the bias transistors in the first row to the Mth row of the single-column storage transistors in region1 are not the same. This is a problem that needs to be solved, but it is also a difficult problem that is extremely difficult to control, because the source and generation mechanism of the difference between the bias values ​​Bias1_1 to Bias1_M are various, such as the back propagation iterative weight matrix of the neural network NET. The first row of transistors in the storage transistor array is an interpretation example: the first row of weights W in the weight matrix 11 -W 1N Each of the weights will be iterated, and the floating gate of the transistor whose weight is iterated will be programmed and the weight W 11 -W 1N When any of the above is iterated, a programming voltage is applied to the word line G1 where the first row of transistors is located. Single-column storage transistors, such as the first bias transistor in the first row of region1, are synchronously fine-programmed by the shared word line G1. 11 -W 1N When N iterations occur, the first bias transistor is slightly programmed N times by the common word line G1 and generates an undesired floating gate charge which is not noticeable.

[0159] See also Figure 5 , as mentioned above, the iteration weight matrix is ​​for each element. The second row of transistors in the storage transistor array is an interpretation example: the second row of weights W in the weight matrix 21 -W 2N Each of the weights will be iterated, and the floating gate of the transistor whose weight is iterated will be programmed and the weight W 21 -W 2N When any of the two is iterated, a programming voltage is applied to the word line G2 where the second row of transistors is located, and a single column of storage transistors, such as the second bias transistor in the second row of region1, is synchronously finely programmed by the shared word line G2. 21 -W 2N When N iterations occur, the second bias transistor is slightly programmed N times by the common word line G2 and generates an undesired floating gate charge which is not noticeable.

[0160] See also Figure 5, the iteration weight matrix is ​​for each element. The Mth row of transistors in the storage transistor array is interpreted as: the Mth row weight W in the weight matrix M1 -W MN Each of the weights will be iterated, and the floating gate of the transistor whose weight is iterated will be programmed and the weight W M1 -W MN When any one of the above is iterated, a programming voltage will be applied to the word line GM where the Mth row transistor is located. A single column of storage transistors, such as the Mth bias transistor in the Mth row in region1, is synchronously fine-programmed by the shared word line GM. M1 -W MN When N iterations occur, the Mth bias transistor is slightly programmed N times by the common word line GM and generates unnoticeable undesired floating gate charge. If the weight changes very little between the two iterations, and the voltage applied to the word line GM is also very small or not applied, it is obvious that this iteration will hardly have a charge programming effect on the Mth bias transistor in the Mth row. The same is true for other bias transistors.

[0161] See also Figure 5 As mentioned above, for example Figure 3 It is ideal to use the same bias value Bias2 for the hidden layer Lay2 in the network layer, but the bias values ​​Bias2_1, Bias2_2…Bias2_M of the bias transistors in the first to Mth rows of the single-column storage transistors corresponding to Lay2 are not the same. This is a problem that needs to be solved.

[0162] See also Figure 5 , the floating gates of the bias transistors in the first to Mth rows of a single column of storage transistors, such as region1, are programmed in an unexpectedly subtle manner and soon produce an imbalance between the bias values ​​Bias1_1, Bias1_2, ..., Bias1_M.

[0163] See also Figure 6 , the single-column storage transistors such as the bias transistors in the first row to the Mth row in region1 with large charge injection will soon produce a threshold saturation trend, which is a further concern. The gate-source voltage of the bias transistor with threshold saturation minus the threshold voltage is K (V GS -V TH ) term usually approaches zero or is close to zero and can only maintain a relatively small bias value or intercept term, while the gate-source voltage of the non-threshold saturated bias transistor minus the threshold voltage basically does not approach zero or is close to zero and maintains a relatively large bias value or intercept term.

[0164] See also Figure 6, the neural network NET constructed with relatively small bias values ​​or intercept terms relative to non-threshold saturated bias transistors and threshold saturated bias transistors is one of the cases where the bias value is not reasonably configured. Take the illustrated classifier NET_Cla as an example of such a neural network. In the Cartesian coordinate system shown in the figure, the classification function of the classifier NET_Cla, such as a linear function, is difficult to deviate from the origin of coordinates [0,0] because it has an extremely small bias value or intercept term, and the functions 110a, 110b, 110c, 110d, etc. represented by separation planes or separation lines in the figure are examples. They all pass through the coordinates [0,0] under the conditions of relatively small bias values ​​or intercept terms.

[0165] See also Figure 6 , if the classifier NET_Cla attempts to separate the coordinates [0,0], [1,0], [1,1], [0,1], the coordinates depicted as black stars and the coordinates depicted as white stars are the classified objects (more classified objects can also be drawn). Functions 110a, 110b, 110c, 110d, etc. represented by the separation plane or separation line cannot escape the coordinate [0,0], so trying to successfully separate the classified objects is almost an impossible task. This is a typical example of the unreasonable configuration of the bias value causing the neural network-based perceptron to fail to generate a separation plane.

[0166] See also Figure 7 , reasonably configure the bias value such as: adjusting the threshold voltages of the single-column storage transistors (in region1) to a similar mode, including, after the weight matrix of the neural network NET is configured, resetting the floating gate charges of the single-column storage transistors (such as region1) synchronously. Configuring the weight matrix first means that it is necessary to select word lines such as G1-GM and select bit lines B1-BN to inject charges into the floating gates of each transistor in the storage transistor array (such as in region0). The subsequent synchronous resetting of the floating gate charge of the single-column storage transistor (such as in region1) requires selecting word lines such as G1-GM and bit lines B_Bias to re-inject charges into the floating gates of each transistor in the single-column storage transistor (such as in region1). In an optional embodiment, B_Bias can be released when bit lines B1-BN are selected and B1-BN can be released when the corresponding bit lines B_Bias are selected.

[0167] See also Figure 7In an optional embodiment, the method of resetting the floating gate charge of each single-column storage transistor (such as region1) includes: first programming the low data bit of the bias transistor of each row (first row to Mth row) of the single-column storage transistor and then programming the high data bit of the bias transistor of each row (first row to Mth row) of the single-column storage transistor. First program the low data bit and then program the high data bit, for example, programming from code element 11 to 10 and then programming to 00. First program the low data bit and then program the high data bit, such as programming from code element 10 to 01 and then programming to 00. The code element can also be three or more bits. Resetting the floating gate charge of the single-column storage transistor (such as in region1) can select word lines such as G1-GM and bit lines B_Bias to inject charges into the floating gates of each transistor of the single-column storage transistor (such as in region1). The purpose of programming the floating gate charge of each single-row storage transistor with a low data bit first is to make the floating gate charge of each bias transistor in the first row to the Mth row fuzzy and solve the barrel effect caused by the imbalance of their floating gate charge. It is necessary to solve the problem that the floating gates of different rows in the first row to the Mth row of single-row storage transistors are modulated by the charge of each weight transistor in the same row. For example, the floating gate charge of the bias transistor in the Mth row is modulated by the transistors (W M1 -W MN ), each of the transistors in this row of weight carriers will modulate the floating gate charge of the Mth row bias transistor once during the weight adjustment phase and thereby modulate the threshold of the Mth row bias transistor to an unknown state. M1 The carrier transistor will modulate the floating gate charge of the Mth row bias transistor once during the weight adjustment phase. M2 The carrier transistor will modulate the floating gate charge of the Mth row bias transistor once during the weight adjustment phase. M3 The floating gate charge of the bias transistor in the first row is modulated by the transistors (W) of each weight carrier in the first row. 11 -W 1N ), each of the transistors in this row of weight carriers will also modulate the floating gate charge of the first row bias transistor once during the weight adjustment phase, thereby modulating the threshold of the first row bias transistor to an unknown state. Similarly, the floating gate charge of the second row bias transistor is affected by the transistors (W) of each weight carrier in the second row. 21 -W 2N) is affected by the charge modulation of the second row of bias transistors. Each of the transistors in this row of weight carriers will also modulate the floating gate charge of the second row of bias transistors once during the weight adjustment stage, thereby modulating the threshold of the second row of bias transistors to an unknown state. The floating gate charges of the bias transistors in the first to Mth rows have a large difference and imbalance, resulting in the barrel effect. The purpose of programming low data bits is to make the imbalance of the floating gate charges of each bias transistor and the uncontrolled situation of the unknown state roughly controllable. The floating gate charges of each bias transistor are blurred and close when programming low data bits. Similar to the transition from a chaotic state to a critical state. The purpose of programming the floating gate charges of each single-column storage transistor with high data bits is to make the floating gate charges of each bias transistor in the first to Mth rows aligned or approximate, so that the floating gate charges of each bias transistor in the first to Mth rows transition or align from the charge amount corresponding to the low data bit to the charge amount corresponding to the high data bit. Similar to compressing the critical state range. The low data bit programming can be performed on each bias transistor synchronously and the high data bit programming can be performed on each bias transistor synchronously.

[0168] See also Figure 7 In an optional embodiment, resetting the programming low data bit of the floating gate charge of each single-column storage transistor (such as region1) allows the unknown chaotic state of the transistor's respective bias values ​​Bias1_1, Bias1_2...Bias1_M to reach the critical state of their bias values ​​Bias1_md1, Bias1_md2...Bias1_mdM. In the critical state, the floating gate charges of each single-column storage transistor are approximately close and can be approximately within a critical range. The problem of floating gates of different rows of single-column storage transistors being modulated by the charges of each weight carrier transistor in the same row is solved. The programming high data bit of the floating gate charge of each single-column transistor allows the critical range of each bias value Bias1_md1, Bias1_md2...Bias1_mdM to reach the final state of the transistor's bias values ​​Bias1_ba, Bias1_ba...Bias1_ba. The bias transistors in different rows of a single column of transistors can have the same low data bit in the low data bit programming stage, and the bias transistors in different rows of a single column of transistors can have the same high data bit in the high data bit programming stage.

[0169] See also Figure 7 In an optional embodiment, for example Figure 3It is ideal to use the same bias value Bias1 for the input layer Lay1 in the neural network, but the bias values ​​Bias1_1, Bias1_2…Bias1_M of the bias transistors in the first row to the Mth row of the single-column storage transistors, such as region1, are not exactly the same. As mentioned above, the bias values ​​of each bias transistor can be transitioned to the final alignment state of Bias1_ba, Bias1_ba…Bias1_ba. By adjusting the threshold voltages of the single-column storage transistors to the same state, it is avoided that the same network layer in the neural network NET, such as the input layer Lay1, uses different bias values. The same bias value Bias1_ba: for example, refers to making the errors between the bias values ​​Bias1_1, Bias1_2…Bias1_M as small as possible (such as the difference between them is within the allowable error range) or Bias1_1 to Bias1_M are completely the same, etc.

[0170] See also Figure 7 In an optional embodiment, for example Figure 3 It is ideal to use the same bias value Bias2 for the hidden layer Lay2 in the network layer, but the bias values ​​Bias2_1, Bias2_2...Bias2_M of the bias transistors in the first row to the Mth row in the single-column storage transistor corresponding to Lay2 are not exactly the same. As mentioned above, the bias values ​​of each bias transistor can be transitioned to the final alignment state of Bias2_ba, Bias2_ba...Bias2_ba. By adjusting the threshold voltages of the single-column storage transistors to the same state, it is avoided that the same network layer in the neural network NET, such as the hidden layer Lay2, uses different bias values. The same bias value Bias2_ba: for example, refers to making the errors between the bias values ​​Bias2_1, Bias2_2...Bias2_M as small as possible (such as the difference between them is within the allowable error range) or Bias2_1 to Bias2_M are completely the same, etc.

[0171] See also Figure 8 , based on the situation that the bias values ​​or intercept terms of the non-threshold saturated bias transistor and the threshold saturated bias transistor are nearly aligned and then participate in the construction of a neural network NET according to this condition, such a neural network is taken as an example of the illustrated classifier NET_Cla. In the Cartesian coordinate system shown, the classification function of the classifier NET_Cla, such as a linear function, is allowed to deviate from the origin of the coordinate [0,0] because it has a corrected bias value or intercept term, and the figure takes a separation surface 110d that replaces the previous functions 110a, 110b, 110c, 110d, etc. as an example, and its corrected bias value makes it no longer necessary to pass through the coordinate [0,0].

[0172] See also Figure 8 , the classifier NET_Cla attempts to separate the coordinates [0,0], [1,0], [1,1], [0,1], and the coordinates depicted as black stars and the coordinates depicted as white stars are the classified objects (more classified objects can also be drawn). Functions 110a, 110b, 110c, 110d, etc. represented by separation planes or separation lines cannot escape from the coordinate [0,0], so trying to successfully separate the classified objects is almost an impossible task, but function 110d, which has escaped from the coordinate [0,0], can successfully separate the classified objects, which is an ideal configuration of the bias value and guides the neural network-based perceptron or classifier to adaptively generate a separation plane. Below function 110d are the classified white stars and above are the classified black stars.

[0173] See also Figure 8 In an optional embodiment, adjusting the threshold voltages of the single-column storage transistors (such as in region1) to a mode that tends to be the same includes: after the weight matrix of the neural network is configured, resetting the floating gate charges of the single-column storage transistors synchronously. The synchronous resetting of the floating gate charges of the single-column storage transistors includes: first programming the low data bits of each bias transistor and then programming the high data bits of each bias transistor. The programming of the low data bits is used to suppress the floating gates of the bias transistors located in any row of the single-column storage transistors from being affected by the charge modulation of the transistors of each weight carrier in the same row. The programming of the high data bits is used to make the floating gate charges of each bias transistor transition from the charge amount corresponding to the low data bits to the charge amount corresponding to the high data bits, so that the floating gate charges of the bias transistors located in different rows of the single-column storage transistors tend to be equal (such as their charges are very close, close or even the same). The training of the neural network will induce the floating gate charges of the single-column storage transistors (the corresponding biases are actually Bias1_1 to Bias1_M) to vary greatly and there is no regularity to follow. One of the typical reasons is that the iteration of each element in the weight matrix Ma_wei is related to the training method of the neural network, and the weight carrier transistor corresponding to each element will affect the floating gate charge of the bias transistor in the same row. For example, if two trainings use different training sets, the bias difference between the bias transistors in the first training will be different from the bias difference in the second training. The specific solutions described in the previous text of this application are sufficient to deal with these difficult problems and overcome the technical problems mentioned in the background technology.

[0174] The above description and drawings provide typical embodiments of specific structures of specific embodiments. The above invention provides existing preferred embodiments, but these contents are not intended to be limiting. For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the attached claims should be regarded as covering all changes and modifications of the true intent and scope of the present invention. Any and all equivalent scopes and contents within the scope of the claims should be considered to still be within the intent and scope of the present invention.

Claims

1. A method suitable for storage and computing integration, characterized in that: include: In a flash memory, a storage transistor array is used as a carrier of a weight matrix of a neural network and a single-column storage transistor is used as a carrier of a bias value of the neural network. The weight of any transistor in the storage transistor array is adjusted using its threshold voltage, thereby configuring a weight matrix for the neural network. Setting the input data of the neural network to be transmitted to a series of bit lines of the storage transistor array and setting the bias data of the neural network to be transmitted to the bias bit line where the single column storage transistor is located; The output data of the neural network is set to be captured from a series of source lines of a memory transistor array, wherein each row of the memory transistor array is provided with a bias transistor sharing the same source line with the row; By adjusting the threshold voltages of the storage transistors in the single column to be close to each other, it is avoided that a same network layer in the neural network uses different bias values.

2. The method according to claim 1, characterized in that: The raw input data of the neural network is converted into an input quantity in the form of a voltage value, so as to be transmitted to a series of bit lines of the memory transistor array based on the input quantity sorted into a vector; and The original bias data of the neural network is converted into an input quantity in the form of a voltage value and transmitted to the bias bit line.

3. The method according to claim 1, characterized in that: The output data of the neural network is represented by the output current of the storage transistor array, and the output current of a series of source lines of the storage transistor array is regarded as the output quantity of the storage transistor array sorted into a vector; as well as The current value of the bias transistor configured on any source line is merged into the output current of any source line, thereby serving as a bias value in the output quantity of any source line.

4. The method according to claim 1, characterized in that: The means of adjusting the weight of any transistor in the memory transistor array includes changing the charge injected into its floating gate; The weight of any transistor in the memory transistor array is adjusted by changing the charge injected into the floating gate of the transistor.

5. The method according to claim 1, characterized in that: When setting bias values ​​for the network level of the neural network, the manner of adjusting the bias value of any bias transistor in the single column storage transistor at least includes changing the charge injected into its floating gate; The magnitude of a bias value corresponding to the position of any bias transistor in the single column of storage transistors is adjusted by changing the floating gate charge of the bias transistor.

6. The method according to claim 1, characterized in that: When setting a bias value for a network level of a neural network, the manner of adjusting the bias value of any bias transistor in the single-column storage transistor at least includes changing bias data transmitted to the single-column storage transistor; By changing the bias data, a bias value corresponding to the position of any bias transistor in the single column of storage transistors is adjusted.

7. The method according to claim 1, characterized in that: Adjusting the threshold voltages of the respective single-column storage transistors to be close to each other includes: after the weight matrix of the neural network is configured, synchronously resetting the floating gate charges of the respective single-column storage transistors.

8. A storage device suitable for storage and computing integration, characterized in that: include: Flash memory having an array of memory transistors and a single column of memory transistors presented in columns; The storage transistor array is regarded as the carrier of the weight matrix of the neural network. The weight of any transistor in the storage transistor array is adjusted by using its threshold voltage, thereby configuring the weight matrix for the neural network. A single row of memory transistors is considered as a carrier of bias values ​​for the neural network; Setting the input data of the neural network to be transmitted to a series of bit lines of the storage transistor array and setting the bias data of the neural network to be transmitted to the bias bit line where the single column storage transistor is located; The output data of the neural network is set to be captured from a series of source lines of a memory transistor array, wherein each row of the memory transistor array is provided with a bias transistor sharing the same source line with the row; For the single-column storage transistors, the difference between the bias values ​​of the single-column storage transistors is reduced by adjusting the threshold voltages of the single-column storage transistors to be close to each other.

9. The storage device suitable for storage and computing integration according to claim 8, characterized in that: The original input data of the neural network is converted into an input quantity in the form of a voltage value, and is transmitted to a series of bit lines of the storage transistor array based on the input quantity sorted into a vector, wherein the original bias data of the neural network is converted into an input quantity in the form of a voltage value and is transmitted to the bias bit line; and The output data of the neural network is represented by the output current of the storage transistor array. The output current of a series of source lines of the storage transistor array is regarded as the output quantity of the storage transistor array sorted into a vector, wherein the current value of the bias transistor configured on any source line is merged into the output current of any source line, thereby serving as a bias value in the output quantity of any source line.

10. A storage system suitable for storage and computing integration, characterized in that: include: Flash memory having an array of memory transistors and a single column of memory transistors presented in columns; A neural network, which is attached to a flash memory, uses a storage transistor array as a carrier of a weight matrix of the neural network and uses a single-row storage transistor as a carrier of a bias value of the neural network, and the size of the weight of any transistor in the storage transistor array is adjusted using its threshold voltage, thereby configuring the weight matrix for the neural network; Setting the input data of the neural network to be transmitted to a series of bit lines of the storage transistor array and setting the bias data of the neural network to be transmitted to the bias bit line where the single column storage transistor is located; The output data of the neural network is set to be captured from a series of source lines of a memory transistor array, wherein each row of the memory transistor array is provided with a bias transistor sharing the same source line with the row; By adjusting the threshold voltages of the storage transistors in the single column to be close to each other, it is avoided that a same network layer in the neural network uses different bias values.

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