Memory controller, operating method thereof, and memory system

Abstract

The invention relates to a memory controller, an operating method thereof and a memory system. A memory controller includes: a scheduler configured to generate an active command and an active address, and determine whether to issue the active command and the active address according to an output control signal; a hammer detector configured to generate an output control signal by checking a hammer likelihood based on the activity command and the activity address; and a memory interface configured to provide the activity command and the activity address issued by the scheduler to a memory device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0081037, filed on June 23, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present invention relate to semiconductor design technology, and more particularly, to a memory system including a memory controller and a memory device. Background Art

[0004] As the integration degree of memory devices increases, the intervals between a plurality of word lines included in the memory devices are decreasing. As the intervals between the plurality of word lines decrease, the coupling effect between adjacent word lines increases.

[0005] Whenever data is input or output to a memory cell, the word line switches between an active state and an inactive state. Due to the increased coupling effect between adjacent word lines, data stored in a memory cell coupled to an adjacent word line that is disposed adjacent to a target word line having a large number of activations or high frequency activations may be damaged. Such a phenomenon is known as a row hammer attack, and various methods have been studied to mitigate the effects of a row hammer attack. In order to select a target word line to be refreshed during a target refresh operation, a memory device needs to count all row addresses input together with an active command. The memory device has a counting circuit to count the number of inputs of the row address, and as the technology scale develops, the narrower the line width of the memory device, the larger the portion occupied by the counting circuit. Summary of the invention

[0006] An embodiment of the present invention is directed to a memory system including a memory controller capable of issuing an active command to a memory device by checking an active command repeatedly / frequently input to a specific word line.

[0007] According to one embodiment of the present invention, a memory controller includes: a scheduler configured to generate an active command and an active address, and determine whether to issue the active command and the active address based on an output control signal; a row hammer detector configured to generate an output control signal by checking a row hammer possibility based on the active command and the active address; and a memory interface configured to provide the active command and the active address issued by the scheduler to a memory device.

[0008] According to one embodiment of the present invention, a memory system includes: a memory device including a plurality of rows respectively coupled to memory cells; and a memory controller configured to generate an access command and an access address for each row, check a row hammer possibility based on the access command and the access address to generate an output control signal, and determine whether to issue the access command and the access address to the memory device according to the output control signal.

[0009] According to one embodiment of the present invention, a method for operating a memory controller includes: generating an active command and an active address; comparing the active address with multiple candidate addresses stored in an address queue; and based on a determination that the active address is different from all candidate addresses in the multiple candidate addresses, issuing an active command and an active address to a memory device, while storing the active address as one of the multiple candidate addresses in the address queue.

[0010] Furthermore, according to an embodiment of the present invention, a memory system may implement row hammer mitigation in such a manner that a memory controller may detect an active command repeatedly input for a specific word line for each unit segment and delay issuance of the detected active command until the next unit segment. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1A and Figure 1B is a graph illustrating the number of inputs of active addresses.

[0012] Figure 2 is a block diagram illustrating a memory system according to one embodiment of the present invention.

[0013] Figure 3 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 2 A detailed block diagram of the memory controller is shown in FIG.

[0014] Figure 4 It is used to describe an embodiment according to the present invention. Figure 3 A flow chart of the operation of a memory controller.

[0015] Figure 5 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 3 The detailed configuration diagram of the hammer detector is shown in FIG.

[0016] Figure 6 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 5 Detailed circuit diagram of the address queue.

[0017] Figure 7 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 5 Detailed configuration diagram of the address comparison circuit.

[0018] Figure 8 is a timing diagram for describing the operation of a hammer detector according to one embodiment of the present invention.

[0019] Fig. 9 is a table showing the number of row hammer counts according to the depth of the address queue according to one embodiment of the present invention. DETAILED DESCRIPTION

[0020] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention can be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. Throughout the present disclosure, throughout the various figures and embodiments of the present invention, similar reference numerals refer to similar parts.

[0021] It will be understood that when an element is referred to as being "coupled" or "connected" to another element, this may mean that the two elements are directly coupled, or that the two elements are electrically connected to each other with another circuit interposed between them. It will be further understood that when used in this specification, the terms "comprises," "comprising," "having," and the like specify the presence of recited features, quantities, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof. In the present disclosure, the singular is intended to include the plural, unless the context clearly indicates otherwise.

[0022] Figure 1A and Figure 1B is a graph illustrating the number of inputs of active addresses.

[0023] refer to Figure 1A , illustrating that the addresses input together with the active command during one refresh cycle (hereinafter referred to as "active addresses") are evenly distributed. That is, Figure 1A The following case is shown: the risk of a row hammer attack is low because the number of activations per address is evenly distributed. In this case, since the number of activations per address (hereinafter referred to as "active attackers") is small within one refresh cycle, the memory device can respond to the risk of a row hammer attack by autonomously performing a targeted refresh operation.

[0024] refer to Figure 1B , illustrating that the active addresses during a refresh cycle are concentrated only on some specific addresses. That is, Figure 1BThe following situation is shown: due to a special event such as hacking, the number of active attackers per address increases abnormally, resulting in a high risk of row hammer attack. In this case, since the target refresh operation performed alone in the memory device makes it difficult to respond to the row hammer attack, additional help from the memory controller is required.

[0025] A scheme for implementing row hammer mitigation of a memory system is disclosed below. According to one embodiment of the present invention, a memory controller can detect a situation where the number of active attacks is concentrated at a specific active address, and schedule the issuance of active commands for the specific active address to be delayed.

[0026] Figure 2 is a block diagram illustrating a memory system 10 in accordance with one embodiment of the present invention.

[0027] refer to Figure 2 , the memory system 10 may include a memory controller 100 and a semiconductor memory device 200 .

[0028] The memory controller 100 may control the overall operation of the memory system 10, and control data communication between the host 20 and the semiconductor memory device 200. The memory controller 100 may generate a command / address signal C / A according to a request REQ from the host 20, and provide the generated command / address signal C / A to the semiconductor memory device 200. The memory controller 100 may provide data DQ corresponding to host data HDATA provided from the host 20 to the semiconductor memory device 200. The memory controller 100 may receive data DQ read from the semiconductor memory device 200, and provide the data DQ as host data HDATA to the host 20.

[0029] The host 20 may include a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), etc. The memory controller 100 may be included in the CPU, the GPU, the AP, etc., and in this case, the host 20 may mean a configuration other than the memory controller 100 among these configurations. For example, when the memory controller 100 is included in the CPU, the host 20 may represent the remaining components of the CPU other than the memory controller 100.

[0030] In detail, the memory controller 100 may include a host interface 110 , a scheduler 120 , a hammer detector 130 , a refresh manager 140 , a memory interface 150 , and a bus 170 .

[0031] The host interface 110 may be configured to communicate with the host 20 connected to the memory system 10. For example, the host interface 110 may receive a request REQ and host data HDATA from the host 20. The host interface 110 may provide the host data HDATA to the semiconductor memory device 200 through the memory interface 150, and provide the host data HDATA to the host 20 by receiving data DQ read from the semiconductor memory device 200 via the memory interface 150.

[0032] The scheduler 120 may receive a request REQ from the host 20 through the host interface 110. The scheduler 120 may generate an address and various commands such as an active command, a precharge command, a read command, a write command, etc. according to the request REQ. The scheduler 120 may determine the order of requests to be directed to the semiconductor memory device 200 among the requests REQ from the host 20, and generate commands and addresses to be provided to the semiconductor memory device 200 according to the order of predetermined operations. The scheduler 120 may change the order of receiving the request REQ from the host 20 and the order of operations to be indicated to the semiconductor memory device 200 to improve the performance of the semiconductor memory device 200. For example, the scheduler 120 may adjust the order so that even if the host 20 first requests a read operation of the semiconductor memory device 200 and later requests a write operation, the write operation is performed before the read operation.

[0033] In one embodiment, the scheduler 120 may determine whether to issue an active command and an active address provided with the active command according to the output control signal. When the output control signal is activated, the scheduler 120 may issue an active command and an active address to the memory interface 150. When the output control signal is deactivated, the scheduler 120 may interrupt (i.e., block or disable) the issuance of the active command and the active address. The scheduler 120 may transmit the active command and the active address to the memory interface 150 after delaying the issuance of the active command and the active address for a predetermined time.

[0034] The row hammer detector 130 may generate an output control signal by checking the possibility (i.e., probability or likelihood) of a row hammer attack (hereinafter, referred to as row hammer possibility) based on the active command and the active address. The row hammer detector 130 may store the active address as a candidate address for each preset unit section (i.e., unit time period), deactivate the output control signal when the currently input active address matches one of the candidate addresses, and activate the output control signal when the currently input active address is different from all the candidate addresses.

[0035] The refresh manager 140 may generate commands related to the refresh operation and provide the refresh related commands to the memory interface 150. The refresh related commands may include normal refresh commands and refresh management commands. The refresh manager 140 may generate a preset number of normal refresh commands at regular intervals during the refresh time defined in the specification. The refresh manager 140 may generate a refresh management command based on the active command provided from the scheduler 120. For example, the refresh manager 140 may generate a refresh management command whenever the number of inputs of the active command reaches a certain number.

[0036] In one embodiment, the refresh manager 140 may generate a row hammer address by collecting information about a word line (hereinafter referred to as a row) in the semiconductor memory device 200 that has been attacked by a row hammer based on an active address provided from the scheduler 120. The refresh manager 140 may collect information about rows attacked by a row hammer using a combination of various methods, such as counting the number of activations of each row of the semiconductor memory device 200 or randomly sampling rows activated in the semiconductor memory device 200. The refresh manager 140 may transmit a refresh-related command and a row hammer address to the memory interface 150. In one embodiment, the refresh manager 140 may transmit the refresh-related command and the row hammer address to the scheduler 120, and the scheduler 120 may schedule the refresh-related command and the row hammer address according to the operation timing of the semiconductor memory device 200.

[0037] The memory interface 150 may be configured to communicate with the semiconductor memory device 200. For example, the memory interface 150 may transmit a command / address signal C / A and data DQ to the semiconductor memory device 200, and receive the data DQ from the semiconductor memory device 200. The memory interface 150 may provide the command / address signal C / A to the semiconductor memory device 200 by receiving a command and address issued by the scheduler 120 and a refresh-related command and a row hammer address generated by the refresh manager 140. In addition, the memory interface 150 may receive host data HDATA from the host interface 110, and provide the data DQ to the semiconductor memory device 200.

[0038] The memory controller 100 may transfer data between the host interface 110, the scheduler 120, the row hammer detector 130, the refresh manager 140, and the memory interface 150 via the bus 170. In one embodiment, the host interface 110, the scheduler 120, the row hammer detector 130, the refresh manager 140, and the memory interface 150 may independently communicate with each other without passing through the bus 170. For example, the refresh manager 140 and the host interface 110 may communicate directly with each other without passing through the bus 170. The refresh manager 140 and the memory interface 150 may communicate directly with each other without passing through the bus 170. The host interface 110 and the memory interface 150 may also communicate directly with each other without passing through the bus 170.

[0039] The semiconductor memory device 200 may include a memory cell region in which a plurality of memory cells coupled to a plurality of word lines (hereinafter referred to as a plurality of rows) and a plurality of bit lines (hereinafter referred to as a plurality of columns) may be arranged in an array. The plurality of memory cells may include memory cells that may cause a row hammer phenomenon or memory cells that require a refresh operation to ensure data retention time. The semiconductor memory device 200 may perform an active operation, a precharge operation, a refresh operation, a write operation, and a read operation according to a command / address signal C / A and / or data DQ provided from the memory controller 100.

[0040] For example, the semiconductor memory device 200 may perform an active operation of activating a row corresponding to an active address among a plurality of rows according to an active command, and may perform a precharge operation of deactivating (or precharging) the active row according to a precharge command. For reference, in one embodiment, an active operation performed in a row unit by an active address may be referred to as an access operation, and an active command may be referred to as an access command. The active address may include a row address for selecting one of the plurality of rows.

[0041] The refresh operation may include: a normal refresh operation of sequentially refreshing a plurality of rows according to a normal refresh command, and a target refresh operation of refreshing one or more adjacent rows disposed adjacent to a target row having a large number of activations or high frequency activations according to a refresh management command. For reference, in order to indicate the target row, a row hammer address may be provided from the memory controller 100. In one embodiment, the semiconductor memory device 200 may collect information about rows that have been attacked by a row hammer by itself, and generate a row hammer address.

[0042] Hereinafter, a configuration related to an embodiment of the present invention among the configurations of the memory controller 100 will be described in detail with reference to the drawings.

[0043] Figure 3 is a diagram showing a first embodiment of the present invention. Figure 2A detailed block diagram of the memory controller 100 is shown in FIG. Figure 3 In order to focus on the characteristics of the embodiment, data-related configurations are omitted, and only command / address-related configurations are illustrated.

[0044] refer to Figure 3 The scheduler 120 may generate a command CMD and an address ADDR by receiving a request REQ via the host interface 110. The command CMD may include an active command ACT, a precharge command, a read command, a write command, etc. The address ADDR may include a bank address, a row address, and a column address.

[0045] For example, the scheduler 120 may generate an active command ACT and an active address according to the request REQ. The active address may include a row address RADD for selecting one of the rows of the semiconductor memory device 200. The scheduler 120 may provide the active command ACT and the active address RADD to the row hammer detector 130.

[0046] The scheduler 120 may issue a command CMD and an address ADDR other than an active command ACT and an active address RADD to the memory interface 150. On the other hand, in one embodiment, the scheduler 120 may determine whether to issue the active command ACT and the active address RADD according to the output control signal OUT_EN. When the output control signal OUT_EN is activated, the scheduler 120 may issue the active command ACT and the active address RADD, and provide the active command ACT and the active address RADD to the memory interface 150. When the output control signal OUT_EN is deactivated, the scheduler 120 may interrupt the issuance of the active command ACT and the active address RADD, and may store the active address RADD in the internal storage circuit 122. The scheduler 120 may reschedule the active command ACT and the active address RADD after a predetermined delay time, and provide the active command ACT and the active address RADD to the memory interface 150.

[0047] The row hammer detector 130 may generate an output control signal OUT_EN by checking the row hammer possibility based on the active command ACT and the active address RADD. The row hammer detector 130 may pre-set a plurality of unit segments, and for each of the preset unit segments, store the active address RADD in the address queue 132 as the candidate address LADD#, where # is an integer greater than or equal to two. The row hammer detector 130 may initialize the address queue 132 for each unit segment. The row hammer detector 130 may compare the currently input active address RADD with the candidate address LADD# to deactivate the output control signal OUT_EN when the currently input active address RADD matches one of the candidate addresses LADD#, and activate the output control signal OUT_EN when the currently input active address RADD is different from all the candidate addresses LADD#. In this case, the row hammer detector 130 may store the active address RADD as one of the candidate addresses LADD# according to the output control signal OUT_EN to prevent the storage of overlapping candidate addresses LADD#. In the Figures 5 to 8 The detailed configuration and operation of the hammer detector 130 according to one embodiment of the present invention are described in detail.

[0048] The memory interface 150 may provide a command / address signal C / A to the semiconductor memory device 200 by receiving a command CMD and an address ADDR issued by the scheduler 120. In addition, the memory interface 150 may receive host data HDATA from the host interface 110 and provide data DQ to the semiconductor memory device 200. Although not shown, the memory interface 150 may provide a command / address signal C / A to the semiconductor memory device 200 by receiving a refresh-related command and a row hammer address generated from the refresh manager 140.

[0049] Figure 4 It is used to describe an embodiment according to the present invention. Figure 3 Flowchart of the operation of the memory controller 100.

[0050] refer to Figure 4 , the scheduler 120 may generate an activity command ACT according to the request REQ, and generate an activity address RADD corresponding to the activity command ACT (at S410 ).

[0051] The row hammer detector 130 may check the address queue 132 (at S420 ). The row hammer detector 130 may compare the currently input active address RADD with the candidate addresses LADD# stored in the address queue 132 , respectively.

[0052] If the currently input active address RADD is found in the address queue 132, that is, if the currently input active address RADD matches one of the candidate addresses LADD# (i.e., "Yes (Found)" of S430), the row hammer detector 130 may deactivate the output control signal OUT_EN (at S440). Therefore, the scheduler 120 may interrupt the issuance of the currently input active command ACT and the currently input active address RADD (at S450). The scheduler 120 may store the active command ACT and the active address RADD in the internal storage circuit 122, and issue the active command ACT and the active address RADD stored in the internal storage circuit 122 after a predetermined delay time (at S460). Therefore, the active command ACT and the active address RADD may be transmitted to the memory interface 150. For example, the scheduler 120 may issue the active command ACT and the active address RADD again in one of the subsequent unit segments.

[0053] In addition, if the currently input active address RADD is not found in the address queue 132, that is, if the currently input active address RADD is different from all candidate addresses LADD# (i.e., "No (not found)" of S430), the row hammer detector 130 may activate the output control signal OUT_EN (at S470). Therefore, the scheduler 120 may issue and provide the currently input active command ACT and the currently input active address RADD to the memory interface 150 (at S480). When the output control signal OUT_EN is activated, the row hammer detector 130 may store the active address RADD in the address queue 132 as one of the candidate addresses LADD# (at S490). The address queue 132 is initialized for each preset unit segment, and therefore, the candidate address LADD# stored in the address queue 132 may be initialized.

[0054] As described above, in the memory system 10, the memory controller 100 can store the active address as a candidate address for each preset unit segment, and interrupt the issuance of the active command and the active address when the currently input active address matches one of the candidate addresses. The memory controller 100 can issue the interrupted active command and the interrupted active address in the next unit segment. Therefore, by preventing the issuance of overlapping active addresses in the unit segment, the risk of a row hammer attack in the entire segment can be reduced.

[0055] In the following, reference will be made to Figures 5 to 8 The detailed configuration and operation of the hammer detector 130 are described.

[0056] Figure 5 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 3 Detailed configuration diagram of the hammer detector 130 is shown in FIG.

[0057] refer to Figure 5 , the row hammer detector 130 may include a control signal generating circuit 210 , an address combining circuit 220 , an address queue 230 , and an address comparing circuit 250 .

[0058] The control signal generating circuit 210 may generate a reset signal RSTB and an active pulse signal ACT_P based on the active command ACT. For example, the control signal generating circuit 210 may generate a reset signal RSTB and an active pulse signal ACT_P, wherein the reset signal RSTB is activated at a logic low level during an initial portion of each unit segment and the active pulse signal ACT_P is pulsed at a logic high level whenever the active command ACT is input for a predetermined segment.

[0059] The address combination circuit 220 may insert a logic high bit (ie, a signal at a power supply voltage (VDD) level) into the active address RADD consisting of n bits. <n-1:0>To generate a combined address IADD consisting of (n+1) bits <n:0>, where n is an integer greater than or equal to two. A logic high bit can be inserted into the active address RADD <n-1:0>The most significant bit (MSB), active address RADD <n-1:0>The least significant bit (LSB) or active address RADD <n-1:0>For example, the address combination circuit 220 may generate a combined address of "100000001" by inserting a logic high bit into the MSB of the active address of "00000001". In one embodiment, the address combination circuit 220 may generate a combined address of "100000001" by inserting one or more bits into the active address RADD <n-1:0>Generate the combined address IADD <n:0>.

[0060] The address queue 230 may correspond to Figure 3 The address queue 230 may sequentially store the combined address IADD for each preset unit segment. <n:0>As the candidate address LADD1 <n:0>To LADD8 <n:0>, and selectively stores the combined address IADD according to the output control signal OUT_EN <n:0>The address queue 230 may be composed of multiple candidate addresses LADD1 <n:0>To LADD8 <n:0>The plurality of storage circuits 230_1 to 230_8 are formed. Figure 5 , the diagram shows the first candidate address LADD1 for storing <n:0>To the eighth candidate address LADD8 <n:0>The first storage circuit 230_1 to the eighth storage circuit 230_8 are configured.

[0061] The first to eighth storage circuits 230_1 to 230_8 may be initialized according to the reset signal RSTB, enabled according to the output control signal OUT_EN, and sequentially store the combined address IADD according to the active pulse signal ACT_P. <n:0>The first candidate address LADD1 <n:0>To the eighth candidate address LADD8 <n:0>Each candidate address in can be composed of the address IADD <n:0>The address queue 230 may be composed of (n+1) bits corresponding to the number of bits of the candidate address. The width of the address queue 230 may be determined by the number of bits of each candidate address (i.e., (n+1) bits). The number of storage circuits provided in the address queue 230 (i.e., the depth of the address queue 230) may be determined depending on the length of the unit segment and the row activity time (tRAS). Therefore, the size of the address queue 230 may be set to width*depth.

[0062] The address comparison circuit 250 can be realized by converting the combined address IADD <n:0>With the first candidate address LADD1 <n:0>To the eighth candidate address LADD8 <n:0>The comparison is performed to generate the output control signal OUT_EN. <n:0>With the first candidate address LADD1 <n:0>To the eighth candidate address LADD8 <n:0>When one of the candidate addresses in the combined address IADD matches, the address comparison circuit 250 may deactivate the output control signal OUT_EN. <n:0>Different from the first candidate address LADD1 <n:0>To the eighth candidate address LADD8 <n:0>When all candidate addresses are compared, the address comparison circuit 250 may activate the output control signal OUT_EN.

[0063] For reference, the address queue 230 stores the combined address IADD <n:0>Instead of the active address RADD <n-1:0>The reason is as follows. When the reset signal RSTB is activated for each unit segment, the first candidate address LADD1 <n:0>To the eighth candidate address LADD8 <n:0>Initialized to all zero bits. In this case, the active address RADD is input with all zero bits. <n-1:0>Therefore, in one embodiment, since the address comparison circuit 250 can insert the combined address IADD with the logic high bit, the output control signal OUT_EN may be inadvertently deactivated. <n:0>With candidate address LADD1 <n:0>To LADD8 <n:0>So even at the first candidate address LADD1 <n:0>To the eighth candidate address LADD8 <n:0>The active address RADD is initialized to all zero bits. <n-1:0>, and can also prevent the output control signal OUT_EN from being inadvertently deactivated.

[0064] Figure 6 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 5 Detailed circuit diagram of the address queue 230.

[0065] refer to Figure 6 , the address queue 230 may include the first candidate addresses LADD1 <n:0>To the eighth candidate address LADD8 <n:0>The first storage circuit 230_1 to the eighth storage circuit 230_8 are configured.

[0066] The first storage circuit 230_1 to the eighth storage circuit 230_8 may be initialized when the reset signal RSTB is activated, and may be activated when the output control signal OUT_EN is activated at a logic high level. The first storage circuit 230_1 to the eighth storage circuit 230_8 are connected in series to each other, and the first storage circuit 230_1 set at the first stage may receive the combined address IADD. <n:0>When the active pulse signal ACT_P pulses, each of the first to eighth storage circuits 230_1 to 230_8 may receive and store the address stored in the previous stage as the first candidate address LADD1. <n:0>To the eighth candidate address LADD8 <n:0>For example, each storage circuit in the first storage circuit 230_1 to the eighth storage circuit 230_8 can be connected to the combined address IADD. <n:0>It consists of (n+1) flip-flops corresponding to each bit.

[0067] With the above configuration, the address queue 230 can store the combined address IADD corresponding to the active address RADD for each preset unit segment. <n:0>As the candidate address LADD1 <n:0>To LADD8 <n:0>At the same time, according to the output control signal OUT_EN, the candidate address LADD1 that is overlapped is prevented from being stored. <n:0>To LADD8 <n:0>.

[0068] Figure 7 FIG. 1 is a diagram illustrating an embodiment of the present invention. Figure 5 Detailed configuration diagram of the address comparison circuit 250.

[0069] refer to Figure 7 , the address comparison circuit 250 may include first to eighth comparators 250_1 to 250_8 and an output control circuit 252 .

[0070] The first to eighth comparators 250_1 to 250_8 may correspond to the first candidate address LADD1, respectively. <n:0>To the eighth candidate address LADD8 <n:0>The first comparator 250_1 to the eighth comparator 250_8 can generate a signal by sending the combined address IADD <n:0>Respectively with the first candidate address LADD1 <n:0>To the eighth candidate address LADD8 <n:0>Each of the first to eighth comparators 250_1 to 250_8 can compare the combined address IADD to generate the first to eighth comparison result signals COMP1 to COMP8. <n:0>The corresponding bit of the first comparator 250_1 is compared with the corresponding candidate address to generate a corresponding comparison result signal of a logic high level when all bits are the same, or to generate a corresponding comparison result signal of a logic low level when any bit is different. For example, each of the first comparator 250_1 to the eighth comparator 250_8 can be composed of a logic circuit that performs a logical exclusive OR (XOR) operation or a logical exclusive NOR (XNOR) operation.

[0071] The output control circuit 252 may generate an output control signal OUT_EN based on the first comparison result signal COMP1 to the eighth comparison result signal COMP8. When any one of the first comparison result signal COMP1 to the eighth comparison result signal COMP8 has a logic high level, the output control circuit 252 may deactivate the output control signal OUT_EN to a logic low level. When all comparison result signals among the first comparison result signal COMP1 to the eighth comparison result signal COMP8 are at a logic low level, the output control circuit 252 may activate the output control signal OUT_EN to a logic high level. For example, the output control circuit 252 may include a first OR gate OR1 to a fourth OR gate OR4 and a NOR gate NR1. Each of the first OR gates OR1 to the fourth OR gate OR4 may perform a logic OR operation on two comparison result signals among the first comparison result signal COMP1 to the eighth comparison result signal COMP8. The NOR gate NR1 may perform a logic NOR operation on the output signals of the first OR gate OR1 to the fourth OR gate OR4.

[0072] With the above configuration, when the combined address IADD corresponding to the active address RADD <n:0>With candidate address LADD1 <n:0>To LADD8 <n:0>When one of the candidate addresses in the address comparison circuit 250 matches, the address comparison circuit 250 may deactivate the output control signal OUT_EN at a logic low level, and when the combined address IADD <n:0>Different from all candidate addresses LADD1 <n:0>To LADD8 <n:0>, the address comparison circuit 250 may activate the output control signal OUT_EN at a logic high level.

[0073] In the following, reference will be made to Figures 2 to 8 The operation of the hammer detector 130 according to one embodiment of the present invention is described.

[0074] Figure 8 is a timing diagram for describing the operation of the hammer detector 130 according to one embodiment of the present invention.

[0075] refer to Figure 8 , the row hammer detector 130 can preset a certain number of unit segments U_SEC[1] to U_SEC[k], where k is an integer greater than or equal to two. The length of each segment in the unit segments U_SEC[1] to U_SEC[k] can be set to m times the row activity time (tRAS), where m is a positive real number greater than 1. The depth of the address queue 230 can be determined based on the length of each segment and the row activity time (tRAS). For example, when the row activity time (tRAS) is 50ns and the length of each segment is set to 400ns, the depth of the address queue 230 can be determined to be 8, which is obtained by dividing the length of each segment by the row activity time (tRAS), i.e. 400 / 50. That is, the address queue 230 can store eight candidate addresses. In this case, the size of the address queue 230 can be determined as width*depth=8*(n+1) bits.

[0076] exist Figure 8 , 8 activity commands ACT and 8 activity addresses RADD are input during each unit segment of the unit segments U_SEC[1] to U_SEC[k]. The control signal generation circuit 210 of the row hammer detector 130 may generate a reset signal RSTB, which is activated during the initial part of each unit segment of the unit segments U_SEC[1] to U_SEC[k]. According to the reset signal RSTB, the address queue 230 may be initialized for the initial part of each unit segment of the unit segments U_SEC[1] to U_SEC[k]. When the activity command ACT is input, the control signal generation circuit 210 may generate an activity pulse signal ACT_P, and the address combination circuit 220 may generate a combination address by inserting a logic high bit into the activity address RADD.

[0077] For example, during the first unit section U_SEC[1], the active address RADD of "A" is input together with the active command ACT. The address comparison circuit 250 can generate a logic high level output control signal OUT_EN by comparing the combined address of "A'" corresponding to the active address RADD of "A" with the initialized candidate addresses LADD1 to LADD8. The address queue 230 stores the combined address of "A'" as the first candidate address LADD1 according to the active pulse signal ACT_P. In this case, by using the combined address instead of the active address RADD, even if the active address RADD of all zero bits is input, the output control signal OUT_EN can be prevented from being unintentionally deactivated. When the output control signal OUT_EN is activated, the scheduler 120 can issue the active command ACT and the active address RADD of "A" to the memory interface 150. The memory interface 150 can receive the active command ACT and the active address RADD issued from the scheduler 120 to transmit the command / address signal C / A to the memory device 200.

[0078] Next, the active address RADD of "B" is input together with the active command ACT. The address comparison circuit 250 can generate an output control signal OUT_EN of a logic high level by comparing the combined address of "B'" corresponding to the active address RADD of "B" with the candidate addresses LADD1 to LADD8. According to the active pulse signal ACT_P, the address queue 230 can shift and store the first candidate address LADD1 of "A'" as the second candidate address LADD2, and store the combined address of "B'" as the first candidate address LADD1. Similarly, since the output control signal OUT_EN is activated, the scheduler 120 can issue the active command ACT and the active address RADD of "B" to the memory interface 150. The memory interface 150 can receive the active command ACT and the active address RADD issued from the scheduler 120 to transmit the command / address signal C / A to the memory device 200.

[0079] Next, the active address RADD of "A" is input together with the active command ACT. The address comparison circuit 250 may compare the combined address of "A'" with the candidate addresses LADD1 to LADD8 to output a logic low output control signal OUT_EN because the combined address of "A'" is the same as the second candidate address LADD2 of "A'". According to the output control signal OUT_EN of the logic low, the address queue 230 may maintain the previously stored candidate addresses LADD1 to LADD8 without storing the combined address of "A'". Since the output control signal OUT_EN is deactivated, the scheduler 120 may interrupt the issuance of the active command ACT and the active address RADD of "A", while storing the active address RADD of "A" in the internal storage circuit 122.

[0080] Next, the active address RADD of "C" is input together with the active command ACT. The address comparison circuit 250 can generate an output control signal OUT_EN of a logic high level by comparing the combined address of "C'" corresponding to the active address RADD of "C" with the candidate addresses LADD1 to LADD8. According to the active pulse signal ACT_P, the address queue 230 can shift and store the second candidate address LADD2 of "A'" as the third candidate address LADD3, shift and store the first candidate address LADD1 of "B'" as the second candidate address LADD2, and store the combined address of "C'" as the first candidate address LADD1. Similarly, since the output control signal OUT_EN is activated, the scheduler 120 can issue the active command ACT and the active address RADD of "C" to the memory interface 150. The memory interface 150 can receive the active command ACT and the active address RADD issued from the scheduler 120 to transmit the command / address signal C / A to the memory device 200.

[0081] Next, the active address RADD of "A" is input together with the active command ACT. The address comparison circuit 250 may compare the combined address of "A'" with the candidate addresses LADD1 to LADD8 to output a logic low output control signal OUT_EN because the combined address of "A'" is the same as the third candidate address LADD3 of "A'". According to the output control signal OUT_EN of the logic low, the address queue 230 may maintain the previously stored candidate addresses LADD1 to LADD8 without storing the combined address of "A'". Since the output control signal OUT_EN is deactivated, the scheduler 120 may interrupt the issuance of the active command ACT and the active address RADD of "A", while storing the active address RADD of "A" in the internal storage circuit 122.

[0082] As described above, during the first unit section U_SEC[1], the row hammer detector 130 may detect the active command ACT repeatedly input for the same active address RADD of "A", and the scheduler 120 may store the active command ACT and the active address RADD. After the first unit section U_SEC[1] ends, the scheduler 120 may reschedule and issue the active command ACT and the active address RADD stored in the internal storage circuit 122.

[0083] The above process is repeated for each unit segment U_SEC[2] to U_SEC[k], active commands ACT repeatedly input for the same active address RADD are detected, and the active commands ACT and active addresses RADD are delayed to be issued to the memory device, thereby reducing the risk of a row hammer attack.

[0084] Fig. 9 is a table showing the number of row hammer counts according to the depth of the address queue 230 according to one embodiment of the present invention.

[0085] refer to Fig. 9 , which shows that as the depth of the address queue 230 increases from 1 to 64, the maximum row hammer (RH) count decreases proportionally.

[0086] A depth of 1 for the address queue 230 may mean that the address queue 230 may store one candidate address during each unit segment, and a depth of 64 for the address queue 230 may mean that the address queue 230 may store 64 candidate addresses during each unit segment. The maximum RH count may mean the maximum number of active commands that may be issued to the memory device.

[0087] That is, as the number of candidate addresses stored in the address queue 230 during a unit sector increases, the maximum number of active commands that can be issued to the memory device decreases, thereby reducing the risk of a row hammer attack.

[0088] Various embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only used to describe the embodiments of the present disclosure. Therefore, the present disclosure is not limited to the above-described embodiments, and many variations are possible within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may be made based on the technical scope of the present disclosure. The embodiments may be combined to form additional embodiments.

[0089] It should be noted that although the technical spirit of the present disclosure has been described in conjunction with the embodiments of the present disclosure, this is for descriptive purposes only and should not be interpreted as limiting. It should be understood by those skilled in the art that various changes may be made thereto without departing from the technical spirit of the present disclosure and the appended claims.

[0090] For example, for the logic gates and transistors provided as examples in the above-described embodiments, different positions and types may be implemented depending on the polarity of an input signal.

Claims

1. A memory controller, comprising: a scheduler configured to generate an activity command and an activity address, and determine whether to issue the activity command and the activity address according to an output control signal; a row hammer detector configured to generate the output control signal by checking a row hammer possibility based on the active command and the active address; as well as A memory interface is configured to provide the active command and the active address issued by the scheduler to a memory device.

2. The memory controller of claim 1 , wherein the scheduler is configured to: issuing the active command and the active address when the output control signal is activated; and The issuing of the active command and the active address is delayed for a predetermined time while the output control signal is deactivated.

3. The memory controller of claim 1 , wherein the row hammer detector is configured to: For each preset unit section of the plurality of preset unit sections, storing the active address as a plurality of candidate addresses; deactivating the output control signal when the active address matches one of the plurality of candidate addresses; and The output control signal is activated when the active address is different from all candidate addresses of the plurality of candidate addresses.

4. The memory controller of claim 1 , wherein the row hammer detector comprises: an address queue configured to sequentially store, for each of a plurality of preset unit sections, a combination address corresponding to the active address as a plurality of candidate addresses, and selectively store the combination address according to the output control signal; as well as The address comparison circuit is configured to compare the combined address with the plurality of candidate addresses to generate the output control signal.

5. The memory controller according to claim 4, wherein the address queue comprises a plurality of storage circuits respectively corresponding to the plurality of candidate addresses and coupled in series, wherein a storage circuit disposed at a first stage among the plurality of storage circuits receives the combined address, and The plurality of storage circuits are initialized according to a reset signal activated for each unit sector, are activated according to the output control signal, and sequentially store the combined address into the plurality of candidate addresses according to the active command.

6. The memory controller according to claim 4, wherein the address comparison circuit comprises: a plurality of comparators, which correspond to the plurality of candidate addresses respectively and are configured to compare the combined address with the plurality of candidate addresses respectively to generate a plurality of comparison result signals; as well as An output control circuit is configured to generate the output control signal based on the plurality of comparison result signals.

7. The memory controller according to claim 4, further comprising: An address combining circuit is configured to insert at least one bit into the active address to generate the combined address.

8. A memory system comprising: a memory device comprising a plurality of rows respectively coupled to memory cells; as well as A memory controller is configured to generate an access command and an access address for each row, check a row hammer possibility based on the access command and the access address to generate an output control signal, and determine whether to issue the access command and the access address to the memory device according to the output control signal.

9. The memory system of claim 8, wherein the memory controller comprises: a scheduler configured to generate the access command and the access address, and determine whether to issue the access command and the access address according to the output control signal; an address queue configured to sequentially store a combination address corresponding to the access address as a plurality of candidate addresses for each of a plurality of preset unit sections, and selectively store the combination address according to the output control signal; as well as The address comparison circuit is configured to compare the combined address with the plurality of candidate addresses to generate the output control signal.

10. The memory system according to claim 9, wherein the address queue comprises a plurality of storage circuits respectively corresponding to the plurality of candidate addresses and coupled in series, wherein a storage circuit disposed at a first stage among the plurality of storage circuits receives the combined address, and The plurality of storage circuits are initialized according to a reset signal activated for each unit sector, are activated according to the output control signal, and sequentially store the combined address into the plurality of candidate addresses according to the access command.

11. The memory system according to claim 9, wherein the address comparison circuit comprises: a plurality of comparators, which correspond to the plurality of candidate addresses respectively and are configured to compare the combined address with the plurality of candidate addresses respectively to generate a plurality of comparison result signals; as well as An output control circuit is configured to generate the output control signal based on the plurality of comparison result signals.

12. The memory system of claim 9, further comprising: An address combining circuit is configured to insert at least one bit into the active address to generate the combined address.

13. A method for operating a memory controller, the method comprising: Generate activity commands and activity addresses; comparing the active address with a plurality of candidate addresses stored in an address queue; as well as Based on a determination that the active address is different than all of the plurality of candidate addresses, the active command and the active address are issued to a memory device while storing the active address as one of the plurality of candidate addresses in the address queue.

14. The operating method according to claim 13, further comprising: For each preset unit section of a plurality of preset unit sections, the address queue is initialized.

15. The operating method according to claim 14, further comprising: interrupting said issuing of said active command and said active address based on a determination that said active address is equal to one of said plurality of candidate addresses, and storing said active address in an internal storage circuit; as well as After a predetermined delay time, the active address and the active command stored in the internal storage circuit are issued.

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