Method for manufacturing semiconductor device
By forming a low resistance second nitride semiconductor layer in a nitride semiconductor device, the problem of difficulty in reducing contact resistance in the prior art is solved, and a higher operating speed and performance improvement is achieved.
Patent Information
- Application Number
- CN202410751975.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-06-22
- Filing Date
- 2024-06-12
- Publication Date
- 2024-12-24
AI Technical Summary
The prior art is difficult to further reduce the contact resistance in a nitride semiconductor device, which limits the increase in the operating speed of the device.
A first nitride semiconductor layer containing gallium is formed on the substrate, and an opening is formed through the mask layer, a mixed gas containing hydrogen and ammonia is used for reduction treatment, and then a low resistance is formed in the chamber by metal organic chemical vapor deposition method. A nitride semiconductor layer is finally formed on it.
Effectively reduces contact resistance and improves the performance of semiconductor devices, especially in high electron mobility transistors.
Smart Images
Figure CN119181639A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a method for manufacturing a semiconductor device. Background Art
[0002] In order to reduce the contact resistance in a semiconductor device using a nitride semiconductor, a structure in which a nitride semiconductor layer containing impurities at a high concentration is regrowthed has been proposed.
[0003] Prior art literature
[0004] Patent Literature
[0005] Patent Document 1: Japanese Patent Application No. 2007-538402
[0006] Patent Document 2: Japanese Patent Application Publication No. 2019-033155
[0007] In recent years, in order to further increase the operating speed, there is a demand for further reduction of the contact resistance. However, in the conventional manufacturing method, it is difficult to further reduce the contact resistance. Summary of the invention
[0008] An object of the present disclosure is to provide a method for manufacturing a semiconductor device capable of further reducing contact resistance.
[0009] The manufacturing method of the semiconductor device disclosed in the present invention has the following steps: forming a first nitride semiconductor layer containing gallium on a substrate; forming a mask layer on the first nitride semiconductor layer; forming an opening in the mask layer to expose a portion of the first nitride semiconductor layer; using a first mixed gas containing hydrogen and ammonia, reducing the first surface of the first nitride semiconductor layer exposed from the opening in a chamber; using a second mixed gas containing hydrogen, nitrogen, ammonia and raw materials of group III elements, forming a second nitride semiconductor layer of a first conductivity type on the first surface by metal organic chemical vapor deposition in the chamber; and forming an electrode on the second nitride semiconductor layer.
[0010] Effects of the Invention
[0011] According to the present disclosure, the contact resistance can be further reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (Part 1).
[0013] Figure 2 This is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (part 2).
[0014] Figure 3This is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (Part 3).
[0015] Figure 4 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (Part 4).
[0016] Figure 5 This is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (Part 5).
[0017] Figure 6 This is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (part 6).
[0018] Figure 7 This is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (part 7).
[0019] Figure 8 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment (the eighth).
[0020] Fig. 9 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a second embodiment (Part 1).
[0021] Fig.10 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment (Part 2).
[0022] Fig.11 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment (Part 3).
[0023] Fig.12 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment (Part 4).
[0024] Fig.13 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment (Part 1).
[0025] Fig.14 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment (part 2).
[0026] Fig.15 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment (Part 3).
[0027] Fig.16 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment (Part 4).
[0028] Fig.17 This is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment (Part 5).
[0029] Fig.18 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment (the sixth one).
[0030] Fig.19 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment (part 7).
[0031] Fig. 20 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment (the eighth one).
[0032] Fig.21 This is a cross-sectional view showing the method for manufacturing the semiconductor device according to the third embodiment (No. 9).
[0033] Fig. 22 This is a diagram showing an example of the relationship between the ratio of the flow rate of nitrogen in the second mixed gas to the total flow rate of hydrogen and nitrogen in the second mixed gas and the second nitride semiconductor layer.
[0034] Description of reference numerals:
[0035] 1, 2, 3: Semiconductor devices
[0036] 101, 301: Substrate
[0037] 110, 310: Nitride semiconductor layer
[0038] 110A, 310A: Surface
[0039] 110D, 110S, 210D, 210S, 310D, 310S: Surface
[0040] 111: Buffer layer
[0041] 112, 312: Barrier layer
[0042] 113, 311: Channel layer
[0043] 113c, 311c: Channel area
[0044] 113D, 113S, 315D, 315S: concave part
[0045] 121, 122, 123: SiN layer
[0046] 121D, 121G, 121S, 122G: Open
[0047] 131D, 131S, 331, 331D, 331S: n-type GaN layer
[0048] 132D: Drain electrode
[0049] 132G: Gate electrode
[0050] 132S: Source electrode
[0051] 151: Resist pattern
[0052] 151D, 151S: Open
[0053] 313: Cap layer. DETAILED DESCRIPTION
[0054] [Description of Embodiments of the Present Disclosure]
[0055] First, embodiments of the present disclosure will be described by way of examples.
[0056] [1] A method for manufacturing a semiconductor device according to one embodiment of the present invention comprises the following steps: forming a first nitride semiconductor layer comprising gallium on a substrate; forming a mask layer on the first nitride semiconductor layer; forming an opening in the mask layer to expose a portion of the first nitride semiconductor layer; performing a reduction treatment on a first surface of the first nitride semiconductor layer exposed from the opening in a chamber using a first mixed gas comprising hydrogen and ammonia; forming a second nitride semiconductor layer of a first conductivity type on the first surface by metal organic chemical vapor deposition in the chamber using a second mixed gas comprising hydrogen, nitrogen, ammonia and a raw material of a group III element; and forming an electrode on the second nitride semiconductor layer.
[0057] The reduction treatment is performed in the chamber for forming the second nitride semiconductor layer, and the second nitride semiconductor layer is formed in the chamber. Therefore, even if a natural oxide film is formed on the first surface of the first nitride semiconductor layer before the reduction treatment, the second nitride semiconductor layer is formed in a state where the natural oxide film is removed. Therefore, the contact resistance between the electrode and the first nitride semiconductor layer can be reduced.
[0058] [2] In [1], the mask layer may be a silicon nitride layer. In this case, the mask layer may be used as a gate insulating film.
[0059] [3] In [1] or [2], the second nitride semiconductor layer may be an n-type gallium nitride layer. In this case, the n-type gallium nitride layer has low resistance, so it is easy to reduce the contact resistance between the electrode and the first nitride semiconductor layer.
[0060] [4] In any one of [1] to [3], the first mixed gas may contain nitrogen. In this case, the nitrogen can suppress etching of the first nitride semiconductor layer caused by hydrogen.
[0061] [5] In any one of [1] to [4], the first surface may be a nitrogen polar surface. In this case, the contact resistance can be suppressed while the resistance of the current path in the first nitride semiconductor layer can be easily reduced.
[0062] [6] Alternatively, in [5], the step of forming the first nitride semiconductor layer includes the steps of: forming a barrier layer; and forming a channel layer on the barrier layer. In this case, a high electron mobility transistor having a low contact resistance between the electrode and the first nitride semiconductor layer can be formed.
[0063] [7] Alternatively, in [6], between the step of forming the opening and the step of performing the reduction treatment, there is a step of forming a recessed portion in the portion of the channel layer exposed from the opening, and the first surface is the inner surface of the recessed portion. In this case, the distance between the second nitride semiconductor layer and the channel region of the high electron mobility transistor can be reduced. Therefore, further reduction in contact resistance can be achieved.
[0064] [8] Alternatively, in any one of [1] to [7], the second mixed gas may contain triethylgallium as the raw material of the Group III element. In this case, the growth rate of the second nitride semiconductor layer is easily reduced, and the formation of the second nitride semiconductor layer on the mask layer is easily suppressed.
[0065] [9] In any one of [1] to [8], the ratio of the flow rate of nitrogen in the second mixed gas to the total flow rate of hydrogen and nitrogen in the second mixed gas may be 30% or more and 95% or less. In this case, the sheet resistance of the second nitride semiconductor layer can be easily reduced.
[0066] [Details of the embodiments of the present disclosure]
[0067] Hereinafter, the embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto. It should be noted that in the present specification and the drawings, for components having substantially the same functional configuration, duplicate descriptions may be omitted by marking the same reference numerals.
[0068] (First Embodiment)
[0069] A first embodiment will be described. The first embodiment relates to a method for manufacturing a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Figures 1 to 8 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.
[0070] In the first embodiment, first, as Figure 1 As shown, for example, a nitride semiconductor layer 110 containing gallium (Ga) is formed on a substrate 101 by metalorganic chemical vapor deposition (MOCVD). In the formation of the nitride semiconductor layer 110, a buffer layer 111, a barrier layer 112, and a channel layer 113 are sequentially formed. The nitride semiconductor layer 110 is an example of a first nitride semiconductor layer.
[0071] The substrate 101 is, for example, a substrate for growing a gallium nitride (GaN) semiconductor, and in one example is a semi-insulating silicon carbide (SiC) substrate. When the substrate 101 is a SiC substrate, the surface of the substrate 101 is a carbon (C) polar surface. When the surface of the substrate 101 is a C polar surface, the buffer layer 111, the barrier layer 112, and the channel layer 113 can be crystal-grown with the nitrogen (N) polar surface as the growth surface. It should be noted that a sapphire substrate can also be used as a substrate for growing a GaN semiconductor. In addition, the substrate 101 may not be a substrate for crystal growth. In this case, the substrate may be removed from the buffer layer 111, the barrier layer 112, and the channel layer 113 grown on another substrate, and the substrate 101 may be bonded to the buffer layer 111, the barrier layer 112, and the channel layer 113. In this case, a semi-insulating substrate made of various materials can be used as the substrate 101 , for example, a sapphire substrate, a silicon (Si) substrate, a SiC substrate, an aluminum nitride (AlN) substrate, a sintered substrate, or the like can be used.
[0072] The buffer layer 111 is, for example, an AlN layer. The thickness of the AlN layer is, for example, greater than 5 nm and less than 100 nm. Alternatively, the buffer layer 111 includes an AlN layer and a GaN layer or an aluminum gallium nitride (AlGaN) layer on the AlN layer. The thickness of the GaN layer or the AlGaN layer is, for example, greater than 300 nm and less than 2000 nm.
[0073] The barrier layer 112 is, for example, an AlGaN layer. The band gap of the barrier layer 112 is larger than the band gap of the channel layer 113. The thickness of the barrier layer 112 is, for example, not less than 5 nm and not more than 50 nm, and as an example, may be 30 nm. x Ga 1－x In the case of an N layer, its Al composition x is, for example, greater than 0.15 and less than 0.55, and as an example, may be 0.35. The conductivity type of the barrier layer 112 is, for example, n-type or non-doped (i-type). An indium aluminum nitride (InAlN) layer or an indium aluminum gallium nitride (InAlGaN) layer may be used instead of the AlGaN layer.
[0074] The channel layer 113 is, for example, a GaN layer. The band gap of the channel layer 113 is smaller than the band gap of the barrier layer 112. The thickness of the channel layer 113 is, for example, greater than 5 nm and less than 30 nm, and as an example, it can also be 9 nm. Between the channel layer 113 and the barrier layer 112, strain is generated due to the difference in their lattice constants, and the strain induces piezoelectric charge on the interface between the two. As a result, a two-dimensional electron gas (two dimensional electron gas: 2DEG) is generated near the interface between the channel layer 113 and the barrier layer 112, thereby forming a channel region 113c. The conductivity type of the channel layer 113 is, for example, n-type or non-doped (i-type). The surface of the channel layer 113 constitutes the surface 110A of the nitride semiconductor layer 110. In addition, a spacer layer can also be formed between the barrier layer 112 and the channel layer 113. The spacer layer is, for example, an AlN layer. The thickness of the spacer layer is, for example, not less than 0.5 nm and not more than 3.0 nm, and as an example, may be 1.0 nm.
[0075] On the C polarity surface of the SiC substrate, the buffer layer 111, the barrier layer 112, and the channel layer 113 grow crystals with the N polarity surface as the growth surface. Therefore, in each of the buffer layer 111, the barrier layer 112, and the channel layer 113, the principal surface (upper surface) far from the substrate 101 of the two principal surfaces becomes the N polarity surface, and the principal surface (lower surface) close to the substrate 101 becomes the Ga polarity surface.
[0076] Then, if Figure 2 As shown, a silicon nitride (SiN) layer 121 is formed in contact with the surface 110A of the nitride semiconductor layer 110. The SiN layer 121 can be formed, for example, by a low pressure CVD (LPCVD) method. Next, a resist pattern 151 is formed on the SiN layer 121. The resist pattern 151 has an opening 151S for a source and an opening 151D for a drain. The SiN layer 121 is an example of a mask layer.
[0077] Then, if Figure 3 As shown, the SiN layer 121 is etched using the resist pattern 151 as a mask. The etching is, for example, reactive ion etching (RIE) using a fluorine-based gas. As a result, an opening 121S is formed in the SiN layer 121 below the opening 151S, and an opening 121D is formed in the SiN layer 121 below the opening 151D. A portion of the nitride semiconductor layer 110 is exposed from the opening 121S, and another portion of the nitride semiconductor layer 110 is exposed from the opening 121D.
[0078] Then, if Figure 4As shown, a chemical solution is used to remove the resist pattern 151. Next, in the MOCVD chamber, a first mixed gas containing nitrogen (N2), hydrogen (H2) and ammonia (NH3) is used to perform a reduction treatment on the surface 110S exposed from the opening 121S and the surface 110D exposed from the opening 121D of the nitride semiconductor layer 110. In this reduction treatment, for example, the temperature of the substrate 101 is set to be greater than 700°C and less than 900°C, and may also be set to be greater than 750°C and less than 850°C. During the period from the formation of the opening 121S and the opening 121D to the removal of the resist pattern 151, a natural oxide film may be formed on the surface 110S and the surface 110D, but the natural oxide film will be removed by the reduction treatment. For example, the surface 110S and the surface 110D are part of the surface 110A. The surface 110S and the surface 110D are an example of a first surface.
[0079] Then, if Figure 5 As shown, an n-type GaN layer 131S is formed on the surface 110S, and an n-type GaN layer 131D is formed on the surface 110D. In the formation of the n-type GaN layer 131S and the n-type GaN layer 131D, the MOCVD chamber is not open to the atmosphere, and a second mixed gas containing N2, H2, NH3 and gallium is used to form a film in the same MOCVD chamber. For example, triethylgallium (TEG) is used as a gallium raw material. For example, the n-type dopant is silicon (Si) or germanium (Ge), and the concentration of the n-type dopant is 1×10 17 cm -3 In the film formation, for example, the temperature of the substrate 101 is set to be 700°C or higher and 900°C or lower, or 750°C or higher and 850°C or lower. In the film formation, for example, the pressure in the MOCVD chamber is set to be 13.3 kPa (100 Torr) or higher and 101.3 kPa (760 Torr) or lower, or 40.0 kPa (300 Torr) or higher and 101.3 kPa (760 Torr) or lower. The n-type GaN layer 131S and the n-type GaN layer 131D are examples of the second nitride semiconductor layer.
[0080] Then, if Figure 6As shown, a source electrode 132S is formed on the n-type GaN layer 131S, and a drain electrode 132D is formed on the n-type GaN layer 131D. In the formation of the source electrode 132S and the drain electrode 132D, first, a plurality of metal layers constituting the source electrode 132S and the drain electrode 132D are evaporated to form a stacked structure. Thereafter, the stacked structure is heat treated for alloying. In the formation of the stacked structure, for example, a tantalum (Ta) layer, an aluminum (Al) layer, and a Ta layer can be formed in sequence, or a titanium (Ti) layer, an Al layer, and a Ti layer can be formed in sequence. The source electrode 132S and the drain electrode 132D are an example of an electrode.
[0081] Then, if Figure 7 As shown, a SiN layer 122 is formed on the SiN layer 121. The SiN layer 122 covers the n-type GaN layer 131S, the source electrode 132S, the n-type GaN layer 131D and the drain electrode 132D. Next, an opening 122G is formed in the SiN layer 122 between the source electrode 132S and the drain electrode 132D. A portion of the SiN layer 121 is exposed from the opening 122G. Next, a gate electrode 132G is formed that is connected to the SiN layer 121 through the opening 122G. In the formation of the gate electrode 132G, a plurality of metal layers constituting the gate electrode 132G are evaporated to form a stacked structure. In the formation of the stacked structure, for example, a nickel (Ni) layer, a palladium (Pd) layer and an Au layer may also be formed in sequence.
[0082] Then, if Figure 8 As shown, a SiN layer 123 is formed on the SiN layer 122. The SiN layer 123 covers the gate electrode 132G.
[0083] In this way, the semiconductor device 1 can be manufactured.
[0084] In the first embodiment, the reduction treatment is performed in the MOCVD chamber for forming the n-type GaN layer 131S and the n-type GaN layer 131D, and the n-type GaN layer 131S and the n-type GaN layer 131D are formed in the MOCVD chamber. Therefore, the n-type GaN layer 131S and the n-type GaN layer 131D are formed in a state where the natural oxide film is removed. Therefore, the contact resistance between the source electrode 132S and the drain electrode 132D and the nitride semiconductor layer 110 can be reduced. In addition, the SiN layer 121 is used as a gate insulating film.
[0085] H 2 contained in the first mixed gas contributes to the reduction, NH 3 suppresses the separation of Ga from the nitride semiconductor layer 110 , and N 2 suppresses the etching of the nitride semiconductor layer 110 caused by H 2 .
[0086] The raw materials of NH3 and gallium contained in the second mixed gas are used as the raw materials of the n-type GaN layer 131S and the n-type GaN layer 131D. H2 is contained in the second mixed gas, which makes it easy to reduce the growth rate of the n-type GaN layer when forming the n-type GaN layer 131S and the n-type GaN layer 131D. Therefore, it is easy to make the n-type GaN layer 131S and the n-type GaN layer 131D contain n-type dopants at a high concentration. In addition, H2 is contained in the second mixed gas, which makes it easy to suppress the formation of the n-type GaN layer on the SiN layer 121. Even if TEG is used as a raw material for gallium, it is easy to reduce the growth rate of the n-type GaN layer when forming the n-type GaN layer 131S and the n-type GaN layer 131D, and it is easy to make the n-type GaN layer 131S and the n-type GaN layer 131D contain n-type dopants at a high concentration. For example, the growth rate of the n-type GaN layer 131S and the n-type GaN layer 131D may be greater than or equal to 0.04 nm / sec and less than or equal to 0.08 nm / sec, or may be greater than or equal to 0.05 nm / sec and less than or equal to 0.07 nm / sec.
[0087] The nitride semiconductor layer formed between the nitride semiconductor layer 110 and the source electrode 132S and the drain electrode 132D is the n-type GaN layer 131S and the n-type GaN layer 131D, and thus it is easy to reduce the contact resistance.
[0088] The surface 110A of the nitride semiconductor layer 110 is an N-polar surface, so even if the Al composition of the barrier layer 112 is high, the contact resistance can be prevented from increasing. Therefore, it is easy to increase the concentration of 2DEG and reduce the resistance of the channel region 113c. In particular, the channel layer 113 is formed on the barrier layer 112, so it is easy to reduce the resistance of the channel region 113c.
[0089] (Second Embodiment)
[0090] Next, a second embodiment will be described. The second embodiment relates to a method for manufacturing a semiconductor device including a GaN-based HEMT. Figures 9 to 12 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.
[0091] In the second embodiment, first, the process up to the formation of the opening 121S and the opening 121D is performed in the same manner as in the first embodiment (see Figure 3 ). Then, if Fig. 9As shown, the channel layer 113 is etched using the resist pattern 151 as a mask, thereby forming a recess 113S connected to the opening 121S and a recess 113D connected to the opening 121D in the channel layer 113. The etching is, for example, RIE using a chlorine-based gas. For example, the recess 113S and the recess 113D are formed at a depth that does not reach the channel region 113c. That is, with the surface 110A of the nitride semiconductor layer 110 as a reference, the depths of the recess 113S and the recess 113D are smaller than the depth of the channel region 113c.
[0092] Then, if Fig.10 As shown, a chemical solution is used to remove the resist pattern 151. Next, in the MOCVD chamber, a first mixed gas containing N2, H2 and NH3 is used to perform a reduction treatment on the surface 210S exposed from the opening 121S and the surface 210D exposed from the opening 121D of the nitride semiconductor layer 110. During the period from the formation of the opening 121S and the opening 121D to the removal of the resist pattern 151, a natural oxide film may be formed on the surface 210S and the surface 210D, but the natural oxide film will be removed by the reduction treatment. For example, the surface 210S is the inner surface (bottom surface and side wall surface) of the recess 113S, and the surface 210D is the inner surface (bottom surface and side wall surface) of the recess 113D. The surface 210S and the surface 210D are an example of a first surface.
[0093] Then, if Fig.11 As shown, an n-type GaN layer 131S is formed on the surface 210S, and an n-type GaN layer 131D is formed on the surface 210D. In the formation of the n-type GaN layer 131S and the n-type GaN layer 131D, the MOCVD chamber is not open to the atmosphere, and film formation is performed in the same MOCVD chamber using a second mixed gas containing N2, H2, NH3 and gallium raw materials. For example, TEG is used as the gallium raw material.
[0094] Then, if Fig.12 As shown in FIG. 1 , similarly to the first embodiment, the processes after the formation of the source electrode 132S and the drain electrode 132D are performed.
[0095] In this way, the semiconductor device 2 can be manufactured.
[0096] The second embodiment can also achieve the same effect as the first embodiment. In the second embodiment, the recessed portion 113S and the recessed portion 113D are formed, the n-type GaN layer 131S is formed on the surface 210S, and the n-type GaN layer 131D is formed on the surface 210D, so that the distance between the n-type GaN layer 131S and the n-type GaN layer 131D and the channel region 113c can be reduced. Therefore, further reduction in contact resistance can be achieved.
[0097] (Third Embodiment)
[0098] Next, a third embodiment will be described. The third embodiment relates to a method for manufacturing a semiconductor device including a GaN-based HEMT. Figures 13 to 21 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment.
[0099] In the third embodiment, first, as Fig.13 As shown, a nitride semiconductor layer 310 containing Ga is formed on a substrate 301 by, for example, MOCVD. In the formation of the nitride semiconductor layer 310, a channel layer 311, a barrier layer 312, and a cap layer 313 are sequentially formed. The nitride semiconductor layer 310 is an example of a first nitride semiconductor layer.
[0100] The substrate 301 is, for example, a substrate for growing GaN-based semiconductors, and in one example is a semi-insulating SiC substrate. When the substrate 301 is a SiC substrate, the surface of the substrate 301 is a Si polar surface. When the surface of the substrate 301 is a Si polar surface, the channel layer 311, the barrier layer 312, and the cap layer 313 can grow crystals with the Ga polar surface as the growth surface.
[0101] The channel layer 311 is, for example, a GaN layer. The thickness of the channel layer 311 is, for example, not less than 200 nm and not more than 2000 nm, and as an example, may be 1000 nm. A buffer layer may be formed between the channel layer 311 and the substrate 301 .
[0102] The barrier layer 312 is, for example, an AlGaN layer. The band gap of the barrier layer 312 is larger than the band gap of the channel layer 311. The thickness of the barrier layer 312 is, for example, not less than 5 nm and not more than 30 nm, and as an example, may be 15 nm. x Ga 1－x In the case of an N layer, its Al composition x is, for example, greater than 0.15 and less than 0.35, and as an example, it can also be 0.25. Between the channel layer 311 and the barrier layer 312, strain is generated due to the difference in their lattice constants, and the strain induces piezoelectric charge on the interface between the two. As a result, 2DEG is generated near the interface between the channel layer 311 and the barrier layer 312, thereby forming a channel region 311c. An InAlN layer or an InAlGaN layer can also be used instead of the AlGaN layer. In addition, a spacer layer can also be formed between the channel layer 311 and the barrier layer 312. The spacer layer is, for example, an AlN layer. The thickness of the spacer layer is, for example, greater than 0.5nm and less than 3.0nm, and as an example, it can also be 1.0nm.
[0103] The cap layer 313 is, for example, a GaN layer. The thickness of the cap layer 313 is, for example, not less than 1 nm and not more than 5 nm, and may be 2 nm as an example. The surface of the cap layer 313 constitutes the surface 310A of the nitride semiconductor layer 310 .
[0104] On the Si polar surface of the SiC substrate, the channel layer 311, the barrier layer 312, and the cap layer 313 grow crystals with the Ga polar surface as the growth surface. Therefore, in each of the channel layer 311, the barrier layer 312, and the cap layer 313, the main surface (upper surface) far from the substrate 301 of the two main surfaces becomes a Ga polar surface, and the main surface (lower surface) close to the substrate 301 becomes an N polar surface.
[0105] Then, if Fig.14 As shown, the SiN layer 121 is formed in contact with the surface 310A of the nitride semiconductor layer 310. Next, a resist pattern 151 is formed on the SiN layer 121. The resist pattern 151 has an opening 151S for the source and an opening 151D for the drain.
[0106] Then, if Fig.15 As shown, the SiN layer 121 is etched using the resist pattern 151 as a mask. The etching is, for example, RIE using a fluorine-based gas. As a result, an opening 121S is formed in the SiN layer 121 below the opening 151S, and an opening 121D is formed in the SiN layer 121 below the opening 151D. A portion of the nitride semiconductor layer 310 is exposed from the opening 121S, and another portion of the nitride semiconductor layer 310 is exposed from the opening 121D.
[0107] Then, if Fig.16 As shown, the resist pattern 151 is used as a mask to etch the nitride semiconductor layer 310, thereby forming a recess 315S connected to the opening 121S and a recess 315D connected to the opening 121D in the nitride semiconductor layer 310. The etching is, for example, RIE using a chlorine-based gas. For example, the recess 315S and the recess 315D are formed to a depth that penetrates the channel region 311c. That is, with the surface 310A of the nitride semiconductor layer 310 as a reference, the depth of the recess 315S and the recess 315D is greater than the depth of the channel region 311c. The formation of the recess 315S and the recess 315D may also be stopped in the middle of the barrier layer 312. That is, the recess 315S and the recess 315D may also be formed so that the bottom surfaces of the recess 315S and the recess 315D are located in the barrier layer 312.
[0108] Then, if Fig.17As shown, a chemical solution is used to remove the resist pattern 151. Next, in the MOCVD chamber, a first mixed gas containing N2, H2 and NH3 is used to perform a reduction treatment on the surface 310S exposed from the opening 121S and the surface 310D exposed from the opening 121D of the nitride semiconductor layer 310. In this reduction treatment, for example, the temperature of the substrate 301 is set to be greater than 700°C and less than 900°C, and can also be set to be greater than 750°C and less than 850°C. During the period from the formation of the opening 121S and the opening 121D to the removal of the resist pattern 151, a natural oxide film may be formed on the surface 310S and the surface 310D, but the natural oxide film will be removed by the reduction treatment. For example, the surface 310S is the inner surface (bottom surface and side wall surface) of the recess 315S, and the surface 310D is the inner surface (bottom surface and side wall surface) of the recess 315D. The surface 310S and the surface 310D are examples of the first surface.
[0109] Then, if Fig.18 As shown, an n-type GaN layer 331 is formed by filling the recess 315S and the recess 315D. In the formation of the n-type GaN layer 331, the MOCVD chamber is not open to the atmosphere, and film formation is performed in the same MOCVD chamber using a second mixed gas containing N2, H2, NH3 and gallium as a raw material. For example, trimethylgallium (TMG) or TEG is used as a raw material for gallium. The n-type GaN layer 331 is deposited not only on the nitride semiconductor layer 310, but also on the SiN layer 121. The n-type GaN layer 331 can also be formed in the opening 121S and the opening 121D. On the Ga polar surface of the nitride semiconductor layer 310, the n-type GaN layer 331 grows crystals with the N polar surface as the growth surface. Therefore, on the Ga polarity surface of the nitride semiconductor layer 310 , of the two main surfaces of the n-type GaN layer 331 , the main surface (upper surface) farther from the substrate 301 becomes a Ga polarity surface, and the main surface (lower surface) closer to the substrate 301 becomes an N polarity surface.
[0110] Then, if Fig.19 As shown, an alkaline solution such as an aqueous sodium hydroxide solution is used to remove the n-type GaN layer 331 of the SiN layer 121. On the Ga polarity plane of the nitride semiconductor layer 310, the upper surface of the n-type GaN layer 331 is a Ga polarity plane, so the n-type GaN layer 331 in the recess 315S and the n-type GaN layer 331 in the recess 315D are not etched. As a result, an n-type GaN layer 331S is formed in the recess 315S, and an n-type GaN layer 331D is formed in the recess 315D. The n-type GaN layer 331S and the n-type GaN layer 331D are examples of the second nitride semiconductor layer.
[0111] Then, if Fig. 20As shown, a source electrode 132S is formed on the n-type GaN layer 331S, and a drain electrode 132D is formed on the n-type GaN layer 331D. Next, an opening 121G is formed in the SiN layer 121 between the source electrode 132S and the drain electrode 132D. A portion of the nitride semiconductor layer 310 is exposed from the opening 121G. Next, a gate electrode 132G is formed to be in contact with the nitride semiconductor layer 310 through the opening 121G.
[0112] Then, if Fig.21 As shown, the SiN layer 123 is formed on the SiN layer 121. The SiN layer 123 covers the n-type GaN layer 331S, the source electrode 132S, the n-type GaN layer 331D, the drain electrode 132D, and the gate electrode 132G.
[0113] In this way, the semiconductor device 3 can be manufactured.
[0114] In the third embodiment, the n-type GaN layer 331 is formed in the MOCVD chamber in which the reduction treatment is performed for forming the n-type GaN layer 331. Therefore, the n-type GaN layer 331 is formed in a state where the natural oxide film is removed. Therefore, the contact resistance between the source electrode 132S and the drain electrode 132D and the nitride semiconductor layer 310 can be reduced.
[0115] In the present disclosure, the relative ratio of hydrogen and nitrogen in the second mixed gas is not limited, but when the ratio R of the flow rate of nitrogen to the total flow rate of hydrogen and nitrogen is greater than 30% and less than 95%, it is easy to obtain a low sheet resistance in the second nitride semiconductor layer. When the ratio R is greater than 60% and less than 90%, it is easy to obtain a lower sheet resistance in the second nitride semiconductor layer, and when the ratio R is greater than 75% and less than 85%, it is easy to obtain a particularly low sheet resistance in the second nitride semiconductor layer. In the case where the ratio R is less than 30%, the proportion of hydrogen is too high, the growth rate will increase excessively, and the surface morphology will deteriorate, so the sheet resistance is likely to become high. On the other hand, in the case where the ratio R is greater than 95%, the crystallinity of the second nitride semiconductor layer will decrease and the sheet resistance may become high. Fig. 22 This is a diagram showing an example of the relationship between the ratio R of the flow rate of nitrogen in the second mixed gas to the total flow rate of hydrogen and nitrogen in the second mixed gas and the second nitride semiconductor layer.
[0116] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes can be made within the scope described in the claims.
Claims
1. A method for manufacturing a semiconductor device, comprising the following steps: forming a first nitride semiconductor layer including gallium on a substrate; forming a mask layer on the first nitride semiconductor layer; forming an opening in the mask layer to expose a portion of the first nitride semiconductor layer; performing a reduction treatment on a first surface of the first nitride semiconductor layer exposed from the opening in a chamber using a first mixed gas including hydrogen and ammonia; Using a second mixed gas including hydrogen, nitrogen, ammonia, and a Group III element as a raw material, forming a second nitride semiconductor layer of the first conductivity type on the first surface by metal organic chemical vapor deposition in the chamber; and An electrode is formed on the second nitride semiconductor layer.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: The mask layer is a silicon nitride layer.
3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The second nitride semiconductor layer is an n-type gallium nitride layer.
4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The first mixed gas contains nitrogen.
5. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The first face is a nitrogen-polar face.
6. The method for manufacturing a semiconductor device according to claim 5, wherein: The step of forming the first nitride semiconductor layer includes the following steps: forming a barrier layer; and A channel layer is formed over the barrier layer.
7. The method for manufacturing a semiconductor device according to claim 6, wherein: A step of forming a recessed portion in a portion of the channel layer exposed from the opening is provided between the step of forming the opening and the step of performing the reduction treatment. The first surface is an inner surface of the recessed portion.
8. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The second mixed gas contains triethylgallium as a raw material of the group III element.
9. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: A ratio of a flow rate of nitrogen in the second mixed gas to a total flow rate of hydrogen and nitrogen in the second mixed gas is 30% or more and 95% or less.