Manufacturing method of semiconductor device with near gate field plate and semiconductor device

Abstract

The embodiment of the invention discloses a manufacturing method of a semiconductor device with a near gate field plate and the semiconductor device, and is applied to the technical field of electronic devices. In the process of manufacturing a semiconductor device with a near-gate field plate, the formation of a second-layer field plate, a source electrode and a drain electrode in the semiconductor device is concentrated in the same step, so that the formed source electrode, the drain electrode and the second-layer field plate are on the same layer, and the formation of a gate electrode, a first-layer field plate and even a third-layer field plate is concentrated in the same step. Therefore, the manufacturing steps of the semiconductor device with the near-gate field plate can be simplified, and the implementation cost and time of setting the field plate in the semiconductor device are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic devices, and in particular to a method for manufacturing a semiconductor device with a near-gate field plate and the semiconductor device. Background Art

[0002] As a representative of wide bandgap (WBG) power semiconductor devices, GaN HEMTs have great potential in high-frequency power applications. In the design of lateral GaN HEMT switch devices, the voltage withstand capability of the switch device is a very important performance parameter. When the switch device is turned off, the main voltage withstand structure of the lateral GaN HEMT switch device is the depletion region between the gate (G) and the drain (D). Under the same depletion region size, the electric field distribution determines the size of the voltage withstand value, and there is an electric field concentration effect at the gate corner close to the drain side, resulting in an electric field peak here. When the electric field peak reaches a certain critical value, electric field breakdown will occur, which will affect the reliability of the device and even cause irreversible damage.

[0003] In order to improve the voltage resistance of semiconductor devices, a field plate structure is generally used. The main function of the field plate is to adjust the electric field distribution in the drift region, weaken the electric field spike that originally existed near the gate, and improve the voltage resistance of the semiconductor device. The introduction of the field plate will reduce the original electric field spike, but there will be a new electric field spike at the end of the field plate. For high-voltage semiconductor devices, a single field plate is often difficult to achieve an ideal electric field distribution. Generally, high-voltage semiconductor devices have a multi-level field plate structure for modulating the electric field distribution. Using this method, each layer of field plate from the gate to the drain will further modulate the electric field spike generated by the previous field plate. By adjusting the length and height of each level of field plate, an optimized electric field distribution is obtained to achieve higher voltage resistance and reliability.

[0004] In order to realize multi-layer field plates in semiconductor devices, the existing structure often requires etching of multiple dielectric layers and metals and multiple photolithography steps. Moreover, as the number of field plate layers increases, the process cost and time cost will also increase significantly. For example, in the current mainstream 650V GaN HEMT chip, 3 to 4 layers of field plates are generally required, and the production of gate and field plate metal requires a total of 4 to 5 photolithography steps, which accounts for 20% to 30% of the process cost and time cost of the entire chip tape-out process. Summary of the invention

[0005] The embodiments of the present invention provide a method for manufacturing a semiconductor device with a near-gate field plate and a semiconductor device, which simplifies the implementation cost and time of setting a field plate in the semiconductor device.

[0006] An embodiment of the present invention provides a method for manufacturing a semiconductor device having a near-gate field plate, comprising: Depositing a first dielectric layer and a base dielectric layer on the epitaxial layer of the substrate, wherein the base dielectric layer includes a plurality of dielectric layers and at least one barrier layer sandwiched between the plurality of dielectric layers, and performing dielectric etching on the first dielectric layer and the base dielectric layer to form source and drain dielectrics; Performing metal deposition and metal etching on the source and drain dielectrics to form a source, a drain and a second field plate of the semiconductor device, and reserving a gate and at least one first field plate between the source and the second field plate; Depositing a second dielectric layer, and performing dielectric etching on the second dielectric layer and the base dielectric layer at the reserved position to form a gate dielectric and at least one first-layer field plate dielectric, wherein any first-layer field plate dielectric is under a corresponding barrier layer; Metal deposition and metal etching are performed on the gate dielectric and at least one first-layer field plate dielectric to form a gate and at least one first-layer field plate of the semiconductor device.

[0007] Another aspect of an embodiment of the present invention provides a method for manufacturing a semiconductor device having a near-gate field plate, comprising: Depositing a first dielectric layer and a base dielectric layer on the epitaxial layer of the substrate, wherein the base dielectric layer includes a plurality of dielectric layers and at least one barrier layer sandwiched between the plurality of dielectric layers, and performing dielectric etching on the first dielectric layer and the base dielectric layer to form source and drain dielectrics; Performing metal deposition and metal etching on the source and drain dielectrics to form a source, a drain and a second field plate of the semiconductor device, and reserving a gate and at least one first field plate between the source and the second field plate; Depositing a second dielectric layer, performing metal deposition and metal etching on the second dielectric layer to form a third field plate, wherein the third field plate is above the second field plate, and the projections of the third field plate and the second field plate in the direction of the substrate have an overlapping area; Depositing a third dielectric layer, and performing dielectric etching on the second dielectric layer and the base dielectric layer at the reserved position to form a gate dielectric and at least one first-layer field plate dielectric, wherein any first-layer field plate dielectric is under a corresponding barrier layer; Metal deposition and metal etching are performed on the gate dielectric and at least one first-layer field plate dielectric to form a gate and at least one first-layer field plate of the semiconductor device.

[0008] Another aspect of the embodiments of the present invention further provides a semiconductor device with a near-gate field plate, wherein the semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device with a near-gate field plate according to one or another aspect of the embodiments of the present invention.

[0009] It can be seen that in the embodiment of the present invention, in the process of manufacturing a semiconductor device with a near-gate field plate, the formation of the second-layer field plate in the semiconductor device and the source and drain are concentrated in the same step, so that the formed source, drain and second-layer field plate are on the same layer, and the formation of the gate and the first-layer field plate and even the third-layer field plate are concentrated in the same step, which can simplify the manufacturing steps of the semiconductor device with a near-gate field plate, thereby simplifying the implementation cost and time of setting the field plate in the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0011] Figure 1 It is a flow chart of a method for manufacturing a semiconductor device with a near-gate field plate provided by an embodiment of the present invention; Figure 2a is a cross-sectional view of a semiconductor device with three field plates in an embodiment of the present invention; Figure 2b is a cross-sectional view of a semiconductor device during metal deposition and metal etching in an embodiment of the present invention; Figure 2c is a schematic diagram of a source electrode, a drain electrode, and a second field plate formed after metal deposition and metal etching in an embodiment of the present invention; Figure 3 is a cross-sectional view of another semiconductor device including a three-layer field plate in an embodiment of the present invention; Figure 4 is a cross-sectional view of a semiconductor device including four-layer field plates in an embodiment of the present invention; Figure 5a is a cross-sectional view of another semiconductor device including four-layer field plates in an embodiment of the present invention; Figure 5b is a cross-sectional view of another semiconductor device including four-layer field plates in an embodiment of the present invention; Figure 6 is a flow chart of another method for manufacturing a semiconductor device with a near-gate field plate provided by an embodiment of the present invention; Figure 7is a cross-sectional view of a semiconductor device with four field plates in an embodiment of the present invention; Figure 8 is a cross-sectional view of another semiconductor device with four field plates according to an embodiment of the present invention; Figure 9a is a cross-sectional view of another semiconductor device with four field plates according to an embodiment of the present invention; Figure 9b It is a cross-sectional view of another semiconductor device with four field plates in an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0014] The embodiment of the present invention provides a method for manufacturing a semiconductor device with a near-gate field plate, which can be mainly used to manufacture but not limited to the following structures of semiconductor devices with a near-gate field plate, such as MIS-HEMT devices, P-GaN HEMT devices, SBD-Gate HEMT, etc. These semiconductor devices can be made of a variety of semiconductor materials, such as gallium nitride (GaN), silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium oxide (GaO), etc. Specifically, Figure 1 As shown, the method for manufacturing a semiconductor device with a near-gate field plate in this embodiment includes: Step 101, depositing a first dielectric layer and a base dielectric layer on the epitaxial layer of the substrate, the base dielectric layer comprising a plurality of dielectric layers and at least one barrier layer sandwiched between the plurality of dielectric layers, performing dielectric etching on the first dielectric layer and the base dielectric layer to form source and drain dielectrics.

[0015] Generally speaking, in the process of manufacturing semiconductor devices, the various parts of the semiconductor device, including the source, gate, drain, field plate, etc., are set on the epitaxial layer of the substrate to obtain the semiconductor device. Among them, the epitaxial layer is a semiconductor layer grown on the substrate, which can improve the performance of the device, increase the conductivity or enhance the control of impurities; the source, gate, drain and field plate are all metal parts. By setting the field plate, the electric field between the electrodes can be optimized to make the electric field evenly distributed and improve the reliability of the semiconductor device.

[0016] When manufacturing the semiconductor device in this embodiment, it is necessary to go through a multi-layer process on the epitaxial layer of the substrate to form the final semiconductor device. First, it is necessary to deposit a first dielectric layer on the epitaxial layer of the substrate. The first dielectric layer mainly plays the role of insulation and isolation, and deposit a basic dielectric layer on the first dielectric layer. The basic dielectric layer includes multiple dielectric layers and at least one barrier layer sandwiched between the dielectric layers. Furthermore, when the semiconductor device includes a source and a drain, it is necessary to perform dielectric etching on the first dielectric layer and the basic dielectric layer to form a source and drain dielectric, so that the source and drain formed later are in the same layer.

[0017] Among them, dielectric etching is mainly a process of selectively removing unnecessary materials from the surface of the wafer (specifically the first dielectric layer and the base dielectric layer in this embodiment). This process can be achieved through a variety of methods, including physical means (such as ion milling etching) and chemical means (such as plasma etching). During the dielectric etching process, a mask is used to protect the material that needs to be retained, and the exposed material is removed.

[0018] It should be noted that in this embodiment, the source and gate in the semiconductor device are set in different layers, that is, the depths of the source and the gate are different, which can effectively prevent the short circuit between the source and the gate. In order to facilitate the layering of the source and the gate, it is necessary to set a first dielectric layer and a base dielectric layer on the epitaxial layer. When the first dielectric layer and the base dielectric layer are subjected to dielectric etching to form the source and drain dielectrics, it is necessary to etch through the first dielectric layer and the base dielectric layer to expose the epitaxial layer in the source region and the drain region; subsequently, when dielectric etching is performed to form the gate dielectric, it is not necessary to etch through the first dielectric layer, but only the base dielectric layer to expose the first dielectric layer in the gate region.

[0019] The manufacturing processes of two adjacent dielectric layers can be different, such as the dielectric layer in the first dielectric layer and the dielectric layer in the base dielectric layer, and the dielectric layer at the lower layer is denser, so that the dielectric etching speed is slower, so that when etching reaches the junction of two adjacent dielectric layers, the etching speed will slow down, and the etching depth can be well controlled. In this embodiment, at least one barrier layer in the base dielectric layer is a dielectric layer to protect the etching interface, and materials such as AlN can be used as the barrier layer.

[0020] like Figure 2a The figure shows a cross-sectional schematic diagram of a semiconductor device with a near-gate field plate, where the parts arranged on the epitaxial layer 11 of the substrate 10 include: a source 110, a gate 111, a drain 112 and a multi-layer field plate near the gate 111 (a three-layer field plate is used as an example in the figure), wherein a first-layer field plate 1131 of the multi-layer field plate is connected to the gate 111, a second-layer field plate 1132 is on the same layer as the source 110 and the drain 112, and a third-layer field plate 1133 is connected to a first-layer field plate 1131.

[0021] In this embodiment, a first dielectric layer 12 (a portion filled with oblique lines in the figure) and a base dielectric layer 13 are successively deposited on the epitaxial layer 11 of the substrate 10. The base dielectric layer 13 includes a plurality of dielectric layers 131 and 133 and at least one barrier layer 132 (a portion filled with vertical lines in the figure) sandwiched between the plurality of dielectric layers 131 and 133. In this embodiment, one barrier layer 132 is taken as an example for explanation. Then, dielectric etching is performed on the first dielectric layer 12 and the base dielectric layer 13 to form source and drain dielectrics, specifically, through holes are etched through the first dielectric layer 12 and the base dielectric layer 13 to expose the epitaxial layer 11 in the source region and the drain region.

[0022] Step 102, performing metal deposition and metal etching on the source and drain dielectrics to form the source, drain and second field plate of the semiconductor device, and retaining a reserved position for the gate and at least one first field plate between the source and the second field plate.

[0023] Specifically, for example Figure 2bAs shown, during metal deposition, a metal layer 150 can be deposited on the source and drain dielectric, and then metal etching is performed on the metal layer 150 to form a source 110 (such as an ohmic metal of the source), a drain 112 (such as an ohmic metal of the drain), and a second field plate 1132. A reserved position for the gate and at least one first field plate is reserved between the source 110 and the second field plate 1132, and positions for other multi-layer field plates (such as a third field plate 1133 and a fourth field plate 1134, etc.) are reserved between the drain 112 and the second field plate 1132. In this way, the formation of the source 110, the drain 112, and the second field plate 1132 is concentrated in the same step, which simplifies the steps of setting various parts on the epitaxial layer 11, and the source 110, the drain 112, and the second field plate 1132 are finally formed on the same layer.

[0024] When metal etching is performed, a photoresist 151 may be provided at a position where the metal needs to be retained, and then the metal layer 150 is etched, so that the metal at the position where the photoresist 151 is provided is retained, while the metal at other positions is etched away, and finally the photoresist 151 is removed to form a Figure 2c The source 110, drain 112 and second field plate 1132 are shown. The distance between the source 110 and the second field plate 1132 needs to be large enough to accommodate the gate 111 and the first field plate formed later, and the distance between the second field plate 1132 and the drain 112 also needs to be large enough to accommodate the other field plates formed later.

[0025] Step 103, depositing a second dielectric layer, and performing dielectric etching on the second dielectric layer and the base dielectric layer at the reserved position to form a gate dielectric and at least one first-layer field plate dielectric, wherein any first-layer field plate dielectric is under a corresponding barrier layer. Thus, the same number of first-layer field plate dielectrics can be formed here as the number of barrier layers included in the above-mentioned base dielectric layer.

[0026] like Figure 2aAs shown, after the source 110, the drain 112 and the second field plate 1132 are formed, the second dielectric layer 14 can be deposited, and then dielectric etching is performed at the reserved position between the source 110 and the second field plate 1131 to form a gate dielectric and at least one first field plate dielectric (a first field plate dielectric is used as an example in the figure). Specifically, when forming the first field plate dielectric, it is necessary to etch through the second dielectric layer 14 on both sides of the gate dielectric position, and etch through to a certain barrier layer in the basic dielectric layer 13, for example, etch through a dielectric layer 133 and a barrier layer 132 from top to bottom in the basic dielectric layer 13 to form the first field plate dielectric; when forming the gate dielectric, it is necessary to etch through the second dielectric layer 14 and the basic dielectric layer 13 at the gate dielectric position, and expose the first dielectric layer 12 to form the gate dielectric; wherein the first field plate dielectric and the dielectric layer 133 and the barrier layer 132 corresponding to the gate dielectric can be etched simultaneously.

[0027] In this way, a certain depth difference is formed between the gate dielectric and the first field plate dielectric, that is, the distance to the substrate 10. The material of the dielectric layers 131 and 133 is SiN, and the material of the barrier layer 132 is AlN. Since the etching methods of these two materials are different, when the barrier layer is etched, the first dielectric layer at the bottom is not affected, and when the second dielectric layer 14 is etched, the barrier layer is not affected either, thereby ensuring the flatness of the subsequent gate and the first field plate.

[0028] In this way, by providing at least one barrier layer in the basic dielectric layer 13 , the formation of the gate and the first field plate can be concentrated into one step, and at the same time a certain depth difference can be provided between the gate and the first field plate.

[0029] Step 104 , performing metal deposition and metal etching on the gate dielectric and at least one first-layer field plate dielectric to form a gate and at least one first-layer field plate of the semiconductor device.

[0030] Specifically, in this embodiment, the first field plate and the gate are connected together as a whole. Under normal circumstances, the field plate is connected to a low potential to induce an equivalent negative charge, so that the electric field lines of the positive charge in the depletion region can terminate at the equivalent negative charge in the field plate, thereby alleviating the electric field spike caused by the electric field line aggregation of the gate. The first field plate and the gate are regarded as a whole, so that the electric field lines emitted by the positive charge in the depletion region can smoothly transition from the gate corner to the first field plate.

[0031] It should be noted that the method in steps 101 to 104 is mainly a method for setting two layers of field plates in a semiconductor device. In other embodiments, multiple layers of field plates may be set in the semiconductor device, such as a third layer of field plates, a fourth layer of field plates, etc. Specifically: (1) When forming the third field plate: When metal deposition and metal etching are performed on the gate dielectric and the first field plate dielectric, a third field plate can also be formed, the third field plate is above the second field plate, and the projections of the third field plate and the second field plate in the substrate direction have an overlapping area, wherein the first field plate and the third field plate are connected, or the first field plate and the third field plate are disconnected.

[0032] For example Figure 2a As shown, metal deposition and metal etching are performed on the gate dielectric and the first field plate dielectric to simultaneously form the gate 111, the first field plate 1131 and the third field plate 1133, and the first field plate 1131 is connected to the third field plate 1133. In other embodiments, as Figure 3 As shown, the first field plate 1131 and the third field plate 1133 can be disconnected, so that the independent third field plate 1133 can be more flexibly connected to the source 110 or the gate 111 through a subsequent metal interconnection process. The projections of the third field plate 1133 and the second field plate 1132 in the direction of the substrate 10 have an overlapping area.

[0033] (2) When forming the fourth field plate: A third dielectric layer is deposited, and metal deposition and metal etching are performed on the third dielectric layer to form a fourth field plate. The fourth field plate is above the third field plate, and the projections of the fourth field plate and the third field plate in the substrate direction have an overlapping area.

[0034] For example Figure 4 As shown, after forming the third field plate 1133, a third dielectric layer 15 can be deposited, and metal deposition and metal etching can be performed on the third dielectric layer 15 to form a fourth field plate 1134, and the projections of the fourth field plate 1134 and the third field plate 1133 in the direction of the substrate 10 have an overlapping area.

[0035] It can be seen that in the embodiment of the present invention, in the process of manufacturing a semiconductor device with a near-gate field plate, the formation of the second-layer field plate in the semiconductor device and the source and drain are concentrated in the same step, so that the formed source, drain and second-layer field plate are on the same layer, and the formation of the gate and the first-layer field plate and even the third-layer field plate are concentrated in the same step, which can simplify the manufacturing steps of the semiconductor device with a near-gate field plate, thereby simplifying the implementation cost and time of setting the field plate in the semiconductor device.

[0036] It should also be noted that the above Figure 2a , Figure 3 and Figure 4The semiconductor device described in the above mainly includes a barrier layer 132 in the base dielectric layer 13 deposited on the basis of the first dielectric layer 12 during the process of manufacturing the semiconductor device. In other specific embodiments, the base dielectric layer 13 may include multiple barrier layers. Here, two barrier layers are taken as an example for explanation. Specifically: When performing the above step 101, the basic dielectric layer deposited on the first dielectric layer includes three dielectric layers and two barrier layers sandwiched between the three dielectric layers.

[0037] For example Figure 5a As shown, in this embodiment, a first dielectric layer 12 (the portion filled with oblique lines in the figure) and a base dielectric layer 13 are successively deposited on the epitaxial layer 11 of the substrate 10. The base dielectric layer 13 includes three dielectric layers 131, 133, and 135, a barrier layer 132 sandwiched between the dielectric layers 131 and 133, and a barrier layer 134 (the portion filled with vertical lines in the figure) sandwiched between the dielectric layers 133 and 135.

[0038] Furthermore, when performing the above step 102, when forming the source and the second field plate of the semiconductor device, it is necessary to reserve positions for the gate and the two first field plates between the source and the second field plate.

[0039] Specifically, for example Figure 5a As shown, during metal deposition, a metal layer can be deposited on the source dielectric, and then metal etching is performed on the metal layer to form the source 110, the drain 112, and the second field plate 1132. The reserved positions of the gate and the two first field plates are reserved between the source 110 and the second field plate 1132, and the positions of other multi-layer field plates (such as the third field plate 1133 and the fourth field plate 1134, etc.) are reserved between the drain 112 and the second field plate 1132. In this way, the formation of the source 110, the drain 112, and the second field plate 1132 is concentrated in the same step, which simplifies the steps of setting various parts on the epitaxial layer 11, and the source 110, the drain 112, and the second field plate 1132 are finally formed on the same layer.

[0040] Furthermore, when the above step 103 is performed, a gate dielectric, an upper first layer field plate dielectric and a lower first layer field plate dielectric are formed.

[0041] For example Figure 5aAs shown, after the source 110, the drain 112 and the second field plate 1132 are formed, the second dielectric layer 14 can be deposited, and then dielectric etching is performed at the reserved position between the source 110 and the second field plate 1132 to form a gate dielectric, an upper first field plate dielectric and a lower first field plate dielectric. Specifically, when forming the upper first field plate dielectric, it is necessary to etch through the second dielectric layer 14 on both sides of the lower first field plate dielectric position and etch through to below the barrier layer 134 in the base dielectric layer 13, that is, etch through the base dielectric layer 13 from top to bottom. The dielectric layer 135 and the barrier layer 134 form the upper first layer of field plate dielectric. When forming the lower first layer of field plate dielectric, it is necessary to etch through the second dielectric layer 14 on both sides of the gate dielectric position and to below the barrier layer 132 in the base dielectric layer 13, that is, to etch through the dielectric layers 135, 133 and the barrier layers 134 and 132 from top to bottom in the base dielectric layer 13 to form the lower first layer of field plate dielectric. When forming the gate dielectric, it is necessary to etch through the second dielectric layer 14 and the base dielectric layer 13 at the gate dielectric position and expose the first dielectric layer 12 to form the gate dielectric.

[0042] The second dielectric layer 14 , dielectric layer 135 and barrier layer 134 corresponding to the upper first field plate dielectric layer, the lower first field plate dielectric layer and the gate dielectric layer can be etched simultaneously; the dielectric layer 133 and barrier layer 132 corresponding to the lower first field plate dielectric layer and the gate dielectric layer can be etched simultaneously.

[0043] In this way, a certain depth difference is formed among the gate dielectric, the upper first layer field plate dielectric and the lower first layer field plate dielectric.

[0044] Finally, when the above step 104 is performed, a gate and two first-layer field plates of the semiconductor device are formed.

[0045] Furthermore, when metal deposition and metal etching are performed on the second dielectric layer 14, a third field plate can also be formed, the third field plate is above the second field plate, and the projections of the third field plate and the second field plate in the substrate direction have an overlapping area, wherein the first field plate and the third field plate are connected, or the first field plate and the third field plate are disconnected.

[0046] For example Figure 5a As shown, metal deposition and metal etching are performed on the gate dielectric, the upper first-layer field plate dielectric, the lower first-layer field plate dielectric and the second dielectric layer, and the gate 111, two first-layer field plates 1131 and the third-layer field plate 1133 can be formed at the same time, and a first-layer field plate 1131 is connected to the third-layer field plate 1133. In other embodiments, such as Figure 5bAs shown, a first field plate 1131 and a third field plate 1133 may be disconnected, so that the independent third field plate 1133 may be more flexibly connected to the source 110 or the gate 111 through a subsequent metal interconnection process.

[0047] An embodiment of the present invention provides another method for manufacturing a semiconductor device with a near-gate field plate, which can be mainly used to manufacture but not limited to semiconductor devices with the following structures, such as MIS-HEMT devices, P-GaN HEMT devices, SBD-GateHEMT, etc. These semiconductor devices can be made of a variety of semiconductor materials, such as Si, SiC, GaAs, GaO and other semiconductor materials. The method for manufacturing a semiconductor device with a near-gate field plate in this embodiment is similar to the above method. Figure 1 The manufacturing method shown is similar, except that, in this embodiment, when manufacturing the semiconductor device, after forming the source and the second field plate and before forming the gate, a third field plate needs to be formed.

[0048] Specifically, Figure 6 As shown, the method for manufacturing the semiconductor device of this embodiment includes: Step 201, depositing a first dielectric layer and a base dielectric layer on the epitaxial layer of the substrate, wherein the base dielectric layer includes a plurality of dielectric layers and at least one barrier layer sandwiched between the plurality of dielectric layers, and performing dielectric etching on the first dielectric layer and the base dielectric layer to form source and drain dielectrics.

[0049] Generally, in the process of manufacturing semiconductor devices, various parts of the semiconductor device, including a source, a gate, a drain, a field plate, etc., are arranged mainly on the epitaxial layer of the substrate to obtain the semiconductor device.

[0050] When manufacturing the semiconductor device in the present embodiment, first, it is necessary to deposit a first dielectric layer and a base dielectric layer on the epitaxial layer of the substrate. Furthermore, when the semiconductor device includes a source and a drain, it is necessary to perform dielectric etching on the first dielectric layer and the base dielectric layer to form source and drain dielectrics, so that the source and drain formed later are in the same layer.

[0051] like Figure 7 The figure shows a cross-sectional schematic diagram of a semiconductor device with a near-gate field plate, where the parts arranged on the epitaxial layer 21 of the substrate 20 include: a source 210, a gate 211, a drain 212 and a multi-layer field plate near the gate 211 (a three-layer field plate is used as an example in the figure), wherein at least one first-layer field plate 2131 of the multi-layer field plate is connected to the gate 211, the second-layer field plate 2132 and the third-layer field plate 2133 are on the same layer as the source 210 and the drain 212, and the fourth-layer field plate 2134 is connected to the first-layer field plate 2131.

[0052] In this embodiment, a first dielectric layer 22 (a portion filled with oblique lines in the figure) and a base dielectric layer 23 are successively deposited on the epitaxial layer 21 of the substrate 20. The base dielectric layer 23 includes a plurality of dielectric layers 231, 233 and at least one barrier layer 232 (a portion filled with vertical lines in the figure) sandwiched between the plurality of dielectric layers 231 and 233. In this embodiment, one barrier layer 232 is used as an example for explanation. Then, dielectric etching is performed on the first dielectric layer 22 and the base dielectric layer 23 to form source and drain dielectrics, specifically, through holes that penetrate the first dielectric layer 22 and the base dielectric layer 23 and expose the epitaxial layer 21 in the source region and the drain region.

[0053] Step 202, performing metal deposition and metal etching on the source and drain dielectrics to form the source, drain and second field plate of the semiconductor device, and retaining a reserved position for the gate and at least one first field plate between the source and the second field plate.

[0054] Specifically, for example Figure 7 As shown, during metal deposition, a metal layer can be deposited on the source and drain dielectric, and then metal etching is performed on the metal layer. Specifically, a photoresist can be set at the position where the metal needs to be retained, and then the metal layer is etched, so that the metal at the position where the photoresist is set is retained, and the metal at other positions is etched away, and finally the photoresist is removed to form a source 210 (such as an ohmic metal of the source, etc.), a drain 212 (such as an ohmic metal of the drain, etc.) and a second field plate 2132. A reserved position for the gate and at least one first field plate is retained between the source 210 and the second field plate 2132, and the positions of other multi-layer field plates (such as a third field plate 2133 and a fourth field plate 2134, etc.) are retained between the drain 212 and the second field plate 2132.

[0055] In this way, the formation of the source 210, the drain 212 and the second field plate 2132 is concentrated in the same step, which simplifies the steps of setting each part on the epitaxial layer 21, and the source 210, the drain 212 and the second field plate 2132 are finally formed on the same layer.

[0056] Step 203, depositing a second dielectric layer, performing metal deposition and metal etching on the second dielectric layer to form a third field plate, wherein the third field plate is above the second field plate, and the projections of the third field plate and the second field plate in the substrate direction have an overlapping area.

[0057] like Figure 7As shown, after the source 210, the drain 212 and the second field plate 2132 are formed, the second dielectric layer 24 can be deposited, and then metal deposition and metal etching are performed on the second dielectric layer 24 to form a third field plate 2133. The third field plate 2133 needs to be above the second field plate 2133, and the projections of the third field plate 2133 and the second field plate 2132 in the direction of the substrate 20 have an overlapping area.

[0058] Step 204, depositing a third dielectric layer, and performing dielectric etching on the second dielectric layer and the base dielectric layer at the reserved position to form a gate dielectric and at least one first-layer field plate dielectric, wherein any first-layer field plate dielectric is under a corresponding barrier layer. Thus, the same number of first-layer field plate dielectrics can be formed here as the number of barrier layers included in the above-mentioned base dielectric layer.

[0059] like Figure 7 As shown, after forming the third field plate 2133, the third dielectric layer 25 can be deposited, and then dielectric etching is performed at the reserved position between the source 210 and the second field plate 2132. When forming the first field plate dielectric, it is necessary to etch through the third dielectric layer 25 and the second dielectric layer 24 on both sides of the gate dielectric position, and etch through to a certain barrier layer in the base dielectric layer 23, such as etching through a dielectric layer 233 and a barrier layer 232 from top to bottom in the base dielectric layer 23 to form a first field plate dielectric; when forming the gate dielectric, it is necessary to etch through the third dielectric layer 25, the second dielectric layer 24 and the base dielectric layer 23 at the gate dielectric position, and expose the first dielectric layer 22 to form the gate dielectric. The first field plate dielectric and the dielectric layer 233 and the barrier layer 232 corresponding to the gate dielectric can be etched at the same time. In this way, a certain depth difference is formed between the gate dielectric and the first field plate dielectric.

[0060] Step 205 , performing metal deposition and metal etching on the gate dielectric and at least one first-layer field plate dielectric to form a gate and at least one first-layer field plate of the semiconductor device.

[0061] It should be noted that the method in the above steps 201 to 205 is mainly a method for setting a three-layer field plate in a semiconductor device. In other embodiments, a fourth layer of field plates may also be set in the semiconductor device. Specifically, when forming the fourth layer of field plates: Metal deposition and metal etching are performed on the gate dielectric and at least one first-layer field plate dielectric, and a fourth-layer field plate is formed. The fourth-layer field plate is above the third-layer field plate, and the projections of the fourth-layer field plate and the third-layer field plate in the substrate direction have an overlapping area, wherein a first-layer field plate is connected to the fourth-layer field plate, or a first-layer field plate is disconnected from the fourth-layer field plate.

[0062] For example Figure 7As shown, metal deposition and metal etching are performed on the gate dielectric and the first field plate dielectric to simultaneously form the gate 211, the first field plate 2131 and the fourth field plate 2134, and the first field plate 2131 is connected to the fourth field plate 2134. In other embodiments, as Figure 8 As shown, the first field plate 2131 and the fourth field plate 2134 can be disconnected, so that the fourth field plate 2134 can be more flexibly connected to the source 210 or the gate 211 through a subsequent metal interconnection process. The projections of the fourth field plate 2134 and the third field plate 2133 in the direction of the substrate 20 have an overlapping area.

[0063] It can be seen that in the embodiment of the present invention, in the process of manufacturing a semiconductor device with a near-gate field plate, the formation of the second layer of field plates and the source in the semiconductor device are concentrated in the same step, so that the formed source and the second layer of field plates are on the same layer, and the formation of the gate and the first layer of field plates and even the fourth layer of field plates are concentrated in the same step, and the third layer of field plates is formed before forming the gate. This can simplify the manufacturing steps of the semiconductor device with a near-gate field plate, thereby simplifying the implementation cost and time of setting the field plate in the semiconductor device.

[0064] The method for manufacturing a semiconductor device in this embodiment is similar to the above Figure 1 Compared with the method for manufacturing a semiconductor device shown in the above Figure 1 When manufacturing semiconductor devices according to the method shown, since only the first field plate and the second field plate are formed before the gate dielectric is formed, when dielectric etching is performed to form the gate dielectric, the dielectric etching depth required is relatively low, and the dielectric only needs to be etched to penetrate the second dielectric layer 14 and the base dielectric layer 13, and expose the first dielectric layer 22. This can reduce the dielectric etching time and better control the gate morphology, and is generally suitable for chip designs with smaller circuit board sizes.

[0065] It should also be noted that the above Figure 7 and Figure 8 The semiconductor device described in the above mainly includes a barrier layer 232 in the base dielectric layer 23 deposited on the basis of the first dielectric layer 22 during the manufacturing process of the semiconductor device. In other specific embodiments, the base dielectric layer 23 may include multiple barrier layers. Here, two barrier layers are taken as an example for explanation. Specifically: When performing the above step 201, the basic dielectric layer deposited on the first dielectric layer includes three dielectric layers and two barrier layers sandwiched between the three dielectric layers.

[0066] For example Figure 9aAs shown, in this embodiment, a first dielectric layer 22 (the portion filled with oblique lines in the figure) and a base dielectric layer 23 are successively deposited on the epitaxial layer 21 of the substrate 20. The base dielectric layer 23 includes three dielectric layers 231, 233, and 235, a barrier layer 232 sandwiched between the dielectric layers 231 and 233, and a barrier layer 234 (the portion filled with vertical lines in the figure) sandwiched between the dielectric layers 233 and 235.

[0067] Furthermore, when performing the above step 202, when forming the source and the second field plate of the semiconductor device, it is necessary to reserve positions for the gate and the two first field plates between the source and the second field plate.

[0068] Specifically, for example Figure 9a As shown, during metal deposition, a metal layer can be deposited on the source dielectric, and then metal etching is performed on the metal layer to form the source 210, the drain 212, and the second field plate 2132. The reserved positions of the gate and the two first field plates are reserved between the source 210 and the second field plate 2132, and the positions of other multi-layer field plates (such as the third field plate 2133 and the fourth field plate 2134, etc.) are reserved between the drain 212 and the second field plate 2132. In this way, the formation of the source 210, the drain 212, and the second field plate 2132 is concentrated in the same step, which simplifies the steps of setting various parts on the epitaxial layer 21, and the source 210, the drain 212, and the second field plate 2132 are finally formed on the same layer.

[0069] Furthermore, when the above step 204 is performed, a gate dielectric, an upper first layer of field plate dielectric, and a lower first layer of field plate dielectric are formed.

[0070] For example Figure 9aAs shown, after the source 210, the drain 212 and the second field plate 2132 are formed, and the third field plate 2133 is formed, the third dielectric layer 25 can be deposited, and then dielectric etching is performed at the reserved position between the source 210 and the second field plate 2132 to form a gate dielectric and two first field plate dielectrics. Specifically, when forming the upper first field plate dielectric, it is necessary to etch through the third dielectric layer 25, the second dielectric layer 24 and the barrier layer 234 in the base dielectric layer 23 on both sides of the lower first field plate dielectric position, that is, to etch through the dielectric from top to bottom in the base dielectric layer 23. The first layer of field plate dielectric is formed by cutting through the third dielectric layer 25, the second dielectric layer 24 and the barrier layer 232 on both sides of the gate dielectric position, that is, cutting through the dielectric layers 235, 233 and the barrier layers 234 and 232 from top to bottom in the base dielectric layer 23 to form the first layer of field plate dielectric. When forming the gate dielectric, the third dielectric layer 25, the second dielectric layer 24 and the base dielectric layer 23 are cut through at the gate dielectric position, and the first dielectric layer 22 is exposed to form the gate dielectric.

[0071] The third dielectric layer 25, the second dielectric layer 24, the dielectric layer 235 and the barrier layer 234 corresponding to the upper first layer of field plate dielectric, the lower first layer of field plate dielectric and the gate dielectric can be etched simultaneously; the dielectric layer 233 and the barrier layer 232 corresponding to the lower first layer of field plate dielectric and the gate dielectric can be etched simultaneously.

[0072] In this way, a certain depth difference is formed between the gate dielectric, the lower first layer field plate dielectric and the upper first layer field plate dielectric.

[0073] Finally, when the above step 205 is performed, a gate and two first-layer field plates of the semiconductor device are formed.

[0074] Furthermore, when metal deposition and metal etching are performed on the third dielectric layer 25, a fourth field plate can also be formed, the fourth field plate is above the third field plate, and the projections of the fourth field plate and the third field plate in the substrate direction have an overlapping area, wherein the first field plate is connected to the fourth field plate, or the first field plate is disconnected from the fourth field plate.

[0075] For example Figure 9a As shown, metal deposition and metal etching are performed on the gate dielectric, the upper first-layer field plate dielectric, the lower first-layer field plate dielectric and the third dielectric layer, and the gate 211, two first-layer field plates 2131 and the fourth-layer field plate 2134 can be formed at the same time, and one first-layer field plate 2131 is connected to the fourth-layer field plate 1134. In other embodiments, such as Figure 9bAs shown, a first field plate 2131 and a fourth field plate 2134 can be disconnected, so that the independent fourth field plate 2134 can be more flexibly connected to the source 210 or the gate 211 through a subsequent metal interconnection process.

[0076] An embodiment of the present invention further provides a semiconductor device with a near-gate field plate. The semiconductor device is a semiconductor device manufactured according to any method for manufacturing a semiconductor device with a near-gate field plate described in the above embodiments.

[0077] The above is a detailed introduction to a method for manufacturing a semiconductor device with a near-gate field plate and a semiconductor device provided in an embodiment of the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for manufacturing a semiconductor device having a near-gate field plate, characterized in that: include: Depositing a first dielectric layer and a base dielectric layer on the epitaxial layer of the substrate, wherein the base dielectric layer includes a plurality of dielectric layers and at least one barrier layer sandwiched between the plurality of dielectric layers, and performing dielectric etching on the first dielectric layer and the base dielectric layer to form source and drain dielectrics; Performing metal deposition and metal etching on the source and drain dielectrics to form a source, a drain and a second field plate of the semiconductor device, and reserving a gate and at least one first field plate between the source and the second field plate; Depositing a second dielectric layer, and performing dielectric etching on the second dielectric layer and the base dielectric layer at the reserved position to form a gate dielectric and at least one first-layer field plate dielectric, wherein any first-layer field plate dielectric is under a corresponding barrier layer; Metal deposition and metal etching are performed on the gate dielectric and at least one first-layer field plate dielectric to form a gate and at least one first-layer field plate of the semiconductor device.

2. The method according to claim 1, characterized in that If the base dielectric layer includes two dielectric layers and a barrier layer sandwiched between the two dielectric layers, the forming of the gate dielectric and at least one first layer of field plate dielectric specifically includes: Carving through the second dielectric layer on both sides of the gate dielectric position, and carving through a dielectric layer and a barrier layer from top to bottom in the base dielectric layer to form the first layer of field plate dielectric; The second dielectric layer and the base dielectric layer are cut through at the gate dielectric position to expose the first dielectric layer, so as to form the gate dielectric.

3. The method according to claim 1, characterized in that If the base dielectric layer includes three dielectric layers and two barrier layers sandwiched between the three dielectric layers, the forming of the gate dielectric and at least one first layer of field plate dielectric specifically includes: Carving through the second dielectric layer and a dielectric layer and a barrier layer from top to bottom in the base dielectric layer on both sides of the lower first dielectric layer to form an upper first dielectric layer; Carving through the second dielectric layer on both sides of the gate dielectric position, and carving through the two dielectric layers and two barrier layers from top to bottom in the base dielectric layer to form a lower first layer of field plate dielectric; The second dielectric layer and the base dielectric layer are cut through at the gate dielectric position to expose the first dielectric layer, so as to form the gate dielectric.

4. The method according to any one of claims 1 to 3, characterized in that When metal deposition and metal etching are performed on the gate dielectric and at least one first layer field plate dielectric, the process further includes: forming a third field plate; the third field plate is above the second field plate, and the projections of the third field plate and the second field plate in the direction of the substrate have an overlapping area; The first field plate is connected to the third field plate, or the first field plate is disconnected from the third field plate.

5. The method according to claim 4, characterized in that The method further comprises: A third dielectric layer is deposited, and metal deposition and metal etching are performed on the third dielectric layer to form a fourth field plate, wherein the fourth field plate is above the third field plate, and the projections of the fourth field plate and the third field plate in the direction of the substrate have an overlapping area.

6. A method for manufacturing a semiconductor device having a near-gate field plate, characterized in that: include: Depositing a first dielectric layer and a base dielectric layer on the epitaxial layer of the substrate, wherein the base dielectric layer includes a plurality of dielectric layers and at least one barrier layer sandwiched between the plurality of dielectric layers, and performing dielectric etching on the first dielectric layer and the base dielectric layer to form source and drain dielectrics; Performing metal deposition and metal etching on the source and drain dielectrics to form a source, a drain and a second field plate of the semiconductor device, and reserving a gate and at least one first field plate between the source and the second field plate; Depositing a second dielectric layer, performing metal deposition and metal etching on the second dielectric layer to form a third field plate, wherein the third field plate is above the second field plate, and the projections of the third field plate and the second field plate in the direction of the substrate have an overlapping area; Depositing a third dielectric layer, and performing dielectric etching on the second dielectric layer and the base dielectric layer at the reserved position to form a gate dielectric and at least one first-layer field plate dielectric, wherein any first-layer field plate dielectric is under a corresponding barrier layer; Metal deposition and metal etching are performed on the gate dielectric and at least one first-layer field plate dielectric to form a gate and at least one first-layer field plate of the semiconductor device.

7. The method according to claim 6, characterized in that If the base dielectric layer includes two dielectric layers and a barrier layer sandwiched between the two dielectric layers, the forming of the gate dielectric and at least one first layer of field plate dielectric specifically includes: Carving through the third dielectric layer and the second dielectric layer on both sides of the gate dielectric position, and carving through a dielectric layer and a barrier layer from top to bottom in the base dielectric layer to form the first field plate dielectric; The third dielectric layer, the second dielectric layer and the base dielectric layer are cut through at the gate dielectric position to expose the first dielectric layer, so as to form the gate dielectric.

8. The method according to claim 6, characterized in that If the base dielectric layer includes three dielectric layers and two barrier layers sandwiched between the three dielectric layers, the forming of the gate dielectric and at least one first layer of field plate dielectric specifically includes: Carving through the third dielectric layer, the second dielectric layer and one dielectric layer and a barrier layer from top to bottom in the base dielectric layer on both sides of the lower first dielectric layer to form an upper first dielectric layer; Carving through the third dielectric layer and the second dielectric layer on both sides of the gate dielectric position, and carving through the two dielectric layers and two barrier layers from top to bottom in the base dielectric layer to form a lower first layer of field plate dielectric; The third dielectric layer, the second dielectric layer and the base dielectric layer are cut through at the gate dielectric position to expose the first dielectric layer, so as to form the gate dielectric.

9. The method according to any one of claims 6 to 8, characterized in that When metal deposition and metal etching are performed on the gate dielectric and at least one first layer field plate dielectric, the process further includes: forming a fourth field plate; the fourth field plate is above the third field plate, and projections of the fourth field plate and the third field plate in the direction of the substrate have an overlapping area; The first field plate is connected to the fourth field plate, or the first field plate is disconnected from the fourth field plate.

10. A semiconductor device having a near-gate field plate, characterized in that: The semiconductor device is a semiconductor device manufactured by the method for manufacturing a semiconductor device with a near-gate field plate according to any one of claims 1 to 9.

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