Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a first fin and a gate electrode. The first fin extends in a first direction. The gate electrode has sidewalls extending in a second direction different from the first direction. A sidewall of the gate electrode defines an indentation adjacent to the first fin in a plan view.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Technological evolution of integrated circuit (IC) materials and design has resulted in smaller, more complex circuits with each generation. During this IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down provides the benefits of increased production efficiency and reduced associated costs.

[0003] The aforementioned scaling down further increases the complexity of IC manufacturing, and therefore, corresponding developments in IC manufacturing are needed to fully realize these advances. Summary of the invention

[0004] According to one aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a first fin extending along a first direction; and a gate electrode having a sidewall extending along a second direction different from the first direction, wherein the sidewall of the gate electrode defines a recess adjacent to the first fin in a top view.

[0005] According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a first fin group, comprising a first fin and a second fin adjacent to the first fin, each of the first fin and the second fin extending along a first direction, wherein the first fin is a peripheral fin of the first fin group; and a gate electrode extending along a second direction and crossing over at least the first fin and the second fin of the first fin group, wherein the gate electrode has a first narrow portion adjacent to the first fin.

[0006] According to another aspect of an embodiment of the present application, a method for manufacturing a semiconductor device is provided, comprising: forming a fin group on a substrate, wherein the fin group includes a first fin and a second fin adjacent to the first fin, and the first fin is a peripheral fin of the fin group; forming a semiconductor material layer above the fin group; and patterning the semiconductor material layer to form a dummy gate electrode, wherein the dummy gate electrode has a narrow portion adjacent to the first fin and a wide portion adjacent to the second fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A , Figure 1B , Figure 2A , Figure 2B , Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A and Fig. 9B Various stages of semiconductor device fabrication according to some embodiments of the present disclosure are shown.

[0009] Fig.10 is a top view of a semiconductor device according to some embodiments of the present disclosure.

[0010] Fig.11 is a top view of a semiconductor device according to some embodiments of the present disclosure.

[0011] Fig.12 is a top view of a semiconductor device according to some embodiments of the present disclosure.

[0012] Fig.13 is a flow chart of a method for manufacturing a semiconductor device according to various aspects of the present disclosure. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0015] As used herein, although terms such as "first," "second," and "third" describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, or parts should not be limited by these terms. These terms can only be used to distinguish one element, component, region, layer, or part from another. Unless the context clearly indicates, the terms "first," "second," and "third" as used herein do not imply a sequence or order.

[0016] Although the numerical ranges and parameters describing the wide range of the present disclosure are approximate values, the numerical values ​​described in the specific examples are reported as accurately as possible. However, any numerical value inherently contains certain errors, which are necessarily caused by the standard deviation found in the corresponding test measurement. In addition, as used herein, the terms "substantially", "roughly" and "about" generally mean within the value or range that can be considered by a person of ordinary skill in the art. Alternatively, the terms "substantially", "roughly" and "about" mean that when a person of ordinary skill in the art considers, within the acceptable standard error range of the mean value. It can be understood by a person of ordinary skill in the art that the acceptable standard error may vary depending on different technologies. Except in the operation / working examples, or unless otherwise expressly provided, all numerical ranges, amounts, values ​​and percentages disclosed herein, such as material amount, duration, temperature, operating conditions, amount ratios, etc., should be understood as modified by "substantially", "roughly" and "about" in all cases. Therefore, unless otherwise stated, the numerical parameters proposed in the present disclosure and the scope of the present application are approximate values ​​that can be changed as needed. At least, each numerical parameter should be interpreted at least according to the number of reported significant figures and by applying ordinary rounding techniques. The term is intended to encompass numbers within a reasonable range of the number (e.g., within + / - 10% of the number), or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range of 4.5 nm to 5.5 nm. Ranges may be expressed herein as from one endpoint to another or between two endpoints. Unless otherwise indicated, all ranges disclosed herein include endpoints.

[0017] The present invention relates to semiconductor devices and manufacturing methods. More specifically, the present disclosure relates to a semiconductor device with a modified pseudo gate electrode profile that prevents electrical short circuits between source / drain (S / D) components and gate electrodes. Typically, the pseudo gate electrode may have a bamboo structure, which is a protruding portion of the pseudo gate electrode protruding from a fin. At the stage of removing the pseudo gate electrode, the bamboo structure may cause over-etching, and then expose and / or etch the S / D components, which results in an electrical short circuit between the S / D components and the subsequently formed gate electrode. Due to the load effect, over-etching of the pseudo gate electrode is prone to occur at the outer fin. The present disclosure provides a method for modifying the profile of a pseudo gate electrode to avoid the above-mentioned problems, and this modified pseudo gate electrode profile can be inherited by the gate electrode.

[0018] According to various exemplary embodiments, transistors formed using a replacement gate (or "gate last") process and methods of forming the same are provided. According to some embodiments, intermediate stages of forming a transistor are shown. Some variations of some embodiments are discussed. In the exemplary embodiments shown, the formation of a fin field effect transistor (FinFET) is used as an example to explain the concepts of the present disclosure. Full-all-around (GAA) transistors or planar transistors may also employ embodiments of the present disclosure.

[0019] Figures 1A to 9A and Figures 1B to 9B 1 shows various stages of manufacturing a semiconductor device 10a according to some embodiments of the present disclosure, wherein Figures 1A to 9A They are perspective drawings, Figures 1B to 9B They are Figures 1A to 9A It should be noted that some features have been omitted from the top view for the sake of brevity.

[0020] Reference Figure 1A and Figure 1B , providing a substrate 110. In some embodiments, the substrate 110 is a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor on insulator (SOI) substrate, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 110 may be a semiconductor wafer, such as a silicon wafer. Typically, an SOI substrate includes a layer of semiconductor material (e.g., silicon) formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 110 may include: silicon; germanium; compound semiconductors, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) and / or indium antimonide (InSb); alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof, or made of the above materials.

[0021] According to the design requirements, the substrate 110 may be a p-type substrate, an n-type substrate, or a combination thereof, and may have a doped region therein. The substrate 110 may be configured for an NMOS device, a PMOS device, an n-type FinFET device, a p-type FinFET device, other types of devices (e.g., a multi-gate transistor, a full-ring gate transistor, or a nanowire transistor), or a combination thereof. In some embodiments, the substrate 110 for an NMOS device or an n-type FinFET device may include Si, SiP, SiC, SiPC, InP, GaAs, AlAs, InAs, InAlAs, InGaAs, or a combination thereof. The substrate 110 for a PMOS device or a p-type FinFET device may include Si, SiGe, SiGeB, Ge, InSb, GaSb, InGaSb, or a combination thereof.

[0022] The semiconductor device 10a includes fins 112-1, 112-2, and 112-3. Each of the fins 112-1, 112-2, and 112-3 protrudes from the upper surface (not annotated) of the substrate 110. Each of the fins 112-1, 112-2, and 112-3 extends along the Y direction. In some embodiments, the fins 112-1, 112-2, and 112-3 are part of the substrate 110, so the material of the fins 112-1, 112-2, and 112-3 is the same as the material of the substrate 110. According to an alternative embodiment, the fins 112-1, 112-2, and 112-3 are replacement strips formed by etching a portion of the substrate 110 to form a recess and performing an epitaxial technique to regenerate another semiconductor material in the recess. Therefore, the fins 112-1, 112-2, and 112-3 are formed of a semiconductor material different from the substrate 110. For example, the fins 112 - 1 , 112 - 2 , and 112 - 3 include Si, SiP, SiC, SiPC, SiGe, SiGeB, Ge, or a III-V compound semiconductor such as InP, GaAs, AlAs, InAs, InAlAs, InGaAs, etc., or are made of the above materials.

[0023] Fins 112-1, 112-2, and 112-3 may be patterned by any suitable method. For example, fins 112-1, 112-2, and 112-3 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing for the creation of patterns having, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels may be used to pattern the fins.

[0024] In some embodiments, fins 112-1, 112-2, and 112-3 define or constitute a fin group, each of fins 112-1 and 112-3 is a peripheral fin (or outermost fin) of the fin group, and fin 112-2 is an inner fin in the fin group. As used herein, the term "fin group" refers to a plurality of fins arranged at a relatively small distance (or pitch), wherein the distance between adjacent fins within the same fin group is much smaller than the distance between adjacent fins belonging to different fin groups, which will be described later. Although Figure 1A and Figure 1B The fin group of the semiconductor device 10a is shown to include three fins, but it should be noted that in other embodiments, the fin group may include more fins. That is, the fin group may include two peripheral fins and a plurality of internal fins therebetween.

[0025] The semiconductor device 10a includes an isolation region 116. The isolation region 116 includes a shallow trench isolation (STI) region, which can be formed to extend from the upper surface of the substrate 110. In some embodiments, the isolation region 116 includes a pad oxide (not shown), which can be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 110. The pad oxide can also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), or other suitable techniques. The isolation region 116 can also include a dielectric material above the pad oxide, wherein the dielectric material can be formed using flowable chemical vapor deposition (FCVD), spin coating, etc. In some embodiments, a dielectric material is deposited to fill the recesses between the fins (e.g., fins 112-1, 112-2, and 112-3), and an etching technique is performed to remove a portion of the dielectric material so that the dielectric material is recessed from the top of the fin, thereby forming the isolation region 116. The etching technique can be performed using a dry etching process, wherein HF3 and NH3 are used as etching gases. According to an alternative embodiment of the present disclosure, a wet etching process is used to perform the recessing of the isolation region 116. The etching chemistry may include, for example, an HF solution.

[0026] Reference Figure 2A and Figure 2B, forming a dielectric layer 120', a semiconductor material layer 122' and a mask layer 124 to cover the fins 112-1, 112-2 and 112-3 and the isolation region 116. The dielectric layer 120' is configured to form a dummy gate dielectric in a subsequent stage. The dielectric layer 120' includes one or more suitable dielectric materials, such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), low-k dielectrics (such as carbon-doped oxides), ultra-low-k dielectrics (such as porous carbon-doped silicon dioxide), polymers (such as polyimide), etc. or combinations thereof. In other embodiments, the dielectric layer 120' includes a dielectric material having a high dielectric constant (k value), for example greater than 3.9. The material may include metal oxides such as HfO2, HfZrO x 、HfSiO x 、HfTiO x 、HfAlO x , TiN, etc., or a combination thereof. The dielectric layer 120' is formed by thermal oxidation, CVD, ALD or other suitable techniques.

[0027] A semiconductor material layer 122' is formed on the dielectric layer 120'. The semiconductor material layer 122' is configured to define a dummy gate electrode in a subsequent stage. In some embodiments, the semiconductor material layer 122' includes polysilicon or other suitable materials. In some embodiments, the semiconductor material layer 122' is formed by CVD, PVD or other suitable techniques.

[0028] The mask layer 124 is formed on the semiconductor material layer 122'. In some embodiments, the mask layer 124 includes silicon nitride, silicon oxide, silicon carbonitride or a multi-layer thereof.

[0029] Reference Figure 3A and Figure 3B, a photosensitive material (or photoresist) 126 is formed on the mask layer 124. In some embodiments, the photosensitive material 126 includes a positive or negative photoresist. According to some embodiments, the photoresist includes a polymer material, a photosensitive composition, and a solution. The dotted area 126r of the photosensitive material 126 represents an area defined in the photomask and developed or not developed based on the type of the photosensitive material 126. The photosensitive material or feature below the dotted area 126r is retained after development. In addition, after performing an etching technique to transfer the photoresist pattern to the mask layer 124, the mask layer 124 in the dotted area 126r is retained. In some embodiments, the edge of the dotted area 126r has a substantially straight line above the fin 112-2. In some embodiments, the edge of the dotted area 126r has a curved profile 126c that is recessed inward. In some embodiments, the curved profile 126c is located above the fins 112-1 and 112-3. In some embodiments, the endpoint 126e of the curved profile 126c may be located outside the projection of the fins 112-1 and 112-3. In some embodiments, the profile of the dashed area 126r is adjusted or modified by controlling the process conditions (e.g., recipe and / or parameters) of the photolithography equipment. By modifying the narrow neck pattern defined on the photomask, the gate structure formed subsequently is also modified accordingly, as described below.

[0030] Reference Figure 4A and Figure 4B, an etching technique is performed to pattern the dummy gate material through the opening of the mask layer 124, in particular, to remove a portion of the dielectric layer 120' and the semiconductor material layer 122'. As a result, a dummy gate dielectric 120 and a dummy gate electrode 122 are formed on the fins 112-1, 112-2, and 112-3. The dummy gate electrode 122 is disposed on the dummy gate dielectric 120. The dummy gate electrode 122 extends along the X direction and crosses the fins 112-1, 112-2, and 112-3. The dummy gate electrode 122 has a sidewall 122s1 and a sidewall 122s2 opposite to the sidewall 122s1. In some embodiments, the sidewalls 122s1 and / or 122s2 define a notch (or recess or notch) on the fins 112-1 and / or 112-3. In some embodiments, the notch of the sidewalls 122s1 and / or 122s2 has a curved profile that is recessed inward. In some embodiments, the dummy gate electrode 122 includes a protruding portion 122t adjacent to the sidewalls of the internal fins (e.g., the sidewalls 112-2s1 and 112-2s2 of the fin 112-2). In some embodiments, the protruding portion 122t is formed on the lower portion of the dummy gate electrode 122 so that the upper portion of the dummy gate electrode 112 has a size (e.g., length along the Y direction) smaller than the size of the lower portion in the region adjacent to the internal fin (e.g., the fin 112-2). In some embodiments, the protruding portion 122t contacts the sidewalls 112-2s1 or 112-2s2 of the fin 112-2. In some alternative embodiments, the dielectric layer 120', the semiconductor material layer 122', and the mask layer 124 are patterned together by an etching process using a patterned photoresist as an etching mask.

[0031] In some embodiments, the dummy gate electrode 122 has portions 122p1, 122p2, and 122p3. Portion 122p1 corresponds to an area where a dent (or recess or notch) is formed, and may also be referred to as a narrow portion. Portion 122p3 corresponds to an area where a protruding portion 122t is formed, and may be referred to as a wide portion. Portion 122p2 corresponds to an area where no dent or protruding portion is formed. For example, the area between portions 122p1 and 122p3 of the dummy gate electrode 122 may be defined as portion 122p2. Portion 122p1 has a length L1, and length L1 is defined as the distance between sidewalls 122s1 and 122s2 along the Y direction. Specifically, length L1 may be the minimum distance between sidewalls 122s1 and 122s2 along the Y direction of portion 122p1. Portion 122p2 has a length L2, and length L2 is defined as the distance between sidewalls 122s1 and 122s2 along the Y direction. Portion 122p3 has a length L3, which is defined as the distance between sidewalls 122s1 and 122s2 along the Y direction. Specifically, length L3 can be the maximum distance between sidewalls 122s1 and 122s2 along the Y direction of portion 122p1. In some embodiments, length L3 is greater than length L2. In some embodiments, length L2 is greater than length L1. In further embodiments, ratio L3 / L2 is greater than 1.2 or between 1.1 and 1.3; and ratio L2 / L1 is greater than 1.2 or between 1.1 and 1.3.

[0032] The dummy gate electrode 122 and the fin 112-1 (or 112-3) define an angle θ1 in a top view. The angle θ1 may be defined as an angle between the sidewall 122s1 (or sidewall 122s2) of the dummy gate electrode 122 and the sidewall 112-1s1 of the fin 112-1 (or sidewall 112-1s2 of the fin 112-1) that does not overlap the dummy gate electrode 122 in the Z direction. More specifically, the angle θ1 represents an angle formed between a tangent line of the sidewall 112-1s1 and a sidewall 122s2 of the portion 122p1, wherein the tangent line is taken at the intersection of the sidewall 122s2 and the sidewall 112-1s1, as shown in FIG. Figure 4B As shown. In some embodiments, angle θ1 is an acute angle. In some embodiments, angle θ1 is equal to or greater than about 30° and less than about 90°, such as 30°, 40°, 50°, 60°, 70°, 80°, 85°, or 89°. When angle θ1 is equal to or greater than about 30° and less than about 90°, this means that a bamboo structure that may cause an electrical short circuit is not formed at fin 112-1 (or 112-3).

[0033] The dummy gate electrode 122 and the fin 112-2 define an angle θ2 in a top view. The angle θ2 may be defined as an angle between the sidewall 122s1 (or sidewall 122s2) of the dummy gate electrode 122 and the sidewall 112-2s1 (or 112-2s2) of the fin 112-2 that does not overlap the dummy gate electrode 122 in the Z direction. More specifically, the angle θ2 represents an angle formed between a tangent line of the sidewall 112-2s1 and a sidewall 122s2 of the portion 122t, wherein the tangent line is taken at the intersection of the sidewall 122s2 and the sidewall 112-2s1, as shown in FIG. Figure 4B As shown. In some embodiments, angle θ2 is an obtuse angle. In some embodiments, angle θ2 is greater than about 90° and equal to or less than about 135°, such as 91°, 100°, 110°, 120°, 130°, or 135°. In some embodiments, angle θ2 is greater than angle θ1. In some embodiments, the difference between angles θ1 and θ2 is in the range of about 20° to about 70°, such as 20°, 30°, 40°, 50°, 60°, or 70°. The angles θ1 and θ2 can be measured by state-of-the-art metrology, such as cross-sectional scanning electron microscopy (SEM), transmission electron microscopy (TEM), critical dimension scanning electron microscopy (CD-SEM).

[0034] although Figure 4A and Figure 4B The dielectric layer 120' is shown patterned to form the dummy gate dielectric layer 120 at this stage, but it should be noted that the dielectric layer 120' may not be etched at this stage, but remains on the isolation region 116. In embodiments where the dielectric layer 120' is not patterned, the angle θ1 (or θ2) may be defined as the angle between the sidewall of the dummy gate electrode 122 and the sidewall of the dielectric layer 120'.

[0035] Reference Figure 5A and Figure 5B , a gate spacer 128 is formed to cover the isolation region 116, the dummy gate dielectric 120, the dummy gate electrode 122, and the mask layer 124. The protruding portion 122t is covered by the gate spacer 128. In some embodiments, the gate spacer 128 includes a dielectric material such as silicon nitride, silicon oxide, silicon carbon nitride, silicon oxynitride, silicon carbon nitride oxide, etc., and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers.

[0036] In some embodiments, the gate spacer 128 is conformally formed on the sidewalls 122s1 and 122s2 of the dummy gate electrode 122. Therefore, the sidewalls of the gate spacer 128 have a concave profile adjacent to the fins 112-1 and 112-3. In some embodiments, the formation of the gate spacer 128 includes deposition and an anisotropic etching process, such as plasma etching. After the anisotropic etching process, the portion of the gate spacer 128 deposited on the mask layer 124 and the substrate 110 (specifically, on the isolation region 116 and the S / D region) is removed, as shown in FIG. Fig. 6A and Figure 6B shown.

[0037] Reference Fig. 6A and Figure 6B , source / drain features (S / D features) 130-1, 130-2, and 130-3 are formed on the fins 112-1, 112-2, and 112-3, respectively. In some embodiments, a portion of the gate spacer 128 exposed by the dummy gate electrode 122 and a portion of the fins 112-1, 112-2, and 112-3 are removed to form a recess, and a semiconductor material is formed in the recess and over the isolation region 116, thereby forming a Fig. 6A and Figure 6B The structure shown. In some embodiments, the S / D components 130-1, 130-2 and 130-3 include silicon germanium, silicon or silicon carbide. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be in-situ doped. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), GeB, etc. can be grown. On the contrary, when the resulting FinFET is an n-type FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), etc. can be grown. According to alternative embodiments of the present disclosure, the S / D components 130-1, 130-2 and 130-3 are formed of III-V compound semiconductors, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multilayers thereof. After the S / D features 130-1, 130-2, and 130-3 completely fill the recess, the S / D features 130-1, 130-2, and 130-3 begin to expand horizontally and may form facets. Figure 6B As shown, the S / D features 130 - 1 , 130 - 2 , and / or 130 - 3 may have a curved profile protruding toward the dummy gate electrode 122 in a top view.

[0038] Reference Fig. 7A and Figure 7B, forming a dielectric structure 132. In some embodiments, the dielectric structure 132 includes a multilayer structure. For example, the dielectric structure 132 may include a contact etch stop layer (CESL), an interlayer dielectric (ILD), and other suitable layers. The CESL may include or be made of silicon nitride, silicon carbonitride, etc., and may be formed using a conformal deposition technique such as ALD or CVD. The ILD may include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition technique. The ILD may also be formed of an oxygen-containing dielectric material, which may include a silicon oxide-based material such as tetraethyl orthosilicate (TEOS) oxide, plasma enhanced CVD (PECVD) oxide (SiO2), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or other suitable materials. A planarization technique (such as chemical mechanical polishing (CMP) or mechanical grinding) is performed to planarize the top surface and remove a portion of the dielectric structure 132, the mask layer 124, and the dummy gate electrode 122. As a result, the upper surface of the dummy gate electrode 122 is flush with the upper surface of the dielectric structure 132 .

[0039] Reference Fig. 8A and Figure 8B A removal technique (eg, etching technique) is performed to remove the dummy gate dielectric 120 and the dummy gate electrode 122 including the protruding portion 122 t to form an opening 134 .

[0040] In some embodiments, removing the dummy gate dielectric 120 and the dummy gate electrode 122 includes two or more etching steps, each step targeting a specific material composition. For example, the first etching step can have a high etching selectivity tuned to the dummy gate electrode 122, while substantially no (or minimal) etching loss occurs to the gate spacer 128 or the dummy gate dielectric 120. In some embodiments, the first etching step can be an anisotropic etching process using a process gas selected from, but not limited to, Cl2, BCl3, Ar, CH4, CF4, and combinations thereof.

[0041] The second etching step may have a high etching selectivity tuned to the dummy gate dielectric 120, and substantially no (or minimal) etching loss occurs to the gate spacers 128 or the fins 112-1, 112-2, and 112-3. According to some embodiments of the present disclosure, the second etching step may be a dry etching process, a wet etching process, or other suitable etching process. In some embodiments, the second etching step uses a chemical solution that includes diluted HF.

[0042] although Fig. 8A and Figure 8BThe dummy gate dielectric 120 is shown completely removed at this stage, but may be selectively removed after removing the dummy gate electrode 122. For example, the dummy gate dielectric 120 is removed from a first region (e.g., a core logic region) and remains in a second region (e.g., an input / output region).

[0043] like Figure 8B As shown, the opening 134 inherits the contour of the dummy gate electrode 122. For example, the opening 134 defines an indentation (or recess or notch) adjacent to the fins 112-1 and 112-3. The opening 134 defines a protrusion adjacent to the lower portion of the fin 112-2.

[0044] The protruding portion 122t of the pseudo gate electrode 122 may also be referred to as a bamboo structure, which is formed under certain process conditions. In the comparative example, the bamboo structure is formed not only on the internal fins, but also on the peripheral fins. In some cases, when the bamboo structure is formed on the peripheral fins, due to the load effect, the peripheral fins may be overetched during the removal of the pseudo gate electrode, resulting in exposed or damaged S / D components. In this case, an electrical short circuit may occur between the exposed S / D components and the subsequently formed gate electrode. In an embodiment of the present disclosure, the profile of the pseudo gate electrode 122 is adjusted or modified, and the pseudo gate electrode 112 defines a dent (or recess or notch) at the peripheral fin (e.g., fin 112-1 and / or 112-3), which prevents the formation of a bamboo structure at the peripheral fin. Since no bamboo structure is formed near the peripheral fin, overetching of the peripheral fin caused by the load effect can be avoided. As a result, after this stage, the S / D components 130-1 and / or 130-3 may not be damaged or exposed.

[0045] Reference Fig.9A and Fig. 9B , a gate dielectric 136 and a gate electrode 138 are formed within the opening 134. The gate dielectric 136 is conformally deposited in the opening 134, such as deposited on the upper surfaces and sidewalls (e.g., 112-1s1, 112-1s2, 112-2s1, and 112-2s2) of the fins 112-1, 112-2, and 112-3, and on the sidewalls of the gate spacer 128. In some embodiments, the gate dielectric 136 includes silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric 136 includes a high-k dielectric material, and in these embodiments the gate dielectric 136 may have a k value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric 136 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0046] In some embodiments, gate dielectric 136 is conformally formed within opening 134. Thus, in a top view, sidewalls of gate dielectric 136 have a concave profile adjacent to fins 112-1 and 112-3.

[0047] The gate electrode 138 is disposed on the gate dielectric 136 and fills the remaining portion of the opening 134. The gate electrode 138 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. Fig.9A and Fig. 9B 1, a single layer gate electrode 138 is shown, but the gate electrode 138 may include any number of liners, any number of work function tuning layers, and other suitable fillers. After filling the opening 134, a planarization technique, such as CMP, may be performed to remove excess portions of the gate dielectric 136 and the material of the gate electrode 138. The gate electrode 138 and the gate dielectric 136 may be collectively referred to as a "gate stack."

[0048] like Fig. 9B As shown, the gate electrode 138 extends along the X direction and crosses the fins 112-1, 112-2 and 112-3. The gate electrode 138 has a sidewall 138s1 and a sidewall 138s2 opposite to the sidewall 138s1. In some embodiments, the gate electrode 138 inherits at least a portion of the profile of the dummy gate electrode 122. For example, the sidewalls 138s1 and / or 138s2 define a dent 138r (or a recess or a notch) above the fins 112-1 and / or 112-3. In some embodiments, the dent 138r (or a recess or a notch) includes a curved profile that is recessed inwardly above the fins 112-1 and / or 112-3. In some embodiments, the gate electrode 138 includes a protruding portion 138t adjacent to the sidewalls 112-2s1 and 112-2s2 of the fin 112-2. In some embodiments, the protruding portion 138t contacts the sidewalls 112 - 2s1 and 112 - 2s2 of the fin 112 - 2 .

[0049] In some embodiments, the gate electrode 138 has portions 138p1, 138p2, and 138p3. Portion 138p1 corresponds to an area where a dent 138r (or a recess or a notch) is formed, and may also be referred to as a narrow portion. Portion 138p3 corresponds to an area where a protruding portion 138t is formed, and may also be referred to as a wide portion. Portion 138p2 corresponds to an area where no dent or protruding portion is formed. For example, an area between portion 138p1 and portion 138p3 of the gate electrode 138 may be defined as portion 138p2. Portion 138p1 has a length L4, and length L4 is defined as the distance between sidewalls 138s1 and 138s2 along the Y direction. Portion 138p2 has a length L5, and length L5 is defined as the distance between sidewalls 138s1 and 138s2 along the Y direction. Portion 138p3 has a length L6, and length L6 is defined as the distance between sidewalls 138s1 and 138s2 along the Y direction. In some embodiments, length L6 is greater than length L5. In some embodiments, length L5 is greater than length L4.

[0050] The gate electrode 138 and the fin 112-1 (or 112-3) define an angle θ3 in a top view. The angle θ3 may be defined as an angle between a sidewall 138s1 (or sidewall 138s2) of the gate electrode 138 and a sidewall 112-1s1 (or 112-1s2) of the fin 112-1 that does not overlap the gate electrode 138 in the Z direction. More specifically, the angle θ3 represents an angle formed between a tangent line of the sidewall 112-1s1 of the fin 112-1 and a sidewall 138s2 of the gate electrode 138, wherein the tangent line is taken at the intersection of the sidewall 138s2 and the sidewall 112-1s1, as shown in FIG. Fig. 9B As shown. In some embodiments, angle θ3 is an acute angle. In some embodiments, angle θ3 is equal to or greater than about 30° and less than about 90°, such as 30°, 40°, 50°, 60°, 70°, 80°, 85°, or 89°. When angle θ3 is equal to or greater than about 30° and less than about 90°, this means that a bamboo structure that may cause an electrical short circuit is not formed at fin 112-1 (or 112-3).

[0051] The gate electrode 138 and the fin 112-2 define an angle θ4 in a top view. The angle θ4 may be defined as an angle between the sidewall 138s1 (or the sidewall 138s2) of the gate electrode 138 and the sidewall 112-2s1 of the fin 112-2 that does not overlap the gate electrode 138 in the Z direction. More specifically, the angle θ4 represents an angle formed between the sidewall 112-2s1 of the fin 112-2 and a tangent line to the sidewall 138s2 of the portion 138t, wherein the tangent line is taken at the intersection of the sidewall 138s2 and the sidewall 112-2s1, as shown in FIG. Fig. 9BAs shown. In some embodiments, angle θ4 is an obtuse angle. In some embodiments, angle θ4 is greater than about 90° and equal to or less than about 135°, such as 91°, 100°, 110°, 120°, 130°, or 135°. In some embodiments, angle θ4 is greater than angle θ3. In some embodiments, the difference between angles θ3 and θ4 is in the range of about 20° to about 70°, such as 20°, 30°, 40°, 50°, 60°, or 70°. The angles θ3 and θ4 can be measured by state-of-the-art metrology, such as SEM, TEM, or CD-SEM.

[0052] Similarly, the gate dielectric 136 and the fins 112 - 1 , 112 - 2 , and 112 - 3 may define angles that are the same or similar to angles θ3 and θ4 . Additionally, the gate dielectric 136 defines indentations adjacent to the fins 112 - 1 and 112 - 3 .

[0053] As described above, the bamboo structure is not formed adjacent to the peripheral fins (e.g., fins 112-1 and / or 112-3). As a result, after removing the dummy gate electrode 122, the S / D components 130-1 and 130-3 may not be exposed or damaged by over-etching. Therefore, electrical short circuits between the gate electrode and the S / D components may be avoided.

[0054] Fig.10 is a top view of a semiconductor device 10b according to some embodiments of the present disclosure. The semiconductor device 10b has a similar structure to the semiconductor device 10a, but the differences therebetween are as follows.

[0055] Angle θ5 represents the angle formed between the sidewall 112-1s1 of the fin 112-1 and the tangent line of the sidewall 138s2 of the portion 138r, wherein the tangent line is taken at the intersection of the sidewall 138s2 and the sidewall 112-1s1, as shown in FIG. Fig.10 Angle θ6 represents the angle formed between the sidewall 112-1s2 of the fin 112-1 and the tangent line of the sidewall 138s2 of the portion 138t, wherein the tangent line is taken at the intersection of 138s2 and 112-1s2, as shown in FIG. Fig.10 As shown. In some embodiments, angle θ5 is different from angle θ6. In some embodiments, angle θ5 is equal to or greater than about 30° and less than about 90°, such as 30°, 40°, 50°, 60°, 70°, 80°, 85°, or 89°. In some embodiments, angle θ6 is greater than about 90° and equal to or less than about 135°, such as 91°, 100°, 110°, 120°, 130°, or 135°. In some embodiments, angle θ6 is greater than angle θ5. In some embodiments, the difference between angles θ5 and θ6 is in the range of about 20° to about 70°, such as 20°, 30°, 40°, 50°, 60°, or 70°.

[0056] Similarly, the gate dielectric 136 and the fins 112 - 1 , 112 - 2 , and 112 - 3 may define angles that are the same or similar to angles θ5 and θ6 .

[0057] Under some process conditions, over-etching generally occurs on the outer side (e.g., sidewall 112-1s1) of the peripheral fin (e.g., fin 112-1), and the profile of the dummy gate may be modified so that a protruding portion (e.g., bamboo structure) of the dummy gate may be formed at sidewall 112-1s2, and a dent of the dummy gate may be formed on sidewall 112-1s1. In this embodiment, gate electrode 138 may inherit the profile of the dummy gate, so that gate electrode 138 has a shape similar to that of Fig.10 The structure shown.

[0058] Fig.11 is a top view of a semiconductor device 20 according to some embodiments of the present disclosure. It should be noted that for the sake of brevity, Fig.11 Some features (such as gate dielectrics and gate spacers) are omitted.

[0059] The semiconductor device 20 includes fins 212-1, 212-2, 212-3, and 212-4, each of which extends along the Y direction. The fins 212-1, 212-2, 212-3, and 212-4 may define or constitute a fin group. The fins 212-1 and 212-4 are peripheral fins of the fin group. The fins 212-2 and 212-3 are internal fins of the fin group. The semiconductor device 20 includes gate electrodes 238-1, 238-2, and 238-3, each of which extends along the X direction and crosses the fins 212-1 to 212-4. In some embodiments, the sidewalls of the gate electrode 238-1 (or 238-2 or 238-3) define a dent 250 (or a recess or a notch) that overlaps the fin 212-1 (or 212-4) along the Z direction. Each of the gate electrodes 238 - 1 to 238 - 3 includes a protruding portion 238 t over the sidewalls of the fins 212 - 2 and 212 - 3 .

[0060] Fig.12 is a top view of a semiconductor device 30 according to some embodiments of the present disclosure. It should be noted that for the sake of brevity, Fig.12 Some features (such as gate dielectrics and gate spacers) are omitted.

[0061] The semiconductor device 30 includes a fin group 310-1 and a fin group 310-2. The fin group 310-1 includes fins 312-1, 312-2, 312-3, and 312-4, each of which extends along the Y direction. The fins 312-1 and 312-4 are peripheral fins of the fin group 310-1. The fins 312-2 and 312-3 are internal fins of the fin group 310-1. The fin group 310-2 includes fins 312-5, 312-6, 312-7, and 312-8, each of which extends along the Y direction. The fins 312-5 and 312-8 are peripheral fins of the fin group 310-2. The fin 312-5 is adjacent to the fins 312-4 and 312-6. The fins 312-6 and 312-7 are internal fins of the fin group 310-2. Fins 312-1 to 312-4 (or fins 312-5 to 312-8) define a pitch P1, which is the distance (or length) between adjacent fins belonging to fin group 310-1 (e.g., the distance between sidewalls on the same side). Fin groups 310-1 and 310-2 define a pitch P2, which is the distance (or length) between fins located at corresponding positions of fin groups 310-1 and 310-2 (e.g., the distance between fin 312-1 and corresponding fin 312-5). Pitch P2 is greater than pitch P1. Semiconductor device 30 includes gate electrodes 338-1, 338-2, 338-3, and 338-4, each of which extends along the X direction and crosses fins 312-1 to 312-8. Under some conditions, if a bamboo structure is formed, the fins 312-1, 312-4, 312-5 and / or 312-8 may be overetched at the stage of removing the dummy gate electrode. In some embodiments of the present disclosure, the profile of the dummy gate electrode can be modified so that the sidewalls of the dummy gate define indentations adjacent to the fins 312-1, 312-4, 312-5 and 312-8 in a top view. As a result, the dummy gate electrode has no bamboo structure on the fins 312-1, 312-4, 312-5 and 312-8. The gate electrodes 338-1 to 338-4 can inherit the profile of the dummy gate electrode so that the sidewalls of the gate electrodes 338-1 to 338-4 define indentations 350 (or recesses or notches) adjacent to the fins 312-1, 312-4, 312-5 and 312-8. Each of the gate electrodes 338 - 1 to 338 - 4 includes a protruding portion 338 t on the sidewalls of the fins 312 - 2 , 312 - 3 , 312 - 6 , and 312 - 7 .

[0062] Fig.13 is a flow chart of a method 40 for fabricating a semiconductor device according to various aspects of the present disclosure.

[0063] The method 40 begins with operation 402, where a substrate is provided. A fin group is formed on the substrate. The fin group includes a first fin and a second fin. The first fin is a peripheral fin of the fin group. The second fin is an internal fin between the peripheral fins of the fin group. Figure 1A and Figure 1BA stage corresponding to operation 402 is shown.

[0064] The method 40 continues with operation 404 in which a semiconductor material layer is formed on the first fin and the second fin. Figure 2A and Figure 2B A stage corresponding to operation 404 is shown.

[0065] The method 40 continues with operation 406 in which the semiconductor material layer is patterned to form a dummy gate electrode. The dummy gate electrode includes a narrow portion adjacent to the first fin and a wide portion adjacent to the second fin. FIG. 3A to FIG. 4A and FIG. 3B to FIG. 4B A stage corresponding to operation 406 is shown.

[0066] The method 40 continues with operation 408 in which S / D features are formed adjacent to the first fin and the second fin. Fig. 6A and Figure 6B A stage corresponding to operation 408 is shown.

[0067] The method 40 continues with operation 410 in which the dummy gate electrode is removed to form an opening. Fig. 8A and Figure 8B A stage corresponding to operation 410 is shown.

[0068] The method 40 continues with operation 412 where a gate electrode is formed within the opening. The gate electrode includes a narrow portion adjacent to the first fin and a wide portion adjacent to the second fin. Fig.9A and Fig. 9B A stage corresponding to operation 412 is shown.

[0069] Method 40 is merely an example and is not intended to limit the present disclosure beyond the scope explicitly recited in the claims. Additional operations may be provided before, during, and after method 40, and some of the operations described may be replaced, eliminated, or reordered for additional embodiments of the method.

[0070] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first fin and a gate electrode. The first fin extends along a first direction. The gate electrode has a sidewall extending along a second direction different from the first direction. The sidewall of the gate electrode defines a recess adjacent to the first fin in a top view.

[0071] In some embodiments, the semiconductor device further includes: a second fin extending along the first direction, wherein the sidewall of the gate electrode further extends across the second fin, and the sidewall of the gate electrode defines a protruding portion adjacent to the second fin.

[0072] In some embodiments, the semiconductor device further includes: a second fin extending along a first direction, wherein the gate electrode has a first length along the first direction adjacent to the first fin and a second length along the second direction adjacent to the second fin, wherein the first length is different from the second length.

[0073] In some embodiments, the first fin and the second fin are included in a fin group, and the first fin is a peripheral fin of the fin group.

[0074] In some embodiments, a sidewall of the gate electrode and a sidewall of the first fin form an acute angle in a top view.

[0075] In some embodiments, the acute angle is equal to or greater than about 30° and less than about 90°.

[0076] In some embodiments, a sidewall of the gate electrode and a sidewall of the second fin form an obtuse angle in a top view.

[0077] In some embodiments, the semiconductor device further includes: a gate dielectric disposed on the first fin, wherein the gate dielectric defines a recess adjacent to the first fin in a top view.

[0078] In some embodiments, the indentation overlaps the first fin along a third direction substantially orthogonal to the first direction and the second direction.

[0079] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first fin group and a gate electrode. The first fin group includes a first fin and a second fin adjacent to the first fin, and each of the first fin and the second fin extends along a first direction. The first fin is a peripheral fin of the first fin group. The gate electrode extends along a second direction and crosses at least the first fin and the second fin of the first fin group. The gate electrode has a first narrow portion adjacent to the first fin.

[0080] In some embodiments, the second fin is an inner fin of the first fin group, and the gate electrode has a wide portion adjacent to the second fin.

[0081] In some embodiments, the gate electrode has a middle portion between the first fin and the second fin, and a length of the middle portion is greater than a length of the first narrow portion along the first direction.

[0082] In some embodiments, the length of the middle portion is less than the length of the wide portion along the first direction.

[0083] In some embodiments, the semiconductor device further includes: a second fin group different from the first fin group, wherein a distance between the first fin group and the second fin group is greater than a pitch of the first fin group, and the second fin group includes a third fin, the third fin is a peripheral fin of the second fin group, and the gate electrode has a second narrow portion adjacent to the third fin.

[0084] In some embodiments, in a top view, the gate electrode has a sidewall extending along the second direction, the sidewall of the gate electrode forms a first angle with the sidewall of the first fin, and the sidewall of the gate electrode forms a second angle different from the first angle with the sidewall of the second fin.

[0085] In some embodiments, the first angle is smaller than the second angle.

[0086] In some embodiments, the first angle is an acute angle.

[0087] In some embodiments, the second angle is an obtuse angle.

[0088] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device. The method includes forming a fin group on a substrate, wherein the fin group includes a first fin and a second fin adjacent to the first fin. The first fin is a peripheral fin of the fin group. The method also includes forming a semiconductor material layer on the fin group. The method also includes patterning the semiconductor material layer to form a dummy gate electrode. The dummy gate electrode has a narrow portion adjacent to the first fin and a wide portion adjacent to the second fin.

[0089] In some embodiments, the method further includes: removing the dummy gate electrode; and forming a gate electrode having a narrow portion adjacent to the first fin and a wide portion adjacent to the second fin.

[0090] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A semiconductor device, comprising: a first fin extending along a first direction; as well as a gate electrode having a sidewall extending in a second direction different from the first direction, The sidewall of the gate electrode defines a recess adjacent to the first fin in a top view.

2. The semiconductor device according to claim 1, further comprising: A second fin extends along the first direction, wherein the sidewall of the gate electrode also extends across the second fin, and the sidewall of the gate electrode defines a protruding portion adjacent to the second fin.

3. The semiconductor device according to claim 1, further comprising: A second fin extends along the first direction, wherein the gate electrode has a first length adjacent to the first fin along the first direction and a second length adjacent to the second fin along the second direction, wherein the first length is different from the second length.

4. The semiconductor device according to claim 3, wherein: The first fin and the second fin are included in a fin group, and the first fin is a peripheral fin of the fin group.

5. The semiconductor device according to claim 3, wherein: The sidewall of the gate electrode and the sidewall of the first fin form an acute angle in a top view.

6. A semiconductor device comprising: a first fin group, comprising a first fin and a second fin adjacent to the first fin, each of the first fin and the second fin extending along a first direction, wherein the first fin is a peripheral fin of the first fin group; and a gate electrode extending along a second direction and crossing at least the first fin and the second fin of the first fin group, The gate electrode has a first narrow portion adjacent to the first fin.

7. The semiconductor device according to claim 6, wherein: The second fin is an inner fin of the first fin group, and the gate electrode has a wide portion adjacent to the second fin.

8. The semiconductor device according to claim 6, further comprising: A second fin group different from the first fin group, wherein a distance between the first fin group and the second fin group is greater than a pitch of the first fin group, and the second fin group includes a third fin, the third fin is a peripheral fin of the second fin group, and the gate electrode has a second narrow portion adjacent to the third fin.

9. The semiconductor device according to claim 6, wherein: In a top view, the gate electrode has a sidewall extending along the second direction, the sidewall of the gate electrode forms a first angle with the sidewall of the first fin, and the sidewall of the gate electrode forms a second angle different from the first angle with the sidewall of the second fin.

10. A method for manufacturing a semiconductor device, comprising: forming a fin group on a substrate, wherein the fin group includes a first fin and a second fin adjacent to the first fin, and the first fin is a peripheral fin of the fin group; forming a layer of semiconductor material over the set of fins; and The semiconductor material layer is patterned to form a dummy gate electrode, wherein the dummy gate electrode has a narrow portion adjacent to the first fin and a wide portion adjacent to the second fin.

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