Semiconductor device and preparation method thereof

Abstract

The invention discloses a semiconductor device and a preparation method thereof, the semiconductor device comprises an active region and a terminal region, and the terminal region surrounds the active region; a drift layer of a first conductive type, wherein the drift layer is located in the active region and the terminal region; the active region further comprises a first short circuit region of a first conduction type, the first short circuit region is located on the back face of the drift layer, and a part of the first short circuit region extends into the drift layer in the longitudinal direction of the device; and a barrier layer of a second conductivity type located within the drift layer and surrounding a portion of the first short circuit region extending into the drift layer. According to the semiconductor device and the preparation method thereof, the voltage rebound phenomenon can be inhibited when the device is in forward conduction, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for preparing the semiconductor device. Background Art

[0002] For some semiconductor devices such as RC-IGBT (reverse conducting Insulated Gate Bipolar Transistor), a rebound phenomenon may occur when the device is turned on, seriously affecting the performance of the device. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the first object of the present invention is to provide a semiconductor device that can effectively suppress the rebound phenomenon when turned on and improve the device performance.

[0004] The second object of the present invention is to provide a method for manufacturing a semiconductor device.

[0005] In order to achieve the above-mentioned purpose, a semiconductor device according to an embodiment of the first aspect of the present invention comprises an active area and a terminal area, wherein the terminal area surrounds the active area; a drift layer of a first conductivity type, wherein the drift layer is located in the active area and the terminal area; the active area further comprises: a first short-circuit area of ​​the first conductivity type, wherein the first short-circuit area is located on the back side of the drift layer, and a portion of the first short-circuit area extends into the drift layer in the longitudinal direction of the device; and a blocking layer of a second conductivity type, wherein the blocking layer is located in the drift layer and surrounds a portion of the first short-circuit area extending into the drift layer.

[0006] According to the semiconductor device of the embodiment of the present invention, by setting a blocking layer on the top of the first short-circuit region in the active area, the blocking layer is located in the drift layer and surrounds the part of the first short-circuit region extending into the drift layer. When the device is forward-conducted, it can block the electron current from flowing to the first short-circuit region, that is, at the initial stage of device startup, the resistance of the electron path can be increased, so that the back PN junction can be turned on as soon as possible under a small current, thereby suppressing the voltage rebound phenomenon and improving the device performance.

[0007] In some embodiments, the active area also includes: a collector region of a second conductivity type, the collector region is located on the back side of the drift layer, the collector region and the first short-circuit region are arranged laterally along the device; and a first insulating structure, the first insulating structure is located between the collector region and the first short-circuit region.

[0008] In some embodiments, the semiconductor device includes a buffer layer of a first conductivity type, the buffer layer is located on the back side of the drift layer; the first short-circuit region penetrates the buffer layer and extends into the drift layer, and the collector region is located on a side of the buffer layer away from the drift layer; the first insulating structure extends to the top of the buffer layer and contacts the blocking layer.

[0009] In some embodiments, the termination region includes: a second short-circuit region of the first conductivity type, and the second short-circuit region is located on a side of the buffer layer away from the drift layer.

[0010] In some embodiments, the semiconductor device further includes: a second insulating structure, the second insulating structure is located on a side of the buffer layer away from the drift layer and is located at a junction of the active region and the terminal region.

[0011] In some embodiments, the second insulating structure penetrates the buffer layer and extends into the drift layer in a vertical direction of the device.

[0012] In some embodiments, the semiconductor device further includes: a collector metal layer, the collector metal layer covers the active area and the terminal area, and is located on the first short circuit area, the second short circuit area, the collector area, the first insulating structure and the second insulating structure.

[0013] In some embodiments, the active area also includes an IGBT front structure and an FRD front structure on the front side of the drift layer; the terminal area includes a terminal front structure on the front side of the drift layer; wherein the first short-circuit area is arranged corresponding to the FRD front structure, and the collector area is arranged corresponding to the IGBT front structure.

[0014] In some embodiments, the IGBT front structure includes: a carrier storage layer, which is arranged on the front side of the drift layer; an IGBT well region of the second conductivity type, which is arranged on the carrier storage layer; an IGBT groove, which passes through the IGBT well region, the carrier storage layer and extends into the drift layer, and the IGBT groove includes a gate groove; an emitter region of the first conductivity type, which is located on both sides of the gate groove in the lateral direction of the device.

[0015] In some embodiments, the FRD front structure includes: the carrier storage layer; a second conductivity type FRD well region, the FRD well region is arranged on the carrier storage layer; and an FRD groove, the FRD groove passes through the FRD well region, the carrier storage layer and extends into the drift layer.

[0016] In some embodiments, the IGBT trench further includes at least one of an emission trench and a dummy trench, and the FRD trench includes at least one of an emission trench and a dummy trench.

[0017] In some embodiments, the semiconductor device further includes: an insulating dielectric layer, which is disposed on the IGBT well region and the FRD well region; an emitter metal layer, which is disposed on the insulating oxide layer, and the emitter metal layer is connected to the IGBT well region, the emitter region and the emitter trench through a contact hole.

[0018] In order to achieve the above-mentioned purpose, an embodiment of the second aspect of the present invention proposes a method for preparing a semiconductor device, wherein the semiconductor includes an active area and a terminal area surrounding the active area, and the preparation method includes: preparing a drift layer of a first conductivity type in the active area and the terminal area; preparing a first short-circuit area of ​​the first conductivity type on the back side of the drift layer in the active area, wherein a portion of the first short-circuit area extends into the drift layer in the longitudinal direction of the device; and preparing a blocking layer of a second conductivity type in the drift layer, wherein the blocking layer surrounds the portion of the first short-circuit area extending into the drift layer.

[0019] According to the method for preparing a semiconductor device in an embodiment of the present invention, by preparing a blocking layer, the blocking layer is located in the drift layer and surrounds the portion of the first short-circuit region extending into the drift layer. This can block the flow of electron current to the first short-circuit region when the device is forward-conducted, increase the resistance of the first short-circuit region at the initial stage of device startup, enable the PN junction on the back side of the active region to be turned on as soon as possible, and suppress the occurrence of voltage rebound.

[0020] In some embodiments, the preparation method further includes: preparing a collector region on the back side of the drift layer in the active region, wherein the collector region and the first short-circuit region are arranged laterally along the device; and preparing a first insulating structure between the collector region and the first short-circuit region.

[0021] In some embodiments, before preparing the first short-circuit region and the collector region, the preparation method also includes: preparing a buffer layer of a first conductive type on the back side of the drift layer, the first short-circuit region penetrates the buffer layer and extends into the drift layer, the collector region is located on a side of the buffer layer away from the drift layer, and the first insulating structure extends to the top of the buffer layer and contacts the blocking layer.

[0022] In some embodiments, the preparation method further includes: preparing a second short-circuit region of the first conductivity type on a side of the buffer layer away from the drift layer in the terminal region.

[0023] In some embodiments, the preparation method further includes: preparing a second insulating structure on a side of the buffer layer away from the drift layer and located at the junction of the active area and the terminal area, wherein the second insulating structure penetrates the buffer layer in the vertical direction of the device and extends into the drift layer.

[0024] In some embodiments, the preparation method further includes: covering the active area and the terminal area and preparing a collector metal layer on the first short circuit area, the second short circuit area, the collector area, the first insulating structure and the second insulating structure.

[0025] In some embodiments, the preparation method includes: preparing an IGBT front structure and an FRD front structure on the front side of the drift layer in the active area, and preparing a terminal front structure on the front side of the drift layer in the terminal area; wherein the first short-circuit area is prepared corresponding to the FRD front structure, and the collector area is prepared corresponding to the IGBT front structure.

[0026] In some embodiments, an IGBT front structure and an FRD front structure are prepared on the front side of the drift layer in the active area, including: preparing a carrier storage layer on the front side of the drift layer; preparing an IGBT well region and an FRD well region of a second conductivity type on the carrier storage layer; preparing an IGBT trench and an FRD trench, wherein the IGBT trench region penetrates the IGBT well region, the carrier storage layer and extends into the drift layer, the FRD trench region penetrates the FRD well region, the carrier storage layer and extends into the drift layer, and the IGBT trench region includes a gate trench.

[0027] In some embodiments, the preparation method also includes: preparing an insulating dielectric layer on the IGBT well region and the FRD well region; preparing an emitter metal layer on the insulating dielectric layer, and the emitter metal layer is connected to the IGBT well region, the emitter region and the emitter trench through a contact hole.

[0028] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0030] Figure 1 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0031] Figure 2is a schematic back side view of a semiconductor device according to an embodiment of the present invention;

[0032] Figure 3 A schematic cross-sectional view of an IGBT region of a semiconductor device according to an embodiment of the present invention;

[0033] Figure 4 is a schematic cross-sectional view of an FRD region of a semiconductor device according to an embodiment of the present invention;

[0034] Figure 5 is a flow chart of a method for preparing a semiconductor device according to an embodiment of the present invention;

[0035] Figure 6 is a flow chart of a method for manufacturing a semiconductor device according to another embodiment of the present invention.

[0036] Reference numerals:

[0037] 1 emitter metal; 2 emitter region; 3 well region; 4 carrier storage layer; 5 polysilicon; 6 oxide layer; 7 drift layer; 8 barrier layer; 9 buffer layer; 10 collector region; 111 first short circuit region; 112 second short circuit region; 121 first insulating structure; 122 second insulating structure; 13 collector metal layer; 14 contact hole; 15 insulating dielectric layer; 16 ohmic contact region; 17 gate trench; 18 emitter trench; 19 dummy trench; 31 IGBT well region; 32 FRD well region; 100 active region; 101 terminal region; 200 substrate. DETAILED DESCRIPTION

[0038] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0039] In order to solve the rebound phenomenon generated when the device is forward-conducted, the semiconductor device of the embodiment of the present invention improves the back surface structure.

[0040] Reference below Figure 1-Figure 4 A semiconductor device according to an embodiment of the first aspect of the present invention is described.

[0041] Figure 1 is a schematic diagram of a semiconductor device structure according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device 1000 of the embodiment of the present invention includes an active region 100 and a terminal region 101. The active region structure and the terminal region structure can be prepared on a substrate 200. Figure 2 As shown, the termination region 101 surrounds the active region 100 .

[0042] The active region 100 includes a drift layer 7 of a first conductivity type, a first short-circuit region 111 of the first conductivity type, and a barrier layer 8 of a second conductivity type, wherein the drift layer 7 is also distributed in the terminal region 101 .

[0043] In an embodiment, the first conductivity type may be N-type conductivity or P-type conductivity, wherein when the first conductivity type is N-type conductivity, the second conductivity type is P-type conductivity, and when the first conductivity type is P-type conductivity, the second conductivity type is N-type conductivity. The doped element type of the P-type doping region may be boron (B) and boron fluoride (BF2), etc., and the doped element type of the N-type doping region may be phosphorus (P), arsenic (As), hydrogen (H), etc., and neither is specifically limited.

[0044] The first short-circuit region 111 is located on the back side of the drift layer 7, and part of the first short-circuit region 111 in the longitudinal direction of the device extends into the drift layer 7. In the embodiment, the first short-circuit region 111 may be N-type or P-type, and preferably, the first short-circuit region 111 is N-type, which may enable the device to have a higher turn-off rate.

[0045] Among them, the blocking layer 8 is located in the drift layer 7 and surrounds the part of the first short-circuit region 111 extending into the drift layer 7. The second conductive type blocking layer 8 can block electrons when the device is forward-conducting, increase the resistance of the first short-circuit region 111 at the initial stage of device startup, turn on the back PN junction as soon as possible, and suppress the occurrence of voltage rebound.

[0046] Specifically, for semiconductor devices such as RC-IGBT, at the initial stage of forward conduction of the device, the current density is very small, and only electrons participate in conduction. In the embodiment of the present invention, by setting a second conductive type barrier layer 8 on the top of the first short-circuit area 111, it plays a role in blocking electrons when the device is forward-conducted, increasing the resistance of the short-circuit area, and allowing the PN junction on the back of the IGBT to be turned on as quickly as possible under a small current, thereby suppressing the voltage rebound phenomenon and improving the device characteristics.

[0047] In an embodiment, Figure 1 As shown, the active region 100 further includes a collector region 10 of the second conductivity type. The collector region 10 is located on the back side of the drift layer 7 . The collector region 10 and the first short-circuit region 111 are arranged in the transverse direction of the device.

[0048] Furthermore, a first insulating structure 121 is provided between the collector region 10 and the first short-circuit region 111, so that the second conductive type blocking layer is not in direct contact with the buffer layer and the second conductive type collector region, thereby blocking electrons from passing through the buffer layer through the first short-circuit region and allowing the electron path to pass through the drift layer, thereby increasing the resistance of the electron path and enabling the device to turn on the PN junction on the back side of the IGBT as quickly as possible under a small current, thereby suppressing the occurrence of voltage rebound.

[0049] like Figure 1As shown, the semiconductor device 1000 according to the embodiment of the present invention includes a buffer layer 9 of a first conductivity type. The buffer layer 9 is located on the back side of the drift layer 7 . The buffer layer 9 is distributed in the active region 100 and the terminal region 101 .

[0050] The first short-circuit region 111 penetrates the buffer layer 9 and extends into the drift layer 7. The barrier layer 8 surrounds the portion of the first short-circuit region 111 extending into the drift layer 7. The doping concentration of the drift layer 7 is relatively low. The barrier layer 8 can block the initial electron current of the device from flowing to the first short-circuit region 111, thereby increasing the resistance of the first short-circuit region 111 and suppressing the occurrence of the rebound phenomenon.

[0051] The collector region 10 is located on one side of the buffer layer 9 away from the drift layer 7 and forms a back PN junction with the first short-circuit region 111. The first insulating structure 121 is located between the collector region 10 and the first short-circuit region 111 and extends to the top of the buffer region 9 and contacts the barrier layer 8.

[0052] Furthermore, in some embodiments, Figure 1 As shown, the terminal region 101 includes a second short-circuit region 112 of the first conductivity type, and the second short-circuit region 112 is located on the side of the buffer layer 9 away from the drift layer 7. By designing the second short-circuit region 112 of the first conductivity type on the back of the terminal region 101, the effect of reducing the hole injection of the back collector region 10 when the device is turned off can be achieved, the reverse recovery time of the device can be reduced, and the turn-off loss can be reduced. In addition, the first conductivity type short-circuit region reasonably distributed on the back of the active region 100 and the terminal region 101 avoids the concentration of current and temperature when the device is reversely turned on, thereby improving the stability and reliability of the device.

[0053] Furthermore, if Figure 1 As shown, the semiconductor device 1000 further includes a second insulating structure 122, such as Figure 2 As shown, the second insulating structure 122 is located on the side of the buffer layer 9 away from the drift layer 7 and at the junction of the active area 100 and the terminal area 101 to increase the resistance of the electron path. Figure 1 As shown, in the longitudinal direction of the device, the second insulating structure 122 penetrates the buffer layer 9 and extends into the drift layer 7. By introducing the second insulating structure 122 between the terminal region 101 and the active region 100, the insulating structure completely penetrates the buffer layer and extends to the drift layer 7. The existence of the second insulating structure 122 is to increase the resistance of the electron path in order to allow electrons to flow from the drift layer, so that the PN junction on the back side of the IGBT region is turned on as soon as possible, thereby suppressing the voltage rebound phenomenon.

[0054] like Figure 1As shown, a collector metal layer 13 is provided on the back side of the semiconductor device 1000 of the embodiment of the present invention. The collector metal layer 13 covers the active area 100 and the terminal area 101 and is located on the first short circuit area 111, the second short circuit area 112, the collector area 10, the first insulating structure 121 and the second insulating structure 122.

[0055] In the embodiment, the active region includes an IGBT region and an FRD region. The active region 100 is provided with an IGBT front structure and an FRD front structure on the front of the drift layer 7; the terminal region 101 includes a terminal front structure on the front of the drift layer 7; wherein the first short-circuit region 111 is provided corresponding to the FRD front structure, and the collector region 10 is provided corresponding to the IGBT front structure, forming an IGBT structure and an FRD structure connected in reverse parallel.

[0056] like Figure 3 As shown, the IGBT front structure includes a carrier storage layer 4, an IGBT well region 31 of the second conductivity type, an IGBT trench and an emitter region 2 of the first conductivity type. The IGBT trench includes an oxide layer 6 and polysilicon 5 filled in the oxide layer 6.

[0057] Among them, Figure 3 As shown, the carrier storage layer 4 is arranged on the front side of the drift layer 7; the IGBT well region 31 is arranged on the carrier storage layer 4; the IGBT trench runs through the IGBT well region, the carrier storage layer 4 and extends into the drift layer 7, and the IGBT trench includes a gate trench 17; the emitter region 2 is located on both sides of the gate trench 17 in the lateral direction of the device.

[0058] In some embodiments, Figure 3 As shown, the IGBT trench may further include at least one of an emission trench 18 and a dummy trench 19 .

[0059] like Figure 4 As shown, the FRD front structure includes a carrier storage layer 4, a second conductivity type FRD well region 32 and an FRD trench. Figure 1 The middle well region 3 includes an IGBT well region 31 and an FRD well region 32. The FRD trench includes an oxide layer 6 and polysilicon 5 filled in the oxide layer 6.

[0060] The FRD well region 32 is disposed on the carrier storage layer 4; the FRD trench penetrates the FRD well region 32 and the carrier storage layer 4 and extends into the drift layer 7. In an embodiment, the FRD trench may include at least one of an emission trench 18 and a dummy trench 19.

[0061] like Figure 3 and 4As shown, the semiconductor device 1000 further includes an insulating dielectric layer 15 and an emitter metal layer 1. The insulating dielectric layer 15 is disposed on the IGBT well region 31 and the FRD well region 32. The emitter metal layer 1 is disposed on the insulating dielectric layer 15, and the emitter metal layer 1 is connected to the IGBT well region 32, the emitter region 2 and the emitter trench 18 through the contact hole 14.

[0062] In summary, the semiconductor device 1000 of the embodiment of the present invention is provided with a second conductive type barrier layer 8 on top of the first conductive type first short-circuit region 111 of the active region 100. The first conductive type first short-circuit region 111 of the active region 100 is isolated from the second conductive type collector region 10 by a first insulating structure 121. The second conductive type barrier layer 8 can block electrons when the device is forward-conducted, and increase the resistance of the first short-circuit region 111 at the initial stage of device opening. In addition, a second insulating structure 122 is introduced at the junction of the terminal region 101 and the active region 100. The insulating structure completely penetrates the buffer layer 9 and extends to the drift layer 7. The existence of the second insulating structure allows electrons to flow from the drift layer, increases the resistance of the electron path, and enables the PN junction on the back of the IGBT region to be opened as soon as possible, thereby suppressing the voltage rebound phenomenon. The back of the terminal region 101 is designed as the second short-circuit region 112 of the first conductive type, which can achieve the effect of reducing the hole injection in the back collector region when the device is turned off, reducing the reverse recovery time of the device, and reducing the turn-off loss. In addition, the first conductive type short-circuit regions reasonably distributed on the back of the active region 100 and the terminal region 101 avoid the concentration of current and temperature when the FRD region is turned on, thereby improving the stability and reliability of the device. In summary, the semiconductor device designed in the present invention can suppress the rebound phenomenon of the device and improve the overall performance of the device.

[0063] A method for manufacturing a semiconductor device according to an embodiment of the second aspect of the present invention will be described below with reference to the accompanying drawings.

[0064] Figure 5 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. The semiconductor device according to the embodiment of the present invention includes an active region and a terminal region. Figure 5 As shown, the method for preparing a semiconductor device according to an embodiment of the present invention includes:

[0065] S1, preparing a drift layer of the first conductivity type in the active area and the terminal area.

[0066] S2, preparing a first short-circuit region of the first conductivity type on the back side of the drift layer in the active region, wherein a portion of the first short-circuit region extends into the drift layer in the longitudinal direction of the device.

[0067] S3, preparing a barrier layer of the second conductivity type in the drift layer, wherein the barrier layer surrounds a portion of the first short-circuit region extending into the drift layer.

[0068] According to the method for preparing a semiconductor device in an embodiment of the present invention, by preparing a blocking layer, the blocking layer is located in the drift layer and surrounds the portion of the first short-circuit region extending into the drift layer. This can block the flow of electron current to the first short-circuit region when the device is forward-conducted, increase the resistance of the first short-circuit region at the initial stage of device startup, enable the PN junction on the back side of the active region to be turned on as soon as possible, and suppress the occurrence of voltage rebound.

[0069] Furthermore, in an embodiment, the preparation method further includes: preparing a collector region on the back side of the drift layer in the active region, and the collector region and the first short-circuit region are arranged laterally along the device. A first insulating structure is prepared between the collector region and the first short-circuit region, so that the second conductive type blocking layer is not in direct contact with the buffer layer and the second conductive type collector region, and electrons are blocked from passing through the first short-circuit region from the buffer layer, so that the electron path passes through the drift layer 7, and the resistance of the electron path is increased, so that the PN junction on the back side of the IGBT of the device is turned on as soon as possible under a small current, and the voltage rebound phenomenon is suppressed. Before preparing the first short-circuit region and the collector region, the preparation method further includes:

[0070] In an embodiment, a buffer layer of the first conductivity type is prepared on the back of the drift layer, wherein the first short-circuit region penetrates the buffer layer and extends into the drift layer, the collector region is located on the side of the buffer layer away from the drift layer, and the first insulating structure extends to the top of the buffer layer and contacts the barrier layer. Through the barrier layer and the first insulating structure, the resistance of the short-circuit region can be better increased at the initial stage of device startup, effectively suppressing the phenomenon of voltage rebound.

[0071] Furthermore, a second short-circuit region of the first conductivity type is prepared on the side of the buffer layer away from the drift layer in the terminal region. The back of the terminal region is designed as a first conductivity type short-circuit region, which can achieve the effect of reducing hole injection in the back collector region when the device is turned off, reducing the reverse recovery time of the device, and reducing the turn-off loss. In addition, the first conductivity type short-circuit region reasonably distributed on the back of the active region and the terminal region can avoid the concentration of current and temperature when the device is reversely conducted, thereby improving the stability and reliability of the device.

[0072] Furthermore, a second insulating structure is prepared on one side of the buffer layer away from the drift layer and at the junction of the active region and the terminal region, wherein the second insulating structure penetrates the buffer layer in the longitudinal direction of the device and extends into the drift layer. An insulating structure is introduced into the terminal region, which completely penetrates the buffer layer and extends to the drift layer 7. The existence of the insulating structure is also to allow electrons to flow from the drift layer 7, increase the resistance of the electron path, open the PN junction on the back of the active region as soon as possible, and suppress the voltage rebound phenomenon.

[0073] In the embodiment of the present invention, the method for preparing a semiconductor device further includes: covering the active area and the terminal area and preparing a collector metal layer on the first short circuit area, the second short circuit area, the collector area, the first insulating structure and the second insulating structure.

[0074] In an embodiment, the preparation method also includes: preparing an IGBT front structure and an FRD front structure on the front side of the drift layer in the active area, and preparing a terminal front structure on the front side of the drift layer in the terminal area; wherein the first short circuit area corresponds to the FRD front structure preparation, and the collector area corresponds to the IGBT front structure preparation.

[0075] Among them, an IGBT front structure and an FRD front structure are prepared on the front side of the drift layer in the active area, including: preparing a carrier storage layer on the front side of the drift layer; preparing an IGBT well region and an FRD well region of a second conductivity type on the carrier storage layer; preparing an IGBT groove and an FRD groove, wherein the IGBT groove region penetrates the IGBT well region, the carrier storage layer and extends into the drift layer, the FRD groove region penetrates the FRD well region, the carrier storage layer and extends into the drift layer, and the IGBT groove region includes a gate groove.

[0076] The preparation method further includes: preparing an insulating dielectric layer on the IGBT well region and the FRD well region; preparing an emitter metal layer on the insulating dielectric layer, and the emitter metal layer is connected to the IGBT well region, the emitter region and the emitter groove through contact holes.

[0077] In the above method for preparing the semiconductor device, the specific preparation process of each step can be selected based on the specific situation. For example, deposition, etching, photolithography, ion implantation and other processes can be used. The specific order of the preparation steps can be adjusted as needed.

[0078] Taking the manufacturing method of RC-IGBT device as an example, it includes the following steps:

[0079] (1) Providing a silicon substrate (forming a drift layer).

[0080] (2) Ion implantation forms terminal structures such as field limiting rings, cutoff rings and carrier storage layers.

[0081] (3) Etch a groove on the silicon substrate, grow gate oxide in the groove, and then deposit polysilicon.

[0082] (4) Ion implantation is performed to form a second conductivity type doped well region (IGBT well region and FRD well region) and a first conductivity type doped channel emitter region.

[0083] (5) Etch metal contact holes in the active area and terminal area.

[0084] (6) Deposition of front emitter metal.

[0085] (7) A second conductivity type barrier layer is formed in the active region by ion implantation.

[0086] (8) Ion implantation is used to form the first conductivity type short-circuit region (first short-circuit region and second short-circuit region) and the second conductivity type collector region on the back side.

[0087] (9) Ion implantation forms a first conductivity type buffer layer.

[0088] (10) Etching grooves in the terminal area and the active area and filling them to form an insulating structure (including a first insulating structure in the active area and a second insulating structure at the junction of the active area and the terminal area).

[0089] (11) Deposition of back collector metal.

[0090] In some embodiments, the area ratio of the IGBT region to the FRD region may be between 1:1 and 10:1. The area ratio of the IGBT region to the FRD region may be adjusted according to actual conditions, and the specific implementation case shall be based on actual needs.

[0091] In some embodiments, the terminal region is entirely configured as a second short-circuit region of the first conductivity type, and when the ratio of the FRD area to the IGBT area is changed, the FRD area of ​​the active region may be appropriately adjusted.

[0092] In an embodiment, the IGBT front structure of the embodiment of the present invention can also be a cellular structure of other IGBTs (for example: the cellular structure is a gate trench and three virtual trenches), and the FRD front structure can also be a cellular structure of other FRDs such as an emission trench or a combination of an emission trench and a virtual trench.

[0093] In an embodiment, the second conductive type ion doping concentrations of the IGBT well region and the FRD well region of the embodiment of the present invention are inconsistent, and the second conductive type ion doping dose of the IGBT well region can be 1E13 cm -2 -5E13 cm -2 The second conductivity type ion doping dose of the FRD well region can be 1E12 cm -2 -8E12 cm -2 The ion doping dosage of the IGBT well region and the FRD well region can be adjusted according to actual conditions, and the specific implementation case shall be based on actual needs.

[0094] In the embodiment, the depth, width and thickness of the second insulating structure passing through the buffer zone and extending into the drift layer 7 can be specifically set according to specific requirements of the forward conduction characteristics, breakdown characteristics and the like of the RC-IGBT device.

[0095] In an embodiment, the filler of the insulating structure may be an insulating material such as SiO2 or Si3Ni4, as long as it can achieve an insulating effect, and no specific limitation is made here.

[0096] In an embodiment, the shape of the first short-circuit region doped with the first conductivity type on the back side of the FRD region of the active region may be circular, triangular, rectangular, trapezoidal, ring-shaped, star-shaped or polygonal.

[0097] In an embodiment, the contact hole may be a rectangular groove, a trapezoidal groove, a tapered groove or a special-shaped groove.

[0098] like Figure 6 The flowchart of the manufacturing process of RC-IGBT according to one embodiment of the present invention includes the following steps:

[0099] S11, forming a field limiting ring in the terminal region 101 in the semiconductor substrate 200 by ion implantation and high temperature well driving.

[0100] S12 , forming a gate trench 17 , an emitter trench 18 and a dummy trench 19 of the IGBT region and an emitter trench 18 of the FRD region in the surface of the active region 100 by photolithography and reactive ion etching.

[0101] S13, growing a high-density insulating oxide layer 6 on the inner wall of each trench.

[0102] Specifically, in order to reduce crystal defects and impurities and grow an insulating oxide layer with good density, a sacrificial oxide layer is first grown on the inner wall of each groove area by high temperature oxidation, and then the sacrificial oxide layer is etched away by wet method to ensure the smoothness of the insulating oxide layer, and an insulating oxide layer is grown on the inner wall of each groove area by high temperature oxidation. The thickness of the insulating oxide layer is

[0103] S14, depositing polysilicon 5 doped with the first conductivity type on the oxide layer in the trench.

[0104] Specifically, polysilicon is deposited on the surface of the semiconductor substrate 100 through a high-temperature furnace tube and in-situ doped to form polysilicon doped with a first conductivity type.

[0105] S15, by ion implantation to form Figure 3 The second conductivity type doped well region 31 of the IGBT region shown in FIG. Figure 4 The FRD region is shown with a second conductivity type doped well region 32 .

[0106] Specifically, ion implantation is performed in the IGBT and FRD regions together, and then ion implantation is performed again in the IGBT region through a photolithography mask, thereby forming a second conductivity type doped well region 31 in the IGBT region and a second conductivity type doped base region 32 in the FRD region. The second conductivity type ion dose implanted in the IGBT region and the FRD region for the first time is 2E12-3E14cm -2 The second IGBT region second conductivity type ion implantation dose is 5E12 cm-2 -6E14 cm -2 .

[0107] S16, forming a first conductive type emitter region 2 at the gate trench region 17 of the IGBT region by ion implantation and high temperature well driving.

[0108] Specifically, a photolithography mask is used to form an injection window of the first conductive type emitter region in the gate trench region, and high-energy first conductive type ions are injected into the injection window of the first conductive type highly doped emitter region and pushed into the trap at high temperature, thereby forming a first conductive type emitter region 2 in the gate trench region 17 of the IGBT region. The first conductive type ion implantation dose is 1E15cm -2 -5E15cm -2 .

[0109] S17, etching the insulating dielectric layer 15 of the IGBT region to obtain Figure 3 The contact hole 14 is shown. By implanting the second conductivity type ions into the contact hole 14, a second conductivity type doped ohmic contact region 16 is formed.

[0110] S18, depositing emitter metal 1 on the device surface.

[0111] Specifically, a layer of metal with a thickness of 1um-5um is deposited on the surface of the device. The metal is an aluminum / silicon alloy or an aluminum / silicon / copper alloy or other materials, and is alloyed by thermal annealing to form an ohmic contact between the highly doped silicon and the metal, thereby reducing the contact resistance.

[0112] S19, thinning the back side of the semiconductor substrate 200, and forming a second conductive type barrier layer in the active area by ion implantation; the doping peak concentration of the barrier layer is 1E12cm -3 -3E14cm -3 .

[0113] S20, forming a first conductivity type short-circuit region (a first short-circuit region 111 and a second short-circuit region 112) on the back side of the semiconductor substrate by first conductivity type ion implantation and high temperature well driving process; wherein the doping concentration of the first conductivity type short-circuit region is 5E16 cm -3 -5E18 cm -3 , the short-circuit region of the first conductivity type is formed only in the FRD region and the terminal region.

[0114] S21, forming a second conductivity type collector region 10 on the back side of the semiconductor substrate by second conductivity type ion implantation and high temperature well driving process.

[0115] The ion doping concentration of the second conductive type collector region 10 is 2E16 cm -3 -5E18 cm -3The junction depth is 0.5um-1um, which can achieve the effect of controlling the emission injection efficiency. The second conductive type collector region 10 is only formed in the IGBT region.

[0116] S22, forming a first conductive type buffer layer 9 on the back side of the semiconductor substrate by ion implantation. The ion implantation dose is 5E12cm -2 -8E13cm -2 .

[0117] S23, etching a groove between the second conductivity type collector region 10 and the first conductivity type short circuit region in the active region and in the terminal region.

[0118] S24, filling the grooves in the active area and the terminal area, and forming a first insulating structure 121 and a second insulating structure 122 in the active area and the terminal area.

[0119] S25, depositing the back collector metal 13 of the RC-IGBT device.

[0120] In summary, the method for preparing a semiconductor device of an embodiment of the present invention sets a barrier layer of the second conductivity type on the top of the first short-circuit area of ​​the first conductivity type in the active area, and introduces an insulating structure at the boundary of the terminal area and the active area to increase the resistance of the back electron path, so that the PN junction on the back of the active area is turned on as soon as possible at the initial stage of device opening, which can suppress the rebound phenomenon of the device; in addition, by designing the back of the terminal area as the second short-circuit area of ​​the first conductivity type, the reverse recovery time of the device can be reduced, and the turn-off loss is reduced; the first conductivity type short-circuit area reasonably distributed on the back of the active area and the terminal area can avoid the concentration of current and temperature when the device is reversely turned on, so that the device has good stability and reliability. In summary, the preparation method of the embodiment of the present invention can not only suppress the rebound phenomenon of the device, but also reduce the reverse recovery time of the device, and also improve the reliability of the device.

[0121] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0122] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that: include: an active region and a terminal region, wherein the terminal region surrounds the active region; A drift layer of a first conductivity type, the drift layer being located in the active region and the terminal region; The active region further comprises: A first short-circuit region of a first conductivity type, the first short-circuit region is located on the back side of the drift layer, and a portion of the first short-circuit region extends into the drift layer in a longitudinal direction of the device; A barrier layer of a second conductivity type is located in the drift layer and surrounds a portion of the first short-circuit region extending into the drift layer.

2. The semiconductor device according to claim 1, wherein: The active region further comprises: A collector region of a second conductivity type, the collector region being located on the back side of the drift layer, and the collector region and the first short-circuit region being arranged in a lateral direction of the device; A first insulating structure is located between the collector region and the first short-circuit region.

3. The semiconductor device according to claim 2, characterized in that The semiconductor device comprises a buffer layer of a first conductivity type, wherein the buffer layer is located on the back side of the drift layer; The first short-circuit region penetrates the buffer layer and extends into the drift layer, and the collector region is located on a side of the buffer layer away from the drift layer; The first insulating structure extends to the top of the buffer layer and contacts the barrier layer.

4. The semiconductor device according to claim 3, characterized in that The terminal area includes: A second short-circuit region of the first conductivity type, wherein the second short-circuit region is located on a side of the buffer layer away from the drift layer.

5. The semiconductor device according to claim 4, characterized in that The semiconductor device further comprises: A second insulating structure is located on a side of the buffer layer away from the drift layer and at a junction of the active region and the terminal region.

6. The semiconductor device according to claim 5, characterized in that In the vertical direction of the device, the second insulating structure penetrates the buffer layer and extends into the drift layer.

7. The semiconductor device according to claim 5, characterized in that The semiconductor device further comprises: A collector metal layer covers the active area and the terminal area and is located on the first short-circuit area, the second short-circuit area, the collector area, the first insulating structure and the second insulating structure.

8. The semiconductor device according to claim 4, characterized in that The active region also includes an IGBT front structure and an FRD front structure on the front side of the drift layer; The termination region includes a termination front structure on the front side of the drift layer; The first short-circuit region is arranged corresponding to the FRD front structure, and the collector region is arranged corresponding to the IGBT front structure.

9. The semiconductor device according to claim 8, characterized in that The IGBT front structure comprises: A carrier storage layer, wherein the carrier storage layer is arranged on the front side of the drift layer; an IGBT well region of a second conductivity type, the IGBT well region being arranged on the carrier storage layer; An IGBT trench, wherein the IGBT trench penetrates the IGBT well region, the carrier storage layer and extends into the drift layer, and the IGBT trench comprises a gate trench; An emitter region of a first conductivity type is located at two sides of the gate trench in the lateral direction of the device.

10. The semiconductor device according to claim 9, characterized in that The FRD front structure comprises: the carrier storage layer; A second conductivity type FRD well region, the FRD well region being disposed on the carrier storage layer; An FRD trench penetrates the FRD well region, the carrier storage layer and extends into the drift layer.

11. The semiconductor device according to claim 10, characterized in that The IGBT trench further includes at least one of an emission trench and a dummy trench, and the FRD trench includes at least one of an emission trench and a dummy trench.

12. The semiconductor device according to claim 11, characterized in that The semiconductor device further comprises: An insulating dielectric layer, wherein the insulating dielectric layer is disposed on the IGBT well region and the FRD well region; An emitter metal layer, wherein the emitter metal layer is disposed on the insulating dielectric layer, and the emitter metal layer is connected to the IGBT well region, the emitter region of the first conductivity type, and the emitter trench through a contact hole.

13. A method for preparing a semiconductor device, characterized in that: The semiconductor device comprises an active region and a terminal region surrounding the active region, and the preparation method comprises: Preparing a drift layer of a first conductivity type in the active area and the terminal area; Preparing a first short-circuit region of a first conductivity type on the back side of the drift layer in the active region, wherein a portion of the first short-circuit region extends into the drift layer in the longitudinal direction of the device; A barrier layer of a second conductivity type is prepared in the drift layer, and the barrier layer surrounds a portion of the first short-circuit region extending into the drift layer.

14. The method for preparing a semiconductor device according to claim 13, characterized in that: The preparation method further comprises: A collector region is prepared on the back side of the drift layer in the active region, wherein the collector region and the first short-circuit region are arranged in a lateral direction of the device; A first insulating structure is prepared between the collector region and the first short-circuit region.

15. The method for preparing a semiconductor device according to claim 14, characterized in that: Before preparing the first short-circuit region and the collector region, the preparation method further comprises: A buffer layer of the first conductive type is prepared on the back side of the drift layer, the first short-circuit region penetrates the buffer layer and extends into the drift layer, the collector region is located on a side of the buffer layer away from the drift layer, and the first insulating structure extends to the top of the buffer layer and contacts the barrier layer.

16. The method for preparing a semiconductor device according to claim 15, characterized in that: The preparation method further comprises: A second short-circuit region of the first conductivity type is prepared on a side of the buffer layer away from the drift layer in the terminal region.

17. The method for preparing a semiconductor device according to claim 16, characterized in that: The preparation method further comprises: A second insulating structure is prepared on a side of the buffer layer away from the drift layer and located at the junction of the active area and the terminal area, wherein the second insulating structure penetrates the buffer layer in the longitudinal direction of the device and extends into the drift layer.

18. The method for preparing a semiconductor device according to claim 16, characterized in that: The preparation method further comprises: A collector metal layer is prepared covering the active area and the terminal area and on the first short-circuit area, the second short-circuit area, the collector area, the first insulating structure and the second insulating structure.

19. The method for preparing a semiconductor device according to claim 16, characterized in that: The preparation method comprises: Prepare an IGBT front structure and an FRD front structure on the front side of the drift layer in the active region, and prepare a terminal front structure on the front side of the drift layer in the terminal region; The first short-circuit region is prepared corresponding to the FRD front structure, and the collector region is prepared corresponding to the IGBT front structure.

20. The method for preparing a semiconductor device according to claim 19, characterized in that: The IGBT front structure and the FRD front structure are prepared on the front side of the drift layer in the active region, including: preparing a carrier storage layer on the front side of the drift layer; Preparing an IGBT well region and an FRD well region of a second conductivity type on the carrier storage layer; An IGBT trench and an FRD trench are prepared, wherein the IGBT trench region penetrates the IGBT well region, the carrier storage layer and extends into the drift layer, the FRD trench region penetrates the FRD well region, the carrier storage layer and extends into the drift layer, and the IGBT trench region includes a gate trench.

21. The method for preparing a semiconductor device according to claim 20, characterized in that: The preparation method further comprises: Preparing an insulating dielectric layer on the IGBT well region and the FRD well region; An emitter metal layer is prepared on the insulating dielectric layer, and the emitter metal layer is connected to the IGBT well region, the emitter region of the first conductivity type and the emitter trench through a contact hole.

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