Clock generation circuit and high-speed interconnection interface

Abstract

The invention discloses a clock generation circuit, and the circuit comprises a delay module which is connected with an external differential clock signal, and is used for carrying out the delay processing of the differential clock signal, and obtaining a plurality of delay signals; and the phase equalization module is connected with the output end of the delay module, and outputs an equant clock formed by a plurality of target clock signals to the differential clock signal and the plurality of delay signals. According to the clock generation technology provided by the invention, only the differential clocks with the same frequency are needed as input, so that the requirement on the input differential clocks is low, and extra hardware resources and power consumption do not need to be consumed; a loop structure is not used, so that extra noise is not introduced, and extra power consumption for reducing noise influence is not needed; meanwhile, the requirement for the precision of a passive device (RC) is low, and when an integrated circuit technology is used for achieving, the output four-phase clock has good equal division performance; in addition, the structure is simple, the module reusability is high, the design complexity is low, and the research and development period can be shortened.

Description

Technical Field

[0001] The present application relates to the technical field of four-phase clocks, and in particular to a clock generation circuit and a high-speed interconnection interface. Background Art

[0002] As the requirements for computing power in high-performance computing continue to increase, it is increasingly difficult for a single-chip system to meet the performance requirements of high-performance computing. At the same time, the area of ​​a single computing chip that can provide greater computing power is getting larger and larger, posing a greater challenge to the chip yield. In this case, the use of chiplet integrated system solutions to meet the challenges of high-performance computing has become an important means to solve the above problems.

[0003] In the chiplet integrated system solution, high-frequency data interaction is required between different chiplets to complete related calculations. Therefore, the high-speed interconnect interface used for data transmission between chiplets becomes one of the most important components of the chiplet integrated system. The physical layer of the high-speed interconnect directly processes high-speed data, and its performance directly affects the data transmission efficiency of the high-speed interconnect.

[0004] The performance of high-speed clock is a key factor in the implementation of high-speed interconnection physical layer. Among them, the equally divided four-phase clock (i.e., a four-phase clock with a phase difference of 90° between each phase) has been widely used in the physical layer implementation of high-speed interconnection due to its relatively rich phase information and relatively simple usage. How to efficiently implement high-quality equally divided four-phase clock is an important part of the high-speed interconnection physical layer design.

[0005] In the high-speed interconnect physical layer, differential clocks are often relatively easy to obtain, so generating equally divided four-phase clocks from differential clocks is a common solution. However, many existing solutions have obvious disadvantages in terms of hardware resources, power consumption requirements, output clock quality and design complexity, and are difficult to adapt to the high-performance, high-density and high-energy-efficiency design requirements of high-speed interconnect interfaces serving chiplet integrated systems. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, the present application provides a clock generation circuit and a high-speed interconnection interface to solve at least one defect in the prior art.

[0007] To achieve the above objectives and other objectives, the present application provides a clock generation circuit, the clock generation circuit comprising:

[0008] A delay module, connected to an external differential clock signal, for delaying the differential clock signal to obtain a plurality of delayed signals;

[0009] The phase equalization module is connected to the output end of the delay module, and performs phase equalization processing on the differential clock signal and the multiple delayed signals to output an equally divided clock composed of multiple target clock signals.

[0010] In one embodiment of the present invention, the phase equalization module includes:

[0011] Multiple phase equalizers, each of which uses one of the multiple delayed signals as a first input signal and one of the differential clock signals as a second input signal and performs phase equalization processing on the first input signal and the second input signal to obtain a target clock signal.

[0012] In one embodiment of the present invention, the clock generation circuit further includes:

[0013] The buffer module is connected to an external differential clock signal and is used to perform buffering processing on the differential clock signal to obtain a buffered clock signal, and the buffered clock signal is input into the phase equalization module.

[0014] In one embodiment of the present invention, each of the multiple phase equalizers takes one of the multiple delayed signals as the first input signal and one of the buffered clock signals as the second input signal and performs equalization processing on the first input signal and the second input signal to obtain a target clock signal.

[0015] In one embodiment of the present invention, the delay module includes:

[0016] A first delay chain, used for delaying a first signal in the differential clock signal to obtain a first delayed signal;

[0017] A second delay chain, used for delaying a second signal in the differential clock signal to obtain a second delayed signal;

[0018] a first phase equalizer, receiving the first delayed signal and the first signal, and performing equalization processing on the first delayed signal and the first signal to obtain a first target clock signal;

[0019] a second phase equalizer, receiving the first delayed signal and the second signal, and performing equal division processing on the first delayed signal and the second signal to obtain a second target clock signal;

[0020] a third phase equalizer, receiving the second delayed signal and the second signal, and performing equal division processing on the second delayed signal and the first signal to obtain a third target clock signal;

[0021] a fourth phase equalizer, receiving the second delayed signal and the first signal, and performing equal division processing on the second delayed signal and the first signal to obtain a fourth target clock signal;

[0022] Among them, the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal constitute equally divided four-phase clock signals.

[0023] In one embodiment of the present invention, the phase equalizer includes:

[0024] A first-stage inverter module, configured to perform inversion processing on the first input signal and the second input signal to obtain a first inverted signal corresponding to the first input signal and a second inverted signal corresponding to the second input signal;

[0025] A filtering module, configured to filter the first inverted signal and the second inverted signal to obtain an averaged signal;

[0026] The second stage inverter module is used to reshape the equally divided signal to obtain a target clock signal.

[0027] In an embodiment of the present invention, the filter module is a symmetrical RC filter module.

[0028] In one embodiment of the present invention, the RC filter module includes a resistor structure and a capacitor structure, the resistor structure is implemented by a transmission gate, and the capacitor structure is implemented by a capacitor-connected MOSFET transistor.

[0029] In one embodiment of the present invention, the delay module includes a plurality of delay chains, each of which includes: at least one inverter structure. If the delay module includes a plurality of inverter structures, the plurality of inverter structures are connected in series.

[0030] To achieve the above objectives and other objectives, the present application provides a high-speed interconnect interface, including the clock generation circuit.

[0031] Beneficial effects of this application:

[0032] A clock generation circuit of the present application includes: a delay module, connected to an external differential clock signal, for delaying the differential clock signal to obtain multiple delayed signals; a phase equalization module, connected to the output end of the delay module, for performing phase equalization processing on the differential clock signal and the multiple delayed signals to output an equally divided clock composed of multiple target clock signals. The clock generation technology provided by the present application only requires differential clocks of the same frequency as input, so the demand for input differential clocks is low, and no additional hardware resources and power consumption are required; and no loop structure is used, so no additional noise is introduced, so no additional power consumption is required to reduce the impact of noise; at the same time, the accuracy requirements for passive devices (RC) are low, and when the integrated circuit process is used, the output four-phase clock has good equal division; in addition, the structure of the present application is simple, the module reusability is strong, and the design complexity is low, which is conducive to shortening the research and development cycle.

[0033] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0035] Figure 1 A principle block diagram of a clock generation circuit according to an embodiment of the present application;

[0036] Figure 2 A circuit diagram of a clock generation circuit according to an embodiment of the present application;

[0037] Figure 3 A circuit diagram of a clock generation circuit according to an embodiment of the present application;

[0038] Figure 4 A circuit diagram of a phase equalizer according to an embodiment of the present application;

[0039] Figure 5 FIG. 4 is a circuit diagram of a clock generation circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0041] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application, and thus the drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed at will, and the component layout may also be more complicated.

[0042] Although the terms "first", "second", "A", and "B", etc. may be used herein to describe various elements, these elements should not be limited by these terms and are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the following technology. The term "and / or" includes a combination of multiple related items or any of the multiple related items.

[0043] As used herein, unless the context indicates otherwise, the singular form is intended to include the plural form, and it will be understood that the term "comprising" means the presence of stated features, quantities, steps, operations, elements, or combinations thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0044] Before the detailed description, it is intended to clarify that the division of components in this specification is divided only by the main function of each component. That is, two or more components to be described below can be combined into one component, or can be divided into two or more components according to more detailed functions. In addition to the main function of the component, each component to be described below can also perform some or all of the functions of other components, and some of the main functions of each component can be exclusively performed by other components.

[0045] As the requirements for computing power of high-performance computing continue to increase, it is increasingly difficult for a single-chip system solution to meet the performance requirements of high-performance computing. At the same time, the area of ​​a single computing chip that can provide greater computing power is getting larger and larger, posing a greater challenge to the chip yield. In this case, the use of chiplet integrated system solutions to meet the challenges of high-performance computing has become an important means to solve the above problems.

[0046] In the chiplet integrated system solution, different chiplets need to perform high-frequency data interaction to complete related calculations. Therefore, the high-speed interconnect interface used for data transmission between chiplets has become one of the most important components of the chiplet integrated system. The physical layer of the high-speed interconnect directly processes high-speed data, and its performance directly affects the data transmission efficiency of the high-speed interconnect. The performance of the high-speed clock is a key factor in the implementation of the high-speed interconnect physical layer. Among them, the equally divided four-phase clock (i.e., a four-phase clock with a phase difference of 90° between each phase) has been widely used in the physical layer implementation of the high-speed interconnect due to its relatively rich phase information and relatively simple usage. How to efficiently realize high-quality equally divided four-phase clock is an important content of the high-speed interconnect physical layer design. In the high-speed interconnect physical layer, differential clocks can often be obtained relatively easily. Therefore, generating equally divided four-phase clocks from differential clocks is a common solution. However, many existing solutions have obvious disadvantages in hardware resources, power consumption requirements, output clock quality, and design complexity, and are difficult to adapt to the high-performance, high-density, and high-energy-efficiency design requirements of the high-speed interconnect interface serving the chiplet integrated system.

[0047] There are several methods for generating equally divided four-phase clocks:

[0048] 1. A common method of converting a differential clock into an equally divided four-phase clock is to use a frequency division circuit to divide the differential clock by two, thereby generating an equally divided four-phase clock. Although this method is relatively simple to implement and can achieve an ideal phase division, its disadvantage is that the frequency of the required differential clock must be twice the frequency of the target four-phase clock, thus requiring additional hardware resources and power consumption when generating the differential clock;

[0049] 2. A commonly used method of converting a differential clock into an equally divided four-phase clock is to use an RC phase shift network. By using the phase shift characteristics of the RC network, the input clock is phase-advanced and phase-delayed by 45°, thereby forming a 90° phase difference. Although this method only requires the same-frequency differential clock, it has high requirements on the accuracy and matching of the phase shift device (RC). Considering the absolute deviation of passive devices in the integrated circuit process, the four-phase clock obtained by this method has poor equal division.

[0050] 3. A method of converting a differential clock into an equally divided four-phase clock is to use an injection-locked loop, using a 4-level or 4-level integer multiple oscillation loop. When injection locked, an equally divided four-phase clock is generated. This method only requires clocks of the same frequency, and the generated four-phase clock has better equality. However, this method will introduce additional noise to the output four-phase clock, and in order to reduce the impact of this noise, it usually requires a large amount of power consumption.

[0051] In view of the defects of the above-mentioned method for generating a four-phase clock, the present application provides a new clock generation circuit. Figure 1, Figure 1 A principle block diagram of a clock generation circuit according to an embodiment of the present application.

[0052] See Figure 1 As shown, the clock generation circuit includes:

[0053] The delay module 110 is connected to an external differential clock signal and is used to delay the differential clock signal to obtain a plurality of delayed signals;

[0054] The phase equalization module 120 is connected to the output end of the delay module, and performs phase equalization processing on the differential clock signal and the multiple delayed signals to output an equally divided clock composed of multiple target clock signals.

[0055] Compared with the phase clock generation method in the prior art, the present application has the following advantages:

[0056] a. Different from the frequency division technology, the clock generation circuit proposed in the present invention only needs differential clocks of the same frequency as input, so the demand for input differential clocks is low and no additional hardware resources and power consumption are required;

[0057] b. Different from the phase shift network technology, the clock generation circuit proposed in the present invention has lower accuracy requirements for passive components (RC), and its output clock has better equipartition when implemented using integrated circuit technology;

[0058] c. Different from the injection locking technology, the clock generation circuit proposed in the present invention does not use a loop structure, and thus does not introduce additional noise, and thus does not need to consume additional power to reduce the impact of noise;

[0059] The clock generation circuit proposed in the present invention has a simple structure, strong module reusability, and low design complexity, which is conducive to shortening the research and development cycle; at the same time, it can be implemented in an integrated circuit process in a full CMOS manner, which is conducive to reducing the chip area, reducing costs, and having a high tolerance for integrated circuit process deviations.

[0060] The clock generation circuit in the present application is described in detail below.

[0061] The delay module is connected to an external differential clock signal and is used to delay the differential clock signal to obtain multiple delayed signals. The delay module includes multiple delay chains, each of which is used to delay the differential clock signal and output at least one delayed signal. Multiple delay chains can output multiple delayed signals. The multiple delayed signals are used as input signals of the subsequent phase equalization module, and the phase equalization module performs phase equalization processing on the corresponding delayed signals and the differential clock signal to obtain the required multiple target clock signals. It should be noted that the multiple target clock signals are equally divided clock signals, that is, after the multiple target clock signals are arranged from large to small or from small to large in phase, the phase difference between any two adjacent target clock signals in the multiple target clock signals is the same.

[0062] The following takes the conversion of a differential clock to a four-phase clock with the same frequency as an example for explanation.

[0063] In the present application, the input signals of the clock generation circuit are the clock signal CKI_0 and the clock signal CKI_180 constituting the differential clock signal, and the output signals are the first target clock signal CKO_0, the second target clock signal CKO_90, the third target clock signal CKO_180, and the fourth target clock signal CKO_270 constituting the equally divided four-phase clock signal, and their phases differ by 90° in sequence. The clock generation circuit includes a delay module and a phase equalization module. The delay module takes the clock signal CKI_0 and the clock signal CKI_180 as inputs, and after delaying the clock signal CKI_0 and the clock signal CKI_180, obtains the first delay signal CKI_0d and the second delay signal CKI_180d, and then takes the first delay signal CKI_0d, the second delay signal CKI_180d, the clock signal CKI_0, and the clock signal CKI_180 as inputs of the phase equalization module, and selects the corresponding delay signal and clock signal for equalization processing according to the requirements to obtain the final target clock signal.

[0064] See also Figure 2 In one embodiment, the differential clock signal includes a clock signal CKI_0 and a clock signal CKI_180, both of which have the same frequency and a phase difference of 180°. The delay module includes two delay chains, namely a first delay chain and a second delay chain, and each delay chain processes one signal in the differential clock signal. For example, the first delay chain delays the clock signal CKI_0 to obtain a first delayed signal CKI_0d; the second delay chain delays the clock signal CKI_180 to obtain a second delayed signal CKI_180d. The delayed signal CKI_0d and the delayed signal CKI_180d are used as inputs of a phase divider, and the target clock signal is generated by the phase divider in combination with the differential clock signal.

[0065] In the embodiment of the present application, the delay module 110 includes a plurality of delay chains, each of which includes: at least one inverter structure. If the delay module includes a plurality of inverter structures, the plurality of inverter structures are connected in series.

[0066] It should be noted that each inverter structure is an inverter, and the number of stages of the inverter structure can be fixed or adjustable. When the inverter structure is adjustable, the inverter structure can be implemented by other logic gates, such as an AND gate. However, regardless of whether the number of stages of the inverter structure is fixed or adjustable, the number of stages of the inverter structure must be an even number.

[0067] The role of the delay chain is to add delay to the input clock signal (thus also delaying the phase). This delay can be fixed or configurable. After the delay chain, the phase of the input clock is delayed by ΔΦ. The role of the phase divider is to generate an output clock with a phase between the two input clocks. That is, when the phases of the two input clocks of the phase divider are Φ1 and Φ2, the phase of the output clock is (Φ1+Φ2) / 2, where the phase difference between the two input clocks cannot exceed 180°; the two input clocks of the phase divider need to have the same frequency, and the frequency of its output clock is also the same as the two clock frequencies.

[0068] In an embodiment of the present application, the phase equalization module includes: multiple phase equalizers, each phase equalizer takes one of the multiple delayed signals as the first input signal and one of the differential clock signals as the second input signal and equalizes the first input signal and the second input signal to obtain the target clock signal.

[0069] See also Figure 2 , the phase sharing module includes:

[0070] A first phase equalizer receives the first delayed signal and the first signal, and performs equalization processing on the first delayed signal and the first signal to obtain a first target clock signal;

[0071] A second phase equalizer receives the first delayed signal and the second signal, and performs equal division processing on the first delayed signal and the second signal to obtain a second target clock signal;

[0072] A third phase equalizer receives the second delayed signal and the second signal, and performs equal division processing on the second delayed signal and the first signal to obtain a third target clock signal;

[0073] a fourth phase divider, receiving the second delayed signal and the first signal, and performing equal division processing on the second delayed signal and the first signal to obtain a fourth target clock signal;

[0074] Among them, the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal constitute equally divided four-phase clock signals.

[0075] exist Figure 2 In the figure, the first signal is the clock signal CKI_0, and the second signal is the clock signal CKI_180. The clock signal CKI_0 is input to the first phase equalizer and the fourth phase equalizer, respectively, wherein the clock signal input to the first phase equalizer is CKI_0a, and the clock signal input to the fourth phase equalizer is CKI_0b; the clock signal CKI_180 is input to the second phase equalizer and the third phase equalizer, respectively, wherein the clock signal input to the second phase equalizer is CKI_180a, and the clock signal input to the third phase equalizer is CKI_180b.

[0076] The first phase divider takes the first delayed signal CKI_0d and the clock signal CKI_0 as input signals, divides the first delayed signal CKI_0d and the clock signal CKI_0 equally, and obtains the output first target clock signal CK0_0; the second phase divider takes the first delayed signal CKI_0d and the clock signal CKI_180 as input signals, divides the first delayed signal CKI_0d and the clock signal CKI_180 equally, and obtains the output second target clock signal CK0_90;

[0077] The third phase equalizer takes the second delayed signal CKI_180d and the clock signal CKI_180 as input signals, performs equal division processing on the second delayed signal CKI_180d and the clock signal CKI_18, and obtains the output third target clock signal CK0_180;

[0078] The fourth phase divider takes the second delayed signal CKI_180d and the clock signal CKI_180 as input signals, divides the second delayed signal CKI_180d and the clock signal CKI_0 equally, and obtains the output first target clock signal CK0_270.

[0079] See also Figure 1 , 3 In an embodiment of the present application, the clock generation circuit also includes: a buffer module 130, which is connected to an external differential clock signal and is used to buffer the differential clock signal to obtain a buffered clock signal, and the buffered clock signal is input into the phase equalization module.

[0080] It should be noted that the buffer module will also introduce a certain delay. In most cases, the delay is very small compared to the input clock period, so it can be considered that the buffer module does not change the phase of the input clock. Even when the input clock frequency is high and the phase change introduced by the buffer module cannot be ignored, the phase change introduced by the buffer module will not affect the equipartition of the output. The main function of the buffer module is to increase the driving capability of the signal, and its output clock signal is in phase with the input clock signal. When the driving capability of the input differential clock signal is strong enough, the buffer module can be omitted.

[0081] It should be noted that the differential clock signal here is the clock signal CKI_180 and the clock signal CKI_0 in the above embodiment. The buffer module includes:

[0082] The first buffer stage performs buffering processing on the clock signal CKI_0 to obtain a buffered signal CKI_0a;

[0083] The second buffer stage performs buffering processing on the clock signal CKI_180 to obtain a buffered signal CKI_180a;

[0084] The third buffer stage performs buffering processing on the clock signal CKI_180 to obtain a buffered signal CKI_180b;

[0085] The fourth buffer stage performs buffering processing on the clock signal CKI_0 to obtain a buffered signal CKI_0b.

[0086] In an embodiment of the present application, the phase equalizer includes:

[0087] A first-stage inverter module is used to perform inversion processing on the first input signal and the second input signal to obtain a first inverted signal corresponding to the first input signal and a second inverted signal corresponding to the second input signal;

[0088] A filtering module, used for filtering the first inverted signal and the second inverted signal to obtain an averaged signal;

[0089] The second stage inverter module is used to reshape the divided signal to obtain a target clock signal.

[0090] In the embodiment of the present application, the filter module is a symmetrical RC filter module.

[0091] See also Figure 4In a specific embodiment, the first-stage inverter module includes: a first inverter and a second inverter, the second-stage inverter module includes a third inverter, the filtering module includes a first resistor, a second resistor, and a filtering capacitor, the input end of the first inverter is connected to the first input signal, the output end of the first inverter is connected to one end of the first resistor, the other end of the first resistor is connected to the input end of the third inverter and forms a connection node, and the output end of the third inverter outputs the target clock signal; the input end of the second inverter is connected to the second input signal, the output end of the second inverter is connected to one end of the second resistor, the other end of the second resistor is connected to the input end of the third inverter, one end of the filtering capacitor is connected to the connection node, and the other end of the filtering capacitor is grounded.

[0092] For the phase divider, two inputs, namely the first input signal and the second input signal, are injected into the RC filter module through the first-stage inverter module, and phase equalization is achieved under the action of the symmetrical RC filter module. The second-stage inverter module shapes the signal and restores the clock signal after phase equalization. Among them, the RC filter module is only used for filtering, and does not need to achieve precise phase shift, so the accuracy requirements for the passive device RC are relatively low.

[0093] See also Figure 5 In an embodiment of the present application, the RC filter module includes a resistor structure and a capacitor structure. The resistor structure is implemented by a transmission gate, and the capacitor structure is implemented by a capacitor-connected MOSFET transistor.

[0094] The resistance structure is realized by a transmission gate, and the capacitance structure is realized by a capacitor-connected MOSFET transistor, so that the entire circuit is composed of CMOS without using passive devices (RC), and can therefore be better realized in integrated circuit technology.

[0095] In summary, the input of the clock generation circuit of the present invention is a pair of differential clocks CKI_0 and CKI_180, whose phases are 0° and 180° respectively. The four clocks CKI_0a, CKI_0b, CKI_180a, and CKI_180b obtained by the pair of differential clocks through the buffer module (the buffer module can be removed in some cases) have phases of 0°, 0°, 180°, and 180° respectively. The two clock signals CKI_0d and CKI_180d obtained by the pair of differential clocks through the delay chain have their phases increased by ΔΦ, which are ΔΦ and 180°+ΔΦ respectively. For the first phase divider, the phases of its input clocks CKI_0a and CKI_0d are 0° and ΔΦ respectively, so the phase of its output clock is ΔΦ / 2; similarly, the phases of the output clocks of the second, third, and fourth phase dividers are 90°+ΔΦ / 2, 180°+ΔΦ / 2, and 270°+ΔΦ / 2 respectively. It should be noted that when calculating the output phase of the fourth phase divider, the phase of CKI_0b needs to be replaced from 0° to 360°, otherwise the phase difference between the two input clocks of the phase divider will be greater than 180°. From the above description, it can be seen that as long as the phase divider meets its working conditions, that is, the phase delay ΔΦ provided by the delay chain is less than 180°, the four-phase clocks output by the circuit structure proposed in the present invention are 90° apart in sequence, that is, the input differential clock can be converted into an equally divided four-phase clock.

[0096] The present application provides a high-speed interconnect interface, including Figure 1-5 The clock generating circuit.

[0097] The above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A clock generation circuit, characterized in that: The clock generation circuit comprises: A delay module, connected to an external differential clock signal, for delaying the differential clock signal to obtain a plurality of delayed signals; The phase equalization module is connected to the output end of the delay module, and performs phase equalization processing on the differential clock signal and the multiple delayed signals to output an equally divided clock composed of multiple target clock signals.

2. The clock generation circuit according to claim 1, characterized in that: The phase averaging module comprises: Multiple phase equalizers, each of which uses one of the multiple delayed signals as a first input signal and one of the differential clock signals as a second input signal and performs phase equalization processing on the first input signal and the second input signal to obtain a target clock signal.

3. The clock generation circuit according to claim 2, characterized in that: The clock generation circuit further includes: The buffer module is connected to an external differential clock signal and is used to perform buffering processing on the differential clock signal to obtain a buffered clock signal, and the buffered clock signal is input into the phase equalization module.

4. The clock generation circuit according to claim 3, characterized in that: Each of the multiple phase equalizers uses one of the multiple delayed signals as a first input signal and one of the buffered clock signals as a second input signal and performs equalization processing on the first input signal and the second input signal to obtain a target clock signal.

5. The clock generation circuit according to claim 2, characterized in that: The delay module comprises: A first delay chain, used for delaying a first signal in the differential clock signal to obtain a first delayed signal; A second delay chain, used for delaying a second signal in the differential clock signal to obtain a second delayed signal; a first phase equalizer, receiving the first delayed signal and the first signal, and performing equalization processing on the first delayed signal and the first signal to obtain a first target clock signal; a second phase equalizer, receiving the first delayed signal and the second signal, and performing equal division processing on the first delayed signal and the second signal to obtain a second target clock signal; a third phase equalizer, receiving the second delayed signal and the second signal, and performing equal division processing on the second delayed signal and the first signal to obtain a third target clock signal; a fourth phase equalizer, receiving the second delayed signal and the first signal, and performing equal division processing on the second delayed signal and the first signal to obtain a fourth target clock signal; The first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal constitute equally divided four-phase clock signals.

6. The clock generation circuit according to claim 2, characterized in that: The phase equalizer comprises: A first-stage inverter module, configured to perform inversion processing on the first input signal and the second input signal to obtain a first inverted signal corresponding to the first input signal and a second inverted signal corresponding to the second input signal; A filtering module, configured to filter the first inverted signal and the second inverted signal to obtain an averaged signal; The second stage inverter module is used to reshape the equally divided signal to obtain a target clock signal.

7. The clock generation circuit according to claim 6, characterized in that: The filter module is a symmetrical RC filter module.

8. The clock generation circuit according to claim 7, characterized in that: The RC filter module includes a resistor structure and a capacitor structure. The resistor structure is implemented by a transmission gate, and the capacitor structure is implemented by a capacitor-connected MOSFET transistor.

9. The clock generation circuit according to claim 1, characterized in that: The delay module includes a plurality of delay chains, each of which includes at least one inverter structure. If the delay module includes a plurality of inverter structures, the plurality of inverter structures are connected in series.

10. A high-speed interconnect interface, characterized in that: Comprising a clock generating circuit as described in any one of claims 1-9.

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