One-out-of-two high-energy-performance clock fan-out circuit

Abstract

The invention discloses an either-or high-energy-performance clock fan-out circuit, and belongs to the field of integrated circuit signal processing. The clock fan-out circuit comprises an input buffer module used for amplifying an input signal; the input selection module is used for controlling and selecting one path of signal input in the two paths of input signals through an external level; the amplification module is used for amplifying the selected input signal and transmitting the amplified signal to the output module; and the output buffer module is used for buffering and outputting the clock signal. The clock fan-out circuit further comprises a band-gap reference module and a bias module which are used for providing stable bias voltage and current for the amplitude limiting input buffer module, the amplification module, the output buffer module and the input selection module and outputting two paths of bias voltage outwards. The high-frequency multi-channel fan-out circuit has the performance of high frequency, multi-channel fan-out, low noise and low jitter.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit signal processing, and in particular to a two-choice high-performance clock fan-out circuit. Background Art

[0002] Clock fan-out technology is a technology that distributes clock signals to multiple channels for buffer output. Clock fan-out circuits directly affect the performance of multi-channel data transmission and reception, data conversion and other systems, and are widely used in signal processing, military communications, radar, electronic countermeasures and other fields.

[0003] With the continuous improvement of the application requirements of the whole system, data conversion technology is developing towards high speed and high precision. As a key component of high-speed and high-precision digital-to-analog converters and analog-to-digital converters, the performance of the clock directly determines the signal-to-noise ratio, dynamic range and other performance of the data converter.

[0004] When the conversion clock speed is required to reach above 5GHz, the clock period is less than 200ps. The 100ps clock offset caused by typical process, power supply voltage and temperature changes will have a significant impact on the converter performance. Especially in multi-channel data conversion systems, the greater the delay deviation between channels, the lower the effective accuracy of the system, and the conversion speed is also limited. Therefore, it is very necessary to design a high-frequency, low-noise clock fan-out circuit in the system. Summary of the invention

[0005] The object of the present invention is to provide a two-choice high-performance clock fan-out circuit to solve the problems in the background technology.

[0006] In order to solve the above technical problems, the present invention provides a two-choice high-performance clock fan-out circuit, including an input buffer module, an input selection module, an amplification module, and an output buffer module;

[0007] The input buffer module amplifies the input signal;

[0008] The input selection module controls the selection of one of the two input signals through an external level;

[0009] The amplification module amplifies the selected input signal and transmits it to the output buffer module;

[0010] The output buffer module buffers and outputs the clock signal, and the output signal mode is CML level.

[0011] In one embodiment, the input selection module includes a first NPN bipolar transistor to an eighteenth NPN bipolar transistor, a first resistor to an eighth resistor; the first end of the first resistor and the first end of the second resistor are both connected to the power supply voltage VDD, and the second end of the first resistor is simultaneously connected to the base of the sixteenth NPN bipolar transistor, the collector of the second NPN bipolar transistor, and the collector of the ninth NPN bipolar transistor; the second end of the second resistor is simultaneously connected to the base of the fifteenth NPN bipolar transistor, the collector of the third NPN bipolar transistor, and the collector of the tenth NPN bipolar transistor; the collector of the first NPN bipolar transistor is connected to the power supply voltage VDD, the base is connected to the input selection signal SEL, the emitter is connected to the emitter of the second NPN bipolar transistor, the base of the second NPN bipolar tube is connected to the reverse signal SELN of the input selection signal, and the emitter is simultaneously connected to the first end of the third resistor and the fifth The collector of the NPN bipolar tube; the collector of the fourth NPN bipolar tube is connected to the power supply voltage VDD, the base is connected to the input selection signal SEL, the emitter is connected to the emitter of the third NPN bipolar tube, the base of the third NPN bipolar tube is connected to the reverse signal SELN of the input selection signal, and the emitter is simultaneously connected to the second end of the third resistor and the collector of the sixth NPN bipolar tube; the base of the fifth NPN bipolar tube is connected to the I0_N signal, the base of the sixth NPN bipolar tube is connected to the I0_P signal, and the emitter of the fifth NPN bipolar tube and the emitter of the sixth NPN bipolar tube are both connected to the collector of the seventh NPN bipolar tube; the base of the seventh NPN bipolar tube is connected to the first bias voltage, and the emitter is grounded through the fifth resistor; wherein the I0_P signal and the I0_N signal are signals after the input signals IN0_P and IN0_N are buffered by the input buffer stage;

[0012] The collector of the eighth NPN bipolar transistor is connected to the power supply voltage VDD, the base is connected to the inverse signal SELN of the input selection signal, the emitter is connected to the emitter of the ninth NPN bipolar transistor, the base of the ninth NPN bipolar transistor is connected to the input selection signal SEL, and the emitter is simultaneously connected to the first end of the fourth resistor and the collector of the twelfth NPN bipolar transistor; the collector of the eleventh NPN bipolar transistor is connected to the power supply voltage VDD, the base is connected to the inverse signal SELN of the input selection signal, the emitter is connected to the emitter of the tenth NPN bipolar transistor, the base of the tenth NPN bipolar transistor is connected to the input selection signal SEL, The emitter is connected to the second end of the fourth resistor and the collector of the thirteenth NPN bipolar tube at the same time; the base of the twelfth NPN bipolar tube is connected to the I1_N signal, the base of the thirteenth NPN bipolar tube is connected to the I1_P signal, the emitter of the twelfth NPN bipolar tube and the emitter of the thirteenth NPN bipolar tube are both connected to the collector of the fourteenth NPN bipolar tube; the base of the fourteenth NPN bipolar tube is connected to the first bias voltage, and the emitter is grounded through the sixth resistor; wherein the I1_P signal and the I1_N signal are signals after the input signals IN1_P and IN1_N are buffered by the input buffer stage;

[0013] The collector of the fifteenth NPN bipolar tube and the collector of the sixteenth NPN bipolar tube are both connected to the power supply voltage VDD, the emitter of the fifteenth NPN bipolar tube is connected to the collector of the seventeenth NPN bipolar tube, the base of the seventeenth NPN bipolar tube is connected to the second bias voltage, and the emitter is grounded through the seventh resistor; the emitter of the sixteenth NPN bipolar tube is connected to the collector of the eighteenth NPN bipolar tube, the base of the eighteenth NPN bipolar tube is connected to the second bias voltage, and the emitter is grounded through the eighth resistor.

[0014] In one embodiment, the amplification module includes nineteenth to twenty-seventh NPN bipolar tubes and ninth to thirteenth resistors; the collector of the nineteenth NPN bipolar tube and the collector of the twentieth NPN bipolar tube are both connected to the power supply voltage VDD, the base of the nineteenth NPN bipolar tube and the base of the twenty-th NPN bipolar tube are respectively connected to the power supply voltage VDD through the ninth resistor and the tenth resistor, and the emitter of the nineteenth NPN bipolar tube is simultaneously connected to the collector of the twenty-first NPN bipolar tube and the base of the twenty-fourth NPN bipolar tube. , the emitter of the twentieth NPN bipolar tube is connected to the collector of the twenty-second NPN bipolar tube and the base of the twenty-third NPN bipolar tube at the same time; the base of the twenty-first NPN bipolar tube is connected to the differential input positive port IN_P, and the base of the twenty-second NPN bipolar tube is connected to the differential input negative port IN_N; the emitter of the twenty-first NPN bipolar tube and the emitter of the twenty-second NPN bipolar tube are both connected to the collector of the twenty-fifth NPN bipolar tube; the base of the twenty-fifth NPN bipolar tube is connected to the third bias voltage, and the emitter is grounded through the eleventh resistor;

[0015] The collector of the twenty-third NPN bipolar tube and the collector of the twenty-fourth NPN bipolar tube are both connected to the power supply voltage VDD, the emitter of the twenty-third NPN bipolar tube is connected to the collector of the twenty-sixth NPN bipolar tube, and the emitter of the twenty-fourth NPN bipolar tube is connected to the collector of the twenty-seventh NPN bipolar tube; the base of the twenty-sixth NPN bipolar tube is connected to the fourth bias voltage, and the emitter is grounded through the twelfth resistor; the base of the twenty-seventh NPN bipolar tube is connected to the fourth bias voltage, and the emitter is grounded through the thirteenth resistor.

[0016] In one embodiment, the two-choice high-performance clock fan-out circuit also includes a reference module and a bias module, which are used to provide stable bias voltage and current for the input buffer module, the amplification module, the output buffer module, and the input selection module, and output two bias voltages to the outside.

[0017] In one implementation, the two-to-one high-performance clock fan-out circuit is designed and taped out based on a SiGe BiCMOS device.

[0018] The present invention provides a two-choose-one high-performance clock fan-out circuit, in which two differential input clock signals are optional, and one of the two input signals is selected through the input selection signal SEL port, thereby improving the flexibility of clock input selection and facilitating application. Compared with the traditional two-choose-one structure: first, the input selection signal SEL of the input selection module is connected to 8 switch tubes, and no matter whether the input selection signal SEL is high or low, the two tail currents remain in an open state, which can increase the speed of the switch and reduce the signal delay caused by the input selection switching. Second, a resistor is connected across the collectors of the signal input differential pair, which can ensure that current always flows through the two differential pair tubes, and the collector voltage of the differential input tube is maintained, reducing the transmission delay of the signal. The circuit load of the amplifier module adopts an active inductor structure, and the capacitance from the output stage to the ground causes a decrease in bandwidth. The circuit adds resistance to the base of the top bipolar transistor to make the output impedance show inductive properties. The gain curve can produce a peak, which increases the bandwidth of the amplifier. The present invention is based on SiGe BiCMOS device design and tape-out, giving full play to the advantage of high characteristic frequency of HBT device. It has been verified that a high-frequency, low-additional phase noise and jitter high-frequency low-noise clock fan-out circuit can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of a two-choice high-performance clock fan-out circuit provided by the present invention;

[0020] Figure 2 It is a circuit diagram of an input selection module in a two-choice high-performance clock fan-out circuit;

[0021] Figure 3 The invention is a circuit diagram of an amplification module in a two-choice high-performance clock fan-out circuit. DETAILED DESCRIPTION

[0022] The following is a further detailed description of a two-choice high-performance clock fan-out circuit proposed by the present invention in combination with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0023] The present invention provides a two-choice high-performance clock fan-out circuit, which is designed and taped out based on SiGe BiCMOS devices. Figure 1 As shown, it includes an input buffer module, an input selection module, an amplification module, an output buffer module, a reference module, and a bias module.

[0024] The input buffer module amplifies the input signal; the input selection module controls the selection of one of the two input signals through an external level; the amplification module amplifies the selected input signal and transmits it to the output buffer module; the output buffer module buffers and outputs the clock signal, and the output signal mode is CML level. The reference module and the bias module are used to provide stable bias voltage and current for the input buffer module, the amplification module, the output buffer module, and the input selection module, and output two bias voltages to the outside.

[0025] like Figure 2 As shown, the input selection module includes a first NPN bipolar transistor N1 to an eighteenth NPN bipolar transistor N18, a first resistor R1 to an eighth resistor R8; the first end of the first resistor R1 and the first end of the second resistor R2 are both connected to the power supply voltage VDD, and the second end of the first resistor R1 is simultaneously connected to the base of the sixteenth NPN bipolar transistor N16, the collector of the second NPN bipolar transistor N2, and the collector of the ninth NPN bipolar transistor N9; the second end of the second resistor R2 is simultaneously connected to the base of the fifteenth NPN bipolar transistor N15, the collector of the third NPN bipolar transistor N3, and the collector of the tenth NPN bipolar transistor N10. The collector of the first NPN bipolar transistor N1 is connected to the power supply voltage VDD, the base is connected to the input selection signal SEL, the emitter is connected to the emitter of the second NPN bipolar transistor N2, the base of the second NPN bipolar transistor N2 is connected to the reverse signal SELN of the input selection signal, and the emitter is simultaneously connected to the first end of the third resistor R3 and the collector of the fifth NPN bipolar transistor N5; the collector of the fourth NPN bipolar transistor N4 is connected to the power supply voltage VDD, the base is connected to the input selection signal SEL, the emitter is connected to the emitter of the third NPN bipolar transistor N3, the base of the third NPN bipolar transistor N3 is connected to the reverse signal SELN of the input selection signal, and the emitter is simultaneously connected to the second end of the third resistor R3 and the collector of the sixth NPN bipolar transistor N6. The base of the fifth NPN bipolar transistor N5 is connected to the I0_N signal, the base of the sixth NPN bipolar transistor N6 is connected to the I0_P signal, and the emitter of the fifth NPN bipolar transistor N5 and the emitter of the sixth NPN bipolar transistor N6 are both connected to the collector of the seventh NPN bipolar transistor N7. The base of the seventh NPN bipolar transistor N7 is connected to the bias voltage Vbias1, and the emitter is grounded through the fifth resistor R5, wherein the I0_P signal and the I0_N signal are signals after the input signals IN0_P and IN0_N are buffered by the input buffer stage.

[0026] The collector of the eighth NPN bipolar transistor N8 is connected to the power supply voltage VDD, the base is connected to the reverse signal SELN of the input selection signal, the emitter is connected to the emitter of the ninth NPN bipolar transistor N9, the base of the ninth NPN bipolar transistor N9 is connected to the input selection signal SEL, and the emitter is simultaneously connected to the first end of the fourth resistor R4 and the collector of the twelfth NPN bipolar transistor N12; the collector of the eleventh NPN bipolar transistor N11 is connected to the power supply voltage VDD, the base is connected to the reverse signal SELN of the input selection signal, the emitter is connected to the emitter of the tenth NPN bipolar transistor N10, the base of the tenth NPN bipolar transistor N10 is connected to the input selection signal SEL, and the emitter is simultaneously connected to the second end of the fourth resistor R4 and the collector of the thirteenth NPN bipolar transistor N13. The base of the twelfth NPN bipolar transistor N12 is connected to the I1_N signal, the base of the thirteenth NPN bipolar transistor N13 is connected to the I1_P signal, and the emitter of the twelfth NPN bipolar transistor N12 and the emitter of the thirteenth NPN bipolar transistor N13 are both connected to the collector of the fourteenth NPN bipolar transistor N14. The base of the fourteenth NPN bipolar transistor N14 is connected to the bias voltage Vbias1, and the emitter is grounded through the sixth resistor R6, wherein the I1_P signal and the I1_N signal are signals after the input signals IN1_P and IN1_N are buffered by the input buffer stage.

[0027] The collector of the fifteenth NPN bipolar transistor N15 and the collector of the sixteenth NPN bipolar transistor N16 are both connected to the power supply voltage VDD, the emitter of the fifteenth NPN bipolar transistor N15 is connected to the collector of the seventeenth NPN bipolar transistor N17, the base of the seventeenth NPN bipolar transistor N17 is connected to the bias voltage Vbias2, and the emitter is grounded through the seventh resistor R7; the emitter of the sixteenth NPN bipolar transistor N16 is connected to the collector of the eighteenth NPN bipolar transistor N18, the base of the eighteenth NPN bipolar transistor N18 is connected to the bias voltage Vbias2, and the emitter is grounded through the eighth resistor R8.

[0028] like Figure 3As shown, the amplification module includes nineteenth to twenty-seventh NPN bipolar transistors N19 to N27, and ninth to thirteenth resistors R9 to R13. The collector of the nineteenth NPN bipolar transistor N19 and the collector of the twentieth NPN bipolar transistor N20 are both connected to the power supply voltage VDD, the base of the nineteenth NPN bipolar transistor N19 and the base of the twentieth NPN bipolar transistor N20 are respectively connected to the power supply voltage VDD through the ninth resistor R9 and the tenth resistor R10, the emitter of the nineteenth NPN bipolar transistor N19 is simultaneously connected to the collector of the twenty-first NPN bipolar transistor N21 and the base of the twenty-fourth NPN bipolar transistor N24, and the emitter of the twentieth NPN bipolar transistor N20 is simultaneously connected to the collector of the twenty-second NPN bipolar transistor N22 and the base of the twenty-third NPN bipolar transistor N23. The base of the twenty-first NPN bipolar transistor N21 is connected to the differential input positive port IN_P, and the base of the twenty-second NPN bipolar transistor N22 is connected to the differential input negative port IN_N; the emitter of the twenty-first NPN bipolar transistor N21 and the emitter of the twenty-second NPN bipolar transistor N22 are both connected to the collector of the twenty-fifth NPN bipolar transistor N25. The base of the twenty-fifth NPN bipolar transistor N25 is connected to the bias voltage Vbias3, and the emitter is grounded through the eleventh resistor R11.

[0029] The collector of the twenty-third NPN bipolar transistor N23 and the collector of the twenty-fourth NPN bipolar transistor N24 are both connected to the power supply voltage VDD, the emitter of the twenty-third NPN bipolar transistor N23 is connected to the collector of the twenty-sixth NPN bipolar transistor N26, and the emitter of the twenty-fourth NPN bipolar transistor N24 is connected to the collector of the twenty-seventh NPN bipolar transistor N27. The base of the twenty-sixth NPN bipolar transistor N26 is connected to the bias voltage Vbias4, and the emitter is grounded through the twelfth resistor R12; the base of the twenty-seventh NPN bipolar transistor N27 is connected to the bias voltage Vbias4, and the emitter is grounded through the thirteenth resistor R13.

[0030] The clock fan-out circuit proposed in the present invention is suitable for the design of a high-frequency and high-performance clock fan-out device, and can achieve a compromise between high frequency and multi-channel fan-out, low noise, and low jitter performance based on the existing mature SiGe BiCMOS process platform.

[0031] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A two-choice high-performance clock fan-out circuit, characterized in that: It includes an input buffer module, an input selection module, an amplification module, and an output buffer module; The input buffer module amplifies the input signal; The input selection module controls the selection of one of the two input signals through an external level; The amplification module amplifies the selected input signal and transmits it to the output buffer module; The output buffer module buffers and outputs the clock signal, and the output signal mode is CML level.

2. The two-choice high-performance clock fan-out circuit according to claim 1, characterized in that: The input selection module includes a first NPN type bipolar transistor to an eighteenth NPN type bipolar transistor, a first resistor to an eighth resistor; the first end of the first resistor and the first end of the second resistor are both connected to the power supply voltage VDD, and the second end of the first resistor is simultaneously connected to the base of the sixteenth NPN type bipolar transistor, the collector of the second NPN type bipolar transistor, and the collector of the ninth NPN type bipolar transistor; the second end of the second resistor is simultaneously connected to the base of the fifteenth NPN type bipolar transistor, the collector of the third NPN type bipolar transistor, and the collector of the tenth NPN type bipolar transistor; the collector of the first NPN type bipolar transistor is connected to the power supply voltage VDD, the base is connected to the input selection signal SEL, the emitter is connected to the emitter of the second NPN type bipolar transistor, the base of the second NPN type bipolar transistor is connected to the reverse signal SELN of the input selection signal, and the emitter is simultaneously connected to the first end of the third resistor and the collector of the fifth NPN type bipolar transistor. The collector of the fourth NPN bipolar tube is connected to the power supply voltage VDD, the base is connected to the input selection signal SEL, the emitter is connected to the emitter of the third NPN bipolar tube, the base of the third NPN bipolar tube is connected to the reverse signal SELN of the input selection signal, and the emitter is simultaneously connected to the second end of the third resistor and the collector of the sixth NPN bipolar tube; the base of the fifth NPN bipolar tube is connected to the I0_N signal, the base of the sixth NPN bipolar tube is connected to the I0_P signal, and the emitter of the fifth NPN bipolar tube and the emitter of the sixth NPN bipolar tube are both connected to the collector of the seventh NPN bipolar tube; the base of the seventh NPN bipolar tube is connected to the first bias voltage, and the emitter is grounded through the fifth resistor; wherein the I0_P signal and the I0_N signal are signals after the input signals IN0_P and IN0_N are buffered by the input buffer stage; The collector of the eighth NPN bipolar transistor is connected to the power supply voltage VDD, the base is connected to the inverse signal SELN of the input selection signal, the emitter is connected to the emitter of the ninth NPN bipolar transistor, the base of the ninth NPN bipolar transistor is connected to the input selection signal SEL, and the emitter is simultaneously connected to the first end of the fourth resistor and the collector of the twelfth NPN bipolar transistor; the collector of the eleventh NPN bipolar transistor is connected to the power supply voltage VDD, the base is connected to the inverse signal SELN of the input selection signal, the emitter is connected to the emitter of the tenth NPN bipolar transistor, the base of the tenth NPN bipolar transistor is connected to the input selection signal SEL, The emitter is connected to the second end of the fourth resistor and the collector of the thirteenth NPN bipolar tube at the same time; the base of the twelfth NPN bipolar tube is connected to the I1_N signal, the base of the thirteenth NPN bipolar tube is connected to the I1_P signal, the emitter of the twelfth NPN bipolar tube and the emitter of the thirteenth NPN bipolar tube are both connected to the collector of the fourteenth NPN bipolar tube; the base of the fourteenth NPN bipolar tube is connected to the first bias voltage, and the emitter is grounded through the sixth resistor; wherein the I1_P signal and the I1_N signal are signals after the input signals IN1_P and IN1_N are buffered by the input buffer stage; The collector of the fifteenth NPN bipolar tube and the collector of the sixteenth NPN bipolar tube are both connected to the power supply voltage VDD, the emitter of the fifteenth NPN bipolar tube is connected to the collector of the seventeenth NPN bipolar tube, the base of the seventeenth NPN bipolar tube is connected to the second bias voltage, and the emitter is grounded through the seventh resistor; the emitter of the sixteenth NPN bipolar tube is connected to the collector of the eighteenth NPN bipolar tube, the base of the eighteenth NPN bipolar tube is connected to the second bias voltage, and the emitter is grounded through the eighth resistor.

3. The two-choice high-performance clock fan-out circuit according to claim 1, characterized in that: The amplification module includes nineteenth to twenty-seventh NPN bipolar tubes and ninth to thirteenth resistors; the collector of the nineteenth NPN bipolar tube and the collector of the twentieth NPN bipolar tube are both connected to the power supply voltage VDD, the base of the nineteenth NPN bipolar tube and the base of the twentieth NPN bipolar tube are respectively connected to the power supply voltage VDD through the ninth resistor and the tenth resistor, the emitter of the nineteenth NPN bipolar tube is simultaneously connected to the collector of the twenty-first NPN bipolar tube and the base of the twenty-fourth NPN bipolar tube, and the emitter of the twenty-first NPN bipolar tube is simultaneously connected to the collector of the twenty-first NPN bipolar tube and the base of the twenty-fourth NPN bipolar tube. The emitter of the PN type bipolar transistor is connected to the collector of the twenty-second NPN type bipolar transistor and the base of the twenty-third NPN type bipolar transistor at the same time; the base of the twenty-first NPN type bipolar transistor is connected to the differential input positive port IN_P, and the base of the twenty-second NPN type bipolar transistor is connected to the differential input negative port IN_N; the emitter of the twenty-first NPN type bipolar transistor and the emitter of the twenty-second NPN type bipolar transistor are both connected to the collector of the twenty-fifth NPN type bipolar transistor; the base of the twenty-fifth NPN type bipolar transistor is connected to the third bias voltage, and the emitter is grounded through the eleventh resistor; The collector of the twenty-third NPN bipolar tube and the collector of the twenty-fourth NPN bipolar tube are both connected to the power supply voltage VDD, the emitter of the twenty-third NPN bipolar tube is connected to the collector of the twenty-sixth NPN bipolar tube, and the emitter of the twenty-fourth NPN bipolar tube is connected to the collector of the twenty-seventh NPN bipolar tube; the base of the twenty-sixth NPN bipolar tube is connected to the fourth bias voltage, and the emitter is grounded through the twelfth resistor; the base of the twenty-seventh NPN bipolar tube is connected to the fourth bias voltage, and the emitter is grounded through the thirteenth resistor.

4. The two-choice high-performance clock fan-out circuit according to claim 1, characterized in that: The two-choice high-performance clock fan-out circuit also includes a reference module and a bias module, which are used to provide stable bias voltage and current for the input buffer module, the amplification module, the output buffer module, and the input selection module, and output two bias voltages to the outside.

5. The two-choice high-performance clock fan-out circuit according to claim 1, characterized in that: The two-choice high-performance clock fan-out circuit is designed and taped out based on SiGe BiCMOS devices.

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