System and method for quadrature delay clock generation

Abstract

The present disclosure provides systems and methods for quadrature delayed clock generation. A solution for generating a clock using quadrature delay may include a first plurality of in-phase (I) inverter pairs configured to output an I signal in accordance with a first input and an inverted in-phase (inverted I) signal in accordance with a second input, with a phase delay circuit coupled in parallel to each of the plurality of pairs. The solution may include a second plurality of quadrature (Q) inverter pairs configured to input and output a Q signal in accordance with a third clock signal and to input and output an inverted Q signal (inverted Q) in accordance with a fourth clock signal, and a phase detector including a plurality of cells, each of the cells may receive at least one of the I signal, the inverted I signal, the Q signal, or the inverted Q signal and include at least one or more transistors connecting gates to ground.

Description

Technical Field

[0001] The present disclosure relates generally to phase-locked loop (PLL) systems, including but not limited to systems and methods for generating clock signals in PLL designs. Background Art

[0002] Phase-locked loops (PLLs) can be used in a variety of systems such as, for example, communication systems, data processing and instrumentation, and test equipment. PLL circuitry can work with other integrated circuits or devices to provide or facilitate, for example, timing synchronization for various processing operations. PLLs can vary in design and functionality depending on their use. Summary of the invention

[0003] The present disclosure relates to a solution for providing quadrature delay high speed clock generation. When designing a PLL with a voltage controlled oscillator (VCO) operating at about 40 to 50 GHz or higher to provide data rates of about 160 to 200 Gbps or higher, the noise, parasitic capacitance, and narrow tuning range of the circuit system (e.g., quadrature delay design) may make it difficult to operate the VCO at frequencies greater than 34 GHz, limiting the data rate to about 136 Gbps. To overcome this challenge, the present solution provides a buffer chain circuit with pairs of in-phase inverters and quadrature inverters, wherein a phase delay circuit is located on the in-phase side of the buffer chain. The present solution provides a phase detector with multiple cells for processing a buffer chain output signal, wherein each cell may include one or more (e.g., a pair) of p-type metal oxide semiconductor (PMOS) transistors having a gate tied to a voltage source power supply (VSS), also known as ground or zero voltage. To this end, the present solution allows the VCO of the PLL to operate at about 40 to 50 GHz or higher and provide data rates of about 160 to 200 Gbps or higher, allowing about 20% frequency tuning range and improved performance while saving energy.

[0004] In some aspects, the present solution relates to a circuit system or system. The circuit system or system may include a first plurality of pairs of inverters configured to output an in-phase signal (I) according to a first clock signal. The first clock signal may be received as a first input. The first plurality of pairs of inverters may be configured to output an inverted I signal (inverted I) according to a second clock signal. The second clock signal may be received as a second input. Each pair of the first plurality of pairs of inverters may be coupled in parallel by a first circuit to control the phase delay between the I and the inverted I. The circuit system or system may include a second plurality of pairs of inverters configured to output a quadrature signal (Q) according to a third clock signal. The third clock signal may be received as a third input. The second plurality of pairs of inverters may output an inverted Q signal (inverted Q) according to a fourth clock signal. The fourth clock signal may be received as a fourth input. The circuit system or system may include a second circuit, the second circuit comprising a plurality of units. Each of the plurality of units may be configured to receive at least one of the I signal, the inverted I signal, the Q signal, or the inverted Q signal. Each cell may include at least one or more transistors having a gate connected to ground.

[0005] The first plurality of pairs of inverters may include a first set of four inverters connected in a first series to provide the I. The first plurality of pairs of inverters may include a second set of four inverters connected in a second series to provide the inversion I. The second plurality of pairs of inverters may include a first set of three inverters connected in a third series to provide the Q and a second set of three inverters connected in a fourth series to provide the inversion Q.

[0006] The first circuit to control the phase delay may include one of a varactor diode oriented in reverse bias or a combination of a capacitor and a diode. The first circuit to control the phase delay includes a first capacitor connected to a first diode oriented in forward bias, the first diode connected to a second diode oriented in reverse bias, the second diode connected to a second capacitor.

[0007] The circuit system or the system may include a first inverter in a first pair of the first plurality of pairs of inverters. The first inverter may include a first output connected to the first capacitor and configured in a first group of inverters in a first series connection to provide the I. The circuit system or the system may include a second inverter in the first pair of the first plurality of pairs of inverters. The second inverter may include a second output connected to the second capacitor and configured in a second group of inverters in a second series connection to provide the inverted I.

[0008] The at least one or more transistors of each cell of the second circuit may include two p-channel metal oxide semiconductor (PMOS) transistors. Each of the two PMOS transistors may be configured to operate in a triode region. Each cell of the plurality of cells may include a first n-channel metal oxide semiconductor (NMOS) transistor having a drain of the first NMOS transistor connected to a drain of a first PMOS transistor of the two PMOS transistors and a gate of the first NMOS transistor coupled to a source of a second PMOS transistor of the two PMOS transistors. Each cell of the plurality of cells may include a second NMOS transistor having a drain of the second NMOS transistor coupled to a drain of the second PMOS transistor and a gate of the second NMOS transistor coupled to a source of the first PMOS transistor.

[0009] The plurality of cells of the second circuit may include a first cell, a second cell, a third cell, and a fourth cell, which are configured such that a source of the first PMOS transistor of the first cell is connected to a source of the second PMOS transistor of the fourth cell and a source of the second PMOS transistor of the first cell is connected to a source of the first PMOS transistor of the second cell. The plurality of cells may also include a source of the first PMOS transistor of the third cell, the source of which is connected to a source of the second PMOS transistor of the second cell and a source of the second PMOS transistor of the third cell, and the source of the second PMOS transistor of the third cell is connected to a source of the first PMOS transistor of the fourth cell.

[0010] The circuit system or the system may include a quadrature generator of a phase locked loop (PLL). The quadrature generator may include an inductor to provide the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal as outputs. The first plurality of pairs and the second plurality of pairs may be part of a buffer chain circuit of a phase locked loop (PLL). The buffer chain circuit may be configured to provide at least one of the I, the inverted I, the Q, and the inverted Q to a phase detector of the PLL at a frequency between 40 GHz and 50 GHz.

[0011] In some aspects, the present solution relates to a method, such as a method for providing quadrature delayed high-speed clock generation. The method may include a first plurality of pairs of inverters providing an in-phase signal (I) as an output based on a first clock signal received as a first input. The method may include the first plurality of pairs of inverters providing an inverted I signal (Inverted I) as an output based on a second clock signal received as a second input. Each pair of the first plurality of pairs of inverters may be coupled in parallel by a first circuit to control a phase delay between the I and the inverted I. The method may include providing a quadrature signal (Q) as an output by a second plurality of pairs of inverters based on a third clock signal received as a third input. The method may include providing an inverted Q signal (Inverted Q) as an output by the second plurality of pairs of inverters based on a fourth clock signal received as a fourth input. The method may include receiving the inverted I signal, the Q signal, and the inverted Q signal by a plurality of units of a second circuit to generate an output. Each of the plurality of cells may be configured to receive at least one of the I signal, the inverted I signal, the Q signal, or the inverted Q signal and include at least one or more transistors having a gate connected to ground.

[0012] The method may include a first group of four inverters in the first plurality of pairs of inverters providing the I signal. The first group of four inverters may be connected in a first series. The method may include a second group of four inverters in the first plurality of pairs of inverters providing the inverted I signal. The second group of four inverters are connected in a second series. The method may include a first group of three inverters in the second plurality of pairs of inverters providing the Q. The first group of three inverters may be connected in a third series. The method may include a second group of three inverters in the second plurality of pairs of inverters providing the inverted Q. The second group of three inverters may be connected in a fourth series.

[0013] The method may include the first circuit for controlling the phase delay including a first capacitor, the first capacitor connected to a first diode oriented in a forward bias, the first diode connected to a second diode oriented in a reverse bias, the second diode connected to a second capacitor. The method may include the first plurality of pairs of inverters including a first inverter in a first pair of the first plurality of pairs. The first inverter may include a first output connected to the first capacitor and configured in a first set of inverters connected in a first series connection to provide the I. The method may include a second inverter in the first pair of the first plurality of pairs of inverters. The second inverter may include a second output connected to the second capacitor and configured in a second set of inverters connected in a second series connection to provide the inverted I.

[0014] The at least one or more transistors of each cell of the second circuit may include two p-channel metal oxide semiconductor (PMOS) transistors, each of the two PMOS transistors being configured to operate in a triode region. Each cell of the plurality of cells may include a first n-channel metal oxide semiconductor (NMOS) transistor having a drain of the first NMOS transistor connected to a drain of a first PMOS transistor of the two PMOS transistors and having a gate of the first NMOS transistor coupled to a source of a second PMOS transistor of the two PMOS transistors. Each cell of the plurality of cells may include a second NMOS transistor having a drain of the second NMOS transistor coupled to a drain of the second PMOS transistor and having a gate of the second NMOS transistor coupled to a source of the first PMOS transistor.

[0015] The plurality of cells of the second circuit may include a first cell, a second cell, a third cell, and a fourth cell, which are configured such that a source of the first PMOS transistor of the first cell is connected to a source of the second PMOS transistor of the fourth cell and a source of the second PMOS transistor of the first cell is connected to a source of the first PMOS transistor of the second cell. The plurality of cells of the second circuit may each include a source of the first PMOS transistor of the third cell, the source of the first PMOS transistor of the third cell being connected to a source of the second PMOS transistor of the second cell and a source of the second PMOS transistor of the third cell, and the source of the second PMOS transistor of the third cell being connected to a source of the first PMOS transistor of the fourth cell.

[0016] The method may include a quadrature generator of a phase locked loop (PLL) including an inductor and providing the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal as outputs. The first plurality of pairs and the second plurality of pairs may be part of a buffer chain circuit of a phase locked loop (PLL). The buffer chain circuit may be configured to provide at least one of the I, the inverted I, the Q, and the inverted Q to a phase detector of the PLL at a frequency between 40 GHz and 50 GHz.

[0017] In some aspects, the present solution may relate to a system. The system may include a circuit system for providing a clock signal. The circuit system may include a voltage-controlled oscillator that generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal using an inductor. The circuit system may include a buffer chain circuit. The buffer chain circuit may include a first plurality of pairs of inverters, the first plurality of pairs of inverters being configured to output an in-phase signal (I) according to a first clock signal received as a first input and to output an inverted I signal (inverted I) according to a second clock signal received as a second input. Each pair of the first plurality of pairs of inverters may be coupled in parallel by a first circuit to control a phase delay between the I and the inverted I. The circuit system may include a second plurality of pairs of inverters, the second plurality of pairs of inverters being configured to output a quadrature signal (Q) according to a third clock signal received as a third input and to output an inverted Q signal (inverted Q) according to a fourth clock signal received as a fourth input. The circuit system may include a phase detector including a plurality of cells, each of the plurality of cells being configured to receive at least one of the I signal, the inverted I signal, the Q signal, or the inverted Q signal. Each cell may include at least one or more transistors having a gate connected to ground.

[0018] The system may include the first plurality of pairs of inverters including a first set of four inverters connected in a first series to provide the I and a second set of four inverters connected in a second series to provide the inverted I. The system may include the second plurality of pairs of inverters including a first set of three inverters connected in a third series to provide the Q and a second set of three inverters connected in a fourth series to provide the inverted Q. The first circuit to control the phase delay may include one of a reverse bias oriented varactor or a combination of a capacitor and a diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] These and other aspects and features of the present embodiment will become apparent to those skilled in the art after reading the following description of the specific embodiment in conjunction with the accompanying drawings.

[0020] Figure 1 is a block diagram of an example system for quadrature-delay high-speed clock generation for a phase-locked loop (PLL).

[0021] Figure 2 is an example of a quadrature generator for use in systems with quadrature-delayed high-speed clock generation.

[0022] Figure 3 It is an example of a buffer chain circuit for a system with quadrature delay high-speed clock generation.

[0023] Figure 4 is an example of a phase detector circuit for a system with quadrature-delayed high-speed clock generation.

[0024] Figure 5 is an example of a diagram of a buffer chain output signal.

[0025] Figure 6 An example flow chart illustrating a method for providing quadrature delayed high speed clock generation according to an embodiment of the present solution. DETAILED DESCRIPTION

[0026] The present embodiment should now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples of the embodiments so that those skilled in the art can practice embodiments and alternatives that are obvious to those skilled in the art. The following figures and examples are not meant to limit the scope of the present embodiment to a single embodiment, but other embodiments are possible by interchanging some or all of the elements described or illustrated or those elements that are obvious to those skilled in the art. Some elements of the present embodiment may be implemented in part or in whole using known components, and only those parts of such known components that are necessary for understanding the present embodiment should be described, and detailed descriptions of other parts of such known components will be omitted to avoid blurring the present embodiment. The embodiments described in the context in which they are described should not be limited thereto. For example, unless otherwise specified herein, it will be apparent to those skilled in the art that embodiments described as implemented with software should not be limited to this implementation, but rather they may include embodiments implemented with hardware or a combination of software and hardware, and vice versa. In this specification, embodiments showing a single component should not be considered restrictive; on the contrary, the present disclosure is intended to cover other embodiments including multiple identical components and vice versa, unless otherwise explicitly stated herein. Furthermore, applicant does not intend that any term in the specification or claims be assigned an uncommon or special meaning unless expressly so stated.In addition, the present embodiments encompass current and future known equivalents of the known components mentioned herein by way of illustration.

[0027] When designing a quadrature phase-locked loop (PLL), it may be desirable to provide an in-phase signal (I), an in-phase anti-phase signal (Inverted I), a quadrature signal (Q), and an inverted quadrature signal (Inverted Q) at high frequencies greater than 34 GHz. The in-phase signal may include a signal that is in phase (e.g., has the same frequency and phase) as a reference (e.g., sinusoidal) signal, which the PLL may use as a reference for operations (e.g., timing) within the PLL. The inverted I signal may be the complement of the I signal (e.g., phase-shifted 180 degrees from the I signal), while the Q signal may be phase-shifted 90 degrees from the I signal and the inverted Q signal may be the complement of the Q signal (e.g., 180 degrees out of phase with respect to the Q signal and 270 degrees offset from the I signal).

[0028] In one example, the VCO of the PLL may be expected to operate at a frequency of 50 GHz or higher to support a data rate of 200 Gbps or higher. In such examples, it may be difficult to overcome the noise (e.g., phase noise), parasitic capacitance, and narrow tuning range of the PLL circuitry that generates and processes the I, inverted I, Q, and inverted Q signals, which may limit the maximum frequency and data rate of the system. When the system generates a clock signal or clock signal input that may be sent to the buffer chain circuit 110, the sections of the buffer chain circuit that processes the I and Q signals (and their inverted counterparts) may each utilize a separate varactor-based phase delay circuit to help provide tuning control and phase delay adjustment. However, when the frequency increases above 34 GHz, capacitive loading may be difficult to overcome, resulting in accumulation of clock swing and skew mismatches and clock output failures when the system approaches a 136 Gbps data rate. This makes it difficult to provide clock circuitry for a 200 Gbps data rate.

[0029] The present solution overcomes these challenges by providing a buffer chain circuit using an I inverter pair of inverters for processing I and inverted I signals and a Q inverter pair of inverters for processing Q and inverted Q signals, and a phase delay circuit coupled to the output of each of the I inverter pair. The phase delay circuit may be coupled directly or indirectly (e.g., via other circuit systems or components) to the output of each of the I inverter pair. For example, the phase delay circuit may be connected to the output of the inverter of the I inverter pair directly or via other components (e.g., one or more diodes, transistors, and capacitors). The present solution may further include a phase detector configured to include a plurality of cells for receiving and processing buffer chain circuit output signals (e.g., I, inverted I, Q, and inverted Q), such that each of the cells of the phase detector uses one or more (e.g., a pair of) PMOS transistors having their gates tied to a VSS signal (e.g., a ground or zero volt signal). The cell may further include one or more (e.g., a pair) NMOS transistors coupled in series (e.g., drain to drain) with the PMOS transistor and having their gates coupled to the source of another PMOS transistor in the circuit. The transistors and their respective portions (e.g., gates, sources, or drains) may be coupled to each other directly or indirectly (e.g., via other circuitry or components). The present solution may utilize improved buffer chain circuitry and phase detector circuitry to allow the VCO of the PLL to operate at frequencies of 50 GHz or higher, thereby allowing the system to operate at data rates of 200 Gbps or higher. The present solution may also allow for improved system performance for approximately 20% of the system's frequency tuning range while saving energy.

[0030] Figure 1A block diagram illustrating an example system 100 for quadrature delayed clock generation. System 100 may include or be coupled with circuitry for generating, processing, or providing a clock signal using a quadrature-based phase-locked loop (PLL). System 100 may include or include one or more voltage controlled oscillators (VCOs) 140 coupled with or including one or more pre-processing circuits (D2Cs) 142 and a quadrature generator 102. System 100 may also include one or more buffer chain circuits 110, a phase detector 120, and an amplification circuit 130. For example, the system 100 for providing clock signals using a quadrature PLL may include a VCO 140 including a quadrature generator 102, which may provide a first input 202 signal (e.g., an input for an I signal), a second input 204 signal (e.g., an input for an inverted I signal), a third input 206 signal (e.g., an input for a Q signal), and a fourth input 208 signal (e.g., an input for an inverted Q signal) to a buffer chain circuit 110. Upon receiving the input signals 202, 204, 206, and 208, the buffer chain circuit 110 may use its in-phase (I) inverter pair 312 and quadrature (Q) inverter pair 314 and phase delay circuit 320 to provide output signals 302 (in-phase or I signal), 304 (inverted in-phase or inverted I), 306 (quadrature or Q signal), and 308 (inverted quadrature or inverted Q signal) to the phase detector 120. After receiving the I 302, inverted I 304, Q 306, and inverted Q 308 signals, the phase detector 120 may use its unit cell 402 to provide a phase error signal (PES) 330. The amplifier circuit 130 may receive and amplify the PES 330 and provide it back to the VCO 140, which may then use it to provide feedback to the quadrature generator 102 to adjust the signals 202, 204, 206, and 208 for the next cycle (e.g., loop) of the clock generation system 100.

[0031] The system 100 may include or utilize any circuit system or combination of hardware and software to provide a clock signal, such as a quadrature PLL, for synchronizing the processing of a circuit or device. The PLL may include any circuit system that may include feedback that compares the phase of an input signal (e.g., a reference signal) with the phase of an output signal of a controlled oscillator in order to generate an output signal that is synchronized with the reference signal. The output signal may be synchronized with the reference signal, for example, in frequency and / or phase. The system 100 may compare the phase of a reference signal (e.g., in-phase signal 302) and the output from the VCO 140 to generate a phase error signal 330. For example, the VCO 140 may include the quadrature generator 102 and / or the buffer chain circuit 110. The phase error signal 330 may be filtered (e.g., by a loop filter) to remove noise and unwanted frequency components. The signal filtered by the loop filter may be used to control the VCO 140 and adjust its frequency and phase to minimize the phase error. Using the feedback loop, the system 100 can continuously compare the phase of the reference signal (e.g., I signal 302) and the VCO 140 output signal, causing the VCO 140 to adjust its frequency and phase to minimize the phase difference. By continuously minimizing the phase difference, the system 100 can achieve phase lock and maintain a stable and precise phase relationship (e.g., lock) between the VCO 140 output signal and the reference signal (e.g., I signal 302).

[0032] System 100 may include or be coupled to a quadrature PLL (e.g., directly or indirectly via one or more circuits) and used in a variety of systems or devices. For example, the quadrature PLL circuitry may be utilized or coupled (e.g., directly or indirectly) with any system or device in which precise phase synchronization is utilized. For example, system 100 may include or use a quadrature PLL circuitry that may generate, include, use, or process I 302, inverted I 304, Q 306, and inverted Q 308 signals. The quadrature PLL circuitry may be used in a communication system, such as a cellular network (e.g., a 3G, 4G, or 5G network) or a wireless local area network (WLAN), such as to modulate or demodulate a signal. System 100 may include or use a quadrature PLL circuitry in a digital broadcast system, such as a digital audio and video broadcast or a high-definition television system. System 100 may include or use a quadrature PLL circuitry in a radar system, a signal acquisition and monitoring system, or a test device. System 100 may include or use quadrature PLL circuitry in a frequency synthesis system to generate a stable and accurate output frequency.

[0033] Quadrature generator 102 may include any circuitry that can generate two periodic oscillating signals that are 90 degrees out of phase with each other. The two signals (e.g., in-phase (I) clock input signal 202 and quadrature (Q) clock input signal 205) may be used to monitor and control the phase difference between the two signals. Quadrature generator 102 may include any circuitry that generates or provides input signals 202, 204, 206, and 208, which are sometimes referred to as clock signals that may be input into buffer chain circuit 110. Quadrature generator 102 may include pre-processing circuitry (e.g., D2C) 142, which may include buffer circuitry (e.g., such as Figure 2 ), which may be processed using an inverter in parallel with a resistor and diode pair and input into the inductor 210. The clock signal (e.g., signal 202, 204, 206, or 208) may be any oscillating or electrical signal that may serve as or be used as a timing reference for coordinating and synchronizing the operation of the circuit. For example, the clock signal may include an oscillating signal that passes through the inductor 210 before being input into the buffer chain circuit 110. For example, the quadrature generator 102 may generate or produce a signal 202, also referred to as a first clock signal 202, and an input signal 206, also referred to as a second clock signal 206. The first clock signal 202 and the second clock signal 206 may be generated, provided, or used by an inverter pair 312 (also referred to as an I inverter pair 312) of the buffer chain circuit 110 to generate an in-phase 302 (e.g., I 302) and a quadrature 306 (Q 306) signal. Likewise, the quadrature generator 102 may generate or provide an input signal 206, also referred to as the third clock signal 206, and an input signal 208, also referred to as the fourth clock signal 208. The third clock signal 206 and the fourth clock signal 208 may be generated, provided, or used by an inverter pair 314 (also referred to as the Q inverter pair 314) to produce the Q 306 and inverted Q 308 signals.

[0034] The quadrature generator 102 may be included within or coupled (e.g., directly or indirectly) to the VCO 140, which also includes a buffer chain circuit 110, allowing the VCO 140 to generate and provide an I 302 signal, a Q 306 signal, and an inverted I 304 and an inverted Q 308. The quadrature generator 102 may include functionality (e.g., circuitry) for generating or providing inverted counterparts of the I 302 and Q 306 signals (e.g., inverted I 304 and inverted Q 308). In some embodiments, the quadrature generator 102 may include functionality for generating inputs for providing inverted I and Q signals (e.g., input 204 for inverted I signal, input 208 for inverted Q signal) to be processed by the buffer chain circuit 110. The quadrature generator 102 may generate the inputs of the I and Q signals (e.g., 202 and 206) such that they are phase-shifted by 90 degrees (e.g., a quarter cycle or half π offset) from each other. Similarly, quadrature generator 102 may generate inputs of inverted I and Q signals (e.g., 204 and 208), which may be phase-shifted 90 degrees from one another. Signals 202, 204, 206, and 208 may be provided such that they are orthogonal to one another (e.g., signal 202 is 90 degrees from signal 204, signal 204 is 90 degrees from signal 206, signal 206 is 90 degrees from signal 208, and signal 208 is 90 degrees from signal 202). Signals 202, 204, 206, and 208 may be used for various purposes, including generating quadrature local oscillator signals, performing phase detection, or providing phase synchronization. Quadrature generator 102 may be coupled (e.g., directly or indirectly) to or include buffer chain circuit 110 for processing, filtering, or controlling phase or delay between signals (e.g., I, inverted I, Q, and inverted Q) generated by the quadrature generator.

[0035] The quadrature generator 102 may be implemented in a variety of ways. For example, the quadrature generator 102 may include or use digital and / or analog circuitry, such as operational amplifiers (op-amps), filters, and phase shift networks, to produce a desired phase relationship between the I and Q signals. The quadrature generator 102 may include a digital design, where the I and Q signals may be generated using digital signal processing techniques, such as using digital mixers, digital filters, and delay elements to process the phase and frequency of the input signals to achieve a desired quadrature relationship. For example, the quadrature generator 102 may include a Hilbert transform to utilize a technique that can generate quadrature components of a signal by applying a Hilbert transform to an input signal to derive the I and Q signals.

[0036] The amplifier circuit 130 may include any circuitry for amplifying an input signal, such as the phase error signal 330. The amplifier circuit 130 may include a combination of NMOS and / or PMOS devices for amplifying any of the signals described herein. The amplifier circuit 130 may include an operational amplifier (op-amp) 130, which may include any circuit for amplifying and / or processing analog signals. The amplifier circuit 130 may include, for example, a high gain differential amplifier having multiple inputs, such as inputs for inverting and non-inverting signals, and one or more outputs. The amplifier circuit 130 may receive the phase error signal 330 and / or a control signal from the phase detector 120 and amplify the received signal to provide an output of the quadrature generator 102 and / or the VCO 140.

[0037] For example, the amplification circuit 130 (e.g., operational amplifier 130) can be used to multiply the I 302 and Q 306 signals together and produce an output that is proportional to the product of their amplitudes. For example, the output of the operational amplifier 130 can correspond to the phase difference between the I 302 and Q 306 signals. The resulting output can be further processed to generate a control voltage for the VCO 140. For example, the operational amplifier 130 can be used as a mixer or a phase comparator to combine the I 302 and Q 306 signals and perform a phase comparison. The operational amplifier 130 can multiply or compare the phase between any of the signals 302, 304, 306, and / or 308. For example, the output of the operational amplifier 130 can include the phase difference or product of any of the signals 302, 304, 306, and 308. When the operational amplifier 130 is used to provide the phase difference, the output from the operational amplifier 130 can be converted into a control voltage to adjust the VCO 140 frequency and achieve phase locking of the system 100 (e.g., a PLL circuit).

[0038] Voltage controlled oscillator (VCO) 140 may include any circuitry or combination of hardware and software for generating an output signal whose frequency is controlled by a voltage input (e.g., an input from operational amplifier 130). VCO 140 may include circuitry that provides an oscillating signal, producing a periodic waveform (e.g., a sine wave or a square wave) whose frequency can be adjusted by applying a control voltage. VCO 140 may include circuitry for generating an output signal, which may be referred to as a local oscillator (LO) signal. The LO signal of VCO 140 may be phase locked to a reference signal (e.g., I signal 302) through a feedback loop. The phase and frequency of the VCO 140 output signal (e.g., LO) may be continuously adjusted to minimize the phase difference between the reference signal (e.g., in-phase 302) and the VCO output signal (e.g., LO).

[0039] VCO 140 may include or be connected (e.g., directly or indirectly) to pre-processing circuit 142 (e.g., D2C) and / or quadrature generator 102. VCO 140, pre-processing circuit 142, or quadrature generator 102 may receive amplified phase error signal 330 output from phase detector 120 and use it to adjust a voltage that controls the frequency of VCO 140. In doing so, VCO 140 may ensure that its output closely tracks a signal (e.g., LO) of I 302 signal, thereby maintaining a desired quadrature relationship with other signals (e.g., I 304, 306, and 308).

[0040] The VCO 140 may vary based on the design. The VCO 140 may include any combination of hardware and software, including or providing an electronic oscillator whose oscillation frequency is controlled by a voltage input. In some embodiments, the VCO 140 may include a pre-processing circuit 142 and a quadrature generator 102. In some embodiments, the VCO 140 may include a buffer chain circuit 110. For example, the VCO 140 may utilize its own quadrature generator 102 to generate the input signals 202, 204, 206, and 208, and utilize its own buffer chain circuit 110 to utilize inverters 310, which may be arranged as an I inverter pair 312, a Q inverter pair 314, and a phase delay circuit 320 to provide I 302, inverted I 304, Q 306, and inverted Q 308 signals to the phase detector 120.

[0041] The buffer chain circuit 110 may include any combination of hardware and software for processing the input signals 202, 204, 206, and / or 208 to provide output signals I 302, inverted I 304, Q 306, and / or inverted Q 308. The buffer chain circuit 110 may include inverters 310 organized into an I inverter pair 312 and a Q inverter pair 314. The buffer chain circuit 110 may include a phase delay circuit 320 for setting, maintaining, or controlling a phase delay or offset between the I 302 signal and its inverted counterpart, such as the inverted I signal 304, which may be 180 degrees out of phase with the I 302. For example, the inverted I 304 may be a differential signal of the I 302 signal (e.g., 180 degrees offset). The buffer chain circuit 110 may also include functionality for setting, maintaining, or controlling a phase delay or offset between the Q 306 signal and its inverse counterpart (e.g., inverted Q signal 308) such that the inverted Q signal 308 is also 180 degrees out of phase with the Q 306 signal. Similarly, the buffer chain circuit 110 may include functionality (e.g., phase delay circuit 320 and I inverter pair 312 and Q inverter pair 314) for maintaining the I 302 signal 90 degrees out of phase with the Q signal, and therefore maintaining the inverted I signal 304 also 90 degrees out of phase with the inverted Q signal.

[0042] Phase detector (PD) 120 may include any circuitry for comparing the phase difference between an input reference signal (e.g., I 302 signal) and a feedback signal (e.g., a signal generated by buffer chain circuit 110 or VCO 140). The output of phase detector 120 may be used to adjust the VCO frequency to minimize the phase difference between the reference signal and the feedback signal. Phase detector 120 may include a unit 402 for receiving and processing each of the quadrature signals (e.g., I 302, inverted I 304, Q 306, and inverted Q 308). Phase detector 120 may process or operate on signals 302, 304, 306, and 308 to produce an output representing the phase difference between the reference signal and the feedback signal.

[0043] The phase detector 120 may receive an I 302 signal (e.g., a reference signal) from the buffer chain circuit 110 to compare with the feedback signal from the VCO. The phase detector 120 may also receive and use an inverted I 304 (e.g., a complement of the I 302 signal), a Q 306 signal, and an inverted Q signal 308 (e.g., a complement of Q 306). The phase detector 120 may multiply the in-phase (e.g., I 302 and / or inverted I 304) and quadrature (e.g., Q 306 and inverted Q 308) signals, and then subtract the product of the inverted in-phase and inverted quadrature signals to provide a phase error signal 330, which may be represented as PES 330=(I 302×Q 306)−(inverted I 304×inverted Q 308). The phase error signal 330 may then be low pass filtered to remove high frequency components and provided to the VCO 140 to control the frequency of the VCO 140. By adjusting the frequency of VCO 140 based on PES 330 , system 100 can achieve phase synchronization between the input reference signal and the feedback signal, generating an output clock signal that is phase locked to the input reference signal.

[0044] Figures 2 to 4 Instructions for use Figure 2 The orthogonal generator 102 shown in Figure 3 The buffer chain circuit 110 and Figure 4 Example system 100 of generating a clock with phase detector 120. At a high level, Figure 2 The quadrature generator 102 instance may utilize circuitry including an inductor 210 to provide inputs 202 , 204 , 206 , and 208 , which may be provided to the buffer chain circuit 110 . Figure 3The example buffer chain circuit 110 illustrated in FIG. 1 may receive inputs 202, 204, 206, and 208 and process them using inverters 310 (e.g., arranged in an I inverter pair 312 and a Q inverter pair 314) and a fixed delay circuit to generate, process, filter, or provide I 302, inverted I 304, Q 306, and inverted Q 308 signals. Signals 302, 304, 306, and 308 may then be provided to Figure 4 4. The example phase detector 120 illustrated in FIG. 4 is processed using four cells 402 formed using PMOS transistors 404 and NMOS transistors 406 interconnected via their respective sources 410, drains 412, and gates 414.

[0045] Figure 2 is an example of a quadrature generator 102 for a system for quadrature delay high-speed clock generation. The quadrature generator 102 may include, for example, a sinusoidal signal from a device or circuit that provides an oscillating signal. The signal may then be inserted into a buffer circuit. The buffer circuit may be coupled to a coil to assist in impedance matching, filtering or tuning of the signal or signal conditioning. The buffer may provide two outputs, including a positive VCO signal and a negative VCO signal. The two VCO signals may be processed via a set of multiple inverters (e.g., 120 inverters), which may be placed in parallel with a resistor circuit having one or more resistors and a reverse biased diode. The reverse biased diode may be any diode (e.g., a PN junction or a varactor) connected in a reverse bias orientation (e.g., such that the voltage across the diode is in a direction that hinders or stops the flow of current across the diode). The diode may be connected directly or indirectly (e.g., via one or more intervening circuits or components). A varactor, which may also be referred to as a varactor, may be placed or connected in a reverse bias orientation. A varactor or varactor may include any semiconductor device (e.g., a pn junction diode) having a voltage-dependent capacitance. The varactor may also be connected or positioned in forward bias. The varactor may be controlled by an amplifier circuit for loop control. The positive and negative VCO frequency outputs may be provided as inverted clock signals modulated by their inductors 210.

[0046] The quadrature generator 102 may include circuitry for generating one or more signals, such as a function for creating signals 202, 204, 206, and 208. The quadrature generator 102 may include, or be directly or indirectly connected to, a pre-processing circuit 142, which may utilize one or more inverters 310, diodes, and resistors, the output of which may be input into one or more inductors 210. The pre-processing circuit 142 (also referred to as a D2C) may include a digital / analog converter to convert digital to analog signals. For example, the pre-processing circuit 142 may use a digital / analog converter to convert a digital control word representing a desired frequency or phase adjustment from a PLL from a digital loop filter or digital control circuitry into an analog voltage that controls the frequency and phase of the VCO 140. The pre-processing circuit 142 may include a divide-by-two counter to divide the frequency of the input signal, for example, by 2 or 4. The D2C may be used in the feedback path of the PLL to create a frequency divider that ensures that the output signal of the VCO 140 is locked to a reference signal. By dividing the frequency, the D2C may allow precise adjustment of the VCO 140 output frequency.

[0047] Inductor 210 (also referred to as inductor coil 210) may include any configuration or amount of conductive material (e.g., metal wiring) forming a loop to produce induction. Inductor 210 may be included in pre-processing circuit 142 and may receive output from pre-processing circuit 142 to generate signals 202, 204, 206, and 208. The number of loops of the wiring may be configured (e.g., tuned) to match impedance, filter, or tune the signal to increase or enhance the swing of the signal output of the load. Inductor 210 may provide four output signals that may be used as Figure 3 The four output signals may include a first input 202 (eg, an input of an I signal 302), a second input 204 (eg, an input of an inverted I 304), a third input 206 (eg, an input of a Q signal 306), and a fourth input 208 (eg, an input of an inverted Q 308).

[0048] Figure 3 An example 300 of the system 100 is described, in which the buffer chain circuit 110 receives a Figure 2 The input signals 202, 204, 206 and 208 are generated by the quadrature generator 102 and provide corresponding outputs I 302, inverted I 304, Q 306 and inverted Q 308. The output signals I 302, inverted I 304, Q 306 and inverted Q 308 may be provided to the phase detector 120, which may then process these inputs and provide a phase error signal 330 to the amplification circuit 130 (e.g., operational amplifier 130). According to the present solution, in combination with Figure 2 The orthogonal generator 102 and Figure 4The phase detector 120 and the buffer chain circuit 110 may provide the clock generation system 100 with quadrature delays.

[0049] The buffer chain circuit 110 may include a configuration or arrangement of four or five inverters 310 connected in a first series connection and used to provide an I 302 signal based on the first input 202 or the second input 204. Generating the signal 302, 304, 306, or 308 based on the input clock signal 202, 204, 206, or 208 may include using a circuit system (e.g., the buffer chain circuit 110) that processes the input clock signal 202, 204, 206, or 208 to generate, process, or provide an output signal (e.g., 302, 304, 306, or 308). For example, the first input 202 (e.g., the first clock signal) may be input to an I inverter pair 312 of a plurality of I inverter pairs 312 that generate a non-inverting output 302. For example, the I 302 signal may be generated as an output from a last of four cascaded I inverter pairs 312 , where the first input 202 (eg, the first clock signal) is an input to the first inverter 310 in the first I inverter pair 312 .

[0050] The input to the phase detector 120 from the first series of inverters 310 (e.g., the inverted I 304 signal) may be extracted after the fourth inverter 310 in the first series. Similarly, a second configuration of five inverters 310 connected in a second series may be used to provide the inverted I 304 signal based on the second input 204 or the first input 202, while the input to the phase detector 120 from the second series may be extracted after the fourth inverter 310 in the second series. A third configuration of four inverters 310 connected in a third series may be used to provide the Q 306 signal based on the third input 206 or the fourth input 208, while the input to the phase detector 120 from the third series (e.g., the inverted Q 308 signal) may be extracted after the third inverter 310 in the third series. Similarly, a fourth configuration of four inverters 310 connected in a fourth series may be used to provide the Q 306 signal based on the third input 206 or the fourth input 208, wherein the input to the phase detector 120 from the fourth series may be extracted after the third inverter 310 in the fourth series. Thus, I 302 and inverse I 304 may be provided to the phase detector 120 after being processed by the series connected four inverters 310 in each of the two series connected inverters for the I 302 and inverse I 304 inverter arrangements. Similarly, Q 306 and inverse Q 308 may be provided to the phase detector 120 after being processed by the series connected three inverters 310 in each of the two series connected inverters for Q 306 and inverse Q 308.

[0051] The I-inverter pairs 312 may each include a pair of inverters 310, including an inverter 310 from a first series (e.g., an inverter 310 for processing or generating I 302) and an inverter 310 from a second series (e.g., an inverter 310 for processing or generating inversion 304). The buffer chain circuit 110 may include five I-inverter pairs 312, wherein the output signal (e.g., 302, 304) is extracted or provided after the fourth I-inverter pair 312 in the series of I-inverter pairs 312.

[0052] The I-inverter pairs 312 may be organized or arranged such that each of the two inverters 310 in the I-inverter pairs 312 has its output (e.g., the output of the inverter 310) coupled to one of the two ends of a phase delay circuit 320 connected in parallel to the I-inverter pairs 312. For example, a first inverter 310 from a first I-inverter pair 312 (e.g., from a first series connection for the I 302 signal) may have its output coupled to a first input of the phase delay circuit 320, while a second inverter 310 from the same first I-inverter pair 312 (e.g., from a second series connection for the inverted I 304 signal) may have its output coupled to another input of the same phase delay circuit 320. Thus, each of the first four of the five I-inverter pairs 312 of the first and second series inverters 310 may each have its own individual phase delay circuit 320 coupled to the output of the inverter 310 of the given I-inverter pair 312.

[0053] Phase delay circuit (PDC) 320 may include any circuitry for establishing, fixing, setting, maintaining, or correcting a delay in phase (e.g., a phase delay) between inputs 202, 204, 206, and 208 or outputs I 302, inverted I 304, Q 306, and inverted Q 308. The phase delay established or fixed by PDC 320 may be a 90 degree phase between the I and Q signals or the Q and inverted I signals. The phase delay may include a 180 degree phase shift between the I and inverted I signals or between the Q and inverted Q signals. For example, PDC 320 may maintain a 90 degree phase difference between the I 302 and Q 306 signals, either alone or in combination with other circuitry of buffer chain circuit 110. PDC 320 may also maintain a 180 degree phase difference between the I 302 and inverted I 304 signals, either alone or in combination with other circuitry of buffer chain circuit 110. PDC 320 may ensure that each of I 302, Q 306, inverted I 304, and inverted Q 308 are spaced 90 degrees apart from one another, thereby maintaining an orthogonal distribution of signal outputs.

[0054] The PDC 320 may include a combination of capacitors, resistors, and / or diodes. The PDC 320 may include an input capacitor that may be coupled to the output of the inverter 310. For example, a first input capacitor of the PDC 320 may be coupled to the output of the first inverter 310 in the I inverter pair 312 and a second input capacitor of the PDC 320 may be coupled to the output of the second inverter 310 in the I inverter pair 312. The input capacitor of the PDC 320 may be coupled (on an end opposite to the inverter 310) to a diode, such as a varactor or any diode (e.g., a PN junction) that may be arranged or configured to be forward biased oriented (e.g., a voltage across the diode allows current to flow naturally through the diode) or reverse biased oriented (e.g., a voltage across the diode prevents or stops the flow of current across the diode). For example, the varactor may be disposed or connected in a reverse biased orientation. The varactor may be connected or disposed under forward bias. The varactor may be controlled by an amplification circuit for loop control. Coupled to the diodes (eg, between two diodes arranged with opposite biases to each other), there may be a node for tuning or adjusting an input signal to the phase delay circuit 320, or for readout (eg, output analysis).

[0055] For example, the PDC 320 may include a first input capacitor connected to a first inverter 310 in the I inverter pair 312, the first inverter 310 also coupled to a forward biased diode, which may be further coupled to another diode in an opposite bias (e.g., reverse bias), which may be further coupled to a second input capacitor for connecting to the output of the other inverter 310 in the I inverter pair 312. An input signal for tuning the PDC 320 may be provided between the two diodes. The diode used may include any type of diode, such as a PN junction diode, a varactor diode, or any other diode. The buffer chain circuit 110 may include four PDCs 320 for the first four I inverter pairs 312, after which the output signal may be extracted and provided to the phase detector 120. In some embodiments, the PDC 320 is omitted or excluded from the Q inverter pairs 314 on the third and fourth series inverters 310.

[0056] Figure 4 is an example of a phase detector 120 circuit for system 100 for quadrature-delay high-speed clock generation. Figure 4The example phase detector 120 of may include four unit cells 402 for processing input signals (e.g., signals 302, 304, 306, and 308). Each cell 402 may include a combination of transistors (e.g., NMOS 406 and PMOS 404) to compare the phase of the input signal and a reference signal, including the in-phase (302 and 304) component and the quadrature (306 and 308) component of the signal. The output of the cell 402 may provide one or more phase error signals 330, which may be used to drive the VCO 140 to achieve phase synchronization between the input and reference signals in the PLL circuit.

[0057] The cells 402 may include any combination of transistors or other circuit elements (e.g., capacitors, diodes, or resistors) for processing one of the I 302, inverted I 304, Q 306, and inverted Q 308 signals. Each unit cell 402 may include two PMOS 404 transistors coupled with two NMOS 406 transistors. Each of the PMOS 404 and NMOS 406 transistors may include a source 410, a drain 412, and a gate 414. Each cell 402 may receive one of the four signals (e.g., 302, 304, 306, and 308) output from the buffer chain circuit 110. For example, the first cell 402 may receive the I 302 signal, the second cell 402 may receive the Q 306 signal, the third cell 402 may receive the inverted I 304 signal, and the fourth cell 402 may receive the inverted Q 308 signal.

[0058] Each of the cells 402 may couple two sources 410 of two NMOS 406 transistors to an input signal (e.g., 302, 304, 306, or 308). The drain 412 of the same NMOS 406 transistor may be coupled to the drains 412 of the two PMOS 404 on each side, such that each NMOS 406 is coupled to the PMOS 404 drain 412 to drain 412. Each of the PMOS 404 transistors may couple a gate 414 to a VSS signal (e.g., ground). Each of the PMOS 404 transistors may have its source 410 coupled to the gate of another NMOS 406 transistor that is different from the NMOS 406 transistor to which the PMOS 404 is connected via the drain 412. In this configuration, each unit cell 402 may include two NMOS 406 interconnected drain-to-drain with two PMOS 404 whose gates are coupled to VSS (e.g., ground) and where the source of the PMOS 404 is coupled to the gate of the NMOS 406 opposite the NMOS 406 to which the PMOS 404 is drain-to-drain connected. Thus, each of the PMOS 404 transistors may be configured to operate in a triode region. The triode region may include a linear operating region of a transistor, such as an operating region where the relationship between input and output is linear, as opposed to saturation or cutoff. The triode region may include an operating region of a transistor device (e.g., a BJT or MOSFET) where the drain current is controlled by three terminals, rather than two terminals as in a saturated state. The output from the phase detector 120 may be read using output signals labeled P0, P90, P180, and P270, which correspond to the phase angles of the quadrature signal outputs, and (e.g., at Figure 5 Available in.

[0059] Figure 5 is an example of a graph of a signal output from the buffer chain circuit 110 and / or the phase detector 120 . Figure 5 Graph 502 of a sinusoidal reference in-phase 302 signal is illustrated. Graph 504 provides a circular phase graph on an I axis 510 and a Q axis 512. Graph 504 illustrates a compiled example of the output of signals 302, 304, 306, and 308 forming a circle on the IQ plane. Graph 506 illustrates a graph of I 302, Q 306, inverted I 304, and inverted Q 308, each of which has its phase spaced 90 degrees (e.g., T / 4) from the phase of the other. Thus, I 302 leads Q 306 by 90 degrees, which leads inverted I (IB) 304 by 90 degrees, which leads inverted Q (QB) 308 by 90 degrees.

[0060] The present solution may involve a circuit system corresponding to the system 100 for clock generation. The circuit system may include a buffer chain circuit 110 having a first plurality of I inverter pairs 312, which may be configured to process and / or output an in-phase signal (I) 302 according to a first clock signal 202 received as a first input. The first plurality of I inverter pairs 312 may be configured to process and / or output an inverted I 304 signal (Inverted I) according to a second clock signal 204 received as a second input. Each of the first plurality of I inverter pairs 312 may be coupled in parallel by a first circuit, such as a phase delay circuit 320, to control a delay between the I 302 signal and the inverted I 304 signal. The phase delay circuit 320 may be connected between the outputs of each of the inverters 310 in the I inverter pairs 312.

[0061] The circuit system, such as the buffer chain circuit 110, may include a second plurality of Q inverter pairs 314 configured to output a quadrature signal (Q) 306 based on the third clock signal 206 received as a third input. The second plurality of Q inverter pairs 314 may be configured to output an inverted Q signal 308 (Inverted Q) based on the fourth clock signal 208 received as a fourth input. The circuit system may include three Q inverter pairs 314 for outputting the signals 306 and 308 for input into the phase detector 120.

[0062] The circuit system may include a second circuit (e.g., phase detector 120) that may include a plurality of cells 402. Each of the plurality of cells 402 may be configured to receive at least one of the I signal 302, the inverted I signal 304, the Q signal 306, or the inverted Q signal 308. Each cell 402 may include at least one or more transistors, such as a bipolar junction transistor or BJT, a metal oxide semiconductor field effect transistor or MOSFET, a junction gate field effect transistor or JFET, or any other transistor. Each cell 402 may include one or more transistors (e.g., MOSFETs such as PMOS or NMOS) having the gate connected to VSS or ground.

[0063] The first plurality of I inverter pairs 312 may include a first set of four inverters 310 connected (e.g., directly or indirectly) in a first series arrangement or connection to provide I 302. The first plurality of I inverter pairs 312 may include a second set of four inverters 310 connected in a second series arrangement or connection to provide inverted I 304. The second plurality of Q inverter pairs 314 may include a first set of three inverters 310 connected in a third series arrangement or connection to provide a Q 306 signal and a second set of three inverters 310 connected in a fourth series arrangement or connection to provide an inverted Q 308 signal.

[0064] The first circuit (e.g., PDC 320) for controlling the phase delay may include one of a reverse bias oriented variable capacitance diode (e.g., varactor) or a combination of a capacitor and a diode. The first circuit (e.g., PDC 320) for controlling the phase delay may include a first diode connected to a forward bias oriented, the first diode connected to a second diode oriented in reverse bias, the second diode connected to a second capacitor. PDC 320 may include a first contact from the first capacitor coupled to the output from the first inverter 310 in the I inverter pair 312 and a second contact from the first capacitor coupled to the first diode forward biased relative to the first capacitor and relative to the first branch of the resistor circuit in parallel with the first diode. The resistor circuit may include a tuning input signal for tuning the phase. The output from the first diode may be input to the reverse biased second diode, the output from the second diode may be coupled to the second branch of the resistor circuit in parallel with the two diodes. The output of the second diode may be coupled to the first input of the second capacitor, the second input of the second capacitor may be coupled to the output of the second inverter 310 in the same I inverter pair 312. This same arrangement of a PDC 320 coupled in parallel with an I inverter pair 312 may be repeated for each of four of the first five inverter pairs 312 of the buffer chain circuit 110 .

[0065] A first inverter 310 in a first I-inverter pair 312 in the first plurality of I-inverter pairs 312 may include a first output connected to a first capacitor of the PDC 320. The first inverter 310 may be configured in a first set of inverters connected in a first series of inverters 310 to provide the I 302 signal. A second inverter 310 in a first I-inverter pair 312 in the first plurality of I-inverter pairs 312 may include a second output connected to a second capacitor of the PDC 320. The second inverter 310 may be configured in a second set of inverters connected in a second series to provide the inverted I 304 signal.

[0066] At least one or more transistors (e.g., PMOS 404 or NMOS 406) of each cell 402 of the second circuit (e.g., phase detector 120) may include two p-channel metal oxide semiconductor (PMOS) 404 transistors. Each of the two PMOS 404 transistors may be configured to operate in a triode region. Each PMOS 404 may be configured to operate in a triode region based on its gate 414 coupled to VSS, while its source 410 is coupled to the gate 414 of an NMOS 406 that is different (e.g., opposite) from the NMOS 406 to which the drain 412 of the PMOS 404 is connected.

[0067] For example, each cell 402 may include a first n-channel metal oxide semiconductor (NMOS) 406 transistor having a drain 412 of the first NMOS 406 transistor connected to a drain 412 of a first PMOS 404 transistor of the two PMOS 404 transistors. The first NMOS 406 may have a gate 414 of the first NMOS 406 transistor coupled to a source 410 of a second PMOS 404 transistor of the two PMOS 404 transistors. Each cell 402 of the phase detector 120 may include a second NMOS 406 transistor having a drain 412 of the second NMOS 406 transistor coupled to a drain 412 of the second PMOS 404 transistor and a gate 414 of the second NMOS 406 transistor coupled to a source 410 of the first PMOS 404 transistor.

[0068] The plurality of cells 402 of the second circuit (e.g., phase detector 120) may include a first cell 402, a second cell 402, a third cell 402, and a fourth cell 402. The four cells 402 may be configured such that a source 410 of a first PMOS 404 transistor of the first cell 402 is connected to a source 410 of a second PMOS 404 transistor of the fourth cell 402 and a source 410 of the second PMOS 404 transistor of the first cell 402 is connected to a source 410 of a first PMOS 404 transistor of the second cell 402. The four cells 402 may be configured such that a source 410 of a first PMOS 404 transistor of the third cell is connected to a source 410 of a second PMOS 404 transistor of the second cell 402 and a source 410 of the second PMOS 404 transistor of the third cell 402 is connected to a source 410 of a first PMOS 404 transistor of the fourth cell 402.

[0069] The system 100 may include a quadrature generator 102 of a phase locked loop (PLL). The quadrature generator 102 may include an inductor 210 to provide a first clock signal 202, a second clock signal 204, a third clock signal 206, and a fourth clock signal 208 as outputs. A first plurality of I inverter pairs 312 and a second plurality of Q inverter pairs 314 may be part of a buffer chain circuit 110 of the phase locked loop (PLL). The buffer chain circuit 110 may be configured to provide at least one of I 302, inverted I 302, Q 306, and inverted Q 308 to a phase detector 120 of the PLL at a frequency between 40 gigahertz and 50 gigahertz. In some embodiments, the frequency may vary within about 10% above or below a target frequency range.

[0070] The present solution may relate to a system 100 including a circuit system for providing a clock signal. The system 100 may include a voltage controlled oscillator 140 that utilizes an inductor 210 to generate a first clock signal 202, a second clock signal 204, a third clock signal 206, and a fourth clock signal 208. The system 100 may include a buffer chain circuit 110. The buffer chain circuit 110 may include a first plurality of I inverter pairs 312 configured to output an in-phase signal (I) 302 based on a first clock signal 202 received as a first input and an inverted I signal (Inverted I) 304 based on a second clock signal 204 received as a second input. Each of the first plurality of I inverter pairs 312 may be coupled in parallel by a first circuit (e.g., a PDC 320) to control a phase delay between the I 302 and the Inverted I 304 signals. Buffer chain circuit 110 may include a second plurality of Q inverter pairs 314 configured to output a quadrature signal (Q) 306 based on third clock signal 206 received as a third input and an inverted Q signal (Inverted Q) 308 based on fourth clock signal 208 received as a fourth input.

[0071] The system 100 may include a phase detector 120 including a plurality of cells 402. Each of the plurality of cells 402 may be configured to receive at least one of an I 302 signal, an inverted I 304 signal, a Q 306 signal, or an inverted Q 308 signal. Each cell 402 may include at least one or more transistors having their gates connected to ground. For example, each cell 402 may include a pair of PMOS 404 transistors having their gates coupled to VSS or ground while having their drains 412 coupled to the drains 412 of NMOS 406 transistors having their sources 410 coupled to an input signal (e.g., 302, 304, 306, or 308).

[0072] The system 100 may include a first plurality of I inverter pairs 312 including a first set of four inverters 310 connected in a first series to provide I 302 and a second set of four inverters 310 connected in a second series to provide inverted I 304. A second plurality of Q inverter pairs 314 may include a first set of three inverters 310 connected in a third series to provide Q 306 and a second set of three inverters 310 connected in a fourth series to provide inverted Q 308. In some embodiments, the PDC 320 circuit is omitted or excluded from the second plurality of Q inverter pairs 314. The first circuit (e.g., PDC 320) to control the phase delay may include one of a reverse bias oriented varactor or a combination of a capacitor and a diode. The PDC 320 from the first plurality of I inverter pairs 312 in combination with the inverters 310 from the four series inverters may control the fixed phases in I 302, inverted I 304, Q 306, and inverted Q 308.

[0073] Figure 6 is an example flow chart of a method 600 for clock generation using quadrature delays according to an embodiment of the present solution. The method 600 may include, for example, using Figures 1 to 4 The method may include providing an in-phase (I) signal and an inverted in-phase (I) signal at 602. The method may include providing a quadrature (Q) signal and an inverted quadrature (Q) signal at 604. The method may include receiving the I, I, Q, and Q signals to generate an output at 606.

[0074] At 602, the method may include providing an in-phase (I) signal and an inverted in-phase (Inverted I) signal. The method may include providing an in-phase signal (I) as an output by a first plurality of pairs of inverters (e.g., I inverter pairs) based on a first clock signal received as a first input. The first plurality of pairs of inverters may provide an inverted I signal (Inverted I) as an output based on a second clock signal received as a second input. Each of the first plurality of pairs of inverters may be coupled in parallel by a first circuit (e.g., a phase delay circuit) to control a phase delay between I and Inverted I. The phase delay circuit may control a phase delay between I and Inverted I. The phase delay circuit may control a phase delay between the I signal and the Q signal and between the Inverted I and the Inverted Q signal.

[0075] The first group of four inverters in the first plurality of pairs of inverters may provide an I signal. The first group of four inverters may be connected in a first series inverter. The first series inverter may receive a first clock signal or a second clock signal as its input. The second group of four inverters in the first plurality of pairs of inverters may provide an inverted I, and the second group of four inverters may be connected in a second series. The second group of four inverters may be connected in a second series inverter and may receive the first or second clock signal as input.

[0076] A first circuit (e.g., phase delay circuit) for controlling a phase delay may include a first capacitor connected in series with a first diode in a forward bias orientation. The first diode may be connected in series to a second diode in a reverse bias orientation, which may be connected in series to a second capacitor. In parallel with the two diodes may be one or more resistors, which may also include a signal input for tuning the first circuit (e.g., phase delay).

[0077] The first plurality of pairs of inverters (e.g., I inverter pairs) may include a first inverter in a first pair of the first plurality of pairs. The first inverter may include a first output connected to a first capacitor of a phase delay circuit. The first inverter may be configured in a first group of inverters connected in a first series connection to provide an I signal. The first plurality of pairs of inverters may include a second inverter in a first pair of the first plurality of pairs of inverters. The second inverter may include a second output connected to a second capacitor (e.g., the same phase delay circuit) and may be configured in a second group of inverters connected in a second series connection to provide an inverted I signal.

[0078] At 604, the method may include providing a quadrature (Q) signal and an inverted quadrature (Inverted Q) signal. The method may include providing a quadrature signal (Q) as an output by a second plurality of pairs of inverters based on a third clock signal received as a third input. The second plurality of pairs of inverters may provide an inverted Q signal (Inverted Q) as an output based on a fourth clock signal received as a fourth input. For example, the second plurality of pairs of inverters may include three Q inverter pairs, each inverter pair including two inverters, wherein one of the inverters is from a third series inverter for providing the Q signal and the other inverter is from a fourth series inverter for providing the inverted Q signal.

[0079] The first group of three inverters in the second plurality of pairs of inverters may provide a Q signal. The first group of three inverters may be connected or arranged in a third series. The third series may provide a Q signal in response to a third clock signal or a fourth clock signal used as an input to the third series. The second group of three inverters in the second plurality of pairs of inverters may provide an inverted Q signal. The second group of three inverters may be connected or arranged in a fourth series. The fourth series may provide an inverted Q signal in response to a third clock signal or a fourth clock signal used as an input to the fourth series. The first series and the fourth series may be limited to three inverters, after which the Q and inverted Q signals may be provided to the phase detector.

[0080] At 606, the method may include receiving an I, an inverted I, a Q, and an inverted Q signal to generate an output. The method may include a plurality of units of a second circuit (e.g., a phase detector) receiving an inverted I signal, a Q signal, and an inverted Q signal to generate an output. The output may include a phase error signal, which may be provided to an amplifier circuit to amplify and to a voltage controlled oscillator. Each of the plurality of units of the second circuit (e.g., a phase detector) may be configured to receive at least one of an I signal, an inverted I signal, a Q signal, or an inverted Q signal. Each of the plurality of units may include at least one or more transistors having a gate connected to ground.

[0081] At least one or more transistors of each cell of the second circuit having a gate connected to ground may include two p-channel metal oxide semiconductor (PMOS) transistors. For example, a cell of a phase detector may include a pair of PMOS transistors, each having a gate connected to VSS or ground and configured to operate in a triode region. A cell of a second circuit (e.g., a phase detector) may include a first n-channel metal oxide semiconductor (NMOS) transistor having a drain of the first NMOS transistor connected to a drain of a first PMOS transistor of the two PMOS transistors of the cell and having a gate of the first NMOS transistor coupled to a source of a second PMOS transistor of the two PMOS transistors. A second NMOS transistor of the cell may include a drain of the second NMOS transistor coupled to a drain of the second PMOS transistor of the cell and a gate of the second NMOS transistor of the cell coupled to a source of the first PMOS transistor of the cell.

[0082] A plurality of cells of a second circuit (e.g., a phase detector) may include a first cell, a second cell, a third cell, and a fourth cell configured such that a source of a first PMOS transistor of the first cell is connected to a source of a second PMOS transistor of the fourth cell and a source of the second PMOS transistor of the first cell is connected to a source of a first PMOS transistor of the second cell. A second circuit (e.g., a phase detector) may include a source of a first PMOS transistor of the third cell being connected to a source of a second PMOS transistor of the second cell and a source of a second PMOS transistor of the third cell being connected to a source of a first PMOS transistor of the fourth cell. Thus, the second circuit may include four interconnected cells, wherein each of the four cells is connected to at least two other cells of the second circuit via sources of two PMOS transistors of the cell.

[0083] The method may include a quadrature generator of a phase locked loop (PLL), the quadrature generator including an inductor that provides a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal as outputs. The outputs may be used as inputs to a buffer chain circuit. A first plurality of I inverter pairs of the buffer chain circuit of the PLL and a second plurality of Q inverter pairs of the buffer chain circuit may be configured to provide at least one (or each) of I, inverted I, Q, and inverted Q to a phase detector of the PLL at a frequency between about 40 gigahertz and about 50 gigahertz.

[0084] It should be noted that certain paragraphs of this disclosure may refer to terms such as "first" and "second" related to device signals, data, inputs, channels, etc., for the purpose of identifying or distinguishing one from another. These terms are not intended to relate entities (e.g., first input and second input) only in time or according to sequence, although in some cases, these entities may include such a relationship. These terms also do not limit the number of possible entities (e.g., devices) that can operate within a system or environment.

[0085] It should be understood that the system described above may provide multiples of any one or each of those components. In addition, the system and method described above may be provided as one or more computer-readable programs or executable instructions, programmable circuits, or digital logic embodied on or in one or more articles of manufacture. The article of manufacture may be a central processing unit, a microcontroller, a hard disk, a flash card, a PROM, a RAM, a ROM, an ASIC, or a magnetic tape. Typically, the computer-readable program may be implemented in any programming language, such as LISP, PERL, C, C++, C#, PROLOG, or in any byte code language, such as JAVA. The software program or executable instructions may be stored as object code on or in one or more articles of manufacture.

[0086] Although the foregoing written description of the methods and systems enables one of ordinary skill in the art to make and use various embodiments of these methods and systems, one of ordinary skill in the art will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples herein. Therefore, the methods and systems should not be limited by the above-described embodiments, methods, and examples, but by all embodiments and methods within the scope and spirit of the present disclosure.

Claims

1. A circuit system, comprising: a first plurality of pairs of inverters configured to output an in-phase signal (I) according to a first clock signal received as a first input and to output an inverted I signal (Inverted I) according to a second clock signal received as a second input, wherein each pair of the first plurality of pairs of inverters is coupled in parallel by a first circuit to control a phase delay between the I and the Inverted I; a second plurality of pairs of inverters configured to output a quadrature signal (Q) based on a third clock signal received as a third input and to output an inverted Q signal (Inverted Q) based on a fourth clock signal received as a fourth input; and A second circuit includes a plurality of cells, each of the plurality of cells being configured to receive at least one of the I signal, the inverted I signal, the Q signal, or the inverted Q signal, wherein each cell includes at least one transistor having a gate connected to ground.

2. The circuit system of claim 1 , wherein the first plurality of pairs of inverters comprises a first set of four inverters connected in a first series to provide the I and a second set of four inverters connected in a second series to provide the inverted I.

3. The circuit system of claim 2, wherein the second plurality of pairs of inverters comprises a first set of three inverters connected in a third series to provide the Q and a second set of three inverters connected in a fourth series to provide the inverted Q.

4. The circuit system of claim 1, wherein the first circuit to control the phase delay comprises one of a varactor diode or a combination of a capacitor and a diode oriented in a reverse bias.

5. The circuit system of claim 1 , wherein the first circuit for controlling the phase delay comprises a first capacitor connected to a first diode oriented in a forward bias, wherein the first diode is also connected to a second diode oriented in a reverse bias, and wherein the second diode is also connected to a second capacitor.

6. The circuit system according to claim 5, comprising: a first inverter of a first pair of the first plurality of pairs of inverters, the first inverter comprising a first output connected to the first capacitor and arranged in a first group of inverters in a first series connection to provide the I; and A second inverter of the first pair of the first plurality of pairs of inverters, the second inverter including a second output connected to the second capacitor and configured in a second group of inverters connected in a second series to provide the inversion I.

7. The circuit system of claim 1, wherein the at least one or more transistors of each cell of the second circuit comprises two p-channel metal oxide semiconductor (PMOS) transistors, each of the two PMOS transistors being configured to operate in a triode region.

8. The circuit system of claim 7, wherein each of the plurality of cells comprises: a first n-channel metal oxide semiconductor (NMOS) transistor having a drain of the first NMOS transistor connected to a drain of a first PMOS transistor of the two PMOS transistors and having a gate of the first NMOS transistor coupled to a source of a second PMOS transistor of the two PMOS transistors; and A second NMOS transistor has a drain of the second NMOS transistor coupled to a drain of the second PMOS transistor and a gate of the second NMOS transistor coupled to a source of the first PMOS transistor.

9. The circuit system according to claim 8, wherein the plurality of cells of the second circuit include a first cell, a second cell, a third cell and a fourth cell, which are configured such that: A source of the first PMOS transistor of the first unit is connected to a source of the second PMOS transistor of the fourth unit and a source of the second PMOS transistor of the first unit is connected to a source of the first PMOS transistor of the second unit; and A source of the first PMOS transistor of the third unit is connected to a source of the second PMOS transistor of the second unit and a source of the second PMOS transistor of the third unit is connected to a source of the first PMOS transistor of the fourth unit.

10. The circuit system of claim 1, comprising a quadrature generator of a phase locked loop (PLL), the quadrature generator comprising an inductor to provide the first clock signal, the second clock signal, the third clock signal and the fourth clock signal as outputs.

11. The circuit system of claim 1 , wherein the first plurality of pairs and the second plurality of pairs are part of a buffer chain circuit of a phase-locked loop (PLL), the buffer chain circuit being configured to provide at least one of the I, the inverted I, the Q, and the inverted Q to a phase detector of the PLL at a frequency between 40 GHz and 50 GHz.

12. A method comprising: providing an in-phase signal (I) as an output by first multiple pairs of inverters based on a first clock signal received as a first input and providing an inverted I signal (Inverted I) as an output based on a second clock signal received as a second input, wherein each pair of the first multiple pairs of inverters is coupled in parallel by a first circuit to control a phase delay between the I and the Inverted I; providing, by the second plurality of pairs of inverters, a quadrature signal (Q) as an output based on a third clock signal received as a third input and an inverted Q signal (Inverted Q) as an output based on a fourth clock signal received as a fourth input; and The inverted I signal, the Q signal, and the inverted Q signal are received by a plurality of cells of a second circuit to generate an output, wherein each of the plurality of cells is configured to receive at least one of the I signal, the inverted I signal, the Q signal, or the inverted Q signal and includes at least one or more transistors having a gate connected to ground.

13. The method according to claim 12, wherein: The I is provided by a first group of four inverters in the first plurality of pairs of inverters, the first group of four inverters being connected in a first series connection; The inversion I is provided by a second group of four inverters in the first plurality of pairs of inverters, the second group of four inverters being connected in a second series; The Q is provided by a first set of three inverters in the second plurality of pairs of inverters, the first set of three inverters being connected in a third series; and The inversion Q is provided by a second group of three inverters in the second plurality of pairs of inverters, the second group of three inverters being connected in a fourth series connection.

14. The method according to claim 12, wherein: The first circuit for controlling the phase delay comprises a first capacitor connected to a first diode oriented in forward bias, the first diode connected to a second diode oriented in reverse bias, the second diode connected to a second capacitor, The first plurality of pairs of inverters include a first inverter in a first pair of the first plurality of pairs, the first inverter including a first output connected to the first capacitor and configured in a first set of inverters connected in a first series connection to provide the I; and A second inverter of the first pair of the first plurality of pairs of inverters, the second inverter including a second output connected to the second capacitor and configured in a second group of inverters connected in a second series to provide the inversion I.

15. The method of claim 12, wherein the at least one or more transistors of each cell of the second circuit comprises two p-channel metal oxide semiconductor (PMOS) transistors, each of the two PMOS transistors being configured to operate in a triode region.

16. The method of claim 15, wherein each of the plurality of cells comprises: a first n-channel metal oxide semiconductor (NMOS) transistor having a drain of the first NMOS transistor connected to a drain of a first PMOS transistor of the two PMOS transistors and having a gate of the first NMOS transistor coupled to a source of a second PMOS transistor of the two PMOS transistors; and A second NMOS transistor has a drain of the second NMOS transistor coupled to a drain of the second PMOS transistor and a gate of the second NMOS transistor coupled to a source of the first PMOS transistor.

17. The method of claim 16, wherein the plurality of cells of the second circuit include a first cell, a second cell, a third cell, and a fourth cell configured such that: A source of the first PMOS transistor of the first unit is connected to a source of the second PMOS transistor of the fourth unit and a source of the second PMOS transistor of the first unit is connected to a source of the first PMOS transistor of the second unit; and A source of the first PMOS transistor of the third unit is connected to a source of the second PMOS transistor of the second unit and a source of the second PMOS transistor of the third unit is connected to a source of the first PMOS transistor of the fourth unit.

18. The method according to claim 12, comprising: The first clock signal, the second clock signal, the third clock signal and the fourth clock signal are provided as outputs by an orthogonal generator of a phase-locked loop (PLL) including an inductor, wherein the first plurality of pairs and the second plurality of pairs are part of a buffer chain circuit of the phase-locked loop (PLL), and the buffer chain circuit is configured to provide at least one of the I, the inverted I, the Q and the inverted Q to a phase detector of the PLL at a frequency between 40 GHz and 50 GHz.

19. A system comprising: A circuit system for providing a clock signal, comprising: a voltage controlled oscillator using one or more inductors to provide a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; A buffer chain comprising: a first plurality of pairs of inverters configured to output an in-phase signal (I) according to a first clock signal received as a first input and to output an inverted I signal (Inverted I) according to a second clock signal received as a second input, wherein each pair of the first plurality of pairs of inverters is coupled in parallel by a first circuit to control a phase delay between the I and the Inverted I; and a second plurality of pairs of inverters configured to output a quadrature signal (Q) based on a third clock signal received as a third input and to output an inverted Q signal (Inverted Q) based on a fourth clock signal received as a fourth input; and A phase detector comprising a plurality of cells, each of the plurality of cells being configured to receive at least one of the I, the inverted I, the Q, or the inverted Q, wherein each cell includes at least one or more transistors having a gate connected to ground.

20. The system of claim 19, wherein: The first plurality of pairs of inverters include a first set of four inverters connected in a first series to provide the inversion I and a second set of four inverters connected in a second series to provide the inversion I; The second plurality of pairs of inverters include a first set of three inverters connected in a third series to provide the Q and a second set of three inverters connected in a fourth series to provide the inverted Q; and The first circuit to control the phase delay includes one of a varactor diode or a combination of a capacitor and a diode oriented in a reverse bias.

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