Gain-selectable and large-dynamic-range CDS circuit for reading circuit

Abstract

The invention discloses a CDS circuit with selectable gain and large dynamic range for a readout circuit, and belongs to the field of integral charge readout. The reading circuit adopts a low-noise and self-adaptive CTIA input stage and a correlated double sampling circuit (CDS), the CDS circuit consists of an operational amplifier, a gain control capacitor and a sampling / holding capacitor, the operational amplifier in the CDS circuit adopts a folded common source-common gate structure, and four gears of the gain control capacitor are selectable and respectively correspond to four gears of gains. Besides, a capacitor C1 is additionally arranged in the CDS circuit and is matched with a Skimming signal, so that background noise is reduced, and the dynamic range of a detectable signal of the circuit is enlarged. According to the invention, the CDS circuit with selectable gain and large dynamic range is adopted, the adaptability of the reading circuit to signals in different ranges is greatly improved, and the reading circuit has the advantages of low noise, high integration level and the like.

Description

Technical Field

[0001] The invention belongs to the field of integrated charge readout, and in particular relates to a CDS circuit with selectable gain and large dynamic range for a readout circuit. Background Art

[0002] The readout circuit is an important component of the infrared focal plane. It is generally manufactured using standard complementary metal oxide semiconductor (CMOS) technology. Its basic function is to provide the detector with a suitable bias voltage, perform photoelectric conversion integration and a series of processing on the detector signal, and then output it in a time sequence. With the continuous development of infrared focal plane technology, the readout circuit has gradually developed towards the direction of integrated system functions. On the one hand, it has multiple working modes to enhance the flexibility of the entire infrared system; on the other hand, it integrates digital signal processing functions such as analog-to-digital conversion and non-uniformity correction into the chip, reducing noise and signal crosstalk in analog signal transmission, and improving signal processing and transmission speed.

[0003] The basic framework of the readout circuit has become increasingly mature. The traditional analog readout circuit mainly includes input stage circuit, signal preprocessing circuit, multiplexing and output circuit. The input stage circuit of the readout circuit is directly or indirectly connected to the infrared detector, and the photocurrent of the detector is integrated, preprocessed and output. The signal preprocessing circuit mainly includes sample-and-hold circuit, correlated double sampling circuit, unit gain drive op amp circuit, etc. The multiplexing circuit outputs the sampled data in sequence according to the working mode set by the timing. The output circuit usually uses a source follower or buffer amplifier structure to output the signal.

[0004] As the middle part of the readout circuit, correlated double sampling plays an indispensable and key role. At present, the circuit is limited by the inappropriate signal range of the sampling output and the large background noise interference. Therefore, it is crucial to obtain a CDS circuit structure with selectable gain and a large dynamic range that can reduce background noise. Summary of the invention

[0005] In view of the inappropriate sampling output signal range and large background noise interference of the correlated double sampling structure in the current readout circuit, the present invention designs a CDS circuit with optional gain and large dynamic range for the readout circuit. One of the purposes of the present invention is to improve the adaptability of the readout circuit to signals in different ranges, and the second purpose of the present invention is to obtain a low-noise, highly integrated readout circuit.

[0006] The CDS circuit with selectable gain and large dynamic range for a readout circuit designed by the present invention is composed of a capacitor with a skimming function, a folded common source-common gate structure operational amplifier, a gain control capacitor, and a sampling / holding capacitor.

[0007] In the above structure, the front end of the CDS circuit is configured with a C1 capacitor to cooperate with the Skimming signal. According to the "virtual short" principle of the operational amplifier, when the difference between Skimming and CDS_VCLAMPREF is not zero, the difference voltage is added to the C1 capacitor to achieve a voltage divider effect, thereby reducing the background noise and increasing the dynamic range of the detectable signal of the circuit.

[0008] In the above structure, when the CDS circuit is in the reset state, the clamp switch CDS_CLAMP is at a high level, the switch is closed, and the upper plate voltage VCDS of C2 is clamped to the reference level CDS_VCLAMPREF. When the circuit enters the integration stage, the switch CDS_CLAMP is disconnected, and the integration signal charges C2 through the coupling capacitor C1. VCDS starts to integrate upward from the reference level and is then output to the subsequent circuit for analog-to-digital conversion. When the circuit re-enters the reset state, both ends of the switch CDS_CLAMP become high again, VCDS is clamped to CDS_VCLAMPREF, and the circuit starts the next sampling cycle.

[0009] In the above structure, the operational amplifier in the CDS circuit adopts a folded common source-common gate structure, the bias is controlled by Vbias_1 and Vbias_3, and Vbias_2 is switch controlled.

[0010] In the above structure, the gain control capacitor in the CDS circuit has four levels to choose from: 2pF, 1.5pF, 1pF, and 0.5pF, corresponding to four levels of gain: 1.0, 1.33, 2.0, and 4.0, respectively.

[0011] In the above structure, the gain control capacitor in the CDS circuit is composed of three fixed value capacitors and two switch tubes TG1 and TG2, wherein the complementary CMOS transmission gate is used as the switch tube, and the CMOS switch is composed of a PMOS and an NMOS connected in parallel. When Φ is at a low level, both tubes are cut off; when Φ is at a high level, both tubes are turned on. Since the free electrons in the channel of the NMOS tube are electrons and the channel charges in the PMOS tube are holes, when the charges are injected into the two tubes at the same time, they can cancel each other out, and have better switching performance.

[0012] In the above structure, the sampling signal of the CDS (CDS_CLAMP is at a low level) should be started after a reset signal of the CTIA input stage arrives for a period of time to reduce reset noise.

[0013] The present invention solves the existing problems in the field of integral current readout described in the technical background. The main advantages of the present invention are: a CDS module with a Skimming function, optional CDS gain, and a large dynamic range, which greatly improves the adaptability of the readout circuit to signals in different ranges, and has low noise and high integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a general link diagram of a CDS circuit with selectable gain and large dynamic range for a readout circuit in an embodiment of the present invention.

[0015] Figure 2 4 is an internal schematic diagram of an operational amplifier in a CDS circuit according to an embodiment of the present invention.

[0016] Figure 3 1 is an internal schematic diagram of a gain control capacitor in a CDS circuit according to an embodiment of the present invention.

[0017] Figure 4 FIG. 4 is a schematic diagram of the working timing of the readout circuit including the CDS module in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The accompanying drawings are used as a part of the present invention to fully illustrate the present invention. The accompanying drawings show specific embodiments of the present invention and related figures, which are used to explain the CDS circuit with optional gain and large dynamic range for a readout circuit for a photodetector of the present invention. The specific implementation methods described herein are only used to explain the present invention and are not used to limit the scope of protection of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0019] like Figure 1 As shown, a general link diagram of a CDS gain adjustable large dynamic range readout circuit includes a low noise, adaptive CTIA input stage and a correlated double sampling circuit (CDS), wherein the front end of the CDS circuit is configured with a C1 capacitor to cooperate with the OFFSET signal. According to the "virtual short" principle of the operational amplifier, when the difference between VOFFSET and VCLAMPREF is not zero, the difference voltage is added to the C1 capacitor to achieve a voltage divider effect, thereby reducing background noise and increasing the dynamic range of the circuit's detectable signal.

[0020] In this embodiment, the CDS circuit is composed of an operational amplifier, a gain control capacitor, and a sampling / holding capacitor. Figure 2As shown, the internal schematic diagram of the operational amplifier in the CDS circuit in the embodiment of the present invention, the operational amplifier adopts a folded common source-common gate structure, the bias is controlled by Vbias_1 and Vbias_3, and Vbias_2 is switch controlled.

[0021] The internal schematic diagram of the gain control capacitor in the CDS circuit in this embodiment is as follows: Figure 3 As shown in the figure, when the CDS circuit is in the reset state, the clamp switch CDS_CLAMP is high, the switch is closed, and the voltage VCDS on the upper plate of C2 is clamped to the reference level CDS_VCLAMPREF. When the circuit enters the integration stage, the switch CDS_CLAMP is disconnected, and the integral signal charges C2 through the coupling capacitor C1. VCDS starts to integrate upward from the reference level and is then output to the subsequent circuit for analog-to-digital conversion. When the circuit re-enters the reset state, both ends of the switch CDS_CLAMP become high again, VCDS is clamped to CDS_VCLAMPREF, and the circuit starts the next sampling cycle.

[0022] In this embodiment, the gain control capacitor in the CDS circuit has four levels to choose from: 2pF, 1.5pF, 1pF, and 0.5pF, corresponding to four levels of gain: 1.0, 1.33, 2.0, and 4.0, respectively.

[0023] In this embodiment, the gain control capacitor in the CDS circuit is composed of three fixed value capacitors and two switch tubes TG1 and TG2, wherein the complementary CMOS transmission gate is used as the switch tube, and the CMOS switch is composed of a PMOS and an NMOS connected in parallel. When Φ is at a low level, both tubes are cut off; when Φ is at a high level, both tubes are turned on. Since the free electrons in the channel of the NMOS tube are electrons and the channel charges in the PMOS tube are holes, when the charges are injected into the two tubes at the same time, they can cancel each other out, and have better switching performance.

[0024] In this embodiment, the working timing diagram of the readout circuit is as follows: Figure 4 As shown, the sampling signal of CDS (CDS_CLAMP is low level) should be started after the reset signal of the CTIA input stage arrives for a period of time to reduce the reset noise.

[0025] The above specific implementation methods are specific support for the scheme ideas proposed in the present invention, and cannot be used to limit the protection scope of the present invention. Any equivalent changes or equivalent modifications made on the basis of this scheme in accordance with the ideas proposed in the present invention still fall within the protection scope of the scheme of the present invention.

Claims

1. A CDS circuit with selectable gain and large dynamic range for a readout circuit, characterized in that: The CDS circuit is composed of a capacitor with a skimming function, a folded common-source-common-gate operational amplifier, a gain control capacitor, and a sampling / holding capacitor.

2. The CDS circuit according to claim 1, characterized in that: The front end of the CDS circuit is equipped with a C1 capacitor to cooperate with the Skimming signal. According to the "virtual short" principle of the op amp, when the difference between Skimming and CDS_VCLAMPREF is not zero, the difference voltage is added to the C1 capacitor for voltage division.

3. The CDS circuit according to claim 1, characterized in that: When the CDS circuit is in the reset state, the clamp switch CDS_CLAMP is at a high level, the switch is closed, and the voltage VCDS on the upper plate of C2 is clamped to the reference level CDS_VCLAMPREF; when the circuit enters the integration stage, the switch CDS_CLAMP is disconnected, and the integration signal charges C2 through the coupling capacitor C1, and VCDS starts to integrate upward from the reference level and then outputs to the subsequent circuit for analog-to-digital conversion; When the circuit re-enters the reset state, both ends of the switch CDS_CLAMP become high again, VCDS is clamped to CDS_VCLAMPREF, and the circuit starts the next sampling cycle.

4. The CDS circuit according to claim 2, characterized in that: The gain control capacitor in the CDS circuit has four selectable levels: 2pF, 1.5pF, 1pF, and 0.5pF, corresponding to four gain levels: 1.0, 1.33, 2.0, and 4.

0.

5. The CDS circuit according to claim 1, characterized in that: The sampling signal of CDS starts after the reset signal of CTIA input stage arrives for a preset period of time.

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