A dynamic adaptation method and system for PCIE switch port WRR phase table

Abstract

The present invention discloses a dynamic adaptation method and system for a PCIE switch port WRR phase table. The method comprises step 1, determining the number of horizontal phases when the WRR phase table is arranged according to the total number of lanes of the PCIE switch and the maximum number of lanes supported by a single port; step 2, determining the number of phases of blocks when the WRR phase table is vertically arranged according to the maximum number of lanes that can be configured for a single port and the minimum number of lanes that can be configured for a single port; step 3, determining the number of blocks of the vertical arrangement of the WRR phase table according to the link speed of the port; step 4, calculating the minimum number of phases required for the WRR phase table, and arranging the blocks based on steps 1-3; step 5, filling the WRR phase table with the port number according to the port link width and the port link speed, so as to achieve matching of the weight of each port with the bandwidth of each port.

Description

Technical Field

[0001] The present invention relates to the technical field of PCIE design, in particular to a dynamic adaptation method and system applied to a WRR phase table of a PCIE switch port. Background Art

[0002] PCIE switch is widely used because it can expand the connectivity of the system, such as data centers and servers with high bandwidth and performance requirements.

[0003] As one of the PCIE devices, PCIE switch complies with PCIE protocol specifications and supports QoS (Quality of Service). Priority arbitration is an important basis for the PCIE system to support QoS (Quality of Service).

[0004] Two priority arbitrations are performed at the output port of the PCIE switch: port arbitration and virtual channel VC (Virtual Channel) arbitration.

[0005] VC arbitration occurs after port arbitration. It is an arbitration for packets that have entered different VCs and are to be sent to the link from the same output port. VC is a buffer in the device port. Each port can have up to 8 VC buffers (VC0-VC7). If only one buffer is set for the port, VC arbitration is not required. PCIE switch has multiple ports, and priority arbitration is required when multiple input ports send packets to the same output port. Port arbitration is necessary for PCIE switch.

[0006] According to the PCIE protocol specification, port arbitration can support round-robin arbitration RR (Round Robin) and weighted round-robin arbitration WRR (Weighted Round-Robin). There are 5 types of weighted round-robin arbitration WRR: 32-phase WRR, 64-phase WRR, 128-phase WRR, 128-phase WRR based on programmable time, and 256-phase WRR. Each phase corresponds to a port number. If a phase value does not correspond to a valid port number, then the phase is an invalid phase. If the phase value is a valid port number, then when it rotates to that phase, the request of the corresponding port will be authorized.

[0007] Round Robin Arbitration RR is a special form of WRR, that is, each input port is assigned the same weight and has an equal chance of being rotated. This seemingly fair arbitration method is actually unfair because the link width and link speed of each input port may be different. Giving the same weight to input ports of different bandwidths will severely limit the performance of high-bandwidth ports and fail to bring into play the original advantages of high bandwidth. Therefore, the current PCIE switch will support port WRR arbitration. WRR arbitration can flexibly adjust the weight according to the different bandwidth and business conditions of each port to keep the overall high efficiency and low latency of the PCIE system.

[0008] The weight of each port in the current port WRR phase table is generally allocated by configuring the WRR port arbitration table register through software. However, this method is difficult to adapt to the dynamic changes of the link width and link speed of each port in actual applications and is not convenient and flexible enough. Summary of the invention

[0009] Purpose of the invention: To provide a dynamic adaptation method and system for a WRR phase table of a PCIE switch port to solve the above-mentioned problems existing in the prior art.

[0010] Technical solution: A dynamic adaptation method applied to a PCIE switch port WRR phase table, comprising:

[0011] Step 1: Determine the number of horizontal phases when arranging the WRR phase table according to the total number of lanes of the PCIE switch and the maximum number of lanes supported by a single port;

[0012] The calculation formula for determining the number of lateral phases when the WRR phase table is arranged is:

[0013] sn=total_lanes / port_max_lanes;

[0014] Among them, total_lanes is the total number of lanes of the PCIE switch;

[0015] port_max_lanes is the maximum number of lanes supported by a single port;

[0016] sn is the minimum number of configurable ports of the PCIE switch, that is, the number of horizontal phases when the WRR phase table is arranged.

[0017] Step 2: According to the maximum number of lanes that can be configured for a single port and the minimum number of lanes that can be configured for a single port, determine the number of phases of the block when the WRR phase table is arranged vertically;

[0018] The calculation formula for determining the phase number of a block when the WRR phase table is arranged vertically is:

[0019] pn=port_max_lanes / port_min_lanes;

[0020] Among them, port_max_lanes is the maximum number of lanes supported by a single port;

[0021] port_min_lanes is the minimum number of lanes supported by a single port;

[0022] pn is the number of phases in a block when the WRR phase table is arranged vertically.

[0023] Step 3: Determine the number of blocks arranged vertically in the WRR phase table according to the link speed of the port;

[0024] The link speed of the port is based on the PCIE version, and the link speed ratio of a single lane of each PCIE version is the number of blocks arranged vertically in the WRR phase table of each PCIE version;

[0025] The link speed ratio of a single lane of each PCIE version is:

[0026] S5.0: S4.0: S3.0: S2.0: S1.0≈16:8:4:2:1;

[0027] Therefore, when the PCIE version is 5.0, the number of blocks arranged vertically in the WRR phase table is 16, and the number of blocks arranged vertically in the WRR phase table under different versions can be obtained by analogy.

[0028] Step 4: Calculate the minimum number of phases required for the WRR phase table, and arrange the partition blocks based on steps 1-3;

[0029] The formula for calculating the minimum number of phases required for the WRR phase table is:

[0030] PhaseNum = sn*pn*2 gn-1 ;

[0031] The total number of blocks cut out of the WRR phase table is:

[0032] blockNum=sn*2 gn-1 ;

[0033] Wherein, parameter sn is the number of horizontal phases when the aforementioned WRR phase table is arranged;

[0034] The parameter pn is the number of block phases arranged vertically in the aforementioned WRR phase table;

[0035] The parameter gn is the highest speed supported by the port link.

[0036] Step 5: According to the port link width and the port link speed, the WRR phase table is filled with the port number to match the weight of each port with the bandwidth of each port;

[0037] When the port weight matches the port bandwidth, the ratio of the number of times each port appears in the WRR phase table is equal to the ratio of the bandwidth of each port;

[0038] Calculate the bandwidth of each port and compare them to obtain the ratio of the number of times each port appears in the WRR phase table;

[0039] Port bandwidth calculation:

[0040] BW = link_width*link_speed;

[0041] Where link_width is the link width of the port, link_speed is the link speed of the port, and BW is the port bandwidth;

[0042] After obtaining the ratio of the number of times each port appears in the WRR phase table, fill the port number in the WRR phase table;

[0043] When filling the port number, the phase of the vertical block numbered 0 is filled according to the port link width, and then the phase of the remaining vertical blocks is filled according to the port link speed to achieve matching of each port weight with each port bandwidth.

[0044] The present invention determines the effective phase number and specific arrangement of the port WRR phase table according to the number of PCIE ports, the maximum number of lanes that can be configured for a single port, and the link width and link speed of each port, so as to achieve consistency between the weight ratio of each port in the WRR phase table and the bandwidth ratio of each port. Based on the WRR phase table arranged in this way, the WRR arbiter can achieve the best balance of transaction packet transmission requests of each port when performing port arbitration, thereby achieving high performance of the overall PCIE system and low transmission delay.

[0045] It can adapt to the dynamic changes of link width and link speed of each port in the actual application environment. After the link negotiation is completed, the full phase generation module provided by the present application will re-detect the link width and link speed of each port, dynamically generate a new WRR phase table and load it into the WRR arbiter, and always keep the WRR phase table of each port in the best configuration without the participation of software;

[0046] In the case where the user configures the WRR phase table, the WRR phase table is dynamically adapted according to the link width and link speed of each port and automatically loaded into the WRR arbiter, providing a variety of options for port arbitration of the PCIE system and increasing the flexibility of the system.

[0047] A dynamic adaptation system applied to a PCIE switch port WRR phase table, comprising:

[0048] The port link width and port link speed acquisition module is used to read the link status and control register in the PCIE capability register after the PCIE port and the opposite PCIE device have completed the linkup negotiation, and obtain the port link speed and port link width;

[0049] The full phase generation module is used to assign weights to all sn*pn ports of the PCIE switch in the WRR phase table;

[0050] The full phase generation module includes sn station phase generation modules, and each station phase generation module includes 2^(gn-1) basic phase generation modules.

[0051] Phase value injection register module, which realizes dynamic adaptation of WRR phase table according to port link width and link speed;

[0052] The phase table loading module is used to load the WRR phase table.

[0053] Beneficial effects: The present invention discloses a dynamic adaptation method and system for a PCIE switch port WRR phase table. The present invention determines the effective phase number and specific arrangement of the port WRR phase table according to the number of PCIE ports, the maximum number of lanes that can be configured for a single port, and the link width and link speed of each port, so as to achieve consistency between the weight ratio of each port in the WRR phase table and the bandwidth ratio of each port. Based on the WRR phase table arranged in this way, the WRR arbitrator can achieve the best balance of transaction packet transmission requests of each port when performing port arbitration, thereby achieving high performance of the overall PCIE system and low transmission latency.

[0054] It can adapt to the dynamic changes of link width and link speed of each port in the actual application environment. After the link negotiation is completed, the full phase generation module provided by the present application will re-detect the link width and link speed of each port, dynamically generate a new WRR phase table and load it into the WRR arbiter, and always keep the WRR phase table of each port in the best configuration without the participation of software;

[0055] In the case where the user configures the WRR phase table, the WRR phase table is dynamically adapted according to the link width and link speed of each port and automatically loaded into the WRR arbiter, providing a variety of options for port arbitration of the PCIE system and increasing the flexibility of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 It is a schematic diagram of the system structure of the present invention.

[0057] Figure 2 It is a schematic diagram of the link speed of a single lane corresponding to the PCIE version of the present invention.

[0058] Figure 3 It is a schematic diagram of the parameter gn value corresponding to the maximum link speed of the port of the present invention.

[0059] Figure 4 It is a schematic diagram of the arrangement of the WRR phase table of the present invention.

[0060] Figure 5 Schematic diagram of WRR phase arrangement according to an example of the present invention.

[0061] Figure 6 It is a schematic diagram of the configurable ports of the lane of the present invention.

[0062] Figure 7 The present invention uses different configuration forms of 1 port, 2 ports, 3 ports and 4 ports to show the corresponding weight diagrams of different port link width configurations.

[0063] Figure 8 It is a schematic diagram of the complete arrangement of the weights of ports pt0-pt3 in the WRR phase table of the present invention.

[0064] Fig. 9 It is a schematic diagram of the main interface signals of the basic phase generation module of the present invention.

[0065] Fig.10 It is a schematic diagram of the main interface signals of the station phase generation module of the present invention.

[0066] Fig.11 It is a schematic diagram of the generation result of the present invention.

[0067] Fig.12 It is a schematic diagram of the main interface signals of the all-phase generation module of the present invention.

[0068] Fig.13 It is a schematic diagram of parameter configuration and input signal connection of the full phase generation module of the present invention to each station phase generation module. DETAILED DESCRIPTION

[0069] The present application relates to a dynamic adaptation method and system for a PCIE switch port WRR phase table. After careful research by the applicant, the weight of each port in the current port WRR phase table is generally allocated by configuring the WRR port arbitration table register through software. This method is difficult to adapt to the dynamic changes of the link width and link speed of each port in actual applications, and is not convenient and flexible enough;

[0070] The present application proposes a method for dynamically adapting the weight of each port in the WRR phase table according to the port link width and link speed, so that the user can obtain the optimal weight of each port without configuring the WRR port arbitration table register, so that the entire PCIE system can automatically run in an excellent state of high efficiency and low latency.

[0071] The following is a detailed explanation through specific implementation methods.

[0072] A dynamic adaptation method applied to a PCIE switch port WRR phase table, comprising:

[0073] Step 1: Determine the number of phases in a horizontal row when arranging the WRR phase table according to the total number of lanes of the PCIE switch and the maximum number of lanes supported by a single port, which is defined as the number of stations.

[0074] In the PCIE architecture, lane is the basic unit of the data transmission channel. A lane consists of a pair of transmit differential lines and a pair of receive differential lines.

[0075] The number of lanes of the PCIE port can be configured as needed. Common configurations include x1, x2, x4, x8, x16, etc., where x represents the number of lanes.

[0076] The total number of lanes of the PCIE switch divided by the maximum number of lanes supported by a single port is the minimum number of ports that can be configured on the PCIE switch, which is also the number of phases in a horizontal row when the WRR phase table is arranged, that is, the number of stations;

[0077] The calculation formula is as follows:

[0078] sn=total_lanes / port_max_lanes;

[0079] Among them, total_lanes is the total number of lanes of the PCIE switch; port_max_lanes is the maximum number of lanes supported by a single port; sn is the minimum number of configurable ports of the PCIE switch, which is also the number of phases in a horizontal row when the WRR phase table is arranged, that is, the number of stations;

[0080] For example, if the PCIE switch has a total of 48 lanes, and the maximum number of lanes that can be configured for a single port is x16, then the number of stations is 3. According to the arrangement method of the WRR phase table described in this application, 3 phases can be placed in one row of the WRR phase table;

[0081] Step 2: According to the maximum number of lanes that can be configured for a single port and the minimum number of lanes that can be configured for a single port, determine the number of phases of a block when the WRR phase table is arranged vertically, hereinafter referred to as a block;

[0082] The calculation formula is as follows:

[0083] pn=port_max_lanes / port_min_lanes;

[0084] Among them, port_max_lanes is the maximum number of lanes supported by the aforementioned single port; port_min_lanes is the minimum number of lanes supported by a single port; pn is the number of phases in a block when the WRR phase table is arranged vertically;

[0085] The vertically arranged blocks pn in the WRR phase table represent the maximum number of lanes supported by a single port and the maximum number of ports that can be divided;

[0086] For example, if the maximum number of lanes that can be configured for a single port of a PCIE switch is 16, and the minimum number of lanes that can be configured for a single port is 4, then the vertical arrangement of pn in the WRR phase table is 4, which means that 16 lanes can be configured into one port, and can also be split into a maximum of 4 ports. This is very important for how the subsequent ports are arranged in the WRR phase table.

[0087] Step 3: Determine the number of blocks arranged vertically in the WRR phase table according to the link speed of the port;

[0088] From PCIE1.0 to PCIE5.0, the link speed of a single lane in each version is constantly improving. For details, see the attached Figure 2 As shown;

[0089] Considering that PCIE1.0 and PCIE2.0 use 8b / 10b encoding scheme, and later versions of PCIE use 128b / 130b encoding scheme, considering the effective transmission data bandwidth of each version, the link speed ratio of a single lane of each PCIE version is approximately:

[0090] S5.0: S4.0: S3.0: S2.0: S1.0≈16:8:4:2:1;

[0091] The number of blocks arranged vertically in the WRR phase table of a PCIE switch port is determined by the port link speed;

[0092] The higher the maximum link speed of the port, the larger the number of vertically arranged blocks;

[0093] If the highest link speed of the port is PCIE4.0, the number of blocks arranged vertically in the WRR phase table is 8;

[0094] If the highest link speed of the port is PCIE3.0, the number of blocks arranged vertically in the WRR phase table is 4;

[0095] By analogy, if the highest link speed of the port is PCIE2.0, the number of blocks arranged vertically in the WRR phase table is 2;

[0096] If the highest link speed of the PCIE switch is PCIE1.0, the number of blocks arranged vertically in the WRR phase table is 1.

[0097] Step 4: Calculate the minimum number of phases required for the WRR phase table, and arrange the phases in blocks according to the above method;

[0098] According to the arrangement method of the WRR phase table mentioned above, the minimum number of phases required for the WRR phase table of the present application method can be calculated:

[0099] PhaseNum = sn*pn*2 gn-1 ;

[0100] The parameter sn is the number of phases in a horizontal row when the WRR phase table is arranged, that is, the number of stations;

[0101] The parameter pn is the number of block phases arranged vertically in the aforementioned WRR phase table;

[0102] The parameter gn is the maximum speed supported by the port link;

[0103] The parameter gn corresponding to the maximum link speed of a specific port is given in the following table. Figure 3 As shown;

[0104] The total number of blocks cut out of the WRR phase table is:

[0105] blockNum=sn*2 gn-1 ;

[0106] gn takes values ​​of 1, 2, 3, and 4;

[0107] The WRR phase table is arranged as shown in the attached Figure 4 As shown;

[0108] For example, if the total number of lanes of a PCIE switch is 48, the maximum number of lanes of a single port is 16, the minimum number of lanes of a single port is 4, and the maximum link speed of the port is PCIE3.0, according to the above calculation method, sn is 3, pn is 4, the number of blocks divided vertically is 4, the required number of WRR phases is 48, and the total number of blocks that can be divided by the WRR phase table is 12;

[0109] According to the above background technology, the PCIE protocol specification supports 32, 64, 128 or 256 WRR phases for port arbitration; for the requirement of 48 phases, the 64-phase WRR defined in the protocol specification can be selected. For the extra phases, the invalid port number can be filled in as a reserved item;

[0110] The WRR phases in the above example can be arranged as follows: 3 phases per row, 4 phases per vertical block, 4 blocks divided vertically, a total of 12 blocks, as shown in the attached figure. Figure 5 As shown;

[0111] Step 5: According to the port link width and the port link speed, the WRR phase table is filled with the port number to match the weight of each port with the bandwidth of each port;

[0112] After the WRR phase table is arranged, the next step is to fill the port number into the WRR phase table according to the link width and link speed of each port; each phase value corresponds to a port number. If the phase value does not have a valid port number matching it, it means that this phase does not work;

[0113] In order to fill the port number into each phase, so that the weight of each port in the WRR phase table matches the bandwidth of the port, it is first clearly defined here that the port weight matches the port bandwidth, which means that the ratio of the number of times each port appears in the WRR phase table is equal to the ratio of the bandwidth of each port;

[0114] Port bandwidth calculation method:

[0115] BW = link_width*link_speed;

[0116] Here, link_width is the link width of the port, link_speed is the link speed of the port, and BW is the port bandwidth;

[0117] Taking three ports as an example, assuming that the link width of port pt0 is x16 and the link speed is PCIE3.0; the link width of port pt1 is x8 and the link speed is PCIE2.0; the link width of port pt2 is x4 and the link speed is PCIE1.0, then the bandwidth ratio of the three ports is:

[0118] BWpt0:BWpt1:BWpt2=16*S3.0:8*S2.0:4*S1.0;

[0119] It has been explained above that S3.0:S2.0:S1.0≈4:2:1;

[0120] Therefore, BWpt0:BWpt1:BWpt2≈16*4:8*2:4*1≈16:4:1;

[0121] Then, the number of times these three ports appear in the WRR phase table, that is, the ratio of the weights of these three ports, must be 16:4:1;

[0122] Filling the port number in the WRR phase table is done in two steps;

[0123] In the first step, according to the port link width, the phase with the vertical block number of 0 is filled first;

[0124] Each block contains pn phases. The weight of these pn phases added together corresponds to the basic weight of the port corresponding to the aforementioned port_max_lanes lanes at the PCIE1.0 rate.

[0125] According to actual application requirements, the maximum number of lanes that can be configured for a single port can be configured as one port or multiple ports of different widths. If they are all configured according to the minimum number of lanes, a maximum of pn ports can be configured.

[0126] For example, if a single port can be configured as x16 lanes at most and x4 lanes at least, then the configurable ports for these 16 lanes are as shown in the following figure. Figure 6 As shown;

[0127] Attached Figure 6 The following are conventional configuration methods. If the port supports unconventional configuration methods such as x12, you can also follow the attached Figure 6 The same configuration idea is used.

[0128] The application provides a WRR phase table arrangement method, where one phase represents the weight of a port with the minimum link width at the PCIE1.0 rate.

[0129] For example, if the minimum number of lanes that can be configured for a port is 4, one phase represents the weight of a x4 port in PCIE1.0. Then, if the link speed is the same, the x8 port will occupy 2 phase weights, and the x16 port will occupy 4 phase weights.

[0130] If the x16 lane is allocated to multiple ports, then these multiple ports share the weights of the four phases according to the link width. For example, if the x16 lane is configured as three ports, x8x4x4, then these three ports occupy the weights of 2 phases, 1 phase, and 1 phase respectively.

[0131] Regardless of how many ports the maximum number of lanes of a single port is ultimately configured to be, when the link speed of these ports is PCIE1.0, the positions configured in the WRR phase table are always located in the interval with the vertical block number being 0.

[0132] Attached Figure 7 Continuing with the previous example (the maximum number of lanes for a single port is 16, and the minimum number of lanes is 4), let's illustrate the block phase configuration method with station number 0 and vertical block number 0. The figure takes different configuration forms of 1 port, 2 ports, 3 ports and 4 ports to show how to configure the corresponding weights for different port link widths. The phase is retained in the figure and invalid port numbers are filled.

[0133] It can be seen that the width of the port is proportional to the number of phases occupied by the port. When the port is configured as x16, the corresponding port number will occupy 4 phases and appear 4 times; when the port is configured as x8, the corresponding port number will occupy 2 phases and appear 2 times; when the port is configured as x4, the corresponding port number will occupy 1 phase and appear 1 time.

[0134] Attached Figure 7 The example is a weighting method for a port numbered 0 in the vertical block numbered 0. The weighting methods for ports corresponding to other stations in the vertical block numbered 0 are the same. For example, a PCIE switch has a total of 48 lanes, and a single port can be configured as x16 at most and x4 at least. Then the PCIE switch can be divided into 3 stations, and a total of up to 12 ports can be configured. The weighted positions of ports pt0-pt3 correspond to station numbered 0, the weighted positions of ports pt4-pt7 correspond to station numbered 1, and the weighted positions of ports pt8-pt11 correspond to station numbered 2.

[0135] As the port link speed increases, the weight of the corresponding port also increases in a power of 2. If the weight of a PCIE 1.0 x4 port is represented by 1 phase, then the weight of a PCIE 2.0 x4 port is represented by 2 phases, and the weight of a PCIE 3.0 x4 port is represented by 4 phases. Considering the increase in link width, the number of phases will increase proportionally. For example, the weight of a PCIE 3.0 x16 port will be represented by 4*4, or 16 phases.

[0136] Specifically, with regard to the arrangement of the WRR phase table, if the port link speed is PCIE1.0, only the phase of the block with vertical number 0 is filled, and other redundant phases are reserved; if the port link speed is PCIE2.0, the phase of the blocks with vertical number 0 and 1 is filled, and other redundant phases are reserved; if the port link speed is PCIE3.0, the phase of the blocks with vertical numbering from 0 to 3 is filled, and other redundant phases are reserved; and so on for other link speeds.

[0137] As attached Figure 8 As shown, continuing with the previous example, based on the port link width in the previous table, the change of the port link speed is added to completely arrange the weights of ports pt0-pt3 in the WRR phase table.

[0138] From the attached Figure 8 It can be seen that the bandwidth ratio of each port is consistent with the ratio of the number of phases occupied by each port in the phase table. PCIE1.0 ports only occupy the vertical block numbered 0, PCIE2.0 ports occupy the vertical blocks numbered 0 and 1, and PCIE3.0 ports occupy all 4 vertical blocks. PCIE1.0 x4 ports only occupy 1 phase, PCIE2.0 x8 ports occupy 4 phases, and PCIE3.0 x16 ports occupy 16 phases.

[0139] In this arrangement, the weight ratio of each port is consistent with the port bandwidth ratio.

[0140] A dynamic adaptation system for PCIE switch port WRR phase table, as shown in the attached Figure 1 Shown, including

[0141] The port link width and port link speed acquisition module is used to read the link status and control register (offset address 78h) in the PCIE capability register after the PCIE port and the opposite PCIE device have completed the linkup negotiation to obtain the port link speed and port link width.

[0142] The full phase generation module includes sn station phase generation modules, each of which contains 2^(gn-1) basic phase generation modules;

[0143] The full phase generation module contains a total of sn*2^(gn-1) basic phase generation modules;

[0144] The basic phase generation module is the most basic unit module in the full phase generation module. This module is responsible for assigning values ​​to pn phases. This module needs to be able to adapt to different port numbers, different port link widths and different port link speeds to generate values ​​for pn phases.

[0145] Attached Fig. 9 It is the main interface signal of the basic phase generation module.

[0146] The pn phase values ​​output by this module correspond to the partial weights of 1 to pn ports (if the maximum number of lanes for a single port is configured, it is 1 port; if the minimum number of lanes for a single port is configured, it is pn ports) at a certain link rate.

[0147] The weights of all 2^(gn-1) basic phase generation modules in the vertical direction are added together to form the complete weights of these 1 to pn ports (if the maximum number of lanes of a single port is configured, it is 1 port; if the minimum number of lanes of a single port is configured, it is pn ports) in the entire WRR phase table.

[0148] For a specific port, the port number is fixed and is passed in as a parameter.

[0149] Each port corresponds to a port number, and the corresponding parameters are PT_INDEX_0 to PT_INDEX_pn-1.

[0150] The link width of the port varies according to the application situation. Each port also has an independent link width setting, which is introduced through the input interface signals i_pt_linkWidth_0~i_pt_linkWidth_pn-1.

[0151] The link speed of the port is related to whether the phase value output by the module is an invalid port number or a valid port number. As discussed above, when the port is at different link speeds, its position and the number of phases occupied in the WRR phase table are different.

[0152] If the port link speed is PCIE1.0, the scope of the port authorization is limited to the block with vertical number 0, and the phases of other vertical blocks corresponding to the port are all assigned invalid port numbers; if the port link speed is PCIE2.0, the scope of the port authorization is limited to the blocks with vertical number 0 and 1, and the phases of other vertical blocks corresponding to the port are all assigned invalid port numbers; if the port link speed is PCIE3.0, the scope of the port authorization is limited to the blocks with vertical number 0-3, and the phases of other vertical blocks corresponding to the port are all assigned invalid port numbers; the same applies to other port link speeds.

[0153] Whether each port can occupy a position in the pn phases of the basic phase generation module is determined by the link speed enable signals i_pt_linkSpeed_en_0 to i_pt_linkSpeed_en_pn-1 corresponding to the port.

[0154] When the link speed enable signal corresponding to the port is valid, it means that the port can be weighted in these pn phases (the number of weights is determined by the port link width); otherwise, all these pn phase values ​​are set to invalid port numbers.

[0155] The Station phase generation module integrates 2^(gn-1) basic phase generation modules, and all these basic phase generation modules together can generate pn*2^(gn-1) phase values.

[0156] The phase assignments correspond to all the weights of 1 to pn ports (if a single port is configured with a maximum number of lanes, it is 1 port; if a single port is configured with a minimum number of lanes, it is pn ports) in the entire WRR phase table.

[0157] Attached Fig.10 It is the main interface signal of the station phase generation module.

[0158] The parameters of each basic phase generation module remain consistent and all reference the parameter configuration of the station phase generation module.

[0159] The input signal of the internal basic phase generation module - link speed enable i_pt_linkSpeed_en_0~i_pt_linkSpeed_en_pn-1 is generated in the module according to the input signal - link speed signals i_pt_linkSpeed_0~i_pt_linkSpeed_pn-1 of each port.

[0160] The specific generated results are as follows Fig.11 shown.

[0161] Attached Fig.11 In the column, * indicates any value from 0 to sn-1. The port link speed is only displayed up to PCIE3.0. For higher link speeds, the generation idea of ​​the port link speed enable signal is the same.

[0162] At the same time, for the convenience of demonstration, all pn ports maintain the same link speed. In fact, each port can run at a different link speed. The generation method of the link speed enable signal i_pt_linkSpeed_en_x corresponding to each port with different link speeds is the same as the attached Fig.11The ideas shown are also consistent, that is: when the port link speed is PCIE1.0, only the port link speed enable signal of the basic phase generation module numbered S_*0 is 1, and the port link speed enable signals corresponding to the port of other modules are 0; when the port link speed is PCIE2.0, the port link speed enable signals of the basic phase generation modules numbered S_*0 and S_*1 are 1, and the port link speed enable signals corresponding to the port of other modules are 0; when the port link speed is PCIE3.0, the port link speed enable signals of the basic phase generation modules numbered S_*0 to S_*3 are 1, and the port link speed enable signals corresponding to the port of other modules are 0; and so on, for each level of increase in the port link speed, the effective range of the port link speed enable signal of the basic phase generation module is doubled on the basis of the previous speed level.

[0163] The full phase generation module integrates sn station phase generation modules, each station phase generation module outputs pn*2^(gn-1) phase values, and the full phase generation module outputs a total of sn*pn*2^(gn-1) phase values ​​(if these phase numbers are less than the number of phases selected in the PCIE protocol specification - or 32 or 64 or 128 or 256, then the difference in the number of phases is filled with invalid port numbers).

[0164] Each station phase generation module corresponds to the weights of pn ports in the WRR phase table.

[0165] The full phase generation module corresponds to the weighting of all sn*pn ports of the PCIE switch in the WRR phase table.

[0166] The main interface signals of the full phase generation module are as follows: Fig.12 shown.

[0167] The parameter configuration and input signal connection of all phase generation modules for each station phase generation module are shown in the attached figure. Fig.13 shown.

[0168] The phase value injection register module implements dynamic adaptation of the WRR phase table according to the port link width and link speed according to the method of the application. In theory, the software does not need to configure the WRR port arbitration register, but the software is not prohibited from configuring the WRR port arbitration register.

[0169] If the user has specific requirements, the WRR port arbitration register can also be written by software to overwrite the dynamically adapted WRR phase value.

[0170] After the reset is completed and the link is linked up, before the external software writes the WRR port arbitration register, the value of the dynamically adapted WRR phase table is injected into the WRR port arbitration register.

[0171] Phase table loading module, all WRR port arbitration registers are combined together to form a WRR phase table, which is ultimately used by the WRR arbiter.

[0172] In both cases, the WRR phase table needs to be loaded into the WRR arbiter module;

[0173] The first is after the link reset is completed and linkup is completed. At this time, there is no need for software to set the load command. The default value of the WRR phase table, that is, the phase value dynamically adapted according to the port link speed and port link width, is directly loaded into the WRR arbiter.

[0174] In the second case, the WRR phase table is loaded into the WRR arbiter according to the loading command set by the software. At this time, the loaded WRR phase table may be a phase value dynamically adapted according to the port link speed and port link width, or it may be a value set by the user.

[0175] After the WRR phase table is loaded, the WRR arbiter can poll and match the requests of each port according to the empowerment status of each port in the WRR phase table, so that the transaction packets of each port can be output in order according to the priority and weight configuration.

[0176] Working principle description:

[0177] Determine the number of horizontal phases when arranging the WRR phase table based on the total number of lanes of the PCIE switch and the maximum number of lanes supported by a single port;

[0178] According to the maximum number of lanes that can be configured for a single port and the minimum number of lanes that can be configured for a single port, determine the number of phases of the block when the WRR phase table is arranged vertically;

[0179] The number of blocks arranged vertically in the WRR phase table is determined according to the link speed of the port;

[0180] Calculate the minimum number of phases required for the WRR phase table and arrange the partition blocks based on steps 1-3;

[0181] According to the port link width and the port link speed, the WRR phase table is filled with the port number to achieve matching of each port weight with each port bandwidth.

[0182] The preferred specific embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above specific embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical scheme of the present invention, and these equivalent transformations all belong to the protection scope of the present invention.

Claims

1. A dynamic adaptation method for a PCIE switch port WRR phase table, characterized in that: include: Step 1: Determine the number of horizontal phases when arranging the WRR phase table according to the total number of lanes of the PCIE switch and the maximum number of lanes supported by a single port; Step 2: According to the maximum number of lanes that can be configured for a single port and the minimum number of lanes that can be configured for a single port, determine the number of phases of the block when the WRR phase table is arranged vertically; Step 3: Determine the number of blocks arranged vertically in the WRR phase table according to the link speed of the port; Step 4: Calculate the minimum number of phases required for the WRR phase table, and arrange the partition blocks based on steps 1-3; Step 5: According to the port link width and the port link speed, the WRR phase table is filled with the port number to match the weight of each port with the bandwidth of each port; When the port weight matches the port bandwidth, the ratio of the number of times each port appears in the WRR phase table is equal to the ratio of the bandwidth of each port; Calculate the bandwidth of each port and compare them to obtain the ratio of the number of times each port appears in the WRR phase table; Port bandwidth calculation: BW = link_width*link_speed; Where link_width is the link width of the port, link_speed is the link speed of the port, and BW is the port bandwidth; After obtaining the ratio of the number of times each port appears in the WRR phase table, fill the port number in the WRR phase table; When filling the port number, the phase of the vertical block numbered 0 is filled according to the port link width, and then the phase of the remaining vertical blocks is filled according to the port link speed to achieve matching of each port weight with each port bandwidth.

2. The method for dynamic adaptation of a WRR phase table for a PCIE switch port according to claim 1, characterized in that: The calculation formula for the horizontal phase number when the WRR phase table is arranged is: sn=total_lanes / port_max_lanes; Among them, total_lanes is the total number of lanes of the PCIE switch; port_max_lanes is the maximum number of lanes supported by a single port; sn is the minimum number of configurable ports of the PCIE switch, that is, the number of horizontal phases when the WRR phase table is arranged.

3. The method for dynamic adaptation of a WRR phase table for a PCIE switch port according to claim 1, characterized in that: The calculation formula for the phase number of a block when the WRR phase table is arranged vertically is: pn=port_max_lanes / port_min_lanes; Among them, port_max_lanes is the maximum number of lanes supported by a single port; port_min_lanes is the minimum number of lanes supported by a single port; pn is the number of phases in a block when the WRR phase table is arranged vertically.

4. The method for dynamic adaptation of a WRR phase table for a PCIE switch port according to claim 1, wherein: The link speed of the port is based on the PCIE version, and the link speed ratio of a single lane of each PCIE version is the number of blocks arranged vertically in the WRR phase table of each PCIE version; The link speed ratio of a single lane of each PCIE version is: S5.0:S4.0:S3.0:S2.0:S1.0≈16:8:4:2:

1.

5. The method for dynamic adaptation of a WRR phase table for a PCIE switch port according to claim 1, wherein: The formula for calculating the minimum number of phases required for the WRR phase table is: PhaseNum=sn*pn*2 gn-1 ; The total number of blocks cut out of the WRR phase table is: blockNum=sn*2 gn-1 ; Wherein, parameter sn is the number of horizontal phases when the aforementioned WRR phase table is arranged; The parameter pn is the number of block phases arranged vertically in the aforementioned WRR phase table; The parameter gn is the highest speed supported by the port link.

6. A dynamic adaptation system applied to a PCIE switch port WRR phase table, used to implement the dynamic adaptation method according to any one of claims 1 to 5, characterized in that: include: The port link width and port link speed acquisition module is used to read the link status and control register in the PCIE capability register after the PCIE port and the opposite PCIE device have completed the linkup negotiation, and obtain the port link speed and port link width; The full phase generation module is used to assign weights to all sn*pn ports of the PCIE switch in the WRR phase table; Phase value injection register module, which realizes dynamic adaptation of WRR phase table according to port link width and link speed; The phase table loading module is used to load the WRR phase table.

7. The dynamic adaptation system for a PCIE switch port WRR phase table according to claim 6, characterized in that: The full phase generation module includes sn station phase generation modules, and each station phase generation module includes 2^(gn-1) basic phase generation modules.

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