Devices with via structures to reduce crosstalk effects

Abstract

An apparatus having a via structure that reduces crosstalk effects is provided. The apparatus includes: a printed circuit board (PCB) including a plurality of layers sequentially stacked; a first via structure partially penetrating the plurality of layers of the PCB and connected to a first metal plate on a first layer of the plurality of layers; and a second via structure adjacent to the first via structure in a horizontal direction, partially penetrating the plurality of layers of the PCB, and connected to a second metal plate on a second layer of the plurality of layers. A portion where the first metal plate and the second metal plate overlap each other is configured to provide a first mutual capacitive coupling between the first via structure and the second via structure.

Description

Technical Field

[0001] Various example embodiments relate to apparatuses, and more particularly, to apparatuses capable of reducing crosstalk effects. Background Art

[0002] Crosstalk can be defined as inductive coupling between adjacent paths. Far-end crosstalk (FEXT) is crosstalk and / or interference between pairs of signals on an interconnect or bus, and is measured at the end of the signal line opposite to the jammer. Single-ended interconnects and / or buses can be used to connect memory devices to printed circuit boards (PCBs) or packages. Adjacent buses of memory devices may be affected by FEXT of adjacent signals. FEXT is a key limiting factor in high-speed signaling because FEXT acts as a source of harmful noise on the bus and distorts the signal. Reducing the FEXT effect can be beneficial to high-speed and / or high-performance operation of memory devices. Summary of the invention

[0003] Various example embodiments may provide a device having a via structure capable of reducing a crosstalk effect.

[0004] According to various example embodiments, there is provided a device having a via structure, the device comprising: a printed circuit board (PCB), the PCB comprising multiple layers stacked in sequence; a first via structure, the first via structure partially penetrating the multiple layers of the PCB and connected to a first metal plate located on a first layer of the multiple layers; and a second via structure, the second via structure being adjacent to the first via structure in a horizontal direction, partially penetrating the multiple layers of the PCB, and connected to a second metal plate located on a second layer of the multiple layers. The portion where the first metal plate and the second metal plate overlap each other is configured to have a first mutual capacitance coupling between the first via structure and the second via structure.

[0005] Optionally or additionally, according to various example embodiments, a device having a via structure is provided, the device comprising: a printed circuit board (PCB), the PCB comprising N (N is a natural number) layers stacked sequentially; and M (M is a natural number) via structures, the M via structures being respectively configured to transmit M signals and pass through each of the N layers of the PCB, wherein a first mutual capacitance coupling is configured between a first via structure and a second via structure that are adjacent to each other in a horizontal direction of the PCB among the M via structures, and a second mutual capacitance coupling is configured between a third via structure that overlaps with the first via structure and a fourth via structure that overlaps with the second via structure in a vertical direction among the M via structures.

[0006] Optionally or additionally, according to various exemplary embodiments, a pathway structure is provided, comprising: a cylinder, the cylinder being located on a printed circuit board (PCB), the PCB comprising multiple layers stacked in sequence; and a conductive material film, the conductive material film having an insulating material film embedded in the center of the cylinder, wherein the cylinder provides a signal input point and a signal output point and partially penetrates the multiple layers, and a layer in which a metal plate is arranged among the layers penetrated between the signal input point and the signal output point is configured to provide a mutual capacitance point, and the conductive material film located in the area of ​​the signal input point and the area of ​​the signal output point is arranged to have a size larger than the size of the conductive material film located in the area of ​​the mutual capacitance point. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a diagram illustrating a device having a passage structure according to some example embodiments;

[0009] Figure 2 It is along Figure 1 A cross-sectional view of a memory module taken along line XX′;

[0010] FIG. 3A to FIG. 3C It is shown Figure 2 A diagram of the pathway structure of

[0011] 4A to 6C is a diagram illustrating a capacitance pattern included in a via structure according to some example embodiments;

[0012] Figure 7 is a diagram illustrating mutual capacitance of a via structure according to some example embodiments;

[0013] Figure 8 is a diagram showing a pathway structure according to some example embodiments;

[0014] Fig. 9 is a diagram showing a pathway structure according to some example embodiments;

[0015] Figures 10 to 12 is a diagram illustrating a memory module according to some example embodiments; and

[0016] Fig.13 is a block diagram for describing a system of an electronic device including a memory module according to some example embodiments. DETAILED DESCRIPTION

[0017] Example embodiments generally relate to a pathway structure that reduces crosstalk, especially far-end crosstalk (FEXT) of a high-speed single-ended bus. In signaling, FEXT is proportional to the amount of capacitance and inductance [Cm / Cs-Lm / Ls]. Cm, Cs, Lm, and Ls represent mutual capacitance, self-capacitance, mutual inductance, and self-inductance, respectively. Because the Lm / Ls term, which is proportional to the length of the signal line, has a large value, FEXT can be reduced by increasing the Cm term. Example embodiments include a pathway structure that uses a metal plate added to the pathway to reduce the inductive coupling that occurs between adjacent pathways in a bus and / or interconnect technology. The metal plate generates capacitive coupling, which can compensate for the inductive crosstalk that is typically generated between pathways in a printed circuit board (PCB) or package. When the metal plates added to two adjacent pathways overlap each other, capacitive coupling is generated or may be generated, thereby increasing mutual capacitance and improving overall performance. Hereinafter, in order to increase mutual capacitance to balance with inductive coupling, a pathway structure that uses a capacitive pattern to form mutual capacitive coupling is provided.

[0018] Figure 1 is a diagram illustrating a device 100 having a via structure according to some example embodiments. Figure 1 The device 100 is an example of being implemented as a memory module; however, example embodiments are not limited thereto. For ease of description, the device 100 is described as a memory module, which also applies to the following embodiments. The term "device 100" and the term "memory module" may be used interchangeably.

[0019] refer to Figure 1 , the memory module 100 may include a module substrate 110 , a module connector 120 , and memory packages 130 , 140 , 150 , and 160 . In addition, the memory module 100 may further include a passive element 170 disposed on the module substrate 110 .

[0020] The module substrate 110 may be or may include a multilayer circuit board having a first surface (or upper surface) and a second surface (or lower surface) facing each other, or may be included in the multilayer circuit board. For example, the module substrate 110 may be or may include a PCB, or may be included in the PCB, which includes a plurality of layers stacked in sequence. As described below, the PCB may include wiring formed on a surface and / or inside, and a path for connecting the wiring. The wiring may be a conductive pattern such as a printed circuit pattern for interconnecting the module connector 120, the memory packages 130, 140, 150 and 160, and the passive component 170.

[0021] The module connector 120 may be provided on the module substrate 110 to connect to a system board on which the memory module 100 is mounted. The module connector 120 may include a conductive material. The module connector 120 may be provided on a first surface of the module substrate 110 to which the memory packages 130, 140, 150, and 160 are attached. Figure 1 Although not shown in the drawings, the module connector 120 may also be disposed on a second surface opposite to the first surface of the module substrate 110 .

[0022] The memory packages 130, 140, 150, and 160 are volatile memory devices, such as one or more of dynamic random access memory (DRAM), static random access memory (SRAM), mobile DRAM, double data rate synchronous dynamic random access memory (DDR SDRAM), low power DDR (LPDDR) SDRAM, graphic DDR (GDDR), SDRAM, Rambus dynamic random access memory (RDRAM), etc. Alternatively or additionally, the memory packages 130, 140, 150, and 160 are non-volatile memory devices, such as one or more of electrically erasable programmable read-only memory (EEPROM), flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), nano floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), etc.

[0023] The memory packages 130, 140, 150 and 160 each include a ball grid array (BGA) type package and may be disposed on a first surface of the module substrate 110. For example, the memory package 130 may be disposed on a first surface of the module substrate 110, the first surface of the module substrate 110 facing the solder ball type pins 131 of the memory package 130. The passive element 170 is disposed on the first surface of the module substrate 110 and may include an inductor, a capacitor, a resistor, a memristor, etc. For ease of description, the memory packages 130, 140, 150 and 160 are described as including DDR DRAM, but the technical idea of ​​the inventive concept is not limited thereto. In some example embodiments, the memory module 100 is described as a compression attached memory module (CAMM), and the same applies to the following embodiments. The CAMM may be used in a mobile computing environment with limited heat dissipation capability and / or in a standard office environment for a desktop and all-in-one (AIO) system with a heating and / or air conditioning device.

[0024] Figures 2 to 3C is a diagram illustrating a module substrate 110 having a via structure according to some example embodiments. Figure 2 It is along Figure 11 is a cross-sectional view of the memory module 100 taken along line XX′. FIG. 3A to FIG. 3C It is shown Figure 2 For convenience of description, the term "module substrate 110" and the term "PCB 110" may be used interchangeably.

[0025] refer to Figure 1 and Figure 2 , the module substrate 110 may be a multilayer PCB. The PCB 110 may include a first layer L1 to a sixteenth layer L16. The first layer L1 to the sixteenth layer L16 may be divided into an upper layer 201 and a lower layer 202, and the first layer L1 to the eighth layer L8 are included in the upper layer 201, and the ninth layer L9 to the sixteenth layer L16 may be included in the lower layer 202. The first layer L1 to the sixteenth layer L16 include a plurality of via structures 210, 211, 212, 213, 220, and 230, and the plurality of via structures 210, 211, 212 and 213, 220, and 230 may be connected to wiring formed inside the first layer L1 to the sixteenth layer L16. The plurality of via structures 210, 211, 212, 213, 220, and 230 may be signal vias and may be arranged at specific intervals from each other.

[0026] The pins 131 of the memory package 130 may contact the first layer L1 which is the uppermost layer of the PCB 110. For example, the pins 131 of the memory package 130 may be data signal pins DQ0, DQ1, DQ2, and DQ3, respectively. According to various example embodiments, the pins 131 of the memory package 130 may be pins for clock, command / address, and control signals. Each of the data signals DQ0, DQ1, DQ2, and DQ3 of the memory package 130 may be connected to each of the via structures 210, 211, 212, 213, 220, and 230 formed on the PCB 110.

[0027] refer to Figure 3A and Figure 3B , showing Figure 2The passage structures 220 and 210 having different shapes among the passage structures 210, 211, 212, 213, 220 and 230. The passage structures 220 and 210 may include a barrel 300 located within the PCB 110 and a signal input point (e.g., 302) and a signal output point (e.g., 304). In the barrel 300, a conductive material film 310 having an insulating material film 320 is formed at the center of the barrel 300, for example, coaxially. The barrel 300 may include a blind via hole (BVH) barrel or a buried via hole (BVH) barrel, which are configured to connect the signal input point 302 and the signal output point 304 to other layers. The conductive material film 310 located between the signal input point 302 and the signal output point 304 may provide a signal line. A metal plate for increasing mutual capacitance may be formed on the signal line between the signal input point 302 and the signal output point 304. As Figure 3B As shown, the via structure 210 includes a mutual capacitance point 330 located between a signal input point 302 and a signal output point 304 , and a signal line 330 of the mutual capacitance point may be connected to a plate 340 .

[0028] In combination Figure 3A and Figure 3B Reference Figure 2 , the DQ0 data signal of the memory package 130 can be connected to the via structure 210, and the DQ1 data signal can be connected to the via structure 211. The via structures 210 and 211 can be arranged adjacent to each other in the X-axis direction (e.g., in the horizontal axis direction). The via structures 210 and 211 are formed on the upper layer 201 of the PCB 110, the signal input point 302 is formed on the first layer L1, and the signal output point 304 is formed on the eighth layer L8. The mutual capacitance point 330 of the via structure 210 is formed on the fifth layer L5 and can be connected to the via structure 211 formed on the fifth layer L5 (e.g., Figure 4A ) is related or associated with the plate 340 on the sixth layer L6. The mutual capacitance point 330 of the via structure 211 is formed on the sixth layer L6 and can be formed on the sixth layer L6 (for example, Figure 4B ) are related or associated with the board 340 on the fifth layer L5. The board 340 of the fifth layer L5 and the board 340 of the sixth layer L6 may have an area overlapping each other (for example, Figure 4C ), and capacitive coupling can be generated between the plates overlapping each other to increase the mutual capacitance.

[0029] The DQ2 data signal may be connected to the via structure 220, and the DQ3 data signal may be connected to the via structure 230. In the via structures 220 and 230, the signal input point 302 is formed on the first layer L1 of the PCB 110, and the signal output point 304 is formed on the ninth layer L9. The via structures 220 and 230 may be connected to the via structures 212 and 213 in the ninth layer L9, respectively. As an example, Figure 3C As shown, the via structure 220 may be connected to the via structure 212 through the wiring 350 formed in the ninth layer L9. Similarly, the via structure 230 may also be connected to the via structure 213 through the wiring 350 formed in the ninth layer L9.

[0030] As a non-limiting example for descriptive purposes only, the via structures 212 and 213 are formed in the lower layer 202 of the PCB 110, the signal input point 302 is formed in the ninth layer L9, and the signal output point 304 is formed in the sixteenth layer L16. The mutual capacitance point 330 of the via structure 212 is formed on the eleventh layer L11 and can be associated with a board formed on the eleventh layer L11 (e.g., see Fig. 6A ). The mutual capacitance point 330 of the via structure 213 is formed on the twelfth layer L12 and may be associated with a plate formed on the twelfth layer L12 (eg, see Figure 6B ). The plates of the eleventh layer L11 and the plates of the twelfth layer L12 may have regions overlapping each other (see, for example, Figure 6C ), and capacitive coupling can be generated between the overlapping plates to increase the mutual capacitance. For example, the capacitance can be proportional to the total surface area of ​​the overlapping plates.

[0031] The via structures 210 and 212 may be arranged to overlap or at least partially overlap each other in the Z-axis direction. The conductive material film 310 of the eighth layer L8 forming the signal output point 304 of the via structure 210 may be connected to a board (e.g., Figure 5A The conductive material film 310 of the ninth layer L9 forming the signal input point 302 of the via structure 212 may be connected to a board (eg, Figure 5B ). The boards of the eighth layer L8 and the boards of the ninth layer L9 may have overlapping areas (eg, Figure 5C ), and capacitive coupling can be generated between the plates that overlap each other so as to increase the mutual capacitance based on the overlapping area between the respective plates, for example.

[0032] The via structures 211 and 213 may also be arranged to overlap each other in the Z-axis direction. The conductive material film 310 of the eighth layer L8 forming the signal output point 304 of the via structure 211 may be connected to a board formed on the eighth layer L8 (see, for example, Figure 5A). The conductive material film 310 of the ninth layer L9 forming the signal input point 302 of the via structure 213 may be connected to a board formed on the ninth layer L9 (see, for example, Figure 5B ). The boards of the eighth layer L8 and the boards of the ninth layer L9 may have overlapping areas (e.g., Figure 5C ), and capacitive coupling can be generated between the plates overlapping each other to increase the mutual capacitance.

[0033] 4A to 6C is a diagram illustrating a capacitance pattern included in a via structure according to some example embodiments. FIG. 4A to FIG. 4C It is shown Figure 2 FIG. 1 is a diagram of capacitor patterns of a fifth layer L5 and a sixth layer L6 of the PCB 110 . FIG. 5A to FIG. 5C It is shown Figure 2 FIG. 1 is a diagram of capacitor patterns of the eighth layer L8 and the ninth layer L9 of the PCB 110 . FIG. 6A to FIG. 6C It is shown Figure 2 FIG. 1 is a diagram of capacitor patterns of an eleventh layer L11 and a twelfth layer L12 of a PCB 110 .

[0034] In combination Figures 2 to 3C Reference Figure 4A , the via structures 210 and 211 are adjacently disposed on the fifth layer L5 of the PCB 110, the ground vias 410a and 410b are disposed around the via structures 210 and 211, and the conductive material film 310 of the via structure 210 is connected to the metal plate 400. The ground vias 410a and 410b may include a cylinder filled with a conductive material film and may be connected to a ground voltage line of the PCB 110; however, example embodiments are not limited thereto. Figure 4B In the embodiment, the via structures 210 and 211 are adjacently disposed on the sixth layer L6 of the PCB 110, the ground vias 410a and 410b are disposed around the via structures 210 and 211, and the conductive material film 310 of the via structure 211 is connected to the metal plate 401. Figure 4C In the embodiment, mutual capacitance Cm01 due to capacitive coupling may be generated at a portion where the metal plate 400 of the fifth layer L5 and the metal plate 401 of the sixth layer L6 overlap each other. Therefore, the fifth layer L5 forming the metal plate 400 may provide a mutual capacitance point 330 of the via structure 210, and the sixth layer L6 forming the metal plate 401 may provide a mutual capacitance point 330 of the via structure 211.

[0035] refer to FIG. 4A to FIG. 4C At each of the fifth layer L5 and the sixth layer L6, there may be an insulating material, such as but not limited to plastic and / or ceramic, surrounding the metal plates 400 and 401, respectively. Figure 4C, a thin layer, such as a thin dielectric layer, may exist between the metal plate 400 and the metal plate 401 , for example, between the fifth layer L5 and the sixth layer L6 , and the metal plate 400 and the metal plate 401 may not directly contact each other; example embodiments are not limited thereto.

[0036] In combination Figures 2 to 3C Reference Figure 5A , the via structures 210 and 211 are adjacently disposed on the eighth layer L8 of the PCB 110, the ground vias 510a and 510b are disposed around the via structures 210 and 211, the conductive material film 310 of the via structure 210 is connected to the metal plates 500a and 500b, and the conductive material film 310 of the via structure 211 is connected to the metal plates 501a and 501b. Figure 5B In the figure, the via structures 212 and 213 are adjacently arranged on the ninth layer L9 of the PCB 110, the ground vias 510a and 510b are arranged around the via structures 212 and 213, the conductive material film 310 of the via structure 212 is connected to the metal plates 502a and 502b, and the conductive material film 310 of the via structure 213 is connected to the metal plates 503a and 503b.

[0037] The size and / or shape of each of the metal plates 500a, 500b, 501a, and 501b may be the same as each other; alternatively, at least one of the size and / or shape of at least one of the metal plates 500a, 500b, 501a, and 501b may be different from the other metal plates 500a, 500b, 501a, and 501b. In some example embodiments, one or more of the metal plates 500a, 500b, 501a, and 501b may have a rectangular shape or an oblique rectangular shape, such as a square shape or an oblique square shape; however, example embodiments are not limited thereto.

[0038] exist Figure 5CIn the embodiment, mutual capacitance due to capacitive coupling may be generated at the portion where the metal plates 500a, 500b, 501a and 501b of the eighth layer L8 and the metal plates 502a, 502b, 503a and 503b of the ninth layer L9 overlap with each other. As an example, mutual capacitance Cm02 due to capacitive coupling may be generated at the portion where the metal plate 500a of the eighth layer L8 and the metal plate 502a of the ninth layer L9 overlap with each other, mutual capacitance Cm03 due to capacitive coupling may be generated at the portion where the metal plate 500b of the eighth layer L8 and the metal plate 503b of the ninth layer L9 overlap with each other, mutual capacitance Cm13 due to capacitive coupling may be generated at the portion where the metal plate 501a of the eighth layer L8 and the metal plate 503a of the ninth layer L9 overlap with each other, and mutual capacitance Cm12 due to capacitive coupling may be generated at the portion where the metal plate 501b of the eighth layer L8 and the metal plate 502b of the ninth layer L9 overlap with each other.

[0039] In combination Figures 2 to 3C Reference Fig. 6A , the via structures 212 and 213 are adjacently disposed on the eleventh layer L11 of the PCB 110, and the ground vias 610a and 610b are disposed around the via structures 212 and 213, and the conductive material film 303 of the via structure 212 is connected to the metal plate 602. Figure 6B In the embodiment, the via structures 212 and 213 are adjacently disposed on the twelfth layer L12 of the PCB 110, the ground vias 610a and 610b are disposed around the via structures 212 and 213, and the conductive material film 303 of the via structure 213 is connected to the metal plate 603. Figure 6C In the embodiment, mutual capacitance Cm23 due to capacitive coupling may be generated at the portion where the metal plate 602 of the eleventh layer L11 and the metal plate 603 of the twelfth layer L12 overlap each other. Therefore, the eleventh layer L11 formed with the metal plate 602 may provide a mutual capacitance point 330 of the via structure 212, and the twelfth layer L12 formed with the metal plate 603 may provide a mutual capacitance point 330 of the via structure 213.

[0040] Figure 7 is a diagram illustrating mutual capacitance of a via structure according to various example embodiments. Figure 7 Shows Figure 2 The mutual capacitance between the via structures 210, 211, 212, 213 of the PCB 110. The specific arrangement of the via structures 210, 211, 212, 213 of the PCB 110 is not limited thereto, and Figure 7 Illustrative only.

[0041] In combination Figures 2 to 6C Reference Figure 7, the via structures 210 and 211 may be disposed adjacent to each other in the X-axis direction on the upper layer 201 of the PCB 110, and the via structures 212 and 213 may be disposed adjacent to each other in the X-axis direction on the lower layer 202 of the PCB 110. The via structures 210 and 212 may overlap in the Z-axis direction, and the via structures 211 and 213 may overlap in the Z-axis direction.

[0042] At a portion where the metal plate 400 of the fifth layer L5 and the metal plate 401 of the sixth layer L6 of the PCB 110 overlap each other, a coupling capacitor having a mutual capacitance Cm01 may exist between the via structures 210 and 211. At a portion where the metal plate 602 of the eleventh layer L11 and the metal plate 603 of the twelfth layer L12 of the PCB 110 overlap each other, a coupling capacitor having a mutual capacitance Cm23 may exist between the via structures 212 and 213. At a portion where the metal plate 500a of the eighth layer L8 and the metal plate 502a of the ninth layer L9 of the PCB 110 overlap each other, a coupling capacitor having a mutual capacitance Cm02 may exist between the via structures 210 and 212. At a portion where the metal plate 501a of the eighth layer L8 and the metal plate 503a of the ninth layer L9 of the PCB 110 overlap each other, a coupling capacitor having a mutual capacitance Cm13 may exist between the via structures 211 and 213. At a portion where the metal plate 500b of the eighth layer L8 and the metal plate 503b of the ninth layer L9 of the PCB 110 overlap each other, a coupling capacitor having a mutual capacitance Cm03 may exist between the via structures 210 and 213. At a portion where the metal plate 501b of the eighth layer L8 and the metal plate 502b of the ninth layer L9 of the PCB 110 overlap each other, a coupling capacitor having a mutual capacitance Cm12 may exist between the via structures 211 and 212.

[0043] Figure 8 is a diagram illustrating a via structure according to some example embodiments. Hereinafter, a suffix (eg, a of 210a and a of 212a) attached to the same reference numeral in different drawings is used to distinguish a plurality of circuits having similar or identical functions.

[0044] refer to Figure 8, at the portion where the conductive material film 310 of the via pad region of the signal output point 304 of the via structure 210 and the conductive material film 310 of the via pad region of the signal input point 302 of the via structure 212 overlap each other, a coupling capacitor having a mutual capacitance Cm80 may exist. In order to increase the mutual capacitance Cm80, as in the via structures 210a and 212a, a relatively wide conductive material film 810 may be formed in the via pad region of the signal output point 304 and the via pad region of the signal input point 302. In the via structures 210a and 212a that overlap in the Z-axis direction, the mutual capacitance Cm80a generated at the portion where the conductive material film 810 of the via pad region of the signal output point 304 and the conductive material film 810 of the through-hole pad region of the signal input point 302 overlap each other may be increased to be greater than the mutual capacitance Cm80 of the via structures 210 and 212.

[0045] Fig. 9 is a diagram showing a passage structure according to some example embodiments. For the sake of simplicity of the drawings, Fig. 9 Shown is a reference Figure 2 The via structures 910 to 917 are described as being included in the first to fourth layers L4 among the first to sixteenth layers L1 to L16 of the multilayer PCB 110, but in reality, the via structures 910 to 917 may also be included in the first to sixteenth layers L1 to L16.

[0046] refer to Fig. 9 , the path structures 910 to 917 are signal paths and may be provided in corresponding layers in the first layer L1 to the fourth layer L4. As an example, the path structures 910 and 911 respectively connected to the DQ0 data signal and the DQ1 data signal are provided on the first layer L1, the path structures 912 and 913 respectively connected to the DQ2 data signal and the DQ3 data signal are provided on the second layer L2, the path structures 914 and 915 respectively connected to the DQ4 data signal and the DQ5 data signal are provided on the third layer L3, and the path structures 916 and 917 respectively connected to the DQ6 data signal and the DQ7 data signal are provided on the fourth layer L4.

[0047] The via structures 910 to 917 may include a laser via (LVH) cylinder. The LVH cylinder formed on each of the first layer L1 to the fourth layer L4 may include an insulating layer and may be formed by a process comprising: attaching a first metal layer and a second metal layer to the upper and lower surfaces of the insulating layer by applying a specific (such as dynamically determined or predetermined) heat and / or a specific (such as dynamically determined or predetermined) pressure; etching the first metal layer to form a via; forming a via using a laser device; and forming an electroplating layer by electroplating the inside of the via. The electroplating layer formed on the LVH may be electrically connected to the first metal layer and the second metal layer. The first metal layer and the second metal layer connected to the LVH electroplating layer in the via structures 910 to 917 may be used as a metal plate. The first metal layer and the second metal layer overlapping each other in adjacent via structures in the via structures 910 to 917 may exist as a coupling capacitor having mutual capacitance.

[0048] For example, a coupling capacitor having mutual capacitance C901 may exist between via structures 910 and 911, a coupling capacitor having mutual capacitance C902 may exist between via structures 910 and 912, and a coupling capacitor having mutual capacitance C903 may exist between via structures 910 and 913. A coupling capacitor having mutual capacitance C912 may exist between via structures 911 and 912, and a coupling capacitor having mutual capacitance C913 may exist between via structures 911 and 913. A coupling capacitor having mutual capacitance C923 may exist between via structures 912 and 913, a coupling capacitor having mutual capacitance C924 may exist between via structures 912 and 914, and a coupling capacitor having mutual capacitance C925 may exist between via structures 912 and 915. A coupling capacitor having mutual capacitance C934 may exist between via structures 913 and 914, and a coupling capacitor having mutual capacitance C935 may exist between via structures 913 and 915. A coupling capacitor having mutual capacitance C945 may exist between via structures 914 and 915, a coupling capacitor having mutual capacitance C946 may exist between via structures 914 and 916, and a coupling capacitor having mutual capacitance C947 may exist between via structures 914 and 917. A coupling capacitor having mutual capacitance C956 may exist between via structures 915 and 916, and a coupling capacitor having mutual capacitance C957 may exist between via structures 915 and 917. A coupling capacitor having mutual capacitance C967 may exist between via structures 916 and 917. The capacitance of each coupling capacitor may be determined based on, and may be proportional to, the amount of overlap of the corresponding metal plates.

[0049] Figures 10 to 12 is a diagram illustrating a memory module according to some example embodiments.

[0050] refer to Fig.10 , the memory module 1000 may include a module substrate 1010, a module connector 1020, and memory packages 1030, 1040, 1050, and 1060, and a passive element 1070. The memory packages 1030, 1040, 1050, and 1060 may include LPDDR DRAMs, and the memory module 1000 may include a low-power compression additional memory module (LP-CAMM). The module substrate 1010 may include a multi-layer PCB 1010, a plurality of memory packages 1030 to 1060 may be mounted on an upper surface of the multi-layer PCB 1010, and the module connector 1020 may be provided on a lower surface of the PCB 1010 at a position opposite to pins of the memory packages 1030 to 1060.

[0051] refer to Fig.11 , the memory module 1100 may include a plurality of memory chips 1121 to 1129 mounted on the upper surface of the multilayer PCB 1110 and a connector 1160 having a tab pin type. The memory module 1100 may include a registered DIMM (RDIMM); however, example embodiments are not limited thereto. A plurality of memory chips may also be disposed on the lower surface of the multilayer PCB 1110. Although nine memory chips are shown, example embodiments are not limited thereto. The register 1102 may have a function of buffering and re-driving the command, address, and control signals received through the connector 1160. The command, address, and control signals output from the register 1102 may be provided to the memory chips 1121 to 1129. For example, the register 1102 may provide one or more of the command, address, and control signals to all memory chips 1121 to 1129 through a common signal line, through a separate signal line of each memory chip 1121 to 1129, or through a signal line of each of some memory chips in a number of memory chips 1121 to 1129. The number of memory chips 1121 to 1129 may be determined according to the structure and I / O configuration of the memory module 1100 .

[0052] refer to Fig.12, the memory module 1200 may include a plurality of memory chips 1221 to 1229, a controller 1230, data buffers 1241 to 1249, and a connector 1260 having a tap pin type. The memory module 1200 may include a low load dual in-line memory module (LRDIMM). The memory chips 1221 to 1229, the controller 1230, and the data buffers 1241 to 1249 may be implemented in semiconductor packages different from each other, and may be respectively arranged on one side or both sides of the multilayer PCB 1210. The controller 1230 may convert commands, addresses, and control signals received through the connector 1260 into internal commands, internal addresses, and internal control signals, and send the converted internal commands, internal addresses, and internal control signals to the memory chips 1221 to 1229. The controller 1230 may control the memory chips 1221 to 1229 using the internal commands, internal addresses, and internal control signals. The controller 1230 may send a buffer command to the data buffers 1241 to 1249 and use the buffer command to control the data buffers 1241 to 1249. The memory chips 1221 to 1229 are respectively connected to the data buffers 1241 to 1249 and may exchange internal data signals and internal clock signals with the data buffers 1241 to 1249. The data buffers 1241 to 1249 may exchange external data signals and external clock signals with an external memory controller outside the memory module 1200 through the connector 1260.

[0053] Figures 10 to 12PCBs 1010, 1110, and 1210 of the present invention may include a first via structure and a second via structure, the first via structure partially penetrating multiple layers of the PCBs 1010, 1100, and 1210 and connected to a first metal plate disposed on a first layer among the multiple layers, the second via structure being disposed adjacent to the first via structure in a horizontal direction, partially penetrating multiple layers of the PCB, and connected to a second metal plate disposed on a second layer among the multiple layers. The portion where the first metal plate and the second metal plate overlap each other may provide a first mutual capacitance coupling between the first via structure and the second via structure. PCBs 1010, 1110, and 1210 may include N layers stacked in sequence, and may include M via structures that transmit M signals respectively and penetrate each of the N layers of the PCB. The first mutual capacitance coupling may be disposed between the first via structure and the second via structure that are adjacent to each other in the horizontal direction of the PCB among the M via structures, and the second mutual capacitance coupling may be disposed between the third via structure and the fourth via structure that overlap the first via structure and the second via structure in a vertical direction, respectively. The path structure may include a conductive material film including an insulating material layer formed at the center of a cylinder on PCBs 1010, 1110, and 1210. The cylinder partially penetrates multiple layers of PCBs 1010, 1110, and 1210 to provide a signal input point and a signal output point, and among the layers penetrated between the signal input point and the signal output point, a layer forming a metal plate may provide a mutual capacitance point. The size of the conductive material layer located in the region of the signal input point and the region of the signal output point may be greater than the size of the conductive material layer in the region of the mutual capacitance point.

[0054] Fig.13 is a block diagram for describing a system 2000 of an electronic device including a memory module according to some example embodiments.

[0055] refer to Fig.13 , the system 2000 may include a camera 2100, a display 2200, an audio processing unit 2300, a modem 2400, DRAMs 2500a and 2500b, flash memories 2600a and 2600b, I / O devices 2700a and 2700b, and an application processor 2800 (hereinafter referred to as "AP"). The system 2000 is implemented as or includes one or more of a laptop computer, a mobile phone, a smart phone, a tablet personal computer (tablet PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device, or may be included therein. In addition, the system 2000 may be implemented as or includes a server and / or a personal computer, or may be included therein.

[0056] The camera 2100 can capture still images or moving images under user control, and can store captured image / video data and / or send captured image / video data to the display 2200. The audio processing unit 2300 can process audio data or network content included in the flash memory 2600a and 2600b. The modem 2400 modulates and / or transmits a signal for transmission / reception of wired / wireless data, and can demodulate on the receiving side to restore the original signal. The I / O devices 2700a and 2700b may include devices that provide digital input and / or output functions, such as one or more of a universal serial bus (USB), a memory, a digital camera, a secure digital (SD) card, a digital versatile disc (DVD), a network adapter, a touch screen, etc.

[0057] The AP 2800 may control the overall operation of the system 2000. The AP 2800 may include a control block 2810, an accelerator block or an accelerator chip 2820, and an interface block 2830. The AP 2800 may control the display 2200 to display some contents stored in the flash memories 2600a and 2600b on the display 2200. When a user input is received through the I / O devices 2700a and 2700b, the AP 2800 may perform a control operation corresponding to the user input. The AP 2800 may include an accelerator block, which is a dedicated circuit for artificial intelligence (AI) data calculation, or may include an accelerator chip 2820 separated from the AP 2800. In some example embodiments, the DRAM 2500b may be additionally mounted on the accelerator block or the accelerator chip 2820. The accelerator is a functional block specialized in performing specific functions of the AP 2800, and may include one or more of a GPU (a functional block specialized in graphics data processing), a neural processing unit (NPU) (a block specialized in AI calculations and reasoning), and a data processing unit (DPU) (a block specialized in data transmission).

[0058] The system 2000 may include a plurality of DRAMs 2500a and 2500b. The AP 2800 may control the DRAMs 2500a and 2500b through command and mode register (MRS) settings that comply with the Joint Electron Device Engineering Council (JEDEC) standard, or use company-specific functions such as low voltage / high speed / reliability and cyclic redundancy check (CRC) / error correction code (ECC) functions, and DRAM interface rules may be set and communicated. For example, the AP 2800 may communicate with the DRAM 2500a through an interface that complies with the JEDEC standard (such as LPDDR4 and / or LPDDR5), and the accelerator block or accelerator chip 2820 may communicate by setting a new DRAM interface protocol to control the accelerator DRAM 2500b having a higher bandwidth than the DRAM 2500a.

[0059] Despite Fig.13 Only DRAM 2500a and 2500b are shown in the figure, but it is not limited thereto, and if one or more of the bandwidth, response speed and voltage conditions of AP 2800 or accelerator chip 2820 are met, any memory such as one or more of PRAM, SRAM, MRAM, RRAM, FRAM or hybrid RAM can be used. Compared with I / O devices 2700a and 2700b or flash memory 2600a and 2600b, DRAM 2500a and 2500b have relatively small latency and bandwidth. DRAM 2500a and 2500b are initialized when system 2000 is powered on, and when the operating system and application data are loaded, DRAM 2500a and 2500b can be used as a temporary storage device for the operating system and application data or as an execution space for various software codes.

[0060] In DRAM 2500a and 2500b, one or more of the four arithmetic operations of addition / subtraction / multiplication / division and vector operations, addressing operations, or fast Fourier transform (FFT) operations can be performed. In addition, in DRAM 2500a and 2500b, an execution function for reasoning can be performed. Here, an artificial neural network can be used to perform reasoning in a deep learning algorithm. The deep learning algorithm may include a training operation through various data learning models and an inference operation using the learned model to recognize data. In some example embodiments, the image captured by the user through the camera 2100 is signal processed and stored in the DRAM 2500b, and the accelerator block or accelerator chip 2820 can use the data stored in the DRAM 2500b and the function for reasoning to perform AI data operations to recognize data.

[0061] System 2000 may include multiple storage devices or multiple flash memories 2600a and 2600b having a capacity greater than DRAM 2500a and 2500b. The accelerator block or accelerator chip 2820 may use flash memories 2600a and 2600b to perform training operations and AI data operations. In one embodiment, flash memories 2600a and 2600b may include a memory controller 2610 and a flash memory device 2620, and may use an arithmetic unit included in the memory controller 2610 to more efficiently perform training operations and reasoning AI data operations performed by AP 2800 and / or accelerator chip 2820. Flash memories 2600a and 2600b may store photos taken by camera 2100 or data transmitted over a data network. For example, flash memories 2600a and 2600b may store augmented reality / virtual reality, high definition (HD) or ultra high definition (UHD) content.

[0062] In the system 2000, the DRAM 2500a and 2500b and / or the flash memory 2600a and 2600b may include reference Figures 1 to 12 The memory module described. The memory module includes a multi-layer PCB, a first passage structure and a second passage structure, the first passage structure partially penetrates the multiple layers of the PCB and is connected to a first metal plate in the first layer arranged among the multiple layers, the second passage structure is arranged adjacent to the first passage structure in the horizontal direction, partially penetrates the multiple layers of the PCB, and is connected to a second metal plate arranged on the second layer of the multiple layers. The portion where the first metal plate and the second metal plate overlap each other can provide a first mutual capacitance coupling between the first passage structure and the second passage structure. The memory module may include a PCB and M passage structures, the PCB including N layers stacked in sequence, the M passage structures respectively transmitting M signals and penetrating each layer of the N layers of the PCB. In the M passage structures, the first mutual capacitance coupling may be arranged between the first passage structure and the second passage structure adjacent to each other in the horizontal direction of the PCB, and the second mutual capacitance coupling may be arranged between the third passage structure and the fourth passage structure respectively overlapping with the first passage structure and the second passage structure in the vertical direction. The passage structure may include a conductive material film having an insulating material film embedded in the central portion of a cylinder formed on the multiple layers of the PCB. The cylinder can provide a signal input point and a signal output point by partially penetrating multiple layers of the PCB, and in the layers penetrated between the signal input point and the output point, a layer formed with a metal plate can provide a mutual capacitance point. The size of the conductive material film in the area of ​​the signal input point and the area of ​​the signal output point can be larger than the size of the conductive material film in the area of ​​the mutual capacitance point. The memory module can provide a high-speed and high-performance solution for the memory device by effectively reducing crosstalk and removing signal interference and noise using a path structure that forms mutual capacitance coupling.

[0063] Any or all of the elements described with reference to the figures may communicate with any or all of the other elements described with reference to the figures. For example, any element may communicate unidirectionally and / or bidirectionally and / or broadcast with any or all of the other elements in the figures to transmit and / or exchange and / or receive information, such as, but not limited to, data and / or commands, in a manner such as serial and / or parallel, via a bus (not shown) such as a wireless and / or wired bus. The information may be in various encoding formats, such as, analog formats and / or digital formats.

[0064] Any element and / or functional block disclosed above may include a processing circuit or be implemented in a processing circuit, such as hardware including a logic circuit; a hardware / software combination, such as a processor executing software; or a combination thereof. For example, more specifically, the processing circuit may include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc. The processing circuit may include electronic components, such as at least one of a transistor, a resistor, a capacitor, etc. The processing circuit may include electronic components, such as a logic gate including at least one of an AND gate, an OR gate, a NAND gate, a NOT gate, etc.

[0065] Although various inventive concepts have been specifically shown and described with reference to some example embodiments of the inventive concepts, it will be understood that various changes in form and detail may be made thereto without departing from the spirit and scope of the appended claims. In addition, the example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures.

Claims

1. A device having a passage structure, the device comprising: A printed circuit board, the printed circuit board comprising multiple layers stacked in sequence; a first via structure that partially penetrates the multiple layers of the printed circuit board and is connected to a first metal plate on a first layer of the multiple layers; and a second via structure, the second via structure being adjacent to the first via structure in a horizontal direction, partially penetrating the multiple layers of the printed circuit board, and connected to a second metal plate located on a second layer of the multiple layers, The portions where the first metal plate and the second metal plate overlap each other are configured to provide a first mutual capacitive coupling between the first via structure and the second via structure.

2. The device according to claim 1, wherein: The first layer and the second layer are adjacent to each other in a vertical direction of the printed circuit board.

3. The device according to claim 1, further comprising: a third passage structure, the third passage structure being adjacent to the first passage structure in a vertical direction, Wherein, a portion where the first via structure and the third via structure overlap in the vertical direction is configured to provide a second mutual capacitive coupling.

4. The device according to claim 3, wherein: A third mutual capacitive coupling extending from the second via structure to the third via structure is configured to be disposed between the second via structure and the third via structure.

5. The device according to claim 3, further comprising: a fourth passage structure, the fourth passage structure being adjacent to the second passage structure in the vertical direction, Wherein, a portion where the second via structure and the fourth via structure overlap in the vertical direction is configured to provide a fourth mutual capacitive coupling.

6. The device according to claim 5, wherein: A fifth mutual capacitive coupling extending from the first via structure to the fourth via structure is configured to be disposed between the first via structure and the fourth via structure.

7. The device according to claim 1, wherein: The first via structure and the second via structure each independently include at least one of a blind via cylinder or a buried via cylinder partially penetrating the multiple layers.

8. The device according to claim 1, further comprising: A circular passage structure is arranged around the first passage structure and the second passage structure.

9. The device according to claim 1, wherein: The apparatus includes a memory module that is at least one of a compression additional memory module, a low power compression additional memory module, a registered dual in-line memory module, and a low load dual in-line memory module.

10. A device having a passage structure, the device comprising: A printed circuit board, wherein the printed circuit board comprises N layers stacked in sequence, where N is a natural number; and M via structures, the M via structures are respectively configured to transmit M signals and pass through each of the N layers of the printed circuit board, M is a natural number, wherein the first mutual capacitance coupling is configured to be disposed between a first via structure and a second via structure adjacent to each other in a horizontal direction of the printed circuit board among the M via structures, and The second mutual capacitive coupling is configured to be provided between a third via structure overlapping with the first via structure in a vertical direction and a fourth via structure overlapping with the second via structure among the M via structures.

11. The device according to claim 10, wherein: A third mutual capacitive coupling extending from the first via structure to the third via structure is configured to be disposed between the first via structure and the third via structure.

12. The device according to claim 10, wherein: A third mutual capacitive coupling extending from the first via structure to the fourth via structure is configured to be disposed between the first via structure and the fourth via structure.

13. The device according to claim 10, wherein: A third mutual capacitive coupling extending from the second via structure to the third via structure is configured to be disposed between the second via structure and the third via structure.

14. The device according to claim 10, wherein: A third mutual capacitive coupling extending from the second via structure to the fourth via structure is configured to be disposed between the second via structure and the fourth via structure.

15. The apparatus according to claim 10, further comprising: a first metal plate connected to the first via structure in a layer among the N layers in which the first via structure is arranged; and a second metal plate connected to the third via structure in a layer among the N layers in which the third via structure is arranged, The portion where the first metal plate and the second metal plate overlap each other is configured to provide a third mutual capacitive coupling between the first via structure and the third via structure.

16. The device according to claim 10, wherein: The M passage structures each include a laser passage cylinder partially passing through the N layers.

17. The device according to claim 10, wherein: The apparatus includes a memory module of any one of a compression add-on memory module, a low power compression add-on memory module, a registered dual in-line memory module, and a low load dual in-line memory module.

18. A passage structure, comprising: a barrel, the barrel being located on a printed circuit board, the printed circuit board comprising multiple layers stacked in sequence; and a conductive material film having an insulating material film embedded in the center of the barrel, wherein the cylinder is configured to provide a signal input point and a signal output point by partially penetrating the multiple layers, and among the layers penetrated between the signal input point and the signal output point, the layer where the metal plate is arranged is configured to provide a mutual capacitance point, and The conductive material films located in the region of the signal input point and the region of the signal output point are arranged to have a size larger than that of the conductive material film located in the region of the mutual capacitance point.

19. The passage structure according to claim 18, wherein: The cylinder includes at least one of a blind via cylinder or a buried via cylinder.

20. The passage structure according to claim 18, wherein The barrel includes a laser passage barrel.

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