Chip packaging unit, stacked module thereof and manufacturing method of stacked module

Abstract

The invention discloses a chip packaging unit and a stacking module and a manufacturing method thereof, the chip packaging unit stacking module comprises at least two chip packaging units which form an up-down corresponding stacking relation, each chip packaging unit comprises a plurality of conductive columns, and the upper end and the lower end of each conductive column are respectively provided with an upper connecting pad and a lower connecting pad; wherein the chip packaging unit at the upper part is electrically coupled and butted with each upper connecting pad of the chip packaging unit at the lower part through each lower connecting pad so as to be mutually stacked with the chip packaging unit at the lower part; wherein each conductive column of the chip packaging unit at the upper part is correspondingly and electrically connected with each conductive column of the chip packaging unit at the lower part, so that the at least one memory chip of the chip packaging unit at the upper part can be electrically connected with the at least one memory chip of the chip packaging unit at the lower part.

Description

Technical Field

[0001] The present invention relates to a chip packaging unit and a stacking module thereof and a manufacturing method thereof, and in particular to a chip packaging unit and a stacking module thereof in which a conductive column in the packaging unit is embedded and the manufacturing process is simplified, and a manufacturing method thereof. Background Art

[0002] In the field of memory technology in the semiconductor industry, as the times evolve, the memory function / capacity continues to increase. In order to expand the memory function / capacity, there is a technology that uses at least two chips to stack to meet market demand. However, in the chip stacking technology, since the early stage adopted the operation method of stacking chips first and then molding them as a whole, as long as one chip in the stacked chips is defective, the entire chip stack must be replaced or repaired, which increases the manufacturing cost and quality control cost of the manufacturing end, is not conducive to mass production, and does not meet the needs of the modern market. Therefore, in the prior art, there is a technology that uses multiple molded chip packaging units for stacking, such as the stacking technology disclosed in US Patent US 9,685,429 B2 (the technology of this case has also been approved by China Patent CN 204885152 U and Taiwan Patent M509421) and US Patent US 8,502,378 B2 (the technology of this case has also been approved by Taiwan Patent I501365), which can reduce the manufacturing cost and quality control cost of the manufacturing end and make the product easy to mass produce.

[0003] However, the above-mentioned existing technologies still have shortcomings that need to be improved. For example, in the technology disclosed in U.S. Patent No. 9,685,429B2, the conductive pillars in the package unit stacking module are metal pillars exposed outside the insulating layer and are not molded together with the chip, which makes the conductive pillars easily damaged and causes poor product yield, which is not conducive to market competitiveness. In addition, in the technology disclosed in U.S. Patent No. 8,502,378 B2, although the conductive pillars in the package unit stacking module are buried in the insulating layer, because the conductive pillars are connected by two different conductive pillars generated by two different processes, the process is complicated and is not conducive to reducing the cost of the manufacturing end.

[0004] Therefore, a chip packaging unit in which the conductive pillars in the packaging unit are embedded and the manufacturing process is simplified, a stacking module thereof, and a manufacturing method thereof are urgently expected by the current relevant industries. Summary of the invention

[0005] The main purpose of the present invention is to provide a chip packaging unit and its stacking module and a manufacturing method thereof, wherein the chip packaging unit stacking module includes at least two chip packaging units forming a corresponding stacking relationship, each chip packaging unit includes a plurality of conductive pillars, and the upper and lower ends of each conductive pillar are respectively provided with an upper pad and a lower pad; wherein each upper chip packaging unit is stacked with each lower chip packaging unit by electrically coupling and docking with each upper pad of each lower chip packaging unit through each lower pad; wherein each conductive pillar of each upper chip packaging unit is electrically connected to each conductive pillar of each lower chip packaging unit correspondingly, so that each memory chip of each upper chip packaging unit can be electrically connected to each other with each memory chip of each lower chip packaging unit, thereby effectively solving the problem in the prior art that the conductive pillars are easily damaged due to exposure, resulting in poor product yield and complicated process.

[0006] To achieve the above-mentioned purpose, the present invention provides a chip packaging unit, which includes a substrate, a patterned circuit layer, at least one memory chip, an insulating layer, a plurality of vias and a plurality of conductive pillars; wherein the patterned circuit layer is arranged on the surface of the substrate; wherein the at least one memory chip is electrically coupled to the patterned circuit layer by flip chip technology; wherein the insulating layer covers the substrate and covers the gap between the at least one memory chip and the substrate; each of the vias vertically penetrates the substrate and the insulating layer and is arranged at a preset fixed position outside the at least one memory chip; the plurality of conductive pillars are formed in the plurality of vias, and each of the conductive pillars has an upper pad and a lower pad opposite to each other at the upper and lower ends; wherein the at least one memory chip is electrically connected to the plurality of conductive pillars via the patterned circuit layer, and is electrically connected to the outside via the upper pad or the lower pad of each of the conductive pillars, so as to increase the market competitiveness of the product and reduce the cost of the manufacturing end.

[0007] The present invention also provides a chip packaging unit stacking module, which includes at least two chip packaging units, each chip unit is as described above, and two adjacent chip packaging units form a corresponding stacking relationship of one up and one down, each chip packaging unit includes a substrate, a patterned circuit layer, at least one memory chip, an insulating layer, a plurality of conductive holes and a plurality of conductive pillars; wherein each lower pad of the upper chip packaging unit forms an upper and lower corresponding relationship with the position of each upper pad of the lower chip packaging unit; wherein the upper chip packaging unit is stacked with the lower chip packaging unit by electrically coupling and docking each lower pad with each upper pad of the lower chip packaging unit; wherein each conductive pillar of the upper chip packaging unit is electrically connected to each conductive pillar of the lower chip packaging unit, so that the at least one memory chip of the upper chip packaging unit and the at least one memory chip of the lower chip packaging unit can be electrically connected to each other, so as to facilitate the expansion of memory function / capacity.

[0008] In a preferred embodiment of the present invention, the chip package unit stacking module further comprises at least one solder ball, and the at least one solder ball is disposed on each of the lower pads of the lowermost chip package unit in each of the chip package units.

[0009] In a preferred embodiment of the present invention, the chip packaging unit stacking module is further disposed on a circuit board.

[0010] The present invention also provides a method for manufacturing a chip packaging unit stacking module, which includes the following steps: Step S1: providing at least two of the above-mentioned chip packaging units; Step S2: making the two adjacent chip packaging units form an upper and lower corresponding relationship, and each lower pad of the upper chip packaging unit is in a corresponding relationship with each upper pad of the lower chip packaging unit, and is aligned with each other up and down; and Step S3: making the upper chip packaging unit electrically coupled and docked with each upper pad of the lower chip packaging unit via each lower pad, so that the upper chip packaging unit and the lower chip packaging unit are stacked together to form a chip packaging unit stacking module, so as to facilitate mass production. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic plan view of a side section of two chip packaging units in the chip packaging unit stacking module of the present invention.

[0012] Figure 2 It is a schematic plan view of a side cross-section of the chip packaging unit of the present invention.

[0013] Figure 3 yes Figure 1Schematic diagram of the decomposition.

[0014] Figure 4 yes Figure 1 An exploded schematic diagram of a chip packaging unit stacking module stacking another chip packaging unit.

[0015] Figure 5 It is a schematic plan view of a side section showing three chip packaging units in a chip packaging unit stacking module of the present invention.

[0016] Explanation of the reference numerals: 1-chip packaging unit stacking module; 10-chip packaging unit; 11-substrate; 12-patterned circuit layer; 13-memory chip; 14-insulating layer; 15-upper pad; 16-lower pad; 17-conductive hole; 18-conductive column; 20-solder ball; 30-conductive metal; 2-circuit board. DETAILED DESCRIPTION

[0017] With the help of illustrations, the structure and technical features of the present invention are described in detail as follows, wherein each illustration is only used to illustrate the structural relationship and related functions of the present invention, so the size of each element in each illustration is not drawn according to the actual scale and is not used to limit the present invention.

[0018] refer to Figure 1 and Figure 5 The present invention provides a chip packaging unit stacking module 1, the chip packaging unit stacking module 1 comprises at least two chip packaging units 10, and two adjacent chip packaging units 10 form a corresponding stacking relationship of one up and one down, each chip packaging unit 10 comprises a substrate 11, a patterned circuit layer 12, at least one memory chip 13, an insulating layer 14, a plurality of vias 17 and a plurality of conductive pillars 18, such as Figure 2 shown.

[0019] The patterned circuit layer 12 is disposed on the surface of the substrate 11. Figure 2 shown.

[0020] Each memory chip 13 is electrically coupled to the patterned circuit layer 12 by using a flip chip technique. Figure 2 shown.

[0021] The insulating layer 14 covers the substrate 11 and covers the gap between each memory chip 13 and the substrate 11. Figure 2 as shown to help protect the structures.

[0022] Each via 17 vertically penetrates the substrate 11 and the insulating layer 14 and is disposed at a predetermined fixed position around each memory chip 13. Figure 2wherein each via 17 can be formed by laser drilling, mechanical drilling or etching drilling techniques but is not limited.

[0023] Each conductive column 18 is formed in each conductive hole 17. The upper and lower ends of each conductive column 18 respectively have an upper pad 15 and an opposite lower pad 16. Figure 2 shown.

[0024] refer to Figure 2 Each memory chip 13 is electrically connected to each conductive pillar 18 via the patterned circuit layer 12 , and is electrically connected to the outside through the upper pad 15 or the lower pad 16 of each conductive pillar 18 .

[0025] refer to Figure 1 and Figure 5 In the chip packaging unit stacking module 1, the lower pads 16 of the upper chip packaging unit 10 form a vertical corresponding relationship with the positions of the upper pads 15 of the lower chip packaging unit 10; wherein the upper chip packaging unit 10 is stacked with the lower chip packaging unit 10 by electrically coupling and docking with the upper pads 15 of the lower chip packaging unit 10 through the lower pads 16; wherein the conductive pillars 18 of the upper chip packaging unit 10 are electrically connected to the conductive pillars 18 of the lower chip packaging unit 10, so that the memory chips 13 of the upper chip packaging unit 10 can be electrically connected to the memory chips 13 of the lower chip packaging unit 10, so as to expand the memory function / capacity.

[0026] refer to Figure 4 and Figure 5 The number of chip packaging units 10 of the chip packaging unit stacking module 1 is further three but not limited, so as to facilitate the expansion of memory function / capacity.

[0027] refer to Figure 1 , Figures 3 to 5 In the chip packaging unit stacking module 1, there is further a conductive metal 30 between each lower pad 16 of the upper chip packaging unit 10 and each upper pad 15 of the lower chip packaging unit 10, but it is not limited, so that each lower pad 16 and each upper pad 15 can be connected through each conductive metal 30 after reflow, thereby greatly improving the connection strength.

[0028] refer to Figure 1 and Figure 5 The chip package unit stacking module 1 further includes at least one solder ball 20 but is not limited thereto. Each solder ball 30 is disposed on each lower pad 16 of each chip package unit 10 at the bottom of each chip package unit 10 .

[0029] refer to Figure 1 and Figure 5 The chip packaging unit stacking module 1 is further arranged on a circuit board (PCB) 2 but is not limited; wherein the chip packaging unit stacking module 1 is further supplied to the technical field of FOiP (Fan-Out in PCB) but is not limited.

[0030] refer to Figure 1 , Figures 3 to 5 The present invention also provides a method for manufacturing the chip packaging unit stacking module 1, the method comprising the following steps:

[0031] Step S1: providing at least two chip packaging units 10, such as Figure 1 , Figures 3 to 5 shown.

[0032] Step S2: The two adjacent chip packaging units 10 are arranged in a top-bottom relationship, and the lower pads 16 of the upper chip packaging unit 10 are aligned with the upper pads 15 of the lower chip packaging unit 10 to form a top-bottom corresponding relationship, such as Figure 3 and Figure 4 shown.

[0033] Step S3: The upper chip package unit 10 is electrically coupled to the upper pads 15 of the lower chip package unit 10 through the lower pads 16. Figure 1 and Figure 5 As shown, the chip packaging unit 10 on the upper side is stacked with the chip packaging unit 10 on the lower side to form the chip packaging unit stacking module 1, as shown in FIG. Figure 1 and Figure 5 shown.

[0034] Compared with the existing stacking modules, the chip packaging unit stacking module 1 of the present invention has the following advantages:

[0035] (1) Each via hole 17 of the present invention vertically penetrates the substrate 11 and the insulating layer 14 and is disposed at a predetermined fixed position on the periphery of each memory chip 13, such as Figure 2 As shown, each conductive column 18 is formed in each conductive hole 17, which effectively solves the problem of poor product yield caused by the conductive columns of the existing stacked modules being exposed outside the insulating layer and easily damaged, thereby increasing the market competitiveness of the product.

[0036] (2) Each conductive column 18 of the present invention is directly and vertically penetrated through the substrate 11 and the insulating layer 14 to be formed on the chip packaging unit, which effectively solves the problem that the conductive columns of the existing stacking module are formed by connecting two conductive columns generated by two different processes, which complicates the process, and is conducive to reducing the cost of the manufacturing end.

[0037] (3) In the manufacturing method of the chip packaging unit stacking module 1 of the present invention, two adjacent chip packaging units 10 form a corresponding relationship of one above and one below, and the positions of the lower pads 16 of the upper chip packaging unit 10 and the upper pads 15 of the lower chip packaging unit 10 form a corresponding relationship of being aligned with each other up and down, such as Figure 3 and Figure 4 As shown, each chip packaging unit 10 can be stacked more accurately, which helps the manufacturing end to speed up the stacking efficiency and shorten the time cost of mass production.

[0038] The above description is only a preferred embodiment of the present invention, which is only illustrative rather than restrictive of the present invention. A person skilled in the art will understand that many changes, modifications, and even equivalent changes may be made to the present invention within the spirit and scope defined by the claims of the present invention, but all of these will fall within the scope of protection of the present invention.

Claims

1. A chip packaging unit, characterized in that: Include: a substrate; A patterned circuit layer is disposed on the surface of the substrate; At least one memory chip is electrically coupled to the patterned circuit layer by using flip chip technology; an insulating layer covering the substrate and enclosing a gap between the at least one memory chip and the substrate; A plurality of vias vertically penetrating the substrate and the insulating layer and arranged at predetermined fixed positions around the at least one memory chip; and A plurality of conductive posts are formed in the plurality of conductive holes, and each conductive post has an upper pad and an opposite lower pad at the upper and lower ends thereof; The at least one memory chip is electrically connected to each of the conductive pillars via the patterned circuit layer, and is electrically connected to the outside via the upper pad or the lower pad of each of the conductive pillars.

2. A chip packaging unit stacking module, characterized in that: Include: At least two chip packaging units, each of which is the chip packaging unit as claimed in claim 1, and two adjacent chip packaging units form a corresponding stacking relationship one above and one below; wherein each lower pad of the upper chip packaging unit forms a vertical corresponding relationship with each upper pad of the lower chip packaging unit; The upper chip package unit is stacked with the lower chip package unit by electrically coupling each of the lower pads to each of the upper pads of the lower chip package unit; Each of the conductive pillars of the upper chip packaging unit is electrically connected to each of the conductive pillars of the lower chip packaging unit, so that the at least one memory chip of the upper chip packaging unit and the at least one memory chip of the lower chip packaging unit can be electrically connected to each other.

3. The chip packaging unit stacking module according to claim 2, characterized in that: The chip package unit stacking module further includes at least one solder ball, and the at least one solder ball is disposed on each of the lower pads of the lowermost chip package unit among the at least two chip package units.

4. The chip packaging unit stacking module according to claim 2, characterized in that: The chip packaging unit stacking module is further arranged on a circuit board.

5. A method for manufacturing a chip packaging unit stacking module, characterized in that: It includes the following steps: Step S1: providing at least two chip packaging units as claimed in claim 1; Step S2: The two adjacent chip packaging units are arranged in an upper and lower correspondence relationship, and each lower pad of the upper chip packaging unit is aligned with each upper pad of the lower chip packaging unit in a corresponding relationship; and Step S3: The upper chip packaging unit is electrically coupled to each of the upper pads of the lower chip packaging unit through each of the lower pads, so that the upper chip packaging unit and the lower chip packaging unit are stacked together to form a chip packaging unit stacking module.

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