Display substrate, preparation method thereof and display panel

Abstract

The invention provides a display substrate. The display substrate is divided into a plurality of pixel regions and spacer regions filled among the pixel regions; the display panel comprises a substrate base plate; a first electrode layer including a plurality of first electrodes; the pixel limiting layer is arranged on the side, away from the substrate, of the first electrode layer, and the pixel limiting layer comprises a pixel opening located in the pixel area and a pixel retaining wall located in the spacer area; the multiple light-emitting layers cover the side, away from the first electrode layer, of the pixel limiting layer, and the multiple light-emitting layers are stacked in sequence; the connecting layers are arranged between the adjacent light-emitting layers, and the connecting layers cover the light-emitting layers; a second electrode layer including a second electrode of each light emitting unit; the display substrate further comprises a blocking piece located between the pixel retaining wall and one, closest to the substrate, of the multiple light-emitting layers. The blocking piece is provided with a first groove part which is at least partially penetrated along the thickness direction; the conductivity of the part of the connecting layer in the first groove part is smaller than the conductivity of the part of the connecting layer in the pixel area.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a preparation method thereof, and a display panel. Background Art

[0002] Organic light-emitting display devices (OLED) have the advantages of self-luminescence, fast response, wide viewing angle, high brightness, bright colors, and thinness compared to liquid crystal display devices, and are considered to be the next generation of display technology. The self-luminous element, namely the OLED device, is mainly composed of an anode layer, an organic material functional layer (usually including an electron transport layer, a light-emitting layer, and a hole transport layer) and a cathode layer, which are arranged away from the substrate in sequence. In the related art, in order to improve the performance, brightness and life of the display panel, an OLED (Organic Light-Emitting Diode) device with more than two light-emitting layers stacked is introduced, namely tandem OLED, which uses a charge generation layer (CGL) to connect the upper and lower light-emitting layers in series to achieve the effect of light superposition on the device, and successfully improve important optoelectronic performance parameters such as current efficiency, output brightness, and operating life. However, due to the high conductivity of CGL, it is easy to cause lateral crosstalk between pixels. In the related art, a partition structure is used to partition the CGL, but the partition structure is prone to cause problems such as uneven electric field distribution within the pixel and increased edge stray light. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display substrate, which is divided into a plurality of pixel areas and a spacer area filled between the pixel areas; the display substrate comprises:

[0004] substrate substrate;

[0005] A first electrode layer, disposed on the base substrate, wherein the first electrode layer includes a first electrode of each light-emitting unit;

[0006] A pixel defining layer, disposed on a side of the first electrode layer away from the base substrate, the pixel defining layer comprising a pixel opening located in the pixel area and a pixel retaining wall located in the spacer area;

[0007] A plurality of light-emitting layers are covered on a side of the pixel defining layer away from the first electrode layer, and the plurality of light-emitting layers are stacked in sequence;

[0008] A connecting layer, wherein the connecting layer is arranged between the adjacent light-emitting layers and covers the light-emitting layers;

[0009] A second electrode layer is arranged on a side of the multi-layer light-emitting layer that is farthest from the base substrate and away from the base substrate; the second electrode layer includes a second electrode of each of the light-emitting units;

[0010] Among them, the display substrate also includes a blocking member located between the pixel blocking wall and the one of the multilayer light-emitting layers closest to the base substrate; the blocking member has a first groove portion that at least partially penetrates along its thickness direction; the conductivity of the portion of the connecting layer located in the first groove portion is lower than the conductivity of the portion located in the pixel area.

[0011] In some embodiments, for the first groove portion, a longitudinal section thereof along the thickness direction of the display substrate includes a first side edge and a second side edge that are oppositely disposed, and a connecting bottom edge connecting the first side edge and the second side edge;

[0012] The included angle between the first side edge and the connecting bottom edge is 100° to 120°, and / or the included angle between the second side edge and the connecting bottom edge is 100° to 120°.

[0013] In some embodiments, a ratio of the depth of the first groove portion to the thickness of the blocking member is 0.8-1.

[0014] In some embodiments, the orthographic projection of the pixel blocking wall on the base substrate covers the orthographic projection of the blocking member on the base substrate, and the distance between the edges of the two is a first distance, and the first distance is greater than zero.

[0015] In some embodiments, an orthographic projection of the first electrode on the base substrate at least partially overlaps with an orthographic projection of the blocking member on the base substrate.

[0016] In some embodiments, the thickness of the blocking member is greater than two-thirds of the total thickness of each of the light-emitting layers and each of the connecting layers, and greater than one-half of the distance between the first electrode layer and one of the multiple connecting layers farthest from the base substrate.

[0017] In some embodiments, the width of the first groove at a position of half its depth is less than two-thirds of the distance between two adjacent first electrodes.

[0018] In some embodiments, the display substrate further comprises an isolation layer disposed between one of the multiple light-emitting layers closest to the base substrate and the blocking member; the isolation layer covers the blocking member and at least a portion of the pixel blocking wall.

[0019] In some embodiments, the pixel blocking wall has a first through hole penetrating along the thickness direction thereof, and the orthographic projection of the first groove portion on the base substrate covers the orthographic projection of the first through hole on the base substrate;

[0020] The first through hole is filled with a heat-conducting structure.

[0021] In some embodiments, the display substrate further includes an encapsulation layer disposed on a side of the second electrode layer away from the base substrate.

[0022] The present disclosure also provides a method for preparing the above-mentioned display substrate, comprising:

[0023] A base substrate is provided; the base substrate is divided into a plurality of pixel areas and spacer areas filled between the pixel areas;

[0024] Forming a metal layer on the base substrate and patterning it to form a first electrode layer including a plurality of first electrodes; the first electrodes cover the pixel area and at least a portion of the spacer area;

[0025] A pixel defining layer is formed on a side of the first electrode layer away from the base substrate and patterned to form a pixel opening located in the pixel area and a pixel blocking wall located in the spacing area; the pixel opening exposes at least a portion of the first electrode, and the pixel blocking wall covers at least a portion of the first electrode;

[0026] A blocking member is formed on a side of the pixel blocking wall away from the base substrate and patterned to form a first groove portion; the first groove portion penetrates at least a portion of the blocking member along a thickness direction thereof; and an orthographic projection of the pixel blocking wall on the base substrate covers an orthographic projection of the blocking member on the base substrate;

[0027] A plurality of light-emitting layers and a connection layer disposed between adjacent light-emitting layers are formed on a side of the blocking member away from the base substrate; the light-emitting layer covers the pixel defining layer, and the connection layer covers the light-emitting layer;

[0028] A second electrode layer is formed on a side of one of the multiple light-emitting layers that is farthest from the base substrate and faces away from the base substrate; the second electrode layer includes a plurality of second electrodes.

[0029] In some embodiments, the preparation method further includes forming an isolation layer; the isolation layer is located between the one of the multiple light-emitting layers closest to the base substrate and the blocking member, and the isolation layer covers the blocking member and at least a portion of the pixel blocking wall.

[0030] In some embodiments, the preparation method further includes forming an encapsulation layer on a side of the second electrode layer facing away from the base substrate.

[0031] In some embodiments, the preparation method further includes forming a first mask on a side of the encapsulation layer away from the base substrate, and patterning the first mask to remove at least a portion of the first mask within a range defined by an orthographic projection of the first groove on the base substrate;

[0032] Laser irradiation or ion implantation is performed on the light emitting surface side of the display substrate so that the conductivity of the connection layer portion located in the first groove portion is smaller than the conductivity of the connection layer portion located in the pixel area.

[0033] In some embodiments, when the display substrate is irradiated with laser, the materials constituting the first mask and the blocking member include photoresist, and the material constituting the isolation layer includes a heat insulating material.

[0034] In some embodiments, when ion implantation is performed on the display substrate, the material constituting the first mask and the blocking member includes a black matrix paste, and the material constituting the isolation layer includes a material that blocks ion diffusion.

[0035] In some embodiments, when the first mask is patterned, a length of the first mask removed in a width direction of the first groove is smaller than a width of the first groove at a position of half its depth.

[0036] In some embodiments, the preparation method also includes forming a first through hole and forming a heat conductive structure in the first through hole; the first through hole penetrates the pixel blocking wall along the thickness direction of the pixel blocking wall, and the orthographic projection of the first groove on the base substrate covers the orthographic projection of the first through hole on the base substrate.

[0037] In some embodiments, the length of the first through hole in the width direction of the first groove is a, a∈(b-0.15um, b+0.15um); b is the length of the removed first mask in the width direction of the first groove.

[0038] The present disclosure also provides a display panel, comprising the display substrate of the above embodiment. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1a A schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0040] Figure 1b for Figure 1a An enlarged view of the first groove portion of the substrate is shown in FIG.

[0041] Figure 1c A schematic structural diagram of another display substrate provided in an embodiment of the present disclosure;

[0042] Figure 1d for Figure 1c An enlarged view of the first groove portion of the substrate is shown in FIG.

[0043] Figure 2 A schematic structural diagram of another display substrate provided in an embodiment of the present disclosure;

[0044] Figure 3a A structural schematic diagram corresponding to step S1 in a process for preparing a display substrate provided in an embodiment of the present disclosure;

[0045] Figure 3b A schematic structural diagram corresponding to step S2 in a process for preparing a display substrate provided in an embodiment of the present disclosure;

[0046] Figure 3c A schematic structural diagram corresponding to step S3 in a process for preparing a display substrate provided in an embodiment of the present disclosure;

[0047] Figure 3d A schematic structural diagram corresponding to step S4 in a process for preparing a display substrate provided in an embodiment of the present disclosure;

[0048] Figure 3e A structural schematic diagram corresponding to step S5 in a process for preparing a display substrate provided in an embodiment of the present disclosure;

[0049] Figure 3f A schematic structural diagram corresponding to step S6 in a process for preparing a display substrate provided in an embodiment of the present disclosure;

[0050] Figure 3g A structural schematic diagram corresponding to step S7 in a process for preparing a display substrate provided in an embodiment of the present disclosure;

[0051] Figure 3h A schematic structural diagram corresponding to step S8 in a process for preparing a display substrate provided in an embodiment of the present disclosure;

[0052] Figure 3i A structural schematic diagram corresponding to step S9 in a process for preparing a display substrate provided in an embodiment of the present disclosure;

[0053] Figure 4 A schematic diagram of a circuit structure of a pixel driving circuit provided in an embodiment of the present disclosure;

[0054] Figure 5 for Figure 4 The working timing diagram corresponding to the pixel driving circuit in . DETAILED DESCRIPTION

[0055] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0056] Unless otherwise defined, the technical terms or scientific terms involved in this application should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the" and the like involved in this application do not indicate a quantitative limitation, and may represent the singular or plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects. "Up", "down", "left", "right", etc. are only used to indicate relative position relationships. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

[0057] In the related art, the CGL charge generation layer is a commonly used charge generation technology, which is usually composed of two parts, namely a photosensitive material layer and a carrier transport layer. The photosensitive material layer is responsible for photoelectric conversion, converting light energy into electrical energy; the carrier transport layer is responsible for transferring the generated charge from the photosensitive material layer to the light-emitting layer connected thereto, and the two cooperate with each other to jointly realize the generation and transmission of charges. The currently commonly used CGL layer is usually formed by doping metal lithium (Li) or metal ytterbium (Yb) in an electron transport material (ETL), but due to the strong metallic activity and diffusion ability of Li, the conductivity of the CGL layer is relatively high, which is easy to cause lateral crosstalk between pixels. In the prior art, the CGL layer is isolated by adding an undercut partition structure, but the partition structure is prone to cause problems such as uneven electric field distribution within the pixel and increased edge stray light.

[0058] Based on this, the present disclosure provides a display substrate, which includes a plurality of light-emitting units arranged in an array, and the display panel can be divided into a plurality of pixel areas AA and a spacing area PA filled between the pixel areas AA. For example, the plurality of pixel areas AA are arranged in an array, and the spacing area PA is a grid structure filled between the pixel area AA arrays. Specifically, refer to Figures 1a to 1d , the display substrate includes: a base substrate 1, and a first electrode layer 2, a pixel defining layer 3, a multi-layer light-emitting layer 4, a connection layer 5 arranged in two adjacent light-emitting layers, and a second electrode layer 6, which are sequentially arranged on the base substrate 1. For the sake of convenience, in the embodiment of the present disclosure, only two light-emitting layers 4 are taken as an example, and the two light-emitting layers are respectively referred to as a first light-emitting layer 41 and a second light-emitting layer 42. The first light-emitting layer 41 is closer to the base substrate 1 than the second light-emitting layer 42. Correspondingly, a connection layer 5 is arranged between the two light-emitting layers 41 / 42. Specifically, the first electrode layer 2 includes a first electrode 21 of a plurality of light-emitting units. The pixel defining layer 3 includes a pixel opening 32 located in the pixel area AA, and a pixel retaining wall 31 located in the spacing area PA. One pixel opening 32 corresponds to one first electrode 21, and at least part of the first electrode 21 is exposed. The first light-emitting layer 41 covers the pixel defining layer 3, the connection layer 5 covers the first light-emitting layer 41, and the second light-emitting layer 42 covers the connection layer 5. The second electrode layer 6 includes the second electrode of each light-emitting unit.

[0059] It should be noted that the junction position of the pixel retaining wall 31 and the pixel opening 32 is the junction of the pixel area AA and the spacing area PA, and the portion of the light-emitting layer located at the pixel opening 32 (i.e., the portion of the light-emitting layer located at the pixel area AA) is used as the light-emitting portion of the light-emitting unit. Taking the display substrate including the first light-emitting layer 41 and the second light-emitting layer 42 as an example, each light-emitting unit includes a first light-emitting portion and a second light-emitting portion, the first light-emitting portion is the portion of the first light-emitting layer 41 in the pixel opening 32 corresponding to the light-emitting unit, and the second light-emitting portion is the portion of the second light-emitting layer 42 in the pixel opening 32 corresponding to the light-emitting unit.

[0060] In particular, the display substrate of the embodiment of the present disclosure further includes a blocking member 8 located between the pixel blocking wall 31 and one of the multi-layer light-emitting layers 4 closest to the base substrate 1, and the blocking member 8 has a first groove portion 82 that at least partially penetrates along its thickness direction. The blocking member 8 is used to block light, heat and ions, so as to avoid affecting the light-emitting unit when the display substrate is subsequently subjected to laser irradiation or ion implantation. It should be noted that the laser irradiation or ion implantation treatment of the connection layer 5 can affect the photosensitive material layer or the carrier transport layer in the connection layer 5, thereby reducing the conductivity of the connection layer 5, so that the conductivity of the treated connection layer 5 is less than the conductivity of the untreated connection layer 5. Here, preferably, the connection layer 5 located in the first groove portion 82 can be treated so that the conductivity of the connection layer 5 located in the first groove portion 82 is less than the conductivity of the connection layer 5 located in the pixel area AA, thereby avoiding lateral crosstalk between pixels.

[0061] In some examples, reference Figure 1b , the thickness h1 of the blocking member 8 is greater than two-thirds of the total thickness h2 of each light-emitting layer 4 and each connecting layer 5, and is greater than one-half of the distance d1 between the first electrode layer 2 and the one of the multiple connecting layers 5 that is farthest from the base substrate 1. Take the display substrate including two stacked light-emitting layers 4 and one connecting layer 5 as an example, the two light-emitting layers 4 are the first light-emitting layer 41 and the second light-emitting layer 42, and the former is closer to the base substrate 1 than the latter. In this embodiment, h2 is the total thickness of the first light-emitting layer 41, the second light-emitting layer 42 and the connecting layer 5, and d1 is the distance between the first electrode layer 2 and the connecting layer 5. Setting h1>2 / 3*h2 can ensure that the blocking member 8 can block most of the ions and heat to prevent them from diffusing and affecting the light-emitting unit, and setting h1>1 / 2*d1 can ensure that the connecting layer 5 located above the blocking member 8 has enough length to consume the diffused ions, prevent the diffused ions from affecting the connecting layer 5 located in the pixel area AA, and reduce its conductivity. In some examples, the material of the blocking member 8 may be an inorganic film with a thermal conductivity of less than 8 W / m*K or other insulating and heat-isolating materials, such as photoresist.

[0062] Continue to refer to Figure 1b, the first groove portion 82 located in the blocking member 8, its longitudinal section along the thickness direction of the display substrate includes a first side P1 and a second side P2 arranged opposite to each other, and a connecting bottom P3 connecting the first side P1 and the second side P2. In some examples, the angle α1 between the first side P1 and the connecting bottom P3 is 100° to 120°, and / or, the angle α2 between the second side P2 and the connecting bottom P3 is 100° to 120°. It can be understood that the shape of the longitudinal section of the first groove portion 82 is a trapezoid, the length of the upper base is greater than the length of the lower base, the first side P1 and the second side P2 are the two waists of the trapezoid, the connecting bottom P3 is the lower base of the trapezoid, the angle between the first side P1 and the connecting bottom P3, and the angle between the second side P2 and the connecting bottom P3 are the two bottom angles of the trapezoid. Preferably, it can be set to an isosceles trapezoid, that is, the length of the first side P1 is equal to the length of the second side P2. More preferably, the bottom angle can be set to 120°, which can reduce the area of ​​the spacing area PA and form a gentler slope to prevent other film layers in the first groove portion 82, such as the connecting layer 5 and the light-emitting layer 4, from breaking when climbing the slope.

[0063] In some examples, the ratio of the depth of the first groove 82 to the thickness of the blocking member 8 is 0.8 to 1. In one example, the first groove 82 may penetrate the blocking member 8 along its thickness direction. Figure 1a-1b As shown, at this time, the ratio of the depth of the first groove 82 to the thickness of the blocking member 8 is 1, and the blocking member 8 is divided into two sub-blocking members 81 arranged opposite to each other on the left and right. This arrangement can simplify the preparation process. For example, when etching the first groove 82 on the blocking member 8, it is not necessary to accurately etch the depth, and the processing speed is fast. In another example, the first groove 82 can also partially penetrate the blocking member 8 along its thickness direction, such as Figure 1c-1d As shown, at this time, the blocking member 8 includes not only two sub-blocking members 81 arranged opposite to each other, but also a sub-blocking portion 83 connecting the two. The longitudinal section of the sub-blocking portion 83 is also a trapezoid. At this time, the upper bottom of the sub-blocking portion is the connecting bottom edge of the first groove portion 82. The ratio of the thickness h3 of the sub-blocking portion to the thickness h1 of the blocking member 8 is less than 0.2 to ensure a good blocking effect. The setting of the sub-blocking portion 83 can increase the distance between the connecting layer 5 and the base substrate 1. Under the premise that the diffusion range of ions and heat is the same, the contact surface of the processed connecting layer 5 is reduced, thereby preventing ions and heat from affecting the connecting layer 5 located in the pixel area AA. In addition, through the connection of the sub-blocking portion 83, the supporting effect of the blocking member 8 can be improved, thereby improving the pressure resistance of the display substrate, and further improving the reliability and service life of the display device.

[0064] In some examples, continue to refer to Figure 1bThe width w1 of the first groove 82 at the half depth position is less than two-thirds of the distance d2 between two adjacent first electrodes 21, that is, w1<2 / 3*d2. In this way, the orthographic projections of the first groove 82 and the first electrode 21 on the substrate 1 can be controlled to have no overlap, thereby avoiding the injected ions or laser from affecting the carriers in the first electrode layer 2 and reducing its conductivity.

[0065] In some examples, the orthographic projection of the pixel retaining wall 31 on the substrate 1 covers the orthographic projection of the blocking member 8 on the substrate 1, and the distance between the edges of the two is a first distance d3, and the first distance d3 is greater than zero. Preferably, the centers of the pixel retaining wall 31 and the blocking member 8 coincide, so as to form a symmetrical pattern and improve the neatness and aesthetics of the circuit layout. The junction of the pixel retaining wall 31 and the pixel opening 32 in the pixel defining layer 3 is the junction of the pixel area AA and the spacing area PA. The blocking member 8 is arranged in the spacing area PA, and a certain distance (i.e., the first distance d3) is set between the edge of the blocking member 8 and the edge of the spacing area PA in order to leave a certain buffer space to avoid the reduction of the area of ​​the pixel area AA and the decrease of the aperture ratio due to the displacement of the blocking member 8. In some examples, the orthographic projection of the first electrode 21 on the substrate 1 overlaps at least partially with the orthographic projection of the blocking member 8 on the substrate 1. Here, it can be understood that the orthographic projection of the first electrode 21 on the substrate 1 and the orthographic projection of the pixel retaining wall 31 on the substrate 1 must have an overlapping part. However, it should be noted that, although the first electrode 21 overlaps with the orthographic projection of the blocking member 8, the orthographic projection of the first electrode 21 does not overlap with the first groove portion 82. The first electrode 21 is used to provide carriers for the display substrate, so if conditions permit, the larger the first electrode 21 is, the more carriers it has and the better the conductivity. Therefore, in this embodiment, the first electrode 21 not only covers the pixel area AA, but also covers at least part of the spacing area PA, that is, the overlapping part with the pixel blocking wall 31.

[0066] In some embodiments, the display substrate further includes an isolation layer 9 disposed between the first light emitting layer 41 and the blocking member 8, Figure 2 , the isolation layer 9 covers the blocking member 8 and part of the pixel retaining wall 31. In one example, the isolation layer 9 is used to isolate the heat generated by laser irradiation to prevent the heat from diffusing into the first light-emitting layer 41 and affecting the display effect. In this example, the material constituting the isolation layer 9 may include a heat-insulating material, such as glass fiber, asbestos, rock wool, silicate, aerogel felt, vacuum board, etc. In another example, the isolation layer 9 is used to isolate the ions diffused during ion implantation to prevent the ions from diffusing into the first light-emitting layer 41 and causing corrosion, thereby affecting the life of the device. In this example, the material constituting the isolation layer 9 may include a material that blocks ion diffusion, such as polyethylene, fluoroplastics, ceramics, etc.

[0067] In some examples, the display substrate further includes a first through hole 102 provided with a heat conducting structure 101, Figure 2 , the first through hole 102 penetrates the pixel blocking wall 31 along the thickness direction of the pixel blocking wall 31, and the orthographic projection of the first through hole 102 on the substrate substrate 1 is covered by the orthographic projection of the first groove 82 on the substrate substrate 1, and further, the orthographic projection of the first through hole 102 on the substrate substrate 1 is covered by the orthographic projection of the bottom surface of the first groove 82 on the substrate substrate. The heat-conducting structure 101 fills the first through hole 102, and the heat-conducting structure 101 is used to quickly conduct the heat generated during laser irradiation to the substrate substrate 1, and then the substrate substrate 1 diffuses the heat to the external environment. The material of the heat-conducting structure 101 may include silicon carbide, diamond, graphite, ceramics, plastics, etc.

[0068] In some examples, reference Figure 1a to Figure 2 , the display substrate further includes an encapsulation layer 7 disposed on the side of the second electrode layer 6 away from the base substrate 1. The material of the encapsulation layer 7 may include insulating materials such as silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), and polymer resins. Inorganic materials such as silicon oxynitride (SiON), silicon oxide (SiOx), and silicon nitride (SiNx) have high density and can prevent the intrusion of water, oxygen, etc.; the material of the organic encapsulation layer 7 may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to planarize the surface of the display substrate, and may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that invade the interior.

[0069] The present disclosure also provides a method for preparing a display substrate, referring to Figures 3a to 3i , the preparation method comprises the following steps:

[0070] S1. Provide a substrate 1, which is divided into a plurality of pixel areas AA and a spacer area PA filled between the pixel areas AA, such as Figure 3a shown.

[0071] In some examples, step S1 may specifically include: cleaning the substrate substrate 1 by a standard cleaning process. The cleaning method of the substrate substrate 1 may include: alkaline cleaning, soaking the substrate substrate 1 in a solution containing sodium hydroxide or ammonium hydroxide, the commonly used solution concentration is 5% to 10%, which can clean the organic matter and metal ions on the surface of the substrate substrate 1; acid cleaning, soaking the substrate substrate 1 in a solution containing hydrofluoric acid or hydrochloric acid, the commonly used solution concentration is 10% to 30%, which can clean the oxide and silica gel impurities on the surface of the substrate substrate 1; oxidation cleaning, soaking the substrate substrate 1 in a solution containing potassium hydroxide or hydrogen peroxide, the commonly used solution concentration is 5% to 10%, which can clean the carbon and metal elements on the surface of the substrate substrate 1; ultrapure water cleaning, soaking or spraying the substrate substrate 1 in ultrapure water, which can clean the tiny particles on the surface of the substrate substrate 1.

[0072] S2. A first electrode layer 2 including a plurality of first electrodes 21 is formed on the base substrate 1, wherein the first electrode layer 2 covers the pixel area AA and at least a portion of the spacer area PA. Figure 3b shown.

[0073] In some examples, the material constituting the first electrode 21 includes: gold (Au), gold alloy, silver (Ag), silver alloy, aluminum (Al), aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc.

[0074] S3. A pixel defining layer 3 is formed on the side of the first electrode layer 2 away from the base substrate 1, which includes a pixel opening 32 located in the pixel area AA and a pixel barrier 31 located in the spacing area PA, such as Figure 3c shown.

[0075] In some embodiments, a pixel defining layer 3 may be prepared by a deposition process, and then patterned by an etching process to remove the portion of the pixel defining layer 3 located in the pixel area AA, so as to form a pixel opening 32 and a pixel blocking wall 31. The pixel opening 32 exposes at least a portion of the first electrode 21, and the pixel blocking wall 31 covers at least a portion of the first electrode 21.

[0076] Specifically, the pixel defining layer 3 may be deposited by sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), or electron cyclotron resonance chemical vapor deposition (ECRCVD). The pixel defining layer 3 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or inorganic insulating materials such as silicon oxide and silicon nitride. The pixel defining layer 3 may have a multilayer structure.

[0077] In some examples, the etching process may be dry etching or wet etching. In dry etching, the surface of the pixel defining layer 3 is exposed to plasma generated in a gaseous state, and the plasma reacts physically or chemically with the pixel defining layer 3 through a window opened in the photoresist, thereby removing the exposed surface material. Dry etching may specifically include: ion milling etching, plasma etching, and reactive ion etching.

[0078] Wet etching is to immerse the pixel defining layer 3 in a certain chemical reagent or reagent solution, so that the part of the film surface not masked by the resist reacts chemically with the reagent and is removed. Compared with dry etching, wet etching is simple to operate, has low equipment requirements, and is easy to achieve mass production. However, dry etching greatly improves the anisotropic properties of etching and can ensure the accuracy of the pattern.

[0079] In some embodiments, continue to refer to Figure 3c Step S3 further includes forming a first through hole 102 and forming a heat-conducting structure 101 in the first through hole 102. The first through hole 102 penetrates the pixel blocking wall 31 along the thickness direction of the pixel blocking wall 31, and the orthographic projection of the first groove portion 82 on the base substrate 1 covers the orthographic projection of the first through hole 102 on the base substrate 1. Figure 3i, the length of the first through hole 102 in the width direction of the first groove 82 is a, and the length of the removed first mask 9 in the width direction of the first groove 82 is b, a∈(b-0.15um, b+0.15um). In some examples, the first through hole 102 can be formed on the pixel retaining wall 31 by an etching process. Among them, the etching process can be dry etching or wet etching. Dry etching is to expose the surface of the pixel retaining wall 31 to the plasma generated in the gas state, and the plasma reacts physically or chemically with the blocking member 8 through the window opened in the photoresist, thereby removing the exposed surface material. Dry etching can specifically include: ion milling etching, plasma etching and reactive ion etching. Wet etching is to immerse the pixel retaining wall 31 in a certain chemical reagent or reagent solution, so that the part of the film surface that is not masked by the resist reacts chemically with the reagent and is removed. Compared with dry etching, wet etching is simple to operate, has low equipment requirements, and is easy to achieve mass production. However, dry etching greatly improves the anisotropic properties of etching and can ensure the accuracy of the pattern. After the first through hole 102 is prepared, the heat conducting structure 101 can be formed by sputtering or deposition. Exemplarily, the material constituting the heat conducting structure 101 may include silicon carbide, diamond, graphite, ceramic, plastic, etc.

[0080] S4. A blocking member 8 is formed on the side of the pixel blocking wall 31 away from the base substrate 1, and a first groove 82 is formed by patterning the blocking member 8. The first groove 82 penetrates at least a portion of the blocking member 8 along its thickness direction, and the orthographic projection of the pixel blocking wall 31 on the base substrate 1 covers the orthographic projection of the blocking member 8 on the base substrate 1, and the distance between the edges of the two is a first distance d3, and the first distance d3 is greater than zero. Figure 3d shown.

[0081] In some examples, the blocking member 8 may include an inorganic film or an insulating and heat-insulating material, such as: photoresist, black matrix glue, silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc.

[0082] In some examples, the first groove portion 82 can be formed on the blocking member 8 by an etching process. The etching process can be dry etching or wet etching. Dry etching is to expose the surface of the blocking member 8 to the plasma generated in the gas state, and the plasma reacts physically or chemically with the blocking member 8 through the window opened in the photoresist, thereby removing the exposed surface material. Dry etching can specifically include: ion milling etching, plasma etching and reactive ion etching. Wet etching is to immerse the blocking member 8 in a certain chemical reagent or reagent solution so that the part of the film surface that is not masked by the resist reacts chemically with the reagent and is removed. Compared with dry etching, wet etching is simple to operate, has low equipment requirements, and is easy to achieve mass production. However, dry etching greatly improves the anisotropic properties of etching and can ensure the accuracy of the pattern.

[0083] S5. Forming an isolation layer 9 on the side of the blocking member 8 away from the substrate 1, referring to Figure 3e , the isolation layer 9 covers the blocking member 8 and a portion of the pixel blocking wall 31 .

[0084] Specifically, the isolation layer 9 can be deposited by sputtering, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD) or electron cyclotron resonance chemical vapor deposition (ECRCVD). In one example, the isolation layer 9 is used to isolate the heat generated by laser irradiation to prevent the heat from diffusing into the first light-emitting layer 41 and affecting the display effect. In this example, the material constituting the isolation layer 9 may include heat-insulating materials, such as glass fiber, asbestos, rock wool, silicate, aerogel felt, vacuum board, etc. In another example, the isolation layer 9 is used to isolate the ions diffused during ion implantation to prevent the ions from diffusing into the first light-emitting layer 41 and causing corrosion, thereby affecting the device life. In this example, the material constituting the isolation layer 9 may include materials that block ion diffusion, such as polyethylene, fluoroplastics, ceramics, etc.

[0085] S6. A multi-layer light-emitting layer 4 and a multi-layer connecting layer 5 arranged between two adjacent light-emitting layers 4 are formed on the side of the isolation layer 9 facing away from the base substrate 1. The light-emitting layer 4 covers the pixel defining layer 3, and the connecting layer 5 covers the light-emitting layer 4. Figure 3f shown.

[0086] It should be noted that Figure 3f Only two light-emitting layers and one connecting layer are schematically drawn, namely a first light-emitting layer 41, a connecting layer 5 and a second light-emitting layer 42, wherein the first light-emitting layer 41 is arranged on the side of the blocking member 8 away from the base substrate 1 and covers the pixel defining layer 3, the connecting layer 5 is arranged on the side of the first light-emitting layer 41 away from the base substrate 1 and covers the first light-emitting layer 41, and the second light-emitting layer 42 is arranged on the side of the connecting layer 5 away from the base substrate 1 and covers the connecting layer 5.

[0087] Correspondingly, each light-emitting unit includes a first light-emitting portion arranged on the side of the connection layer 5 close to the base substrate 1 and a second light-emitting portion arranged on the side of the connection layer 5 away from the base substrate 1. The portion of the first light-emitting layer 41 located at the pixel opening 32 is used as the first light-emitting portion of each light-emitting unit, and the portion of the second light-emitting layer 42 located at the pixel opening 32 is used as the second light-emitting portion of each light-emitting unit.

[0088] In some examples, the light-emitting layer 4 may include small molecule organic materials or polymer molecule organic materials, specifically fluorescent materials or phosphorescent materials. The light-emitting layer 4 may emit red light, green light, blue light, or white light. The material of the connecting layer 5 may include superlattice, layered silicate, tungsten oxide, zinc oxide, and various semiconductor materials.

[0089] S7. A second electrode layer 6 including a plurality of second electrodes is formed on a side of the multilayer light-emitting layer 4 that is farthest from the substrate 1 and faces away from the substrate 1, such as Figure 3g shown.

[0090] In some examples, the second electrode layer 6 is a whole electrode, that is, the second electrodes of the light-emitting units arranged in an array are a whole electrode.

[0091] In some examples, the materials constituting the second electrode include: indium tin oxide (ITO), metal films, metal grids / nanowires, two-dimensional materials, conductive polymers, ultra-thin ruthenium films of ruthenium oxide (RuO2) sub-layers, silver nanowires, graphene, reduced graphene oxide (r-GO), metal oxides and other transparent electrode materials.

[0092] S8. Forming a packaging layer 7 on the side of the second electrode layer 6 away from the substrate 1, such as Figure 3h shown.

[0093] In some examples, the material of the encapsulation layer 7 may include insulating materials such as silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), and polymer resins. Inorganic materials such as silicon oxynitride (SiON), silicon oxide (SiOx), and silicon nitride (SiNx) have high density and can prevent the intrusion of water, oxygen, etc.; the material of the organic encapsulation layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to planarize the surface of the display substrate, and to relieve the stress of the inorganic encapsulation layer, and may also include a desiccant and other water-absorbing materials to absorb water, oxygen, and other substances that invade the interior.

[0094] S9. Laser irradiation or ion implantation is performed on the light-emitting surface side of the display substrate, so that the conductivity of the portion of the connection layer 5 located in the first groove portion 82 is less than the conductivity of the portion of the connection layer 5 located in the pixel area AA, such as Figure 3i shown.

[0095] It should be noted that the light-emitting surface side of the display substrate is the side of the encapsulation layer 7 away from the base substrate 1. In some examples, step S8 specifically includes: forming a first mask 11 on the side of the encapsulation layer 7 away from the base substrate 1, and patterning the first mask 11, removing at least a portion of the first mask 11 within the range defined by the orthographic projection of the first groove 82 on the base substrate 1, and performing laser irradiation or ion implantation (such as Figure 3i ). Here, when the first mask 11 is patterned, the length of the first mask 11 removed in the width direction of the first groove 82 is less than the width of the first groove 82 at half its depth, and the center of the first mask removed coincides with the center of the first groove 82, so that the uniformity of laser irradiation and ion implantation can be ensured. It should also be noted that when the display substrate is laser irradiated, the material of the blocking member 8 and the first mask 11 is preferably photoresist, and when the display substrate is ion implanted, the material of the blocking member 8 and the first mask 11 is preferably black matrix glue. In addition, the injected ions can be heptavalent ions such as fluorine ions, so that they are neutralized with the lithium ions in the connecting layer 5 to reduce the conductivity of the connecting layer 5.

[0096] It should also be noted that before forming the first electrode layer in step S2, the preparation method further includes the step of forming a driving circuit layer on the base substrate 1. The driving circuit layer includes a plurality of pixel driving circuits respectively connected to the plurality of light-emitting layers, and the orthographic projections of the pixel driving circuits on the base substrate do not overlap. Figure 4 , Figure 4An exemplary circuit diagram of a pixel driving circuit is given, in which the light-emitting device OLED is the light-emitting layer 4, which can be a red light-emitting device, a blue light-emitting device, a green light-emitting device or a white light-emitting device.

[0097] Continue to refer to Figure 4 The pixel driving circuit includes: a data writing subcircuit 100, a first light emitting control subcircuit 200, a driving subcircuit 300, a threshold compensation subcircuit 400, a first reset subcircuit 500, a second light emitting control subcircuit 600 and a second reset subcircuit 700. The data writing subcircuit 100 includes a fourth transistor T4; the first light emitting control subcircuit 200 includes a fifth transistor T5; the driving subcircuit 300 includes a third transistor T3; the threshold compensation subcircuit 400 includes a second transistor T2; the first reset subcircuit 500 includes a first transistor T1; the second light emitting control subcircuit 600 includes a sixth transistor T6; and the second reset subcircuit 700 includes a seventh transistor T7.

[0098] Specifically, the gate of the fourth transistor T4 is connected to the first scanning signal Gate n terminal, the source is connected to the data signal terminal, and the drain is connected to the first node N1. The gate of the fifth transistor T5 is connected to the light emitting control signal terminal, the source is connected to the first node N1, and the drain is connected to the first level signal terminal ELVDD. The gate of the third transistor T3 is connected to the second node N2, the source is connected to the first node N1, and the drain is connected to the third node N3. The gate of the second transistor T2 is connected to the first scanning signal Gate n terminal, the source is connected to the third node N3, and the drain is connected to the second node N2. The gate of the first transistor T1 is connected to the second scanning signal Gate n-1 terminal, the source is connected to the second node N2, and the drain is connected to the initialization signal terminal. The gate of the sixth transistor T6 is connected to the light emitting control signal terminal, the source is connected to the third node N3, and the drain is connected to the fourth node N4. The gate of the seventh transistor T7 is connected to the reset signal terminal, the source is connected to the initialization signal terminal, the drain is connected to the fourth node N4, the anode of the light emitting device oled is connected to the fourth node N4, and the cathode of the light emitting device oled is connected to the second level signal terminal ELVSS.

[0099] Among them, the first scanning signal Gate n terminal provides the first scanning signal Gate n, the second scanning signal Gate n-1 terminal provides the second scanning signal Gate n-1, the data signal VData terminal provides the data signal VData, the light emitting control signal EM terminal provides the light emitting control signal EM, the initialization signal Vinit terminal provides the initialization signal Vinit, the reset signal Reset terminal provides the reset signal Reset, the first level signal terminal ELVDD provides the first level signal VDD, and the second level signal terminal ELVSS provides the second level signal VSS. The first scanning signal Gate n is the output signal of the pixel driving circuit cascaded in the previous row.

[0100] Based on the above circuit structure, the present disclosure provides a working process of the pixel driving circuit. Figure 5 For the corresponding working timing diagram, the following is combined Figure 5 The specific working process of the pixel driving circuit is described, wherein the specific working process may include an initialization phase t1, a data writing phase t2 and a light emitting phase t3.

[0101] In the initialization stage t1, the first scanning signal Gate n and the light-emitting control signal EM are both written as high-level signals, the second scanning signal Gate n-1 and the reset signal Reset are both written as low-level signals, which are working level signals, the first transistor T1 and the seventh transistor T7 are turned on, and the initialization signal Vinit resets the voltages of the second node N2 and the fourth node N4 respectively.

[0102] In the data writing stage t2, the reset signal Reset, the second scanning signal Gate n-1 and the light-emitting control signal EM are all written as high-level signals, and the first scanning signal Gate n is written as a low-level signal, which is a working level signal. The high-level signal written by the data signal VData is transmitted to the first node N1, that is, the first electrode of the third transistor T3, and the threshold voltage of the third transistor T3 is compensated to the second node N2.

[0103] In the light emitting stage t3, the light emitting control signal EM is written as a low level signal, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first level signal VDD is transmitted to the light emitting device OLED through the fifth transistor T5, the third transistor T3 and the sixth transistor T6 to make it emit light.

[0104] It should be noted that the transistors in the pixel driving circuit of the present disclosure are all P-type transistors, so the low level signal is the working level signal, and the high level signal is the non-working level signal. Of course, the pixel driving circuit can also use other circuits such as 2T1C, 19T1C, etc., which are not limited here.

[0105] The present disclosure also provides a display panel, which includes the display substrate in the above embodiment. The display panel can be used in a display device, which can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, etc., or a combination of any electronic device and hardware, which is not limited by the embodiments of the present disclosure.

[0106] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A display substrate, divided into a plurality of pixel areas and spacer areas filled between the pixel areas; The display substrate comprises: substrate substrate; A first electrode layer, disposed on the base substrate, wherein the first electrode layer includes a first electrode of each light-emitting unit; A pixel defining layer, disposed on a side of the first electrode layer away from the base substrate, the pixel defining layer comprising a pixel opening located in the pixel area and a pixel retaining wall located in the spacer area; A plurality of light-emitting layers are covered on a side of the pixel defining layer away from the first electrode layer, and the plurality of light-emitting layers are stacked in sequence; A connecting layer, wherein the connecting layer is arranged between the adjacent light-emitting layers and covers the light-emitting layers; A second electrode layer is arranged on a side of the multi-layer light-emitting layer that is farthest from the base substrate and away from the base substrate; the second electrode layer includes a second electrode of each of the light-emitting units; Among them, the display substrate also includes a blocking member located between the pixel blocking wall and the one of the multilayer light-emitting layers closest to the base substrate; the blocking member has a first groove portion that at least partially penetrates along its thickness direction; the conductivity of the portion of the connecting layer located in the first groove portion is lower than the conductivity of the portion located in the pixel area.

2. The display substrate according to claim 1, wherein: The first groove portion, in a longitudinal section along the thickness direction of the display substrate, includes a first side edge and a second side edge that are oppositely arranged, and a connecting bottom edge connecting the first side edge and the second side edge; The included angle between the first side edge and the connecting bottom edge is 100° to 120°, and / or the included angle between the second side edge and the connecting bottom edge is 100° to 120°.

3. The display substrate according to claim 1, wherein: The ratio of the depth of the first groove portion to the thickness of the blocking member is 0.8-1.

4. The display substrate according to claim 1, wherein: The orthographic projection of the pixel blocking wall on the base substrate covers the orthographic projection of the blocking member on the base substrate, and the distance between the edges of the two is a first distance, and the first distance is greater than zero.

5. The display substrate according to claim 4, wherein: An orthographic projection of the first electrode on the base substrate at least partially overlaps with an orthographic projection of the blocking member on the base substrate.

6. The display substrate according to claim 1, wherein: The thickness of the blocking member is greater than two-thirds of the total thickness of each of the light-emitting layers and each of the connecting layers, and greater than one-half of the distance between the first electrode layer and one of the multiple connecting layers farthest from the base substrate.

7. The display substrate according to claim 1, wherein: The width of the first groove at a position of half its depth is smaller than two-thirds of the distance between two adjacent first electrodes.

8. The display substrate according to claim 1, wherein: The display substrate further comprises an isolation layer disposed between one of the multiple light-emitting layers closest to the base substrate and the blocking member; the isolation layer covers the blocking member and at least a portion of the pixel blocking wall.

9. The display substrate according to claim 1, wherein: The pixel blocking wall has a first through hole penetrating along the thickness direction thereof, and the orthographic projection of the first groove portion on the base substrate covers the orthographic projection of the first through hole on the base substrate; The first through hole is filled with a heat-conducting structure.

10. The display substrate according to claim 1, wherein: The display substrate further includes a packaging layer disposed on a side of the second electrode layer away from the base substrate.

11. A method for preparing a display substrate according to any one of claims 1 to 10, comprising: Providing a substrate; The base substrate is divided into a plurality of pixel areas and spacer areas filled between the pixel areas; Forming a metal layer on the base substrate and patterning the metal layer to form a first electrode layer including a plurality of first electrodes; The first electrode covers the pixel area and at least a portion of the spacer area; Forming a pixel defining layer on a side of the first electrode layer away from the base substrate and patterning the pixel defining layer to form a pixel opening located in the pixel area and a pixel retaining wall located in the spacing area; The pixel opening exposes at least a portion of the first electrode, and the pixel blocking wall covers at least a portion of the first electrode; A blocking member is formed on a side of the pixel blocking wall away from the base substrate and patterned to form a first groove portion; the first groove portion penetrates at least a portion of the blocking member along a thickness direction thereof; The orthographic projection of the pixel blocking wall on the base substrate covers the orthographic projection of the blocking member on the base substrate; Forming a plurality of light-emitting layers and a connecting layer disposed between adjacent light-emitting layers on a side of the blocking member away from the base substrate; The light-emitting layer covers the pixel defining layer, and the connecting layer covers the light-emitting layer; A second electrode layer is formed on a side of one of the multiple light-emitting layers that is farthest from the base substrate and faces away from the base substrate; the second electrode layer includes a plurality of second electrodes.

12. The preparation method according to claim 11, wherein The preparation method further includes forming an isolation layer; the isolation layer is located between the one of the multiple light-emitting layers closest to the base substrate and the blocking member, and the isolation layer covers the blocking member and at least a portion of the pixel blocking wall.

13. The preparation method according to claim 12, wherein: The preparation method further includes forming a packaging layer on a side of the second electrode layer away from the base substrate.

14. The preparation method according to claim 13, wherein: The preparation method further includes forming a first mask on a side of the encapsulation layer away from the base substrate, and patterning the first mask to remove at least a portion of the first mask within a range defined by an orthographic projection of the first groove on the base substrate; Laser irradiation or ion implantation is performed on the light emitting surface side of the display substrate so that the conductivity of the connection layer portion located in the first groove portion is smaller than the conductivity of the connection layer portion located in the pixel area.

15. The preparation method according to claim 14, wherein: When the display substrate is irradiated with laser, the materials constituting the first mask and the blocking member include photoresist, and the material constituting the isolation layer includes a heat insulating material.

16. The preparation method according to claim 14, wherein: When ion implantation is performed on the display substrate, the material constituting the first mask and the blocking member includes a black matrix paste, and the material constituting the isolation layer includes a material that blocks ion diffusion.

17. The preparation method according to claim 14, wherein: When the first mask is patterned, the length of the first mask removed in the width direction of the first groove is smaller than the width of the first groove at a position of half the depth thereof.

18. The preparation method according to claim 14, wherein: The preparation method also includes forming a first through hole and forming a heat-conducting structure in the first through hole; the first through hole penetrates the pixel blocking wall along the thickness direction of the pixel blocking wall, and the orthographic projection of the first groove on the base substrate covers the orthographic projection of the first through hole on the base substrate.

19. The preparation method according to claim 18, wherein: The length of the first through hole in the width direction of the first groove is a, a∈(b-0.15um, b+0.15um); b is the length of the removed first mask in the width direction of the first groove.

20. A display panel comprising the display substrate according to any one of claims 1 to 10.

Images