Data processing array interface with interface patch with multiple direct memory access circuitry

Abstract

An integrated circuit (IC) may include a data processing array including a plurality of compute tiles arranged in a grid. The IC may include an array interface coupled to the data processing array. The array interface comprises a plurality of interface sheets. Each interface sheet includes a plurality of direct memory access circuits. The IC may include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via a separate communication channel.

Description

Technical Field

[0001] The present invention relates to integrated circuits, and in particular, to an array interface for a data processing array, wherein the array interface includes an interface chip having a plurality of direct memory access circuits. Background Art

[0002] Integrated circuits (ICs) have evolved over time to provide increasingly complex computing architectures. While some ICs utilize computing architectures that include a single processor, other ICs include multiple processors. Other ICs also include multiple processors arranged in an array. Such ICs are capable of providing significant computing power and a high degree of parallelism that far exceeds the capabilities of a single processor architecture or even a multi-core processor architecture. Summary of the invention

[0003] In one or more exemplary implementations, an integrated circuit (IC) may include a data processing array including a plurality of computing slices arranged in a grid. The IC may include an array interface coupled to the data processing array. The array interface includes a plurality of interface slices. Each interface slice includes a plurality of direct memory access circuits. The IC may include a network on chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an independent communication channel.

[0004] In one or more exemplary implementations, an array interface for an IC may include a plurality of interface slices. Each interface slice may include a stream switch connected to another stream switch of an adjacent computing slice of a data processing array or an adjacent memory slice of the data processing array. The stream switch is also connected to a stream switch of at least one adjacent interface slice of the array interface. Each interface slice may include a stream multiplexer-demultiplexer connected to the stream switch of the same interface slice. Each interface slice may include a plurality of direct memory access circuits. Each direct memory access circuit is connected to the stream multiplexer-demultiplexer of the same interface slice and is connected to a NoC. The direct memory access circuit is configured to convert a data stream received from the stream multiplexer-demultiplexer into a memory mapping transaction transmitted to the NoC. The direct memory access circuit is also configured to convert a memory mapping transaction received from the NoC into a data stream transmitted to the stream multiplexer-demultiplexer.

[0005] This summary is provided only to introduce certain concepts and is not intended to identify any key or essential features of the claimed subject matter. Other features of the arrangements of the present invention will be apparent from the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The arrangement of the present invention is shown by way of example in the accompanying drawings. However, the accompanying drawings should not be interpreted as limiting the arrangement of the present invention to only the specific implementation shown. Various aspects and advantages will become apparent when viewing the following detailed description and when referring to the accompanying drawings.

[0007] Figure 1 An example of an electronic system is shown.

[0008] Figure 2 Another exemplary implementation of an electronic system is shown.

[0009] Figure 3 An exemplary implementation of a data processing (DP) array and array interface for an electronic system is shown.

[0010] Figure 4 An exemplary implementation of a compute slice of a DP array is shown.

[0011] Figure 5 An exemplary implementation of a memory slice of a DP array is shown.

[0012] Figure 6 An exemplary implementation of an interface tile for an array interface of a DP array is shown.

[0013] Figure 7 Another exemplary implementation of an interface tile for an array interface of a DP array is shown.

[0014] Figure 8 An example of connectivity between interface tiles for an array interface of a DP array is shown.

[0015] Fig. 9 Shown for use with Figure 1 An exemplary implementation of a network on a chip (NoC) for use with an electronic system.

[0016] Fig.10 is a block diagram depicting connections between endpoint circuits of an electronic system as implemented by a NoC. DETAILED DESCRIPTION

[0017] The present invention relates to integrated circuits (ICs), and in particular, to an array interface for a data processing (DP) array, wherein the array interface includes an interface slice having a plurality of direct memory access (DMA) circuits. The DP array may include a plurality of slices. The slices include computing slices or a mix of computing slices and memory slices. The DP array can be configured to perform desired computing activities by loading configuration data into the DP array. Once configured, the DP array can perform computing activities. The configuration data (sometimes referred to as an "application") loaded into the DP array can specify various operating parameters of the DP array, including but not limited to specific kernels to be executed by the computing slices, connectivity between the various slices of the DP array, etc.

[0018] When performing computing activities, the DP array relies on the array interface to obtain input data from other circuits and / or systems and to provide generated output data to such other circuits and / or systems. The other circuits and / or systems may be disposed in the same IC as the DP array or in a system external to the IC in which the DP array is disposed. According to the inventive arrangement described within the present disclosure, the array interface is configured to include additional DMA circuits that increase the data throughput entering and leaving the DP array. The additional DMA circuits facilitate the transfer of larger amounts of data into or out of the DP array per unit time. This enhanced capability of the array interface reduces the latency of data transfers entering and leaving the DP array, thereby increasing the overall throughput of applications executed in the DP array.

[0019] Further aspects of the arrangement of the invention are described below with reference to the accompanying drawings.

[0020] Figure 1 An exemplary system 100 is shown. In one or more exemplary implementations, the system 100 is an electronic system implemented entirely within a single IC. The system 100 can be implemented within a single IC package. In one aspect, the system 100 is implemented using a single die disposed in a single IC package. In another aspect, the system 100 is implemented using two or more interconnected dies disposed within a single IC package.

[0021] System 100 includes a DP array 102, an array interface 104, a network on chip (NoC) 106, and a plurality of subsystems 108, 110, 112, 114, and 116. In this example, DPE array 102 is coupled to NoC 106 via array interface 104. Subsystems 108-116 are coupled to NoC 106. DP array 102 may communicate with one or more or all of subsystems 108-116 via array interface 104 and NoC 106.

[0022] It should be understood that Figure 1The number of subsystems shown in the example is for illustrative purposes. System 100 may include more or fewer subsystems than shown. Different subsystems may represent any of a variety of different types of electronic subsystems and / or circuits. For illustrative purposes, examples of subsystems 108-116 may include, but are not limited to, any combination of processor systems, programmable logic, hardwired circuit blocks (e.g., dedicated circuit blocks), etc.

[0023] Figure 2 Another exemplary implementation of the system 100 is shown. Figure 2 104, and the NoC 106 are implemented in the same IC. In this example, an array controller 202 is shown, which may also be located in the same IC as the DP array 102. The memory 204 and the processor 206 may or may not be provided in the same IC as the DP array 102. In some examples, an IC implementation of the system 100 includes the memory 204 and / or the processor 206. In other examples, an IC implementation of the system 100 does not include the memory 204 and / or the processor 206, where the memory 204 and / or the processor 206 are implemented in a device that is external to and coupled to the IC that includes the DP array 102.

[0024] DP array 102 is formed by a plurality of circuit blocks referred to as slices. As defined in the present invention, the term "array slice" means a circuit block included in the DP array. The array slice of DP array 102 may include only a computing slice or a mixture of computing slices and memory slices. The computing slices and memory slices are hardwired and programmable. Array interface 104 includes a plurality of interface slices. As defined in the present invention, the term "interface slice" means a circuit block included in the array interface. The interface slice of array interface 104 can communicatively link the array slice of DP array 102 to communicate with circuits outside DP array 102, whether such circuits are arranged in the same die, in different dies in the same IC package, or outside the IC package. The interface slice is also hardwired and programmable. As defined in the present invention, the term "slice" means an array slice and / or an interface slice. Thus, a slice may refer to a computing slice, a memory slice, or an interface slice.

[0025] An array controller 202 is optionally included in the system 100. The array controller 202 may be communicatively linked to the DP array 102 and to the array interface 104. In one aspect, the array controller 202 is dedicated to controlling the operation of the DP array 102 and the array interface 104. The array controller 202 may be implemented as a state machine (e.g., a hardened controller) or as a processor. Whether implemented as a state machine or a processor, the array controller 202 may be implemented as a hardwired circuit block or implemented using programmable logic.

[0026] NoC 106 is a programmable interconnect network for sharing data between endpoint circuits in an IC. The endpoint circuits may be provided in DP array 102 or in other subsystems 108-116. Figure 2 In the example of FIG. 1 , one or both of the memory 204 and / or the processor 206 is such as Figure 1 The NoC 106 is an example of a subsystem of the subsystems 108-116 of the IC. The NoC 106 may include a high-speed data path with a dedicated switch. The NoC 106 also supports network connections. In an example, the NoC 106 includes one or more horizontal paths, one or more vertical paths, or both horizontal paths and vertical paths. The NoC 106 is an example of a common infrastructure that can be used within an IC to connect selected components and / or subsystems.

[0027] Generally speaking, the programmability of NoC 106 means that the network to be routed through NoC 106 is unknown before a design (e.g., an application) is created for implementation within system 100. NoC 106 can be programmed by loading configuration data into internal configuration registers that define how elements (such as switches and interfaces) within NoC 106 are configured and operate to pass data from switch to switch and between ingress / egress (e.g., interface) circuits of NoC 106 connected to endpoint circuits. NoC 106 is manufactured as part of system 100 (e.g., is hardwired) and is programmed to establish network connectivity between different master circuits and different slave circuits of a user circuit design.

[0028] In one or more examples, the NoC 106, upon power-up, may implement selected data paths for configuring the system 100. Upon power-up, the NoC 106 may not implement any data paths or routes therein for implementing a user application, at least until the NoC 106 has been configured with configuration data specifying routes for network-connecting endpoint circuits of a user application or design.

[0029] The memory 204 may be implemented as a random access memory (RAM). In one or more exemplary implementations, the memory 204 may be implemented (e.g., embedded) in the same IC that includes the DP array 102. For example, the memory 204 may be a RAM circuit implemented on the same die as the DP array 102 or on a different die within the same IC package. For example, the memory 204 may be implemented as a high bandwidth memory (HBM). On the other hand, the memory 204 may be external to the IC that includes the DP array 102. For example, the memory 204 may be one or more RAM modules that are communicatively linked to the IC that includes the DP array 102 (e.g., located on the same circuit board as the IC).

[0030] In one aspect, processor 206 is implemented (e.g., embedded) in the same IC that includes DP array 102. Processor 206 may be implemented as a hardwired processor within the IC or implemented using programmable logic. In another aspect, processor 206 is external to the IC that includes DP array 102. In this case, processor 206 may be part of another data processing system (such as a host computer) that is communicatively linked to the IC that includes DP array 102.

[0031] exist Figure 2 In an example of a system 100, the DP array 102 and the array interface 104 may operate under the control of another circuit. That is, another circuit (such as a processor 206 and / or an array controller 202) may control the configuration and operation of the DP array 102 and / or the array interface 104 over time. In the case where the system 100 includes both a processor 206 and an array controller 202, the processor 206 may execute an application and provide instructions (e.g., tasks or jobs) to the array controller 202. The array controller 202 may execute the instructions to control the configuration and / or operation of the DP array 102. In other arrangements, the array controller 202 may be omitted so that the processor 206 controls the configuration and / or operation of the DP array 102. In this case, when implemented in the same IC as the DP array 102 and the array interface 104, the processor 206 may include one or more direct connections to the DP array 102 and / or the array interface 104.

[0032] Figure 3 An exemplary implementation of the DP array 102 and array interface 104 is shown. In this example, the DP array 102 includes a compute slice 302 and a memory slice 306. Figure 3 In the example of , computing slices 302 and memory slices 306 are arranged in a grid having a plurality of rows and columns. Interface slices 304 are arranged in rows, wherein each interface slice 304 is aligned with a column of the grid arrangement of DP array 102. Computing slices 302 include computing slices 302-1, 302-2, 302-3, 302-4, 302-5, 302-6, 302-7, 302-8, 302-9, 302-10, 302-11, 302-12, 302-13, 302-14, 302-15, 302-16, 302-17, and 302-18. Interface slices 304 include interface slices 304-1, 304-2, 304-3, 304-4, 304-5, and 304-6. Memory slices 306 include memory slices 306-1, 306-2, 306-3, 306-4, 306-5, and 306-6. In this example, each slice is coupled to neighboring slices to the left (west), right (east), above (north), and below (south) if the slices are located in such positions.

[0033] Provided for illustration purposes only Figure 3 The sequence or order of the number of slices in a given column and / or row, the number of slices included in DP array 102 and / or array interface 104, and the types of slices (e.g., memory and compute slices) in a given column and / or row is for illustrative and non-limiting purposes. Other arrangements with different numbers of slices, rows, columns, a mix of slice types, etc. may be included. For example, Figure 3 The rows of memory slices 306 may be homogeneous in terms of slice type, while the columns may not. In other arrangements, the rows may be heterogeneous in terms of slice type, while the columns may be homogeneous. In addition, additional rows of memory slices 306 may be included in the DP array 102. The rows of such memory slices 306 may be grouped together without intervening rows of compute slices 302, or distributed throughout the DP array 102 such that rows of compute slices 302 do interpose between rows or groups of rows of memory slices 306.

[0034] In another exemplary implementation of the DP array 102, the memory slice 306 may be omitted so that the bottom row of the compute slices 302 are directly coupled to the interface slice 304. For example, in the case where the memory slice 306 is omitted, the interface slice 304-1 would be directly connected to the compute slice 302-3, and so on. In such a case, the various exemplary implementations described herein may replace the memory slice 306 to read data from and write data to the memory 204. However, including the memory slice 306 may increase the data throughput of the DP array 102 because the data may be stored closer to the compute slices 302, rather than having to continuously read data from and / or write data to RAM external to the DP array 102.

[0035] exist Figure 3 In the example of , each of the interface chips 304 includes a plurality of DMA circuits 308. For purposes of illustration, each interface chip 304 includes two DMA circuits 308. Interface chip 304-1 includes DMA circuits 308-1, 308-2; interface chip 304-2 includes DMA circuits 308-3, 308-4; interface chip 304-3 includes DMA circuits 308-5, 308-6; interface chip 304-4 includes DMA circuits 308-7, 308-8; interface chip 304-6 includes DMA circuits 308-9, 308-10; and interface chip 304-6 includes DMA circuits 308-11, 308-12.

[0036] As shown, each of the DMA circuits 308 is capable of communicating with the NoC 106 via an independent communication channel. In one aspect, each DMA circuit 308 is connected to an interface circuit of the NoC 106. Each DMA circuit 308 can be connected to a different and independent interface circuit of the NoC 106. The DMA circuits 308 within the same interface slice 304 can operate simultaneously, so that each DMA circuit can transmit one or more data streams simultaneously with another DMA circuit. This allows each interface slice 304 to simultaneously use two of its DMA circuits 308 to transmit data to the NoC 106 and / or simultaneously use two of its DMA circuits 308 to transmit data streams to the DP array 102.

[0037] Figure 4 An exemplary implementation of a computing slice 302 is shown. Figure 4 The examples are provided to illustrate certain architectural features of the compute slice 302 and are not intended to be limiting of the form of the DP array 102 or the architecture of the compute slice 302 in general. For ease of illustration, some connections between components and / or slices are omitted.

[0038] In the example, each computing slice 302 includes a core 402, a RAM 404, a stream switch 406, a memory mapping switch 408 (e.g., abbreviated as an "MM" switch in the figure), an event broadcast switch 410, an event logic 412, a control register 414, and a direct memory access (DMA) circuit 434. The core 402 includes a processor 420 and a program memory 422. The control register 414 can be written by the memory mapping switch 408 to control the operation of various components included in the computing slice 302. Although not shown, each memory component of the computing slice 302 (e.g., the program memory 422, the control register 414, and the RAM 404) can be read and / or written via the memory mapping switch 408 for configuration and / or initialization purposes.

[0039] Processor 420 may be any of a variety of different processor types. In one aspect, processor 420 is implemented as a vector processor. Program memory 422 may be loaded with one or more sets of executable instructions, typically referred to as "kernels," for example, by loading configuration data. Compute slice 302 is capable of performing data processing operations and operating on large amounts of data through the execution of kernels.

[0040] Each core 402, such as a processor 420, is directly connected to a RAM 404 located in the same computing slice 302 through a memory interface 432. Within the present disclosure, when a memory interface is used by circuits in the same slice to access the RAM, the memory interface is referred to as a "local memory interface." Memory interface 432-1 is an example of a local memory interface because the processor 420 in the same slice utilizes the memory interface to access the RAM 404. In contrast, a memory interface used by circuits outside the slice to access the RAM 404 is referred to as an adjacent memory interface. Memory interfaces 432-2, 432-3, and / or 432-4 are examples of adjacent memory interfaces because such memory interfaces are used by circuits in other adjacent slices to access the RAM 404.

[0041] Thus, each processor 420 is able to access (e.g., read and / or write) RAM 404 in the same computing slice 302 and one or more other RAMs 404 in adjacent slices via standard read and write operations to the memory interface. The processor 420 is able to execute program code stored in the program memory 422. The RAM 404 is configured to store application data. For configuration and / or initialization purposes, the RAM 404 can be read and / or written via the memory mapping switch 408. The RAM 404 can be read and / or written by the processor 420 and / or by the DMA circuit 434 during runtime.

[0042] DMA circuit 434 is capable of reading and writing data to RAM 404 located in the same compute slice 302. DMA circuit 434 can receive data from a source external to the compute slice 302 via stream switch 406 and store such data in RAM 404. DMA 434 can read data from RAM 404 and output the data to stream switch 406 for transmission to one or more other destinations external to the compute slice 302.

[0043] Each core 402, such as a processor 420, can be directly connected to RAM 404 located in adjacent compute slices 302 (e.g., in the north, south, east, and / or west directions) via a memory interface. Thus, the processor 420 can directly access such other adjacent RAM 404 in the same manner as the processor 420 is able to access RAM 404 located in the same compute slice 302, without initiating read or write transactions through the stream switch 406 and / or without using the DMA circuit 434. As an illustrative example, the processor 420 of the compute slice 302-5 can read and / or write to the RAM 404 located in the compute slices 302-5, 302-2, 302-4, and 302-6 without submitting read or write transactions through the stream switch 406 and / or using the DMA circuit 434. However, it should be understood that the processor 420 can initiate read and write transactions to the RAM 404 of any other compute slice 302 and / or memory slice 306 via the stream switch 406 and the DMA circuit 434.

[0044] The processor 420 may also include direct connections to processors 420 of neighboring cores (e.g., in the north, south, east, and / or west directions), referred to as cascade connections (not shown), which allow data stored in internal registers (e.g., accumulator registers) of the processor 420 to be directly shared with other processors 420. This means that data stored in one or more internal registers of one processor 420 may be directly transferred to one or more internal registers of a different processor 420 without first having to write such data to the RAM 404 and / or transfer such data through the stream switch 406.

[0045] Event logic 412 may also be configured by control registers 604. Figure 4 In the example of FIG. 4 , event logic 412 is coupled to event broadcast switch 410 . Configuration data loaded into control registers 414 defines specific events that can be detected locally within compute slice 302 .

[0046] The event logic 412 can detect various different events originating from and / or involving the DMA circuit 434, the memory mapping switch 408, and / or the stream switch 406 according to the control register 414. Examples of events can include, but are not limited to, a DMA complete transfer, a lock being released (e.g., a lock on the RAM 404, not shown), a lock being acquired (e.g., a lock on the RAM 404), or other events related to the start or end of a data flow through the computing slice 302. The event logic 412 can be configured by the control register 414 in the computing slice 302. The event logic 412 can provide such events to the event broadcast switch 410. As shown, the event broadcast switch 410 is coupled to the event broadcast switch in each of the neighboring slices of the west, east, north, and south (if available). Thus, the event broadcast switch 410 can propagate events generated internally by the event logic 412 and / or events received from outside the computing slice 302 to other slices in the DP array 102 and / or array circuit 104.

[0047] In one or more exemplary implementations, the event broadcast switch 410 can collect broadcast events from one or more or all directions. In some cases, the event broadcast switch 410 can perform a logical "OR" of signals and forward the results in one or more or all directions. Each output from the event broadcast switch 410 can include a bit mask that can be configured by configuration data loaded into the control register 414. The bit mask individually determines which events are broadcast in each direction. For example, such a bit mask can eliminate unexpected or duplicate event propagation.

[0048] Figure 5 An exemplary implementation of memory slice 306 is shown. Figure 5 The examples are provided to illustrate certain architectural features of the memory slice 306 and are not intended to be limiting of the form of the DP array 102 or the architecture of the memory slice 306 in general. For ease of illustration, some connections between components and / or slices are omitted. Generally speaking, the memory slice 306 is characterized by the lack of a processor disposed therein.

[0049] Each memory slice 306 includes a stream switch 406, a memory mapping switch 408, a DMA circuit 502, a RAM 504, an event broadcast switch 410, event logic 412, and / or a control register 414. The control register 414 may be written by the memory mapping switch 408 to control the operation of the various components shown in the memory slice 306. Although not shown, each memory component of the memory slice 306 (e.g., the RAM 504 and the control register 414) may be read and / or written via the memory mapping switch 408 for configuration and / or initialization purposes.

[0050] Each DMA circuit 502 of a memory slice 306 is coupled to a RAM 504 within the same memory slice 306 via a local memory interface 532-1, and may be coupled to one or more RAMs 504 of other adjacent memory slices 306. Figure 5 In the example of FIG. 4 , each DMA circuit 502 is capable of accessing (e.g., reading and / or writing) a RAM 504 included in the same memory slice 306 via a local memory interface 532-1. The RAM 504 includes adjacent memory interfaces 532-2 and 532-3, through which the DMA circuits of the east and west memory slices 306 can access the RAM 504. For example, the DMA circuit 502 of the memory slice 306-2 can access the RAM 504 of the memory slice 306-1 and / or the RAM 504 of the memory slice 306-3. The DMA circuit 502 can place data read from the RAM 504 on the stream switch 406, and write data received via the stream switch to the RAM 504.

[0051] The event broadcast switch 410 and event logic 412 within the memory slice 306 may be combined with Figure 4 The depicted event wide switch 410 and event logic 412 operate substantially similarly. Similarly, where the memory mapped switch 408 is used for configuration and initialization purposes of the memory slice 306, the stream switch 406 is used to transfer data during runtime.

[0052] Figure 6 An exemplary implementation of the interface sheet 304 of the array interface 104 is shown. Figure 6 In an exemplary implementation of the present invention, the interface chip 304 includes a flow switch 406, a memory mapping switch 602, a control register 604 (eg, in Figure 6 604), event logic 606, event broadcast switch 608, control, debug and trace (CDT) circuit 610, interrupt handler 612, bridge 614, stream multiplexer-demultiplexer 616, multiple DMA circuits 618, multiple NoC stream interfaces 620 and multiple switches 622.

[0053] The memory mapping switch 602 can be connected to the memory mapping switches in the neighboring slices in the west, east, and north. For example, the memory mapping switch 602 can include one or more memory mapping interfaces, wherein the memory mapping interface has a master device and a slave device connected to the memory mapping switches in the west neighboring slice, the east neighboring slice, and the north neighboring slice. Unlike the memory mapping switch 408 of the array slice, the memory mapping switch 602 of the interface slice 304 can communicate with the memory mapping switches in the neighboring west interface slice and the east interface slice 304.

[0054] Thus, the memory-mapped switch 602 can move data (e.g., configuration, control, and / or debug data) from one interface slice 304 to another interface slice to reach a specific or correct interface slice 304 and direct the data north to one or more specific target array slices. For example, if a memory-mapped transaction is received from another circuit within a specific interface slice 304, the memory-mapped switch 602 can distribute the transaction horizontally to other interface slices 304, such as within the array interface 104.

[0055] In this example, the control register 604 is connected to the memory mapped switch 602 and can be read and / or written via the memory mapped switch 602. Through the memory mapped switch 602, configuration data can be loaded into the control register 604 to control various functions and operations performed by various components within the interface slice 304. For purposes of illustration, the control register 604 is not shown as being coupled to various circuit blocks of the interface slice 304. However, it should be appreciated that the control register 604 can be connected to various circuit blocks of the interface slice 304 via control signals to control the operating characteristics of such circuit blocks (e.g., event logic 606, event broadcast switch 608, CDT 610, interrupt handler 612, stream switch 406, bridge 614, stream multiplexer-demultiplexer 616, DMA circuit 618, NoC stream interface 620, and / or switch 622).

[0056] The memory mapped switch 602 is coupled to the NoC 106 via a bridge 614. The bridge 614 can convert memory mapped data transmissions corresponding to configuration data, control data, and / or debug data from the NoC 106 into memory mapped data receivable by the memory mapped switch 602.

[0057] Event logic 606 may be configured by control register 604. Figure 6In the example of FIG. 6 , the event logic 606 is coupled to the event broadcast switch 608 and to the CDT circuit 610. Configuration data loaded into the control register 604 defines specific events that can be detected locally within the interface slice 304. The event logic 606 is capable of detecting various different events originating from and / or involving the DMA circuit 618, the memory mapping switch 602, the stream switch 406, and / or the NoC stream interface 620 based on the control register 604. Examples of events may include, but are not limited to, a DMA complete transfer, a lock being released, a lock being acquired, or other events related to the beginning or end of a data flow through the interface slice 304. The event logic 606 may provide such events to the event broadcast switch 608 and / or to the CDT circuit 610. In another exemplary implementation, the event logic 606 may not have a direct connection to the CDT circuit 610, but is connected to the CDT circuit 610 via the event broadcast switch 608.

[0058] The event broadcast switch 608 and event logic 606 may operate similarly to the event broadcast switch and logic described in conjunction with the compute slice 302 and memory slice 306. Figure 6 In the example of FIG. 1 , event broadcast switch 608 provides an interface between an event broadcast network formed by event broadcast switches in DP array 102 and interface slice 304. Event broadcast switch 608 is coupled to event broadcast switches in adjacent slices to the west, east, and north of interface slice 304.

[0059] The event broadcast switch 608 is capable of sending events generated internally by the event logic 606, events received from other interface slices 304, and / or events received from array slices (e.g., compute slices 302 and / or memory slices 306) to other slices. Because events can be broadcast between interface slices 304, events can reach any array slice in the DP array 102 by traversing the event broadcast switch 608 in the interface slice 304 to a specific interface slice 304 and then traversing upward to one or more target (e.g., intended) array slices in the DP array 102.

[0060] In another example, events may also be sent from the event broadcast switch 608 to other circuit blocks and / or subsystems in the same IC. The event data may be forwarded to the CDT 610 and on to the flow switch 406 for transmission through the NoC 106. For example, the CDT circuit 610 may packetize the received events and send the packetized events to the flow switch 406.

[0061] In one or more exemplary implementations, the event broadcast switch 608 can collect broadcast events from one or more or all directions. In some cases, the event broadcast switch 608 can perform a logical "or" of signals and forward the results in one or more or all directions (e.g., including to the CDT circuit 610). Each output from the event broadcast switch 608 can include a bit mask that can be configured by configuration data loaded into the control register 604. The bit mask individually determines which events are broadcast in each direction. For example, such a bit mask can eliminate unwanted or duplicate event propagation.

[0062] The interrupt handler 612 is coupled to the event broadcast switch 608 and is capable of receiving events broadcast from the event broadcast switch 608. In one or more exemplary implementations, the interrupt handler 612 can be configured by configuration data loaded into the control register 604 to generate an interrupt to the NoC 106 or another interconnect on the IC in response to a selected event and / or event combination (e.g., an event generated by the DP array 102 and / or an event generated within the interface slice 304) from the event broadcast switch 608. The interrupt handler 612 can generate an interrupt to a circuit and / or subsystem external to the DP array 102 and / or array interface 104 of the same IC based on the configuration data. On the other hand, the interrupt can be transmitted to a system external to the IC in which the DP array 102 and / or array interface 104 is implemented. In one aspect, the interrupt can be transmitted directly to such other circuits and / or subsystems via an interrupt circuit (not shown). On the other hand, the interrupt handler 612 can be connected to the NoC 106 and transmit the interrupt via the NoC 106.

[0063] The flow switch 406 is connected to the flow switches in the west adjacent slice, the east adjacent slice, and the north adjacent slice. The flow switch 406 is also coupled to the DMA circuit 618 and the NoC flow interface 620 through the flow multiplexer-demultiplexer (MD) 616. The flow switch 406 can be configured by the configuration data loaded into the control register 604. For example, the flow switch 406 can be configured to support packet switching and / or circuit switching operations based on the configuration data. In addition, the configuration data defines the specific slice with which the flow switch 406 communicates, whether it is an array slice and / or other interface slice. In general, with reference to the DP array 102 and the array interface 104, the configuration data loaded into the various slices defines the logical connections established between the flow switches 406 during operation (e.g., runtime operation). For example, with reference to the interface slice 304, the configuration data defines a specific array slice in the column of the array slice directly above the interface slice 304 with which the flow switch 406 communicates.

[0064] The flow MD 616 may include a multiplexer that receives data streams from the DMA circuit 618-1, the DMA circuit 618-2, the NoC flow interface 620-1, and / or the NoC flow interface 620-2. The flow MD 616 is capable of multiplexing the received data streams and forwarding the multiplexed data streams to the flow switch 406. The flow switch 406 selectively transmits different data streams in the received data streams to the west adjacent slice, the east adjacent slice, or the north adjacent slice. The flow MD 616 may include a demultiplexer that receives data streams from the flow switch 406 and selectively demultiplexes the data streams to transmit different data streams in the received data streams to the DMA circuit 618-1, the DMA circuit 618-2, the NoC flow interface 620-1, and / or the NoC flow interface 620-2. For example, flow MD 616 may be programmed by configuration data stored in control register 604 that specifies which data flows are routed to DMA circuit 618-1, DMA circuit 618-2, NoC flow interface 620-1, and / or NoC flow interface 620-2.

[0065] DMA circuit 618 converts the data stream from stream MD 616 into memory mapped transactions that are sent to NoC 106. Similarly, DMA circuit 618 converts memory mapped transactions received from NoC 106 into data streams that are forwarded to stream MD 616. NoC stream interface 620 forwards the data stream received from NoC 106 to stream MD 616. Similarly, NoC stream interface 620 forwards the data stream received from stream MD 616 to NoC 106. For example, NoC stream interface 620 transmits the data stream received from stream MD to NoC 106 via switch 622 over the data portion of the communication bus (e.g., without utilizing the address bus portion of the bus). For example, the address information may be embedded in the data stream itself.

[0066] Each of the switches 622 accepts data from a DMA circuit 618 attached thereto or a NoC stream interface 620 attached thereto, arbitrates between the data, and forwards the data to the NoC 106. In this example, the switch 622 is coupled to a NoC master circuit (NMC) 650. A NoC slave circuit (NSC) 652 is connected to the NoC stream interface 620 and to the bridge 614. In one or more exemplary implementations, the DMA circuit 618 includes a hardware synchronization circuit that can be used to synchronize one or more channels in each DMA circuit included in the DMA circuit 618 with a master device that polls and drives a lock request. For example, the master device can be another circuit or subsystem within the IC in which the interface chip 304 is disposed. The master device can also receive interrupts generated by the hardware synchronization circuit within the DMA circuit 618.

[0067] In one or more exemplary implementations, the DMA circuit 618 is capable of accessing memory. As discussed, one or more of the subsystems 108-116 may implement such memory. Alternatively, the memory may be located outside the IC. For example, the DMA circuit 618 and / or the NoC stream interface 620 is capable of receiving a data stream from an array slice of the DP array 102 and sending the data stream to the memory through the NoC 106. Similarly, the DMA circuit 618 is capable of receiving memory mapped data originating from the memory and / or other subsystems and providing the data in the form of a data stream to the stream MD 616 for transmission to other slices. The NoC stream interface 620 is capable of receiving a data stream originating from the memory and / or other subsystems and providing the data stream to the stream MD 616 for transmission to other slices.

[0068] In one or more exemplary implementations, the DMA circuit 618 includes security bits that can be set using certain security registers included in the interface slice 304. The security registers may be included in the control register 604 or implemented independently and separately from the control register 604. In one aspect, the memory and / or subsystems communicatively linked to the interface slice 304 via the NoC 106 may be divided into different areas or partitions, wherein only the DP array 102 or certain array slices thereof, referred to as partitions, are permitted to access specific areas of the memory and / or subsystems. The security bits within the DMA circuit 618 may be set so that the array slices of the DP array 102 can only access specific areas of the memory and / or subsystems that are permitted according to the security bits through the DMA circuit 618. For example, an application implemented in the DP array 102 or a partition thereof (e.g., a subset of the array slices) may be restricted to access only specific areas of the memory and / or subsystems, restricted to read only from specific areas of the memory, and / or restricted to not be able to write to the memory at all using this mechanism.

[0069] Security bits within the DMA circuit 618 that control access to memory and / or other subsystems may be implemented to control the DP array 102 in an overall manner, or may be implemented in a more fine-grained manner where access to memory and / or other subsystems may be specified and / or controlled on a per-array-slice basis.

[0070] The CDT circuit 610 can perform control, debugging, and tracing operations within the interface slice 304. With respect to debugging, each of the registers located in the interface slice 304 is mapped to a memory map accessible via the memory mapping switch 602. The CDT circuit 610 can include circuits such as, for example, tracing hardware, tracing buffers, performance counters, and / or pause logic. The tracing hardware of the CDT circuit 610 can collect tracing data. The tracing buffer of the CDT circuit 610 can buffer tracing data. The CDT circuit 610 can also output tracing data to the stream switch 406.

[0071] In one or more exemplary implementations, the CDT circuit 610 can collect data (e.g., trace and / or debug data), packetize such data, and then output the packetized data through the flow switch 406. For example, the CDT circuit 610 can output the packetized data and provide such data to the flow switch 406. The control registers 604 can be read or written during debugging via memory mapped transactions through the memory mapped switch 602 of the corresponding interface slice. Similarly, the performance counters within the CDT circuit 610 can be read or written during profiling via memory mapped transactions through the memory mapped switch 602 of the corresponding interface slice 304.

[0072] In one or more exemplary implementations, the CDT circuit 610 can receive: any event propagated by the event broadcast switch 608, or selected events according to a bit mask utilized by the event broadcast switch 608 coupled to the CDT circuit 610. The CDT circuit 610 can also receive events generated by the event logic 606. For example, the CDT circuit 610 can receive broadcast events from the array slice, the interface slice 304. The CDT circuit 610 can package (e.g., packetize) multiple such events together in a packet and associate the packetized events with a timestamp. The CDT circuit 610 can also send the packetized events to a destination external to the interface slice 304 through the stream switch 406. The event can be sent to the NoC 106 via the stream switch 406 and the stream MD 616 via the DMA circuit 618 and / or the NoC stream interface 620.

[0073] exist Figure 4 , Figure 5 and Figure 6 In the example of FIG. 4 , flow switch 406 may be implemented with a greater number of ports and channels to accommodate the increased connectivity of interface slice 304 to NoC 106 . The increased number of ports and channels allows flow switch 406 to ensure that a higher level of data throughput provided from interface slice 304 continues to enter DP array 102 .

[0074] Figure 7Another exemplary implementation of the interface sheet 304 of the array interface 104 is shown. Figure 7 , switch 702 has been added. As shown, switch 702-1 and switch 702-2 have been added. Switch 702-1 is connected to switch 622-1 and NMC 650-2. Switch 702-1 is also connected to switch 702-2 in the east adjacent interface slice. Switch 702-2 is connected to switch 622-2 and NMC 650-2. Switch 702-2 is also connected to switch 702-1 in the west adjacent interface slice.

[0075] The switches 702 provide additional flexibility for routing data flows into and out of the DP array 102 relative to the NoC 106. That is, since the network for the user application is routed through the NoC 106 and uses entry / exit points corresponding to the NMC 650 and the NSC 652, respectively, the inclusion of the switches 702 provides greater flexibility in routing the network through the NoC 106. The additional switching capacity provided within the interface slice 304 by including the switches 702 alleviates routing congestion that may occur by allowing data from a particular interface slice 304 to enter the NoC 106 through different interface circuitry than if the switches 702 were omitted. The NMC 650 is an example of an interface circuit for the NoC 106.

[0076] For example, data from the DMA circuit 618 or the NoC flow interface 620 may enter the NoC 106 via the NMC 650-1 or via the NMC 650 in the East Neighbor Interface Slice based on the programming of the switch 702-1. Thus, programming the switch 702-1 and the switch 702-2 in the East Neighbor Slice provides a selection mechanism for determining where the DMA circuit 618-1 and / or the NoC flow interface 620-1 are coupled to the NoC 106. In this regard, the switch 702 may be referred to as a "selector switch" because programming such a switch selects the connection point of certain circuits (e.g., the DMA circuit 618 and / or the NoC flow interface 620) to the NoC 106. The DMA circuit 618-1 and / or the NoC flow interface 620-1 may enter the NoC 106 via the NMC 650-1 or via another NMC 650 (not shown) located below the East Neighbor Interface Slice 304. Thus, switch 702 is programmable to connect different ones of the interface circuits of NoC 106 to different ones of interface slices 304. This flexibility allows implementation tools to avoid over-congesting interface circuits when routing networks into, out of, and / or through NoC 106.

[0077] refer to Figure 6 and Figure 7, both exemplary interface slices 304 provide increased connectivity from the DP array 102 to the NoC 106. Both exemplary interface slices 304 can alleviate routing congestion because each interface slice 304 can be connected to the NoC 106 through different NMCs 650 and NSCs 652. The inclusion of multiple DMA circuits 618 and multiple NoC stream interfaces 620 allows for larger amounts of data to be transferred between the DP array 102 and the NoC 106 on a per-interface slice 304 basis. This translates into significantly larger amounts of data being transferred between the NoC 106 and the DP array 102 as a whole (e.g., for one or more given applications implemented in the DP array 102). As discussed, the ability to transfer larger amounts of data, for example, between any of the subsystems 108-116 and the DP array 102 increases data throughput and reduces latency. Data can be moved from memory to the DP array 102, for example, using twice the bandwidth of a single DMA circuit 618 and / or a single NoC stream interface 620 included in the interface slice 304.

[0078] Reference Figure 6 and Figure 7 Both alleviate routing congestion by allowing data directed to a particular interface slice 304 to leave the NoC 106 via either the NSC 652 - 1 or the NSC 652 - 2 .

[0079] By including Figure 7 The added flexibility of the switches 702 also helps alleviate the additional congestion that may occur in the NoC 106 and the contention for access to the NMC 650 and / or NSC 652 due to including multiple DMA circuits 618 and multiple NoC flow interfaces 620 to support a greater number of connections per interface slice to the NoC 106. For example, in the event that the bandwidth of a particular DMA circuit 618 and / or NoC flow interface 620 of a selected interface slice 304 is underutilized, the switch 702 connected to that DMA circuit 618 and NoC flow interface 620 may be programmed to accept data from a neighboring DMA circuit and / or flow switch.

[0080] Figure 8 An exemplary implementation of connectivity between interface slices 304 of array interface 104 implemented by switch 702 is shown. Figure 7 The example shows that each switch 702-1 (except for example Figure 3304-6) can be communicatively linked to the switch 702-2 of the east adjacent interface slice 304. Each switch 702-2 (except the first switch 702-2 of the interface slice 304-1) is connected to the switch 702-1 of the west adjacent interface slice 304. In this regard, the switch 702-2 of the interface slice 304-1 can be omitted. Similarly, the switch 702-1 of the rightmost interface slice 304 (e.g., the interface slice 304-6) can be omitted.

[0081] exist Figure 8 In the example of FIG. 8 , each interface chip 304 is aligned with a column of an array chip 802 (e.g., a computing chip 302 or a combination of a computing chip 302 and a memory chip 306). That is, one interface chip 304 is aligned with one column of the array chip 802. Each interface chip 304 includes two DMA circuits (not shown).

[0082] Fig. 9 An exemplary implementation of the NoC 106 is shown. The NoC 106 includes an NMC 650, an NSC 652, a network 914, a NoC peripheral interconnect (NPI) 910, and a register 912. Each NMC 650 is an inlet circuit that connects an endpoint circuit to the NoC 106. Each NSC 652 is an egress circuit that connects the NoC 106 to the endpoint circuit. The NMC 650 is connected to the NSC 652 via a network 914. In the example, the network 914 includes a NoC packet switch 906 (NPS) and a route 908 between the NoC packet switches 906. Each NoC packet switch 906 performs the exchange of NoC packets. The NoC packet switches 906 are connected to each other and to the NMC 650 and the NSC 652 via routes 908 to implement multiple physical channels. The NoC packet switches 906 also support multiple virtual channels per physical channel.

[0083] The NPI 910 includes circuits for programming the NMC 650, NSC 652, and NoC packet switches 906. For example, the NMC 650, NSC 652, and NoC packet switches 906 may include registers 912 that determine their functionality. The NPI 910 includes peripheral interconnects coupled to the registers 912 for programming them to set functionality. The registers 912 in the NoC 106 support interrupts, quality of service (QoS), error handling and reporting, transaction control, power management, and address mapping control. The registers 912 may be initialized to a usable state before being reprogrammed, such as by writing to the registers 912 using a write request. Configuration data for the NoC 106, DP array 102, and / or array interface 104 may be stored in non-volatile memory (NVM), e.g., as part of various components and / or subsystems of a programming device image (PDI) that specifies configuration data for an IC (e.g., including the DP array 102 and / or array interface 104), and provided to the NPI 910 for programming the NoC 106 and / or other endpoint circuits.

[0084] NMC 650 is a communication entry point. NSC 652 is a communication exit point. NMC 650 and NSC 652 are examples of interface circuits of NoC 106. Endpoint circuits coupled to NMC 650 and NSC 652 may be hardened circuits. In another aspect, one or more of NMC 650 and / or NSC 652 may be circuits implemented in programmable logic (e.g., where programmable logic is included in an IC as one or more of subsystems 108-116). A given endpoint circuit may be coupled to more than one NMC 650 or more than one NMC 650.

[0085] Fig.10 1 is a block diagram depicting connections between endpoint circuits in an IC through NoC 106 according to an example. In this example, endpoint circuit 1002 is connected to endpoint circuit 1004 through NoC 106. Endpoint circuit 1002 is a master circuit coupled to NMC 650 of NoC 106. Endpoint circuit 1004 is a slave circuit coupled to NSC 652 of NoC 106. Each endpoint circuit 1002 and 1004 can be any of a variety of circuits, such as, for example, interface chip 304 and / or any of various subsystems 108-116. Examples of different subsystems can include, but are not limited to, processor systems, programmable logic, hardwired circuit blocks (e.g., digital-to-analog converters, analog-to-digital converters, transceivers, etc.). For example, one or more of endpoint circuits 1002 and / or 1004 can be processor 206 and / or memory 204.

[0086] The network 914 includes a plurality of physical channels 1006. The physical channels 1006 are implemented by programming the NoC 106. Each physical channel 1006 includes one or more NoC packet switches 906 and associated routing 908. The NMC 650 is connected to the NMC 650 through at least one physical channel 1006. The physical channel 1006 may also have one or more virtual channels 1008.

[0087] The connection through the network 914 uses a master-slave arrangement. In an example, the most basic connection through the network 914 includes a single master device connected to a single slave device. However, in other examples, more complex structures can be implemented.

[0088] Although the present disclosure ends with claims defining novel features, it is believed that the various features described in this disclosure will be better understood by considering the description in conjunction with the accompanying drawings. The processes, machines, manufactures, and any variations thereof described herein are provided for illustrative purposes. The specific structural and functional details described in this disclosure should not be construed as limiting, but merely as a basis for the claims, and as a representative basis for teaching those skilled in the art to variously employ the features described in virtually any appropriately detailed structure. Furthermore, the terms and phrases used in this disclosure are not intended to be limiting, but rather to provide an understandable description of the features described.

[0089] For the purpose of simplicity and clear illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, for clarity, the size of some of the elements may be enlarged relative to other elements. In addition, reference numerals are repeated in the drawings to indicate corresponding, similar or analogous features where deemed appropriate.

[0090] As defined herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0091] As defined herein, the term "approximately" means nearly correct or exact, a value or amount close but not exact. For example, the term "approximately" may mean that the listed characteristic, parameter or value is within a predetermined amount of the exact characteristic, parameter or value.

[0092] As defined herein, the terms "at least one," "one or more," and "and / or" are open-ended expressions that are both conjunctions and transitional conjunctions in operation unless expressly stated otherwise. For example, each of the expressions "at least one of A, B, and C," "at least one of A, B, or C," "one or more of A, B, and C," "one or more of A, B, or C," and "A, B, and / or C" means A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0093] As defined herein, the term "automatically" means without human intervention. As defined herein, the term "user" means a human being.

[0094] As defined herein, the term "if" means "when" or "upon" or "in response to," depending on the context. Thus, the phrase "if it is determined" or "if [a specified condition or event] is detected" may be understood to mean "upon determining" or "in response to determining" or "upon detecting [a specified condition or event]" or "in response to detecting [a specified condition or event]," depending on the context.

[0095] As defined herein, the term "in response to" and similar language as described above (e.g., "if," "when," or "upon") means to be susceptible to a response or reaction to an action or event. The response or reaction is automatically performed. Thus, if a second action is performed "in response to" a first action, there is a causal relationship between the occurrence of the first action and the occurrence of the second action. The term "in response to" indicates a causal relationship.

[0096] As defined herein, the term "output" means storing in a physical memory element (eg, a device), writing to a display or other peripheral output device, sending or transmitting to another system, exporting, and the like.

[0097] As defined herein, the term "real time" means a level of processing responsiveness sensed by a user or system that is sufficiently immediate for a particular process or determination to be made, or that enables a processor to keep up with some external process.

[0098] As defined herein, the term "substantially" means that the characteristics, parameters or values ​​described need not be achieved precisely, but deviations or variations (including, for example, tolerances, measurement errors, measurement precision limitations and other factors known to those skilled in the art) may occur in amounts that do not interfere with the effect that the characteristics are intended to provide.

[0099] The terms first, second, etc. may be used herein to describe various elements. These elements should not be limited by these terms, as these terms are only used to distinguish one element from another element, unless otherwise stated or the context clearly indicates otherwise.

[0100] Flowchart and block diagram in the figure show the possible concrete implementation of the system and method of various aspects of the arrangement of the present invention, functionality and operation.In some alternative concrete implementations, the operation pointed out in the frame may not occur in the order pointed out in the figure.For example, depending on the function involved, two frames shown in succession can be performed substantially simultaneously, or these frames can sometimes be performed in reverse order.In other examples, the frame can be usually performed in increasing numerical order, and in other examples, one or more frames can be performed in a variable order, and its result is stored and used in subsequent frames or frames that do not follow closely thereafter.It will also be noted that each frame in the block diagram and / or the flow chart diagram and the combination of the frames in the block diagram and / or the flow chart diagram can be realized by a system based on special-purpose hardware that performs a specified function or action or performs a combination of special-purpose hardware and computer instructions.

[0101] One or more exemplary implementations include an IC. The IC may include a DP array including a plurality of compute slices arranged in a grid. The IC may include an array interface coupled to the DP array. The array interface includes a plurality of interface slices. Each interface slice includes a plurality of DMA circuits. The IC may include a NoC coupled to the array interface. Each DMA circuit is communicatively linked to the NoC via an independent communication channel.

[0102] The foregoing and other implementations may each optionally include one or more of the following features, alone or in combination. Some exemplary implementations include all of the following features in combination.

[0103] In one aspect, the plurality of DMA circuits of each of the plurality of interface chips are configured to simultaneously transfer a plurality of data streams to the data processing array.

[0104] In another aspect, each interface chip includes a flow switch coupled to the plurality of DMA circuits.

[0105] In another aspect, each flow switch is connected to at least one other flow switch disposed in a west adjacent interface slice or an east adjacent interface slice. Each flow switch is connected to another flow switch in a north adjacent array slice.

[0106] In another aspect, the DMA circuit is configured to convert a data stream received from a flow switch into a memory mapped transaction transmitted to the NoC. The DMA circuit is configured to convert a memory mapped transaction received from the NoC into a data stream transmitted to the flow switch.

[0107] In another aspect, each interface chip includes a stream multiplexer-demultiplexer coupled to each DMA circuit of the interface chip. Each stream multiplexer-demultiplexer is configured to selectively pass data streams received from a plurality of direct memory access circuits to a stream switch and direct the streams received from the stream switch to a selected direct memory access circuit of the plurality of direct memory access circuits.

[0108] In another aspect, each interface slice includes a plurality of NoC flow interfaces corresponding to the plurality of DMA circuits. Each NoC flow interface is configured to receive a data flow from the NoC and transmit the data flow to the flow multiplexer-demultiplexer, and receive a data flow from the flow switch and transmit the data flow to the NoC.

[0109] In another aspect, a grid of a plurality of compute slices includes a plurality of columns, each of the plurality of columns including one or more of the plurality of compute slices. Each column of the grid includes a selected compute slice of the one or more of the plurality of compute slices, the selected compute slice having a flow switch connected to a flow switch of an interface slice aligned with the column.

[0110] In another aspect, the grid of the plurality of compute slices includes a plurality of memory slices. The grid includes a plurality of columns, each of the plurality of columns including one or more compute slices of the plurality of compute slices and one or more memory slices of the plurality of memory slices. Each column of the grid includes a selected memory slice of the one or more memory slices of the plurality of memory slices, the selected memory slice having a flow switch connected to a flow switch of an interface slice aligned with the column.

[0111] In another aspect, each direct memory access circuit is connected to a NoC master circuit of the NoC and is configured to transmit transactions through the NoC via the NoC master circuit.

[0112] In another aspect, each interface tile includes a selector switch that is programmable to connect a selected DMA circuit in the same interface tile or a selected DMA circuit in an adjacent interface tile with a selected interface circuit of the plurality of interface circuits of the NoC.

[0113] In another aspect, the selector switch is programmable to connect a different one of the plurality of interface circuits of the NoC to a different one of the interface slices.

[0114] In one or more exemplary implementations, an array interface for an IC may include multiple interface slices. Each interface slice may include a flow switch connected to another flow switch of an adjacent computing slice of a DP array or an adjacent memory slice of the DP array. The flow switch is also connected to a flow switch of at least one adjacent interface slice of the array interface. Each interface slice may include a flow multiplexer-demultiplexer connected to the flow switch. Each interface slice may include multiple DMA circuits. Each DMA circuit is connected to the flow multiplexer-demultiplexer and connected to the NoC. The DMA circuit is configured to convert a data stream received from the flow multiplexer-demultiplexer into a memory mapping transaction transmitted to the NoC, and convert a memory mapping transaction received from the NoC into a data stream transmitted to the flow multiplexer-demultiplexer.

[0115] The foregoing and other implementations may each optionally include one or more of the following features, alone or in combination. Some exemplary implementations include all of the following features in combination.

[0116] In one aspect, each DMA circuit is communicatively linked to the NoC via an independent communication channel. Each of the plurality of interface slices provides a plurality of independent connections to the NoC.

[0117] In another aspect, each stream multiplexer-demultiplexer is configured to selectively pass data streams received from the plurality of DMA circuits to the stream switch and pass data directed streams received from the stream switch to a selected DMA circuit of the plurality of DMA circuits.

[0118] In another aspect, each interface slice may include a plurality of NoC flow interfaces corresponding to a plurality of DMA circuits. Each NoC flow interface is configured to receive a data stream from the NoC and transmit the data stream to the flow multiplexer-demultiplexer. Each NoC flow interface is configured to receive a data stream from the flow multiplexer-demultiplexer and transmit the data stream to the NoC.

[0119] In another aspect, each DMA circuit is connected to a NoC master circuit of the NoC and is configured to transfer transactions through the NoC via the NoC master circuit.

[0120] In another aspect, each interface tile includes a selector switch that is programmable to connect a selected DMA circuit in the same interface tile or a selected DMA circuit in an adjacent interface tile with a selected interface circuit of the plurality of interface circuits of the NoC.

[0121] In another aspect, the selector switch is programmable to connect a different one of the plurality of interface circuits of the NoC to a different one of the interface slices.

[0122] In another aspect, the plurality of DMA circuits are configured to simultaneously transmit the plurality of data streams to the data processing array via the NoC stream interface.

Claims

1. An integrated circuit, comprising: a data processing array comprising a plurality of computing slices arranged in a grid; an array interface coupled to the data processing array, wherein the array interface comprises a plurality of interface slices, wherein each interface slice comprises a plurality of direct memory access circuits; and A network on chip (NoC) is coupled to the array interface, wherein each direct memory access circuit is communicatively linked to the NoC via an independent communication channel.

2. The integrated circuit of claim 1, wherein the plurality of direct memory access circuits of each of the plurality of interface slices are configured to simultaneously transmit a plurality of data streams to the data processing array.

3. The integrated circuit of claim 1, wherein each interface slice comprises a flow switch coupled to the plurality of direct memory access circuits.

4. The integrated circuit of claim 3, wherein: Each flow switch is connected to at least one other flow switch disposed in a west adjacent interface slice or an east adjacent interface slice; and Each flow switch is connected to another flow switch in the north adjacent array slice.

5. The integrated circuit of claim 3, wherein: The direct memory access circuit is configured to convert a data stream received from the flow switch into a memory mapped transaction transmitted to the NoC; and The direct memory access circuit is configured to convert memory mapped transactions received from the NoC into data flows transmitted to the flow switch.

6. The integrated circuit of claim 5, wherein: Each interface slice includes a stream multiplexer-demultiplexer coupled to each direct memory access circuit of the interface slice; and Each stream multiplexer-demultiplexer is configured to selectively pass data streams received from the plurality of direct memory access circuits to the stream switch and direct the streams received from the stream switch to a selected direct memory access circuit among the plurality of direct memory access circuits.

7. The integrated circuit of claim 6, wherein: Each interface slice includes a plurality of NoC flow interfaces corresponding to the plurality of direct memory access circuits; and Each NoC flow interface is configured to receive a data flow from the NoC and pass the data flow to the flow multiplexer-demultiplexer, and receive a data flow from the flow switch and pass the data flow to the NoC.

8. The integrated circuit of claim 3, wherein: The grid of the plurality of computational tiles comprises a plurality of columns, each of the plurality of columns comprising one or more computational tiles of the plurality of computational tiles; and Each column of the grid includes a selected compute slice of the one or more compute slices of the plurality of compute slices having a flow switch connected to the flow switch of the interface slice aligned with the column.

9. The integrated circuit of claim 3, wherein: said grid of said plurality of compute slices comprises a plurality of memory slices; The grid includes a plurality of columns, each of the plurality of columns including one or more of the plurality of compute slices and one or more of the plurality of memory slices; and Each column of the grid includes a selected memory slice of the one or more memory slices of the plurality of memory slices having a flow switch connected to the flow switch of the interface slice aligned with the column.

10. The integrated circuit of any one of claims 1 to 9, wherein each direct memory access circuit is connected to a NoC master circuit of the NoC and is configured to transfer transactions through the NoC via the NoC master circuit.

11. The integrated circuit of any one of claims 1 to 9, wherein each interface slice comprises a selector switch programmable to connect a selected direct memory access circuit in the same interface slice or a selected direct memory access circuit in an adjacent interface slice with a selected interface circuit among the plurality of interface circuits of the NoC.

12. The integrated circuit of claim 11, wherein the selector switch is programmable to connect different ones of the plurality of interface circuits of the NoC to different ones of the interface slices.

13. An array interface for an integrated circuit, the array interface comprising: A plurality of interface slices, wherein each interface slice comprises: a flow switch connected to another flow switch of an adjacent compute slice of a data processing array or an adjacent memory slice of the data processing array, wherein the flow switch is also connected to the flow switch of at least one adjacent interface slice of the array interface; a stream multiplexer-demultiplexer connected to the stream switch; and a plurality of direct memory access circuits, wherein each direct memory access circuit is connected to the stream multiplexer-demultiplexer and to a network on chip (NoC); The direct memory access circuit is configured to convert a data stream received from the stream multiplexer-demultiplexer into a memory mapped transaction transmitted to the NoC, and convert a memory mapped transaction received from the NoC into a data stream transmitted to the stream multiplexer-demultiplexer.

14. The array interface of claim 13, wherein Each interface slice includes a selector switch that is programmable to connect a selected direct memory access circuit in the same interface slice or a selected direct memory access circuit in an adjacent interface slice with a selected interface circuit among a plurality of interface circuits of the NoC.

15. The array interface of claim 14, wherein the selector switch is programmable to connect different ones of the plurality of interface circuits of the NoC to different ones of the interface slices.

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