Memory device and operating method thereof, memory system

Abstract

Embodiments of the present disclosure provide a memory device and an operating method thereof, and a memory system. The memory device includes a memory cell array including a plurality of memory blocks, and a peripheral circuit coupled with the memory cell array and configured to: apply a first effective erase voltage to a selected memory block among the plurality of memory blocks, and apply a plurality of different erase verify voltages to the selected memory block after applying the first effective erase voltage; and determine a second effective erase voltage applied to the selected memory block based on results of a plurality of erase verifications corresponding to the plurality of different erase verify voltages, the second effective erase voltage being greater than the first effective erase voltage.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a memory device and its operation method, and a memory system. Background Technology

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the memory market due to its high storage density, controllable production cost, suitable erasure speed, and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and their systems.

[0004] Application content

[0005] Based on this, embodiments of this disclosure provide a memory device and its operating method, as well as a memory system. In one aspect, an embodiment of this disclosure provides a memory device comprising: a memory cell array, the memory cell array including a plurality of memory blocks; and

[0006] The peripheral circuitry, coupled to the memory cell array and configured to: apply a first effective erase voltage to a selected memory block among the plurality of memory blocks, and then apply multiple different erase verification voltages to the selected memory block;

[0007] Based on the results of multiple erase verifications corresponding to the multiple different erase verification voltages, a second effective erase voltage is determined on the selected storage block, wherein the second effective erase voltage is greater than the first effective erase voltage.

[0008] In one embodiment, the multiple different erase verification voltages include three different erase verification voltages, and the result of the multiple erase verifications includes the result of the three erase verifications.

[0009] In one embodiment, the three different erase verification voltages include: a first erase verification voltage, a second erase verification voltage, and a third erase verification voltage with sequentially increasing voltage values; the first erase verification voltage, the second erase verification voltage, and the third erase verification voltage correspond to the results of the first erase verification, the second erase verification, and the third erase verification, respectively.

[0010] The peripheral circuit is further configured to: when the result of the first erase verification fails and the result of the second erase verification succeeds, determine that the voltage value of the second effective erase voltage is increased by a first voltage increment compared to the voltage value of the first effective erase voltage;

[0011] When the result of the second erase verification fails and the result of the third erase verification succeeds, it is determined that the voltage value of the second effective erase voltage is increased by a second voltage increment compared to the voltage value of the first effective erase voltage.

[0012] When the result of the third erase verification fails, it is determined that the voltage value of the second effective erase voltage is increased by a third voltage increment compared to the voltage value of the first effective erase voltage.

[0013] Wherein, the third voltage increment is greater than the second voltage increment, and the second voltage increment is greater than the first voltage increment.

[0014] In one embodiment, the memory block includes a drain terminal and a source terminal, wherein the source terminal is provided with a source line and a source select gate.

[0015] The peripheral circuit is further configured to: apply a pulse corresponding to a first erase voltage to the source line of the selected memory block; during the process of the voltage of the source line rising to the first erase voltage, apply a first voltage to the source select gate of the selected memory block and float the source select gate after a preset time; during the process of the voltage of the source line stabilizing at the first erase voltage, stabilize the voltage of the source select gate at a second voltage, the second voltage being less than the first erase voltage, and the difference between the first erase voltage and the second voltage constituting the second effective erase voltage;

[0016] The longer the preset duration, the greater the voltage value of the second effective erasure voltage.

[0017] In one embodiment, the peripheral circuit is further configured to: determine the preset duration as a first duration when the result of the first erase verification fails and the result of the second erase verification succeeds;

[0018] When the result of the second erase verification fails and the result of the third erase verification succeeds, the preset duration is determined to be the second duration.

[0019] When the third erasure verification fails, the preset duration is set to the third duration.

[0020] Wherein, the first duration is less than the second duration, and the second duration is less than the third duration.

[0021] In one implementation, the selected storage block includes a plurality of storage blocks;

[0022] The peripheral circuit is configured to simultaneously apply a pulse corresponding to the first erase voltage to the source line of each of the selected plurality of memory blocks.

[0023] In one embodiment, the storage cell array includes multiple storage surfaces; the selected multiple storage blocks are respectively stored in different storage surfaces;

[0024] The peripheral circuit is further configured to apply different second effective erase voltages to the selected memory blocks in different memory surfaces by changing the preset duration when performing an erase operation on multiple memory blocks selected in multiple memory surfaces.

[0025] In one embodiment, the memory block includes a drain terminal and a source terminal, wherein the source terminal is provided with a source line; the memory block includes multiple word lines located between the drain terminal and the source terminal;

[0026] The peripheral circuit is further configured to: apply a second erase voltage to the source line of the selected memory block and apply a first voltage to all word lines of the selected memory block, wherein the difference between the second erase voltage and the first voltage constitutes the second effective erase voltage;

[0027] The larger the value of the second erase voltage, the larger the value of the second effective erase voltage.

[0028] In one embodiment, the first voltage is ground voltage.

[0029] In one embodiment, the peripheral circuitry is further configured to perform an erase operation on the selected memory block by repeatedly applying an increasingly larger effective erase voltage.

[0030] After each effective erase voltage is applied in the preset sequence, the third erase verification voltage is directly applied to the selected memory block, and the effective erase voltage to be applied to the selected memory block next is determined based on the erase verification result corresponding to the third erase verification voltage.

[0031] After applying an effective erase voltage more than the preset number of times, the selected memory block is subjected to the multiple different erase verification voltages, and the next effective erase voltage applied to the selected memory block is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages.

[0032] In one embodiment, the peripheral circuit is further configured to apply a second erase verification voltage to the selected memory block when the result of the first erase verification fails.

[0033] When the second erase verification fails, the third erase verification voltage is applied to the selected storage block.

[0034] In one implementation, the first voltage is increased by a step voltage.

[0035] On the other hand, embodiments of this disclosure provide a memory system, including:

[0036] One or more memory devices as described in the above embodiments of this disclosure; and

[0037] A memory controller, which is coupled to and controls the memory device.

[0038] In another aspect, embodiments of this disclosure provide an operation method for a memory device, the operation method comprising:

[0039] After applying a first effective erase voltage to a selected memory block of the memory device, multiple different erase verification voltages are applied to the selected memory block.

[0040] Based on the results of multiple erase verifications corresponding to the multiple different erase verification voltages, a second effective erase voltage is determined on the selected storage block, wherein the second effective erase voltage is greater than the first effective erase voltage.

[0041] In one embodiment, the multiple different erase verification voltages include three different erase verification voltages, and the result of the multiple erase verifications includes the result of the three erase verifications.

[0042] In one embodiment, the three different erase verification voltages include: a first erase verification voltage, a second erase verification voltage, and a third erase verification voltage with sequentially increasing voltage values; the first erase verification voltage, the second erase verification voltage, and the third erase verification voltage correspond to the results of the first erase verification, the second erase verification, and the third erase verification, respectively; the method further includes:

[0043] When the result of the first erase verification fails and the result of the second erase verification succeeds, it is determined that the voltage value of the second effective erase voltage is increased by a first voltage increment compared to the voltage value of the first effective erase voltage.

[0044] When the result of the second erase verification fails and the result of the third erase verification succeeds, it is determined that the voltage value of the second effective erase voltage is increased by a second voltage increment compared to the voltage value of the first effective erase voltage.

[0045] When the result of the third erase verification fails, it is determined that the voltage value of the second effective erase voltage is increased by a third voltage increment compared to the voltage value of the first effective erase voltage.

[0046] Wherein, the third voltage increment is greater than the second voltage increment, and the second voltage increment is greater than the first voltage increment.

[0047] In one embodiment, the memory block includes a drain terminal and a source terminal, the source terminal being provided with a source line and a source select gate; the method further includes:

[0048] A pulse corresponding to a first erase voltage is applied to the source line of the selected memory block. During the process of the voltage of the source line rising to the first erase voltage, a first voltage is applied to the source select gate of the selected memory block and the source select gate is floated after a preset time. During the process of the voltage of the source line stabilizing at the first erase voltage, the voltage of the source select gate stabilizes at a second voltage. The second voltage is less than the first erase voltage, and the difference between the first erase voltage and the second voltage constitutes the second effective erase voltage.

[0049] The longer the preset duration, the greater the voltage value of the second effective erasure voltage.

[0050] In one embodiment, the method further includes: when the result of the first erasure verification fails and the result of the second erasure verification succeeds, determining the preset duration as a first duration;

[0051] When the result of the second erase verification fails and the result of the third erase verification succeeds, the preset duration is determined to be the second duration.

[0052] When the third erasure verification fails, the preset duration is set to the third duration.

[0053] Wherein, the first duration is less than the second duration, and the second duration is less than the third duration.

[0054] In one embodiment, the memory block includes a drain terminal and a source terminal, the source terminal being provided with a source line; the memory block includes multiple word lines located between the drain terminal and the source terminal; the method further includes:

[0055] A second erase voltage is applied to the source line of the selected memory block, and a first voltage is applied to all word lines of the selected memory block. The difference between the second erase voltage and the first voltage constitutes the second effective erase voltage.

[0056] The larger the value of the second erase voltage, the larger the value of the second effective erase voltage.

[0057] In one embodiment, the method further includes: performing an erase operation on the selected memory block by repeatedly applying an increasingly larger effective erase voltage;

[0058] After each effective erase voltage is applied in the preset sequence, the third erase verification voltage is directly applied to the selected memory block, and the effective erase voltage to be applied to the selected memory block next is determined based on the erase verification result corresponding to the third erase verification voltage.

[0059] After applying an effective erase voltage more than the preset number of times, the selected memory block is subjected to the multiple different erase verification voltages, and the next effective erase voltage applied to the selected memory block is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages.

[0060] This disclosure provides a memory device and its operation method, as well as a memory system. The memory device includes a memory cell array and peripheral circuitry. The memory cell array includes multiple memory blocks. The peripheral circuitry is configured to: apply a first effective erase voltage to a selected memory block among the multiple memory blocks, then apply multiple different erase verification voltages to the selected memory block; and determine a second effective erase voltage applied to the selected memory block based on the results of multiple erase verifications corresponding to the multiple different erase verification voltages, wherein the second effective erase voltage is greater than the first effective erase voltage. In this embodiment of the present disclosure, after applying a first effective erase voltage to each selected memory block among multiple memory blocks, the degree of erasure of each memory block is determined by applying multiple different erase verification voltages to the multiple memory blocks respectively. Based on the different degrees of erasure of the multiple memory blocks, different second effective erase voltages are applied to them, so that the degree of erasure of the multiple memory blocks after applying different second effective erase voltages tends to be consistent, and the erasure speed also tends to be consistent. In this way, the threshold voltage distribution of the erase state among different memory blocks tends to be uniform and consistent, improving the read window margin of the memory blocks, thereby improving the read performance and erase performance of the memory device. Attached Figure Description

[0061] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0062] Figure 2 a is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of this disclosure;

[0063] Figure 2 b is a schematic diagram of an exemplary solid-state driver with a memory system according to an embodiment of this disclosure;

[0064] Figure 3 a is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0065] Figure 3b is a schematic diagram of an exemplary memory including peripheral circuitry according to an embodiment of this disclosure;

[0066] Figure 4 This is a schematic cross-sectional view of a memory cell array including NAND-type memory strings according to an embodiment of the present disclosure;

[0067] Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure;

[0068] Figure 6 A schematic diagram illustrating a threshold voltage distribution example for a three-bit memory cell, provided as an embodiment of this disclosure;

[0069] Figure 7 This is an example schematic diagram illustrating an embodiment of the present disclosure, which includes applying three different erase verification voltages to a storage block.

[0070] Figure 8 a is an example schematic diagram of an embodiment of the present disclosure, which includes multiple memory blocks to which different second voltages are applied;

[0071] Figure 8 b is a schematic diagram illustrating another example of applying different second voltages to multiple memory blocks according to an embodiment of the present disclosure;

[0072] Figure 9 This is an example schematic diagram illustrating an embodiment of the present disclosure, which includes multiple memory blocks by adjusting the voltage difference between the source line and all bit lines.

[0073] Figure 10 is a schematic diagram of the threshold voltage distribution of the erased state obtained by the storage block under different erase methods in a storage state according to an embodiment of the present disclosure;

[0074] Figure 11 is a schematic diagram of the threshold voltage distribution of the erase state obtained by the storage block using different erase methods in another storage state according to another embodiment of this disclosure.

[0075] In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The figures illustrate, by way of example and not limitation, the various embodiments discussed herein. Detailed Implementation

[0076] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0077] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0078] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0079] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0080] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0081] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0082] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0083] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0084] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0085] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments in solid state drives (SSDs) or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0086] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (pCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0087] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2 In one example shown in Figure a, the memory controller 106 and a single memory device 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2 In another example shown in b, the memory controller 106 and multiple memory devices 104 can be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., ...). Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0088] Figure 3 An exemplary schematic diagram of a three-dimensional NAND flash memory cell array is provided, such as... Figure 3 As shown in Figure a, the memory cell array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered memory cell rows parallel to the gate isolation structure. Each two rows of memory cell rows are separated by a gate isolation structure and an up-select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks. Multiple second gate isolation structures can divide the memory blocks into multiple finger memory regions. An up-select gate isolation structure located in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory chips. Figure 3 The storage block shown in Figure 'a' contains 6 storage chips. In practical applications, the number of storage chips in a storage block is not limited to this.

[0089] In some embodiments, each memory block may be coupled with multiple word lines, and the multiple memory cells coupled to each individually controlled word line constitute a page. For example, Figure 3 In a, all memory cells in each memory chip are coupled together to form a page.

[0090] It should be noted that, Figure 3 The number of cell rows between the gate isolation structure and the top-select gate isolation structure given in section a is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0091] Figure 3 b shows a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are NAND-type memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0092] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0093] like Figure 3As shown in Figure b, each memory string 308 may include a lower selection transistor 310 (also referred to as a source-side selection transistor, which includes a source-select gate BSG) at its source end and an upper selection transistor 312 (also referred to as a drain-side selection transistor, which includes a drain-select gate TSG) at its drain end. The source-select transistor BSG 310 and the drain-select transistor TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0094] like Figure 3 As shown in b, memory strings 308 can be organized into multiple memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) biased and coupled to the source line 314 of the selected memory block 304 and the unselected memory blocks 304 on the same plane as the selected memory block 304 can be used. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, in conjunction with the foregoing... Figure 3a. Multiple memory cells are isolated from each other by an upselect gate isolation structure and a gate isolation structure. The multiple memory cells between the upselect gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each memory cell row being parallel to the gate isolation structure and the upselect gate isolation structure. Memory cells in a memory chip sharing the same word line form a physical page 320. Each physical page 320 can be mapped to at least one logical page according to the memory mode of the corresponding memory cell 306 (e.g., SLC or MLC as mentioned above). Logical pages can constitute the basic data unit for programming and reading operations.

[0095] refer to Figure 3 a, Figure 3 b. Each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 through a corresponding selection transistor (such as the selection transistor (TSG) 312 above).

[0096] Figure 4 A schematic cross-sectional view of an exemplary memory cell array 301, including a memory string 308 exemplified by NAND, is shown according to some aspects of this disclosure. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure and the plurality of gate layers in the stacked structure 410 are coupled to form a memory string 308. The gate layers 411 and the insulating layers 412 may be stacked alternately, and two adjacent gate layers 411 are separated by an insulating layer 412.

[0097] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0098] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0099] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0100] Return to reference Figure 3 b. Peripheral circuitry 302 can be coupled to the memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0101] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store programming data to be programmed into memory cell array 301 (write data). In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0102] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0103] Control logic 512 can be coupled to each of the other parts of the peripheral circuitry described above and is configured to control the operation of each of the other parts of the peripheral circuitry. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0104] return Figure 3 a, Figure 3 b. In NAND flash memory, two methods can be used to erase the memory cell array. One method is P-well erasure, which involves biasing the P-well substrate (such as a P-type doped well region) to a high voltage and applying a lower bias voltage to the control gate of the memory cell to perform the erasure operation. The other method is GIDL erasure, which involves applying a high voltage to the source line or bit line, gradually floating the BSG line 315 or TSG line 313 from a lower voltage to generate a gate-induced drain leakage (GIDL) current. This current is then applied to the control gate of the memory cell to perform the erasure operation. Both P-well erasure and GIDL erasure can be used to reduce the threshold voltage (Vt) of the memory cell. It should be understood that the memory cell array can include multiple memory blocks, and the basic unit of the above erasure operations is the memory block.

[0105] However, as the number of erase and program cycles increases, the tunneling efficiency of the tunneling layer in the memory cell gradually weakens (i.e., the tunneling layer wears down). This increases the number of pulses required for an erase operation by one or even several, which means that the number of erase cycles required for a complete erase operation increases by one or even several. Consequently, the erase speed of a single memory block becomes slower and slower. Furthermore, because the wear of the tunneling layer varies in different memory blocks, the erase speeds between memory blocks also become inconsistent, resulting in significant fluctuations in erase time and impacting the erase performance of NAND flash memory.

[0106] Furthermore, during the aforementioned erase operation, an increase in the number of erase cycles can lead to a shallow erase effect, resulting in different threshold voltage distributions among multiple memory cells within the memory block. This, in turn, causes significant differences in the read window margin / budget between multiple sub-blocks and between memory blocks, impacting the read performance of the memory block and the memory device. Here, multiple memory cells connected to the same word line constitute a sub-block. For example, refer to... Figure 6 The memory device includes multiple memory blocks, and each memory block includes multiple sub-memory blocks. Figure 6 The example only shows one of multiple sub-blocks. The multiple storage cells in the sub-block shown are all three-bit storage cells. Each three-bit storage cell has eight states (L0-L7), which can be further divided into erase state L0 and seven storage states (L1-L7). The eight states correspond to seven read windows (such as RD1, RD2, RD3, RD4, RD5, RD6, RD7). Due to the shallow erase effect, the difference in read window margin E0 between the multiple erase states L0 corresponding to the multiple storage blocks in the memory device is about 400mV, which affects the read performance of the storage blocks and the memory device.

[0107] To address the issue of large differences in the read window margin E0 among multiple memory blocks in the erase state L0 caused by erasure, incremental step pulse erase (ISPE) can be used. An erase process can include multiple erase cycles, each of which includes an erase operation and an erase verification operation. The erase voltage of the erase operation is gradually increased in a step, and an erase verification operation is performed after each erase operation.

[0108] However, reference Figure 6 After erasing the memory blocks using the incremental step pulse erasure method described above, the read window margin E0 of the erase state L0 between multiple memory blocks still has a large difference. This makes it difficult to determine the threshold voltage distribution range of the erase state of the memory block between +3σ and -3σ according to the 3σ (sigma) criterion of normal distribution during subsequent testing, which is too wide and affects the performance of the memory device.

[0109] It should be noted that the 3σ criterion, also known as the Raida criterion, assumes that a set of test data contains only random errors. It calculates the standard deviation and determines an interval based on a certain probability. Errors exceeding this interval are considered gross errors, not random errors, and data containing such errors should be discarded. The 3σ criterion is based on repeated measurements with equal precision and a normal distribution, but outlier or noise data may not conform to a normal distribution. If the absolute value of the residual error of a measurement in a set of data is greater than 3σ, then that measurement is considered a bad value and should be discarded. Errors equal to ±3σ are usually considered the limiting error. For normally distributed random errors, the probability of falling outside ±3σ is only 0.27%, which is very small in a finite number of measurements; hence, the 3σ criterion exists. The 3σ criterion is the most commonly used and simplest gross error criterion. It is generally applied when the number of measurements is sufficiently large (n≥30) or when a rough judgment is made when n>10.

[0110] Therefore, based on one or more of the above-mentioned problems, this disclosure proposes a memory device and its operating method, a memory system; wherein the memory device includes a memory cell array, the memory cell array may include a plurality of memory blocks; peripheral circuitry, coupled to the memory cell array and configured to: apply a first effective erase voltage to a selected memory block among the plurality of memory blocks, then apply multiple different erase verification voltages to the selected memory block; and determine a second effective erase voltage applied to the selected memory block based on the results of multiple erase verifications corresponding to the multiple different erase verification voltages, wherein the second effective erase voltage is greater than the first effective erase voltage.

[0111] The storage cell array and peripheral circuitry are coupled to each other; the storage cell array may include multiple storage surfaces, each storage surface may include multiple storage blocks, each storage block may include multiple storage pages, a storage page is the smallest unit of read and write (i.e., programming) operations, and a storage block is the smallest unit of erase operations.

[0112] Peripheral circuitry may include any suitable digital, analog, and / or mixed-signal circuitry configured to facilitate various operations such as reading, writing, and erasing of the memory device. For example, peripheral circuitry may include control logic (e.g., control circuitry or controller), data buffers, decoders (also called decoders), drivers, and read / write circuitry. When the control logic receives read / write operation commands and address data, the decoder, under the control of the control logic, can apply the corresponding voltage from the driver to the corresponding bit line and word line based on the decoded address to achieve data reading and writing, and interact with the outside world through the data buffer.

[0113] refer to Figure 3b. The memory string 308 includes a plurality of memory cells 306, a drain-side select transistor 312 located at one end of the memory string, which connects the memory string 308 to the bit line 316, and a source-side select transistor 310 located at one end of the memory string, which connects the memory string 308 to the source line 314. The drain-side select transistor 312 has a corresponding drain-select gate (TSG), and the source-side select transistor 310 has a corresponding source-select gate (BSG).

[0114] It should be understood that due to the voltage difference between the drain-select gate (TSG) and the bit line 316, the gate of the drain-side select transistor is negatively biased, thereby forming a PN junction at the drain of the drain-side select transistor 312, generating a hole current flowing downward from the drain side to the source side. The voltage difference between the drain-select gate (TSG) and the bit line 316 applies a high electric field to the PN junction, causing the hole current to propagate downward from the drain side to the source side, and establishing a high potential within the semiconductor channel. Furthermore, the negative bias of the word line relative to the channel portion can inject holes into the memory layer, thereby generating a gate-to-drain leakage current between the bit line and the drain-select gate due to the inter-band tunneling mechanism for data erasure operations.

[0115] Similarly, refer to Figure 4 Due to the voltage difference between the source-side selection gate (BSG) and the N-type doped well region in the source-side selection transistor 310, the gate of the source-side selection transistor is negatively biased, thereby forming a PN junction at the drain of the source-side selection transistor. Furthermore, the voltage difference between the source-side selection gate (BSG) and the N-type doped well region applies a high electric field to the PN junction. This high electric field generates a gate-to-drain leakage current between the N-type doped well region and the source-side selection gate (BSG) due to interband tunneling, thus enabling data erasure operations.

[0116] In this embodiment of the disclosure, during the erasure process using Incremental Step Pulse Erasure (ISPE), the peripheral circuit is configured to apply a first effective erase voltage to a selected memory block among multiple memory blocks. Here, the first effective erase voltage can be the voltage difference between the source line SL and the source select gate (BSG) of the selected memory block in the first erase cycle of an erase process, or it can be the voltage difference between the source line SL of the selected memory block and all word lines WL. After applying the first effective erase voltage, multiple different erase verification voltages are applied to the selected memory block, and the results of multiple erase verifications are obtained based on these different erase verification voltages. Based on the different erase verification results, it can be determined that the second effective erase voltage applied to the selected memory block is different. Here, the second effective erase voltage is the voltage difference between the source line SL and the source select gate (BSG) in the second erase cycle of an erase process, or the voltage difference between the source line SL of the selected memory block and all word lines WL, wherein the second effective erase voltage is greater than the first effective erase voltage.

[0117] In some embodiments, the multiple different erase verification voltages may include three different erase verification voltages, and correspondingly, the result of the multiple erase verifications may include the result of the three erase verifications; in other embodiments, the multiple different erase verification voltages may also include two, four, five... different erase verification voltages, and here only three different erase verification voltages are used as an example.

[0118] It should be noted that when applying multiple different erase verification voltages to the selected memory block, there is a certain correlation between the different erase verification voltages. Specifically, after applying the first erase verification voltage, it is determined whether a second erase verification voltage needs to be applied to the selected memory block based on the result of the first erase verification. For example, if the first erase verification is successful, it indicates that all memory cells in the selected memory block have completed the corresponding degree of erase operation under the first erase verification voltage, that is, it is not necessary to apply a second erase verification voltage to the selected memory block. If the first erase verification fails, it indicates that there are memory cells in the selected memory block that have not been erased to the corresponding degree under the first erase verification voltage, and then it is necessary to apply a second erase verification voltage to the selected memory block. Similarly, after applying the second erase verification voltage, based on the result of the second erase verification, it is determined whether a third erase verification voltage needs to be applied to the selected memory block. If the second erase verification is successful, it indicates that all memory cells in the selected memory block have completed the corresponding degree of erase operation under the second erase verification voltage, and therefore, a third erase verification voltage does not need to be applied to the selected memory block. If the second erase verification fails, it indicates that there are memory cells in the selected memory block that have not been erased to the corresponding degree under the second erase verification voltage, and therefore, the third erase verification voltage needs to be applied to the selected memory block.

[0119] In some embodiments, the three different erase verification voltages include: a first erase verification voltage, a second erase verification voltage, and a third erase verification voltage with successively increasing voltage values; the first erase verification voltage, the second erase verification voltage, and the third erase verification voltage correspond to the results of the first erase verification, the second erase verification, and the third erase verification, respectively.

[0120] For example, refer to Figure 7 The three different erase verification voltages are the first erase verification voltage Vev, the second erase verification voltage Vev_coarse1, and the third erase verification voltage Vev_coarse2. The third erase verification voltage Vev_coarse2 is greater than the second erase verification voltage Vev_coarse1, and the second erase verification voltage Vev_coarse1 is greater than the first erase verification voltage Vev. In some specific embodiments, the voltage difference between the first erase verification voltage Vev and the second erase verification voltage Vev_coarse1 is within 0.5V, and the voltage difference between the second erase verification voltage Vev_coarse1 and the third erase verification voltage Vev_coarse2 is within 0.5V.

[0121] It should be noted that in some embodiments, a state dual strobesense verification method can also be used to simultaneously obtain the three verification results corresponding to the three erase verification voltages. That is, after applying the first erase verification voltage Vev, the verification results after applying the second erase verification voltage Vev_coarse1 and the third erase verification voltage Vev_coarse2 can be obtained at the same time.

[0122] Correspondingly, based on the different erase verification voltages, the results of the three erase verifications are also different; among them, the reference voltage... Figure 7 The first erase verification voltage Vev corresponds to the first erase verification result D1, the second erase verification voltage Vev_coarse1 corresponds to the second erase verification result D2, and the third erase verification voltage Vev_coarse2 corresponds to the third erase verification result D3. The results D1, D2, and D3 can all be used to characterize whether the selected memory block was successfully erased or the extent of erasure at the corresponding erase verification voltage.

[0123] Based on the above multiple erase verification voltages, the corresponding verification results can be categorized as follows: the first erase verification was successful, the first erase verification failed but the second erase verification was successful, the second erase verification failed but the third erase verification was successful, and the third erase verification failed. The voltage value of the second effective erase voltage varies depending on the different erase verification results. Specifically, the peripheral circuit is also configured as follows:

[0124] When the first erase verification fails and the second erase verification succeeds, the voltage value of the second effective erase voltage is determined to be increased by a first voltage increment compared to the voltage value of the first effective erase voltage.

[0125] When the second erase verification fails and the third erase verification succeeds, the voltage value of the second effective erase voltage is determined to be increased by a second voltage increment compared to the voltage value of the first effective erase voltage.

[0126] When the third erase verification fails, the voltage value of the second effective erase voltage is determined to be increased by a third voltage increment compared to the voltage value of the first effective erase voltage.

[0127] Among them, the third voltage increment is greater than the second voltage increment, and the second voltage increment is greater than the first voltage increment.

[0128] refer to Figure 7When the first erase verification result D1 fails, a second erase verification voltage Vev_coarse1 is applied to the selected memory block, and the second erase verification result D2 is obtained. When the second erase verification result D2 succeeds, that is, when the first erase verification result D1 fails and the second erase verification result D2 succeeds, the voltage value of the second effective erase voltage applied to the selected memory block is: the voltage value of the first effective erase voltage plus a first voltage increment; for example, the voltage value of the first effective erase voltage is Vera-init, and the first voltage increment is V... ISPE Then the second effective erase voltage is Vera_init + V ISPE In other embodiments, the first voltage increment V ISPE It can be a step voltage when performing an incremental step pulse erase (ISPE) operation.

[0129] If the second erase verification result D2 fails, a third erase verification voltage Vev_coarse2 is applied to the selected memory block, and the result D3 of the third erase verification is obtained. If the third erase verification result D3 succeeds, that is, if the second erase verification result D2 fails and the third erase verification result D3 succeeds, the voltage value of the second effective erase voltage applied to the selected memory block is: the voltage value of the first effective erase voltage plus a second voltage increment, where the second voltage increment is greater than the first voltage increment. For example, the voltage value of the first effective erase voltage is Vera-init, and the second voltage increment is V... ISPE +ΔV1, then the second effective erase voltage is Vera_init + V ISPE +ΔV1.

[0130] When the third erase verification result D3 fails, the voltage value of the second effective erase voltage applied to the selected memory block is: the voltage value of the first effective erase voltage plus a third voltage increment, where the third voltage increment is greater than the second voltage increment; for example, the voltage value of the first effective erase voltage is Vera-init, and the third voltage increment is V. ISPE +ΔV2, where ΔV2 is greater than ΔV1, then the second effective erase voltage is: Vera_init + V ISPE +ΔV2. In this way, based on different erase verification results, different erase degrees of multiple memory blocks can be determined. For different erase degrees of memory blocks, different second effective erase voltages are applied to them, so that the erase degree of multiple memory blocks tends to be consistent after applying different second effective erase voltages, and the erase speed tends to be consistent. This makes the threshold voltage distribution of the erase state among different memory blocks tend to be uniform and consistent, thereby improving the read performance and erase performance of the memory device.

[0131] It should be noted that when the first erase verification result D1 is successful, it indicates that the erase operation has been completed, and there is no need to perform subsequent erase verification operations at this time.

[0132] To further understand this solution, the following will be combined with... Figure 8 a, Figure 8 b、 Figure 9 The specific operation of applying different second effective erase voltages to memory blocks is described in detail. It should be understood that applying different second effective erase voltages can be done at different times on the same memory block, separately on different memory blocks within the same memory surface, or separately on multiple memory blocks stored in different memory surfaces. However, regardless of whether different second effective erase voltages are applied to the same memory block at different times, or different second effective erase voltages are applied to multiple memory blocks separately, the voltage value of the second effective erase voltage can be adjusted / changed by changing the preset duration. Specifically:

[0133] In some embodiments, a pulse corresponding to a first erase voltage is applied to the source line of the selected memory block. During the process of the voltage of the source line rising to the first erase voltage, a first voltage is applied to the source select gate of the selected memory block, and the source select gate is floated after a preset time. During the process of the voltage of the source line stabilizing at the first erase voltage, the voltage of the source select gate stabilizes at a second voltage, the second voltage being less than the first erase voltage, and the difference between the first erase voltage and the second voltage constituting the second effective erase voltage. The longer the preset time, the greater the voltage value of the second effective erase voltage.

[0134] Here, the initial voltage on the source line SL of the selected memory block and the corresponding source select gate BSG is a first voltage (such as ground voltage Vss). At the first moment, a first erase voltage Vers is applied to the source line SL of the selected memory block. After a period of time, the voltage of the source line SL reaches the first erase voltage Vers and stabilizes at the first erase voltage Vers.

[0135] During the process of the voltage of the source line SL of the selected memory block rising from the ground voltage Vss to the first erase voltage Vers, after a preset time, the source select gate BSG of the selected memory block is changed from being applied with the first voltage (such as the ground voltage Vss) to being floating. Here, the preset time can be set according to actual needs. When the voltage of the source line SL of the selected memory block reaches the first erase voltage Vers, the voltage of the source select gate BSG in the corresponding memory block will stabilize at a second voltage (Vers-V) due to coupling. The second voltage is also called the hold and release (H&R) voltage. It should be noted that the selected memory block may have multiple source select gates BSG, such as the first source select gate BSG0_0, the second source select gate BSG0_1, etc. When there are multiple source select gates BSG in the memory block, after the preset time, the corresponding voltage will be applied to each of the multiple source select gates BSG.

[0136] It should be understood that the voltage difference between the source line SL and the corresponding source select gate BSG of the selected memory block is the second effective erase voltage. When the first erase voltage on the source line SL of the selected memory block remains constant, the longer the preset duration, the longer the voltage of the source select gate BSG in the memory block is forced to remain at the first voltage. This results in a shorter coupling time on the source line SL, a smaller final stable second voltage on the corresponding source select gate BSG, and a larger value for the second effective erase voltage. Therefore, based on the results of different erase verifications, the voltage value of the second effective erase voltage can be adjusted / changed by changing the preset duration, making the erase degree of multiple memory blocks tend to be consistent.

[0137] For example, when the result of the first erase verification fails and the result of the second erase verification succeeds, the preset duration is determined to be the first duration;

[0138] When the result of the second erase verification fails and the result of the third erase verification succeeds, the preset duration is determined to be the second duration.

[0139] When the third erasure verification fails, the preset duration is set to the third duration.

[0140] Wherein, the first duration is less than the second duration, and the second duration is less than the third duration.

[0141] In this embodiment of the disclosure, when the first erase verification fails and the second erase verification succeeds, it indicates that the selected storage block has a relatively deep erase degree, that is, a small number of storage cells in the selected storage block have not been erased (first corresponding degree). At this time, the voltage value of the second effective erase voltage can be increased by a first voltage increment V compared with the voltage value of the first effective erase voltage by controlling a preset time (e.g., setting the preset time to the first time). ISPE .

[0142] When the second erase verification fails and the third erase verification succeeds, it indicates that the current erase level of the selected memory block is shallower than the first level, meaning that a certain number of memory cells in the selected memory block have not been erased (second level). At this time, the voltage value of the second effective erase voltage can be increased by a second voltage increment V compared to the voltage value of the first effective erase voltage by controlling the preset duration (e.g., setting the preset duration to the second duration). ISPE +ΔV1.

[0143] When the third erase verification fails, it indicates that the current erase level of the selected memory block is relatively shallow compared to the second level, meaning that a large number of memory cells in the selected memory block have not been erased (third level). In this case, the voltage value of the second effective erase voltage can be increased by a third voltage increment V compared to the voltage value of the first effective erase voltage by controlling the preset duration (e.g., setting the preset duration to the third duration). ISPE +ΔV2.

[0144] In other words, the degree of erasure of the storage block represented by the first, second, and third degree of erasure gradually becomes shallower, and the corresponding preset durations, such as the first duration, the second duration, and the third duration, gradually increase.

[0145] In other embodiments, reference is made to Figure 8 a. The selected memory blocks include multiple memory blocks; and the selected multiple memory blocks are stored in different memory surfaces; here, applying different second effective erase voltages to the selected multiple memory blocks is equivalent to applying different second effective erase voltages to the selected multiple memory surfaces; the peripheral circuit is configured to simultaneously apply pulses corresponding to the first erase voltage to the source line of each of the selected multiple memory blocks.

[0146] It should be noted that after applying multiple different erase verification voltages to multiple memory blocks in multiple memory planes, the degree of erasure may be the same or different. Specifically, when the degree of erasure of selected memory blocks in multiple memory planes is the same, the reference... Figure 9 The preset duration is the same, t', and the applied second effective erase voltage is the same (v0). When the erase degree of the selected memory blocks in multiple memory planes is different, refer to... Figure 8 a, Figure 8 b. The second effective erase voltage applied will also be different depending on the preset duration (e.g., t1, t2, t3 or t4, t5, t6). To better understand this disclosure, the following embodiments will be illustrated using the example of different erase degrees of multiple memory blocks.

[0147] refer to Figure 8 a. The initial voltage on the source line SL and the corresponding source select gate BSG of each of the selected multiple memory blocks is a first voltage (such as ground voltage Vss). At the first moment (such as t0), the first erase voltage Vers is simultaneously applied to the source line SL of each of the selected multiple memory blocks. After a period of time, the voltage of the multiple source lines SL reaches the first erase voltage Vers and stabilizes at the first erase voltage Vers.

[0148] During the process of the voltage of the source line SL of each selected memory block rising from ground voltage Vss to the first erase voltage Vers, after a preset time, the source select gate BSG of each selected memory block changes from being applied with the first voltage to being floating; here, the preset time can be set according to actual needs. When the voltage of the source line SL of each selected memory block reaches the first erase voltage Vers, the voltage of the source select gate BSG in the corresponding memory block will stabilize at a second voltage (Vers-v*) due to coupling; v* corresponds to different memory blocks.

[0149] Continue to refer to Figure 8 a. Multiple selected memory blocks are stored in the first memory surface (p10), the second memory surface (p11), and the third memory surface (p12), respectively. The erasure degree of the selected memory blocks gradually decreases. After maintaining the first voltage on the source select gate (BSG) for different durations and floating at different times, the second voltages on the source select gates (bsg-p10, bsg-p1, bsg-p2) corresponding to the multiple memory blocks are Vers-v0, Vers-v1, and Vers-v2, respectively. Here, the second voltage on the source select gate (BSG) of the memory blocks corresponding to the first to the third memory surface gradually decreases, such as Vers-v0 > Vers-v1 > Vers-v2. Figure 8(This situation is illustrated in a). In other embodiments, when the erase depth of the selected multiple memory blocks gradually increases sequentially, the second voltage on the source selection gate BSG corresponding to different memory surfaces can also be gradually increased sequentially by adjusting the floating time of the source selection gate BSG, such as Vers-v0 < Vers-v1 < Vers-v2. Other setting methods can also be selected according to actual needs, which will not be elaborated here. When the voltage of the source line SL of each of the selected multiple memory blocks is stable at the first erase voltage, the second effective erase voltages applied to the selected multiple memory blocks are v0, v1, and v2, respectively; wherein, the magnitude relationship of v0, v1, and v2 is related to the second voltage (H&R) on the corresponding source selection gate BSG. Here, the smaller the erase depth of the memory block (the shallower), the larger the second voltage (Vers-v*), and the smaller the corresponding second effective erase voltage (v*).

[0150] Based on this, when performing an erase operation on multiple selected memory blocks in multiple memory planes, the second voltage (hold release voltage) of the source selection gate can be changed by changing the preset duration, so as to apply different second effective erase voltages to the selected memory blocks in different memory planes.

[0151] refer to Figure 8 a) When the first erase verification fails but the second erase verification succeeds, it indicates that the currently selected memory block has been erased to a relatively deep degree. The second effective erase voltage v0 can be determined by setting the preset duration to t1 and obtaining the second voltage Vers-v0. Conversely, when the second erase verification fails but the third erase verification succeeds, it indicates that the currently selected memory block has been erased to a relatively shallow degree. The second effective erase voltage v1 can be determined by setting the preset duration to t2 and obtaining the second voltage Vers-v1.

[0152] When the third erase verification fails, it indicates that the erase level of the currently selected memory block is very shallow. The second effective erase voltage v2 can be determined by setting the preset duration to t3 and obtaining the second voltage Vers-v2. Here, t1 < t2 < t3.

[0153] In other words, in this embodiment of the present disclosure, each storage surface can be controlled individually, and different second voltages (H&R voltages) can be applied to the storage blocks in each storage surface individually, so as to apply different second effective erase voltages to different storage blocks in different storage surfaces. In this way, the second effective erase voltage can be flexibly adjusted / changed according to the different degrees of erasure, reducing the difference in threshold voltage distribution of erase state L0 between storage blocks and improving the read performance and erase performance of the memory device.

[0154] In other embodiments, reference is made to Figure 8b) The selected memory blocks are different memory blocks in the same memory plane (e.g., block-a, block-b, block-c). After the first voltage on the source select gate (BSG) is maintained for different durations and then floated at different times, the second voltages on the BSG corresponding to the memory blocks are Vers-va, Vers-vb, and Vers-vc, respectively. As the erase degree of block-a, block-b, and block-c gradually becomes shallower, the preset durations corresponding to different times gradually increase, such as t4 < t5 < t6, and the corresponding second voltages gradually decrease, such as Vers-va > Vers-vb > Vers-vc; the corresponding second effective erase voltages gradually increase, such as va > vb > vc. Thus, the second effective erase voltage applied to the memory blocks can be adjusted / changed by controlling the preset duration.

[0155] Additionally, it should be noted that after a selected memory block completes an erase cycle, all source lines SL and source select gate BSG are restored to the first voltage (ground voltage, Vss).

[0156] In this embodiment of the disclosure, an example is provided of applying different second effective erase voltages to different memory blocks when using another erase method, that is, changing the second effective erase voltage of the corresponding memory block by changing the voltage difference between the source line SL of the selected memory block and all word lines WL.

[0157] In some embodiments, the memory block includes a drain terminal and a source terminal, the source terminal being provided with a source line; the memory block includes multiple word lines located between the drain terminal and the source terminal;

[0158] The peripheral circuit is further configured to: apply a second erase voltage to the source line of the selected memory block and apply a first voltage to all word lines of the selected memory block, wherein the difference between the second erase voltage and the first voltage constitutes the second effective erase voltage; wherein, when the first voltage is fixed, the larger the voltage value of the second erase voltage, the larger the voltage value of the second effective erase voltage.

[0159] For example, the voltage applied to the source line SL of each of the selected memory blocks is the second erase voltage, and the voltage applied to all word lines WL of the selected memory blocks is the first voltage. The difference between the second erase voltage and the first voltage constitutes the second effective erase voltage. When the first voltage remains constant, the second erase voltage is directly proportional to the value of the second effective erase voltage; for example, the larger the value of the second erase voltage, the larger the value of the second effective erase voltage. Thus, by changing the second erase voltage, different second effective erase voltages can be applied to different memory blocks.

[0160] In some embodiments, the peripheral circuitry is further configured to perform an erase operation on the selected memory block by repeatedly applying an increasingly larger effective erase voltage;

[0161] After each effective erase voltage is applied in the preset sequence, the third erase verification voltage is directly applied to the selected memory block, and the effective erase voltage to be applied to the selected memory block next is determined based on the erase verification result corresponding to the third erase verification voltage.

[0162] After applying an effective erase voltage more than the preset number of times, the selected memory block is subjected to the multiple different erase verification voltages, and the next effective erase voltage applied to the selected memory block is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages.

[0163] Here, during the erasure process using Incremental Step Pulse Erasure (ISPE), an erasure process may include multiple erasure cycles. In the first few erasure cycles (i.e., the preset number of erasure cycles), there may not be a situation where the first erasure verification result is successful after applying the first erasure verification voltage. Therefore, in the first few erasure cycles, the third erasure verification voltage is directly applied to the selected memory block, and the result of the third erasure verification is judged. The preset number of cycles can be estimated based on historical experience; here, the preset number of cycles is the critical number of times the third erasure verification result changes from failure to success.

[0164] If the third erase verification is successful in the current erase cycles, then in each subsequent erase cycle (i.e., beyond a preset number of cycles), after applying the first valid erase voltage to the selected memory block, multiple different erase verification voltages are applied. Based on the results of these multiple erase verifications corresponding to these different erase verification voltages, the second valid erase voltage to be applied to the selected memory block next is determined. This saves time in the erase verification operation and improves its efficiency.

[0165] As previously mentioned, in embodiments of this disclosure, an erase process may include multiple erase cycles. Each erase cycle includes an erase operation and three erase verification operations. Specifically, when the result of the first erase verification, D1, fails, a second erase verification voltage, Vev_coarse1, is applied to the selected storage block, and the result of the second erase verification, D2, is obtained. When the result of the second erase verification, D2, fails, a third erase verification voltage, Vev_coarse2, is applied to the selected storage block, and the result of the third erase verification, D3, is obtained. In another embodiment of this disclosure, in the first few erase cycles of the multiple erase cycles, the third erase verification can be performed directly on the storage cell. That is, after applying the first effective erase voltage to the selected storage block, the third erase verification voltage, Vev_coarse2, is applied directly to the selected storage block, and the result of the third erase verification is judged.

[0166] In the verification results, if no memory cell threshold voltage is lower than the third erase verification voltage Vev_coarse2, it indicates that the threshold voltage of all memory cells will not fall below the second erase verification voltage Vev_coarse1. In this case, the next erase cycle is directly entered. If a memory cell threshold voltage is lower than the third erase verification voltage Vev_coarse2, the second erase verification voltage Vev_coarse1 is used for verification. If no memory cell threshold voltage is lower than the second erase verification voltage Vev_coarse1, the next erase cycle is entered. If a memory cell threshold voltage is lower than the second erase verification voltage Vev_coarse1, the first erase verification voltage Vev is used for verification. Then, the next erase cycle is entered according to the verification results. After that, verification can start from the first erase verification voltage Vev each time. In this way, the initial verification time can be reduced, thereby reducing the erasure time.

[0167] Based on this, in this embodiment of the present disclosure, after applying a first effective erase voltage to each selected memory block among multiple memory blocks, the degree of erasure of each memory block is determined by applying multiple different erase verification voltages to the multiple memory blocks respectively, and different second effective erase voltages are applied to the multiple memory blocks according to their different degrees of erasure, so that the degree of erasure of the multiple memory blocks after applying different second effective erase voltages tends to be consistent, and the erasure speed also tends to be consistent, thereby making the threshold voltage distribution of the erasure state among different memory blocks tend to be uniform and consistent, thereby improving the read performance and erase performance of the memory device.

[0168] Furthermore, this disclosure also provides a comparative example of the threshold voltage distribution of the erase state after the storage block is erased using two different erase methods under different storage states. The first erase method, as described in the above embodiments of this disclosure, involves each erase cycle including one erase operation and three erase verification operations; the second erase method is a related art method where each erase cycle includes one erase operation and one erase verification operation.

[0169] Referring to Figures 10 and 11, Figure 10 shows the threshold voltage distribution of the erase state of the storage block after the first erase method (P1) and the second erase method (P2) are applied when no data is stored in some of its storage cells. Figure 11 shows the threshold voltage distribution of the erase state of the storage block after the first erase method (P3) and the second erase method (P4) are applied when all of its storage cells are stored.

[0170] Combination Figure 6 As shown in Figure 10, when there are memory cells in the memory block that have not yet been filled with data, after applying the second effective erase voltage to the selected memory block using the first erase method, the threshold voltage range of the erase state L0 of the memory block between +3σ and -3σ decreases, that is, the read window margin E0 of the erase state L0 increases. Combined with... Figure 6 As shown in Figure 11, when all memory cells in the memory block are filled with data, after applying the second effective erase voltage to the selected memory block using the first erase method, the threshold voltage range of the erase state L0 of the memory block between +3σ and -3σ decreases, meaning the read window margin E0 of the erase state L0 increases. In other words, regardless of whether there are memory cells in the memory block that have not been filled with data, applying the second effective erase voltage to the selected memory block using the first erase method can increase the read window margin of the erase state of the memory block, thereby improving the read performance of the memory block and the memory device.

[0171] On the other hand, embodiments of this disclosure also provide an operation method for a memory device, the operation method comprising: applying a first effective erase voltage to a selected memory block of the memory device, and then applying multiple different erase verification voltages to the selected memory block;

[0172] Based on the results of multiple erase verifications corresponding to the multiple different erase verification voltages, a second effective erase voltage is determined on the selected storage block, wherein the second effective erase voltage is greater than the first effective erase voltage.

[0173] In some embodiments, the multiple different erase verification voltages include three different erase verification voltages, and the result of the multiple erase verifications includes the result of the three erase verifications.

[0174] In some embodiments, the three different erase verification voltages include: a first erase verification voltage, a second erase verification voltage, and a third erase verification voltage with sequentially increasing voltage values; the first erase verification voltage, the second erase verification voltage, and the third erase verification voltage correspond to the results of the first erase verification, the second erase verification, and the third erase verification, respectively; the method further includes:

[0175] When the result of the first erase verification fails and the result of the second erase verification succeeds, it is determined that the voltage value of the second effective erase voltage is increased by a first voltage increment compared to the voltage value of the first effective erase voltage.

[0176] When the result of the second erase verification fails and the result of the third erase verification succeeds, it is determined that the voltage value of the second effective erase voltage is increased by a second voltage increment compared to the voltage value of the first effective erase voltage.

[0177] When the result of the third erase verification fails, it is determined that the voltage value of the second effective erase voltage is increased by a third voltage increment compared to the voltage value of the first effective erase voltage.

[0178] Wherein, the third voltage increment is greater than the second voltage increment, and the second voltage increment is greater than the first voltage increment.

[0179] In some embodiments, the memory block includes a drain terminal and a source terminal, the source terminal being provided with a source line and a source select gate; the method further includes:

[0180] A pulse corresponding to a first erase voltage is applied to the source line of the selected memory block. During the process of the voltage of the source line rising to the first erase voltage, a first voltage is applied to the source select gate of the selected memory block and the source select gate is floated after a preset time. During the process of the voltage of the source line stabilizing at the first erase voltage, the voltage of the source select gate stabilizes at a second voltage. The second voltage is less than the first erase voltage, and the difference between the first erase voltage and the second voltage constitutes the second effective erase voltage.

[0181] The longer the preset duration, the greater the voltage value of the second effective erasure voltage.

[0182] In some embodiments, the method further includes:

[0183] When the first erase verification fails and the second erase verification succeeds, the preset duration is determined to be the first duration.

[0184] When the result of the second erase verification fails and the result of the third erase verification succeeds, the preset duration is determined to be the second duration.

[0185] When the third erasure verification fails, the preset duration is set to the third duration.

[0186] Wherein, the first duration is less than the second duration, and the second duration is less than the third duration.

[0187] In some embodiments, the memory block includes a drain terminal and a source terminal, the source terminal being provided with a source line; the memory block includes multiple word lines located between the drain terminal and the source terminal; the method further includes:

[0188] A second erase voltage is applied to the source line of the selected memory block, and a first voltage is applied to all word lines of the selected memory block. The difference between the second erase voltage and the first voltage constitutes the second effective erase voltage.

[0189] The larger the value of the second erase voltage, the larger the value of the second effective erase voltage.

[0190] In some embodiments, the method further includes: performing an erase operation on the selected memory block by repeatedly applying an increasingly larger effective erase voltage;

[0191] After each effective erase voltage is applied in the preset sequence, the third erase verification voltage is directly applied to the selected memory block, and the effective erase voltage to be applied to the selected memory block next is determined based on the erase verification result corresponding to the third erase verification voltage.

[0192] After applying an effective erase voltage more than the preset number of times, the selected memory block is subjected to the multiple different erase verification voltages, and the next effective erase voltage applied to the selected memory block is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages.

[0193] Furthermore, this disclosure also discloses a memory system; wherein the memory system includes a memory controller and the memory device described in the above embodiments of this disclosure. The memory controller is used to control the memory device to perform read, write, and erase operations. Here, the memory controller and the memory device can be coupled in any suitable manner. In this disclosure, the memory device can be a non-volatile semiconductor memory for storing data, such as a NAND flash memory. The memory system is connected to a host, which can be an electronic device such as a personal computer or a mobile terminal.

[0194] In some embodiments, the memory system includes a Universal Flash Storage (UFS) device or a solid-state drive.

[0195] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0196] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0197] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory device, comprising: A storage cell array, the storage cell array comprising multiple storage blocks; as well as The peripheral circuitry, coupled to the memory cell array, is configured as follows: After applying a first effective erase voltage to a selected memory block among the plurality of memory blocks, multiple different erase verification voltages are applied to the selected memory block. Based on the results of multiple erase verifications corresponding to the multiple different erase verification voltages, a preset duration is selected from multiple preset durations, and a second effective erase voltage is applied to the selected storage block based on the selected preset duration. The second effective erase voltage is greater than the first effective erase voltage.

2. The memory device according to claim 1, wherein, The multiple different erase verification voltages include three different erase verification voltages, and the results of the multiple erase verifications include the results of the three erase verifications.

3. The memory device according to claim 2, wherein, The three different erase verification voltages include: a first erase verification voltage, a second erase verification voltage, and a third erase verification voltage with successively increasing voltage values; the first erase verification voltage, the second erase verification voltage, and the third erase verification voltage correspond to the results of the first erase verification, the second erase verification, and the third erase verification, respectively; The peripheral circuit is also configured to: When the result of the first erase verification fails and the result of the second erase verification succeeds, it is determined that the voltage value of the second effective erase voltage is increased by a first voltage increment compared to the voltage value of the first effective erase voltage. When the result of the second erase verification fails and the result of the third erase verification succeeds, it is determined that the voltage value of the second effective erase voltage is increased by a second voltage increment compared to the voltage value of the first effective erase voltage. When the result of the third erase verification fails, it is determined that the voltage value of the second effective erase voltage is increased by a third voltage increment compared to the voltage value of the first effective erase voltage. Wherein, the third voltage increment is greater than the second voltage increment, and the second voltage increment is greater than the first voltage increment.

4. The memory device according to claim 3, wherein, The memory block includes a drain terminal and a source terminal, and the source terminal is provided with a source line and a source selection gate. The peripheral circuit is also configured to: A pulse corresponding to a first erase voltage is applied to the source line of the selected memory block. During the process of the voltage of the source line rising to the first erase voltage, a first voltage is applied to the source select gate of the selected memory block and the source select gate is floated after a preset time. During the process of the voltage of the source line stabilizing at the first erase voltage, the voltage of the source select gate stabilizes at a second voltage. The second voltage is less than the first erase voltage, and the difference between the first erase voltage and the second voltage constitutes the second effective erase voltage. The longer the preset duration, the greater the voltage value of the second effective erasure voltage.

5. The memory device according to claim 4, wherein, The peripheral circuit is also configured to: When the first erase verification fails and the second erase verification succeeds, the preset duration is determined to be the first duration. When the result of the second erase verification fails and the result of the third erase verification succeeds, the preset duration is determined to be the second duration. When the third erasure verification fails, the preset duration is set to the third duration. Wherein, the first duration is less than the second duration, and the second duration is less than the third duration.

6. The memory device according to claim 4, wherein, The selected storage block includes multiple storage blocks; The peripheral circuit is configured as follows: A pulse corresponding to the first erase voltage is simultaneously applied to the source line of each of the selected plurality of memory blocks.

7. The memory device according to claim 6, wherein, The storage cell array includes multiple storage surfaces; the selected multiple storage blocks are stored in different storage surfaces. The peripheral circuit is also configured to: When performing an erase operation on multiple selected memory blocks in multiple memory planes, different second effective erase voltages are applied to the selected memory blocks in different memory planes by changing the preset duration.

8. The memory device according to claim 3, wherein, The memory block includes a drain terminal and a source terminal, and the source terminal is provided with a source line; the memory block includes multiple word lines located between the drain terminal and the source terminal; The peripheral circuit is also configured to: A second erase voltage is applied to the source line of the selected memory block, and a first voltage is applied to all word lines of the selected memory block. The difference between the second erase voltage and the first voltage constitutes the second effective erase voltage. The larger the value of the second erase voltage, the larger the value of the second effective erase voltage.

9. The memory device according to claim 4 or 8, wherein, The first voltage is the ground voltage.

10. The memory device according to claim 3, wherein, The peripheral circuit is also configured to: The selected memory block is erased by applying gradually increasing effective erase voltages multiple times. After each effective erase voltage is applied in the preset sequence, the third erase verification voltage is directly applied to the selected memory block, and the effective erase voltage to be applied to the selected memory block next is determined based on the erase verification result corresponding to the third erase verification voltage. After applying an effective erase voltage more than the preset number of times, the selected memory block is subjected to the multiple different erase verification voltages, and the next effective erase voltage applied to the selected memory block is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages.

11. The memory device according to claim 3, wherein, The peripheral circuit is also configured to: When the first erase verification fails, the second erase verification voltage is applied to the selected storage block; When the second erase verification fails, the third erase verification voltage is applied to the selected storage block.

12. The memory device according to claim 3, wherein, The first voltage is increased by a step voltage.

13. A memory system, comprising: One or more memory devices as described in any one of claims 1 to 12; as well as A memory controller, which is coupled to and controls the memory device.

14. A method of operating a memory device, the method comprising: After applying a first effective erase voltage to a selected memory block of the memory device, multiple different erase verification voltages are applied to the selected memory block. Based on the results of multiple erase verifications corresponding to the multiple different erase verification voltages, a preset duration is selected from multiple preset durations, and a second effective erase voltage is applied to the selected storage block based on the selected preset duration. The second effective erase voltage is greater than the first effective erase voltage.

15. The operating method according to claim 14, wherein, The multiple different erase verification voltages include three different erase verification voltages, and the results of the multiple erase verifications include the results of the three erase verifications.

16. The operating method according to claim 15, wherein, The three different erase verification voltages include: a first erase verification voltage, a second erase verification voltage, and a third erase verification voltage with sequentially increasing voltage values; the first erase verification voltage, the second erase verification voltage, and the third erase verification voltage correspond to the results of the first erase verification, the second erase verification, and the third erase verification, respectively; the method further includes: When the result of the first erase verification fails and the result of the second erase verification succeeds, it is determined that the voltage value of the second effective erase voltage is increased by a first voltage increment compared to the voltage value of the first effective erase voltage. When the result of the second erase verification fails and the result of the third erase verification succeeds, it is determined that the voltage value of the second effective erase voltage is increased by a second voltage increment compared to the voltage value of the first effective erase voltage. When the result of the third erase verification fails, it is determined that the voltage value of the second effective erase voltage is increased by a third voltage increment compared to the voltage value of the first effective erase voltage. Wherein, the third voltage increment is greater than the second voltage increment, and the second voltage increment is greater than the first voltage increment.

17. The operating method according to claim 16, wherein, The memory block includes a drain terminal and a source terminal, and the source terminal is provided with a source line and a source selection gate. The method further includes: A pulse corresponding to a first erase voltage is applied to the source line of the selected memory block. During the process of the voltage of the source line rising to the first erase voltage, a first voltage is applied to the source select gate of the selected memory block and the source select gate is floated after a preset time. During the process of the voltage of the source line stabilizing at the first erase voltage, the voltage of the source select gate stabilizes at a second voltage. The second voltage is less than the first erase voltage, and the difference between the first erase voltage and the second voltage constitutes the second effective erase voltage. The longer the preset duration, the greater the voltage value of the second effective erasure voltage.

18. The operating method according to claim 17, wherein, The method further includes: When the first erase verification fails and the second erase verification succeeds, the preset duration is determined to be the first duration. When the result of the second erase verification fails and the result of the third erase verification succeeds, the preset duration is determined to be the second duration. When the third erasure verification fails, the preset duration is set to the third duration. Wherein, the first duration is less than the second duration, and the second duration is less than the third duration.

19. The operating method according to claim 16, wherein, The memory block includes a drain terminal and a source terminal, and the source terminal is provided with a source line; the memory block includes multiple word lines located between the drain terminal and the source terminal; The method further includes: A second erase voltage is applied to the source line of the selected memory block, and a first voltage is applied to all word lines of the selected memory block. The difference between the second erase voltage and the first voltage constitutes the second effective erase voltage. The larger the value of the second erase voltage, the larger the value of the second effective erase voltage.

20. The operating method according to claim 16, wherein, The method further includes: The selected memory block is erased by applying gradually increasing effective erase voltages multiple times. After each effective erase voltage is applied in the preset sequence, the third erase verification voltage is directly applied to the selected memory block, and the effective erase voltage to be applied to the selected memory block next is determined based on the erase verification result corresponding to the third erase verification voltage. After applying an effective erase voltage more than the preset number of times, the selected memory block is subjected to the multiple different erase verification voltages, and the next effective erase voltage applied to the selected memory block is determined based on the results of the multiple erase verifications corresponding to the multiple different erase verification voltages.

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