Power conversion device, method for controlling power conversion device, semiconductor device, and method for controlling semiconductor device

Abstract

A power conversion device for converting power using a semiconductor device is characterized by being provided with: a MOS control diode (1) having an n + layer (11), an n-layer (12), a p-layer (13), a p + layer (14), a cathode electrode (21), anode electrodes (22, 220), and a gate electrode (23); and a voltage applying means that applies a forward voltage between the anode electrodes (22, 220) and the cathode electrode (21) during the forward direction, applies a reverse voltage between the anode electrodes (22, 220) and the cathode electrode (21) during the reverse recovery, and before the reverse recovery, sets the potential of the gate electrode (23) to a potential at which an inversion layer is formed in the third semiconductor layer with respect to the potential of the anode electrodes (22, 220). Thus, provided are a power conversion device, a method for controlling the power conversion device, a semiconductor device, and a method for controlling the semiconductor device, which are capable of further reducing power loss.

Description

Technical Field

[0001] The present invention relates to a power conversion device, a control method for a power conversion device, a semiconductor device, and a control method for a semiconductor device, and particularly to a power conversion device suitable for switching control of a large current. Background Art

[0002] At present, power conversion devices such as inverters and converters are widely used in household appliances such as air conditioners, refrigerators, and electromagnetic cookers, as well as high-voltage and high-power equipment such as electric vehicles, uninterruptible power supplies, solar power generation, and wind power generation, industrial and automotive equipment, railways, construction machinery, steel, and power systems. Power conversion devices are equipment required to achieve energy conservation and new energy, and are key components for achieving a decarbonized society. Therefore, it is necessary to make power conversion devices widely popular, but it is expected to be low-cost and small so that they can be installed anywhere.

[0003] In recent years, power semiconductors using Si, which is a cheap raw material and can fully utilize the huge assets cultivated in LSI, and the control of power conversion devices have been integrated, and research on control has been carried out, which has promoted the development of technology that exceeds the low loss limit of IGBT and pn diodes in the past. In the freewheeling diode, which is a main component of the power conversion device, a MOS (Metal Oxide Semiconductor) gate is newly added to the conventional pn diode, and its gate is controlled to be a low-loss MOS control diode.

[0004] Patent document 1 describes a semiconductor device. In the semiconductor device, the semiconductor substrate side of the gate electrode provided on the surface of the anode electrode 22 side of the semiconductor substrate composed of silicon is surrounded by a p-layer, an n-layer, and a p-layer via a gate insulating film. In addition, the anode electrode contacts the p-layer with low resistance, and also contacts the n-layer or the p-layer, and a Schottky diode is formed between the anode electrode and the n-layer or the p-layer.

[0005] Non-Patent Document 1 describes a MOS controlled diode in which a MOS (Metal Oxide Semiconductor) gate is newly added to a conventional pn diode and the gate is controlled to be a low-loss MOS controlled diode.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2019-149511

[0009] Non-patent document 1: ISPSD (International Symposium on Power Semiconductor or Devices & IC's), 2008, p. 40-43 Summary of the invention

[0010] Problem that the invention aims to solve

[0011] Power conversion devices generate power loss when controlling high voltage and high current power. Therefore, cooling devices and the like tend to be large-scale and costly. Therefore, how to reduce power loss has become an important issue in popularizing and expanding power conversion devices.

[0012] So far, the reduction of power loss in power conversion devices has been mainly improved by reducing the loss of the power semiconductors used in them. However, the low loss of IGBTs (Insulated Gate Bipolar Transistors) and pn diodes for freewheeling diodes, which are currently the mainstream power semiconductors and use silicon (Si), is reaching its limit. There are power conversion devices equipped with MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and Schottky diodes that use silicon carbide (SiC) with less loss than Si, but the price of SiC material itself is high. Therefore, there has been no progress in the formal popularization of a wide range of power conversion devices required for a decarbonized society.

[0013] An object of the present invention is to provide a power conversion device, a control method for a power conversion device, a semiconductor device, and a control method for a semiconductor device, which can further reduce power loss.

[0014] Solutions to the problem

[0015] In order to solve the above-mentioned problems, the present invention provides a power conversion device, which uses a semiconductor device to convert power, characterized in that the power conversion device includes a semiconductor device and a voltage applying component, and the semiconductor device has: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is arranged on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductivity type, which is arranged on one surface side of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is arranged in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer; a cathode electrode, which is arranged on the first semiconductor layer another surface side; an anode electrode, which is arranged on one surface side of the third semiconductor layer and has a protrusion in contact with the fourth semiconductor layer; and a gate electrode, which is arranged with the protrusion sandwiched in a direction intersecting with the direction in which the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are stacked, and is in contact with the third semiconductor layer via a gate insulating film, wherein the voltage applying component applies a forward voltage between the anode electrode and the cathode electrode in the forward direction, and applies a reverse voltage between the anode electrode and the cathode electrode in the reverse recovery, so that the potential of the gate electrode becomes a potential that forms an inversion layer in the third semiconductor layer relative to the potential of the anode electrode before the reverse recovery.

[0016] In addition, the present invention provides a control method for a power conversion device, which is a control method for a power conversion device when the power conversion device using a semiconductor device to convert power is operated, characterized in that the power conversion device is operated by controlling the semiconductor device, and the semiconductor device has: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is arranged on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductivity type, which is arranged on one surface side of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is arranged in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer; a cathode electrode , which is arranged on the other surface side of the first semiconductor layer; an anode electrode, which is arranged on one surface side of the third semiconductor layer and has a protrusion in contact with the fourth semiconductor layer; and a gate electrode, which is arranged with the protrusion sandwiched in a direction intersecting with the direction in which the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are stacked, and is in contact with the third semiconductor layer via a gate insulating film, and the control is that in the forward direction, a forward voltage is applied between the anode electrode and the cathode electrode, and, in the reverse recovery, a reverse voltage is applied between the anode electrode and the cathode electrode, and before the reverse recovery, the potential of the gate electrode is made to be a potential that forms an inversion layer in the third semiconductor layer relative to the potential of the anode electrode.

[0017] Furthermore, the present invention provides a semiconductor device, characterized in that the semiconductor device comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is arranged on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductivity type, which is arranged on one surface side of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is arranged in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer; a cathode electrode, which is arranged on the other surface side of the first semiconductor layer; an anode electrode, which is arranged on one surface side of the third semiconductor layer and has a protrusion in contact with the fourth semiconductor layer; and a gate electrode, which is arranged with the protrusion sandwiched in a direction intersecting with the direction in which the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are stacked, and is in contact with the third semiconductor layer via a gate insulating film.

[0018] In addition, further, the present invention provides a semiconductor device, characterized in that the semiconductor device comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is arranged on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductivity type, which is arranged on one surface side of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is arranged in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer; a cathode electrode, which is arranged on the other surface side of the first semiconductor layer; an anode electrode, which is arranged on one surface side of the third semiconductor layer and is in contact with the fourth semiconductor layer; and a gate electrode, which is arranged adjacent to the anode electrode and the fourth semiconductor layer.

[0019] In addition, further, the present invention provides a control method for a semiconductor device, characterized in that the semiconductor device is controlled, and the semiconductor device comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is arranged on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductivity type, which is arranged on one surface side of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is arranged in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer; a cathode electrode, which is arranged on the other surface side of the first semiconductor layer; an anode electrode, An electrode, which is arranged on one surface side of the third semiconductor layer and has a protrusion in contact with the fourth semiconductor layer; and a gate electrode, which is arranged with the protrusion sandwiched in a direction intersecting with the direction in which the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are stacked, and is in contact with the third semiconductor layer via a gate insulating film, and is controlled by applying a forward voltage between the anode electrode and the cathode electrode in the forward direction, and applying a reverse voltage between the anode electrode and the cathode electrode in the reverse recovery, so that the potential of the gate electrode becomes a potential that forms an inversion layer in the third semiconductor layer relative to the potential of the anode electrode before the reverse recovery.

[0020] Effects of the Invention

[0021] According to the present invention, it is possible to provide a power conversion device, a control method for a power conversion device, a semiconductor device, and a control method for a semiconductor device that can further reduce power loss compared to a case where this configuration is not adopted. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a diagram showing an example of a cross-sectional structure of a MOS control diode mounted in the power conversion device according to the first embodiment of the present invention.

[0023] Figure 2 (a) is represented by a newly created symbol Figure 1 Figure 2 is an example of an equivalent circuit of a MOS controlled diode. Figure 2 (b) is a diagram showing an equivalent circuit of a conventionally proposed MOS controlled diode.

[0024] Figure 3 It means having Figure 2 (a) is a diagram showing an example of circuit symbols of a MOS controlled diode of an equivalent circuit.

[0025] Figure 4 This is a diagram showing the gate voltage dependency of the forward characteristic of the MOS control diode according to the first embodiment.

[0026] Figure 5 This is a diagram showing an example of the gate voltage dependency of the amount of stored charge in the MOS control diode according to the first embodiment.

[0027] Figure 6 This is a diagram showing an example of a circuit configuration of a power conversion device to which the MOS controlled diode according to the present embodiment is applied.

[0028] Figure 7 yes Figure 6 This figure shows an example of the operating waveforms of the MOS control diode and IGBT of the power conversion device during reverse recovery.

[0029] Figure 8 This is a diagram showing the gate voltage dependency of the reverse recovery characteristic in the MOS control diode of the present embodiment.

[0030] Fig. 9 It is a diagram showing an example of a cross-sectional structure of a MOS control diode mounted in a power conversion device according to a second embodiment of the present invention.

[0031] Fig.10 It is a diagram showing an example of a cross-sectional structure of a MOS control diode mounted in a power conversion device according to a third embodiment of the present invention.

[0032] Fig.11 It is a diagram showing an example of a cross-sectional structure of a MOS control diode mounted in a power conversion device according to a fourth embodiment of the present invention.

[0033] Fig.12 It is a diagram showing an example of a cross-sectional structure of a MOS control diode mounted in a power conversion device according to a fifth embodiment of the present invention.

[0034] Fig.13 This is a diagram showing an actual measurement example of the output characteristics of the MOS controlled diode mounted in the power conversion device according to the fifth embodiment of the present invention.

[0035] Fig.14 It is a diagram showing an example of a circuit configuration of a power conversion device according to a sixth embodiment of the present invention.

[0036] Fig.15 It is a diagram showing an example of a circuit configuration of a power conversion device according to a seventh embodiment of the present invention.

[0037] Fig.16 It is a diagram showing an example of a cross-sectional structure of a dual-gate IGBT.

[0038] Fig.17 It shows that Fig.16 A diagram showing an example of circuit notation of a dual-gate IGBT.

[0039] Fig.18 Yes means Fig.15 An example of a drive waveform (or drive signal) of a method for controlling two Gc gates and a Gs gate of a dual-gate IGBT in upper and lower arms of a power conversion device, and a Gd gate (gate electrode) of a MOS control diode. DETAILED DESCRIPTION

[0040] Hereinafter, the embodiments of the present invention will be described in detail through the first to seventh embodiments in conjunction with the accompanying drawings. - 、n、n + Such a statement indicates that the semiconductor layer is of n-type, and in this order, the impurity concentration is relatively high. - ,p,p + Such a description indicates that the semiconductor layer is of p-type, and in this order, the impurity concentration is relatively high. In the drawings, the same reference numerals are given to common components, and duplicate descriptions are omitted.

[0041] <First Embodiment>

[0042] Here, first, the MOS control diode 1 of the first embodiment is described. In the first embodiment, when the MOS control diode 1 is set as an equivalent circuit, the MOS control diode 1 is configured by connecting a pn diode and an n-channel MOSFET in parallel between an anode (A) and a cathode (K). In addition, a pn diode with a low impurity concentration is used as the source (S) of the MOSFET. - Layer 130. In the first embodiment, a first example of this structure will be described.

[0043] Figure 1 It is a diagram showing an example of a cross-sectional structure of a MOS control diode 1 mounted in the power conversion device according to the first embodiment of the present invention.

[0044] The MOS controlled diode 1 shown in the figure is an example of a semiconductor device. Figure 1 In the figure, the upper direction in the figure is regarded as one surface side. In addition, the lower direction in the figure is regarded as the other surface side. This is because, for the laminated body of each layer stacked as described below, when considering a pair of main surfaces, one main surface side is regarded as one surface side, and the other main surface side is regarded as the other surface side. Furthermore, the left and right directions in the figure are set as directions intersecting with the stacking direction of each layer stacked. The intersecting direction is, for example, a direction orthogonal to the stacking direction.

[0045] like Figure 1 As shown, the semiconductor substrate of the MOS control diode 1 is composed of n + Layer 11, n - Layer 12, p - Layers 13, 130 and p + The MOS control diode 1 includes a layer structure of a layer 14. The MOS control diode 1 includes a cathode electrode 21, anode electrodes 22 and 220, and a gate electrode 23 as electrodes.

[0046] n + The layer 11 is an example of a first semiconductor layer of the first conductivity type.

[0047] n - Layer 12 is set at n + On one surface side of layer 11, the concentration of impurities is n + The layer 11 is an example of a second semiconductor layer of the first conductivity type.

[0048] p - Layers 13 and 130 are arranged on n - An example of a third semiconductor layer of the second conductivity type on one surface side of the layer 12. - The layer 130 refers to a region sandwiched between the gate insulating films 32 in the intersecting direction. - Layer 13 refers to the ratio of p- The layer 130 has a region on the other surface side.

[0049] p + Layer 14 is set at p - In layer 130, the concentration of impurities is p - The layer 13 , 130 is an example of a fourth semiconductor layer of the second conductivity type.

[0050] It should be noted that, here, the n-type is set as the first conductivity type, and the p-type is set as the second conductivity type.

[0051] The cathode electrode 21 is arranged at n + The cathode electrode 21 is on the other surface side of the layer 11. + Layer 11 makes electrical contact with low resistance.

[0052] Anode electrodes 22, 220 are arranged at p - The anode electrode 22 and the anode electrode 220 are formed by the anode electrode 22 and the anode electrode 220. The anode electrode 22 is provided on the p-type substrate via the insulating film 31. - The anode electrode 220 is an example of a protrusion, which extends from the layered anode electrode 22 to the p - Layer 130 protrudes and + In addition, Figure 1 In the case of - It should be noted that in this case, it can also be said that p + Layer 14 is configured in p - The anode electrode 220 is disposed in the layer 130 and in contact with the front end of the anode electrode 220. + Layer 14 makes electrical contact with low resistance.

[0053] The gate electrode 23 is connected to n + Layer 11, n - Layer 12 and p - The layers 13 and 130 are stacked in a direction that intersects the direction in which they are stacked. - The gate electrode 23 is surrounded by the layers 13 and 130 and sandwiches the anode electrode 220. In addition, the gate electrode 23 is connected to the p - That is, the gate electrode 23 is in contact with the p-type layer 13 and the p-type layer 130 by the gate insulating film 32. - In this case, the gate electrode 23 can also be said to be insulated from the anode electrode 220 and the p + Furthermore, in this case, the gate electrode 23 and the gate insulating film 32 can also be said to have a trench structure.- The layers 13 and 130 function as n-channel MOSFET (metal-oxide-semiconductor field-effect transistor).

[0054] It should be noted that the insulating film 31 and the gate insulating film 32 are formed integrally. Figure 1 In the embodiment, the gate insulating film 32 is formed from the insulating film 31 to the p - The distance that the layers 13 and 130 protrude is defined as depth D. + Layer 14 is arranged in a manner to be within the depth D. This can also be said to be + The layer 14 is formed inside the recessed portion formed by the gate electrode 23 and the gate insulating film 32. + The layer 14 is sandwiched between two adjacent trench structures formed by the gate electrode 23 and the gate insulating film 32 and is formed inside them.

[0055] In addition, here, Figure 1 As shown, there will be p + The length between the gate insulating film 32 of the layer 14 is set to a distance A, and there is no p + The length between the gate insulating films 32 of the layer 14 is set to distance B. In this case, the structure that falls within the range of the sum of the distance A and the distance B in the cross direction in the figure is called a unit cell or a basic cell. The MOS control diode 1 shown in the figure has a structure in which the unit cells are repeatedly arranged in the cross direction (left-right direction, lateral direction) in the figure. Figure 1 In the depth direction of the MOS control diode 1, the structure shown in the figure becomes a linearly continuous structure. Figure 1 When cutting in the same direction, no matter where you cut, it will be the same Figure 1 Same structure.

[0056] In the MOS control diode 1, a forward voltage is applied between the anode electrodes 22, 220 and the cathode electrode 21 by a voltage applying means (not shown) in the forward direction. That is, a positive potential is applied to the anode electrodes 22, 220 of the MOS control diode 1, and a negative potential is applied to the cathode electrode 21.

[0057] In this case, even if the potential of the gate electrode 23 is the same as that of the anode electrodes 22 and 220, p + Layer 14 and p - Layer 13 and n - Layer 12 is also forward biased. Therefore, holes are transferred from p + Layer 14 via p - Layer 13 is heavily implanted into n- layer 12. That is, even if the gate electrode 23 and p - The MOSFET composed of layers 13 and 130 does not work, and holes also flow from p + Layer 14 via p - The holes promote the injection of a large number of electrons from the n-type layer 13 connected to the cathode electrode 21. + Layer 11 to n - Layer 12 implantation, n - Layer 12 is in a state where a large number of holes and electrons are accumulated. The electrons flow into p - Layer 13, promoting from p + As a result, n - The conductivity of the layer 12 is modulated to be low-resistance, and the forward voltage of the MOS control diode 1 is reduced.

[0058] In the MOS controlled diode 1 of the present embodiment, the current flows in accordance with p + Layer 14 → p - Layer 13 → n - Layer 12 → n + The current flows sequentially through the layers 11 to form a current path. In addition, in the MOS control diode 1, a MOSFET is not added in series to the current path. Therefore, compared with the conventional MOS control diode in which a MOSFET is added in series to the current path, the forward voltage is further reduced and the conduction loss is further reduced. + This effect becomes more significant when the layer 14 is arranged in a manner within the depth D. In addition, by setting the region at the distance B, not only the n + The electrons injected into layer 11 from the region n at a distance from B + The electrons injected from layer 11 also flow into the anode electrode 220 at a distance A, further promoting the electrons from p + In order to reduce the forward voltage, it is preferred that the distance B is greater than the distance A (A < B). Thus, the conductivity modulation is further promoted and the forward voltage is reduced. It should be noted that this can also be said that the p-type gate electrode 23 and the gate insulating film 32 are provided between the two adjacent gate electrodes 23 and the gate insulating film 32 sandwiching the anode electrode 220 as the protrusion. - The distance A in the intersecting direction of the layer 13 is smaller than the distance B between two adjacent gate electrodes 23 and the gate insulating film 32 without sandwiching the anode electrode 220 .

[0059] On the other hand, after the forward current flows through the MOS control diode 1, when the MOS control diode 1 is reversely restored to the blocking state, a negative potential is applied to the anode electrodes 22 and 220 by a voltage applying means (not shown), and a positive potential is applied to the cathode electrode 21. That is, during reverse recovery, a reverse voltage is applied between the anode electrodes 22 and 220 and the cathode electrode 21. And, in the present embodiment, the potential of the gate electrode 23 is made positive relative to the potential of the anode electrodes 22 and 220 just before reverse recovery. Just before reverse recovery is the time before the reverse recovery operation starts. Thus, the gate electrode 23 in contact with the gate insulating film 32 is connected to the gate insulating film 32. - The interface between layers 13 and 130 forms an n-type inversion layer. - Electrons flow more easily than in layer 13. - Layer 12 is injected into p - The electrons in layer 13 bypass the p + layer 14 flows to the n inversion layer via the p - layer 130 flows into the anode electrode 220. As a result, the + The hole injection of layer 14 is suppressed, n - The accumulated charge of holes and electrons in the layer 12 is suddenly reduced. Therefore, when the MOS control diode 1 is reversely recovered, the reverse recovery current is reduced and the reverse recovery loss is also reduced. It should be noted that the control of making the potential of the gate electrode 23 a positive potential relative to the potential of the anode electrodes 22 and 220 can be continued even during reverse recovery.

[0060] In addition, the MOS control diode 1 does not have an n-type diode on the anode electrode side like the MOS control diode of the prior art. + The parasitic npn transistor effect is suppressed by forming a layer. Therefore, the reverse recovery safe operating area can be increased. In addition, by setting the gate electrode 23 to the above-mentioned trench structure, the width of the trench bottom, which is the bottom of the trench structure, becomes smaller. As a result, it also has the advantages of being able to shorten the channel length of the n inversion layer and being less likely to produce a parasitic npn transistor effect.

[0061] Figure 2 (a) is represented by a newly created symbol Figure 1 FIG. 1 is a diagram of an example of an equivalent circuit of a MOS controlled diode.

[0062] It should be noted that Figure 2 The numbers shown in (a) correspond to Figure 1 In this case, a pn diode and an n-channel MOSFET are connected in parallel between the anode (A) and the cathode (K). + Layer 11, n -Layer 12, p - Layer 13 and p + The n-channel MOSFET corresponds to the gate electrode 23 and the p-channel MOSFET. - The anode (A) corresponds to the anode electrodes 22 and 220. The cathode (K) corresponds to the cathode electrode 21. The gate (G) corresponds to the gate electrode 23.

[0063] The drain (D) of an n-channel MOSFET is connected from p - Layer 13 is connected midway, the source (S) is connected via p - Layer 130 is connected to the anode (A). - The drain (D) can be controlled by the gate (G) from the p + Layer 14 to p - The implantation amount of the layers 13 and 130 can increase or decrease the conductivity of the MOS control diode 1 during forward recovery and reverse recovery.

[0064] In contrast, Figure 2 (b) is a diagram showing an equivalent circuit of a conventionally proposed MOS controlled diode.

[0065] exist Figure 2 In the MOS control diode of (b), a pn diode and a p-channel MOSFET are connected in series. That is, a p-channel MOSFET is connected in series to the pn diode current path. In this case, in the forward direction, Figure 2 Compared with the MOS control diode 1 shown in (a), the forward voltage is further increased and the conduction loss is larger. Figure 2 Compared with the MOS control diode 1 shown in (a), the reverse recovery current increases and the reverse recovery loss is also large. This can be said to be Figure 2 Compared with the MOS control diodes proposed in the past, the MOS control diode 1 shown in (a) has a further reduced forward voltage and a smaller conduction loss in the forward direction. Figure 2 The MOS controlled diode 1 shown in (a) has a smaller reverse recovery current and a smaller reverse recovery loss during reverse recovery than a conventionally proposed MOS controlled diode.

[0066] Figure 3 It means having Figure 2 (a) is a diagram showing an example of circuit symbols of the MOS controlled diode 1 which is an equivalent circuit.

[0067] This circuit symbol is newly created for the convenience of explaining the implementation method. It should be noted that this circuit symbol is not only used for example Figure 1 The MOS controlled diode 1 shown is also used in the embodiments described later.

[0068] Figure 4 Graph showing the gate voltage dependency of the forward characteristic of the MOS controlled diode 1 according to the first embodiment. Figure 4 In the figure, the horizontal axis represents the forward voltage and the vertical axis represents the forward current.

[0069] like Figure 4 As shown, even if the gate voltage (V GA ) is set to 0 V and no voltage is applied, conductivity modulation is also promoted, and the forward voltage becomes 3.5 V when the forward current is 200 A. On the other hand, if the gate voltage (V GA ) is set to +15V, the n-channel MOSFET takes effect and the conductivity modulation decreases. As a result, the forward voltage rises to 12V when the forward current is 200A. GA ) can be set to the same power supply as the IGBT described later. Therefore, compared with the prior art that requires the third -15V, the MOS control diode 1 of this embodiment can reduce the number of power supplies and has the advantage of simplifying and miniaturizing the gate circuit. It should be noted that the gate voltage (V GA ) is -15 V. In this case, the p-type capacitor in contact with the gate insulating film 32 - The interface between layers 13 and 130 forms a p accumulation layer. Figure 4 As shown, the forward voltage is further reduced. It should be noted that this control can be performed not only in the forward direction but also in the reverse blocking after reverse recovery. Therefore, in the present embodiment, it can be said that in at least one of the forward direction and the reverse blocking after reverse recovery, the potential difference between the gate electrode 23 and the anode electrodes 22, 220 is controlled to be 0V, or the potential of the gate electrode 23 is controlled to be a potential opposite to the potential of the anode electrodes 22, 220 to form an inversion layer in the third semiconductor layer. In this case, the opposite potential is a negative potential (-15V in the above case).

[0070] Figure 5 2 is a diagram showing an example of the gate voltage dependency of the amount of stored charge in the MOS controlled diode 1 according to the first embodiment. Figure 5 In the figure, the horizontal axis represents the depth and the vertical axis represents the amount of stored charge.

[0071] It should be noted that Figure 5 The amount of stored charge shown is the hole concentration, which is a value obtained by simulation calculation with a forward current of 200 A. Figure 5 It can be seen that by setting the gate voltage to +15V (V GA), compared with the case where the gate voltage is 0V or -15V, the amount of charge stored on the anode side is reduced by about one digit. That is, if the gate voltage (V GA ) to 0V or -15V, reducing the forward voltage can reduce conduction loss. On the other hand, during reverse recovery, the gate voltage (V GA ) is switched to +15V to reduce the amount of stored charge, thereby reducing the reverse recovery current and lowering the reverse recovery loss.

[0072] Figure 6 FIG. 8 is a diagram showing an example of a circuit configuration of a power conversion device 80 to which the MOS control diode 82 of the present embodiment is applied. Figure 3 The circuit symbols of the MOS control diode shown in FIG. 8 are shown in FIG. 8A and FIG. 8B. In addition, the MOS control diode 82 has the same structure as the MOS control diode 1 described above.

[0073] like Figure 6 As shown in FIG. 1 , the power conversion device 80 connects the MOS control diode 82 and the IGBT 81 in series as the upper arm and the lower arm, respectively. In addition, the power conversion device 80 is used as a chopper circuit, and the load inductor 83 is connected in parallel with the MOS control diode 82. The power conversion device 80 increases the gate voltage (V GE ) is turned on and off, thereby adjusting the current flowing through the load inductor 83 and adjusting the output power.

[0074] Here, the gate voltage (V GE ) is turned on, the current supplied from the power supply (Vcc) flows through the load inductor 83 and flows through the IGBT81 (I C Then, at this current (I C ) becomes the desired value, IGBT81 is turned off. C ) becomes a current (I A ) and flows to the MOS control diode 82. This current (I A ) is consumed by the loss of the MOS control diode 82 and the parasitic resistance existing in the circuit, and gradually decreases. Then, if the current (I A ) reaches the lower limit of the desired value, the IGBT81 is turned on again, thereby increasing the current supplied to the load inductor 83 and keeping its current amount within the desired range.

[0075] Figure 7 yes Figure 6 1 and 2 are examples of operation waveforms of the MOS control diode 82 and the IGBT 81 of the power conversion device 80 during reverse recovery.

[0076] Here, the IGBT 81 of the lower arm is turned on at time t0.

[0077] In this case, the MOS control diode 82 of the upper arm reduces the gate voltage V to t1 at a time t1 earlier than the time t0 by the charge extraction period td_rr1. GA Switching from 0V or -15V to +15V reduces the accumulated charge inside the MOS control diode 82. This corresponds to the above-mentioned operation of "making the potential of the gate electrode 23 positive relative to the potential of the anode electrodes 22, 220 just before reverse recovery". GA ) is kept at +15V, and at time t0, the IGBT81 of the lower arm is turned on, causing the MOS control diode 82 of the upper arm to reversely recover. At this time, the gate voltage V GA Maintain +15 V. This corresponds to the above-mentioned operation of "making the potential of the gate electrode 23 a positive potential with respect to the potential of the anode electrodes 22 and 220 during reverse recovery".

[0078] Next, after time t0, when reverse bias starts to be applied to the MOS control diode 82, at an arbitrary time t2, the gate voltage (V GA ) is switched from +15 V to 0 V or -15 V again. The MOS control diode 82 is on standby so that it can cope with the situation that the IGBT 81 of the lower arm is turned off next and the current is commutated to the MOS control diode 82.

[0079] It should be noted that when the IGBT 81 is turned on, the gate voltage (V GA ) becomes 0V or -15V again, the minimum value of the recovery period td_rr2 can be reduced to the time when reverse bias starts to be applied to the MOS control diode 82. By shortening this time, the n inversion layer of the n-channel MOSFET can be eliminated before a large reverse bias voltage is applied, thereby eliminating the parasitic npn transistor effect. As a result, the reverse recovery safe operating area can be further increased.

[0080] Figure 8 Graph showing the gate voltage dependency of the reverse recovery characteristic in the MOS control diode 82 of the present embodiment. Figure 8 In the figure, the horizontal axis represents time and the vertical axis represents voltage.

[0081] exist Figure 8 The voltage (V KA ) and anode current (I A ). And, the solid line represents the control Figure 6 and Figure 7 The gate voltage (VGA ) is from 0 V to +15 V at time t1 immediately before reverse recovery. On the other hand, the dotted line indicates a case where this control is not performed and reverse recovery is performed while maintaining the 0 V state without switching the voltage.

[0082] By controlling the gate voltage from 0V to +15V, as Figure 5 As shown, the amount of stored charge is reduced. As a result, as shown by the solid line, the reverse recovery current is greatly reduced. In addition, it can be seen that the reverse recovery loss is significantly reduced by 15% compared with the case where the reverse recovery is performed while maintaining the 0V state without performing this control (the case of the dotted line).

[0083] <Second Embodiment>

[0084] Next, the MOS control diode 2 of the second embodiment is described. In the second embodiment, as in the first embodiment, the MOS control diode 2 is configured by connecting a pn diode and an n-channel MOSFET in parallel between the anode (A) and the cathode (K) in the equivalent circuit. In addition, a pn diode with a low impurity concentration is used for the source (S) of the MOSFET. - Layer 130. In the second embodiment, a second example of this structure will be described.

[0085] Fig. 9 It is a diagram showing an example of a cross-sectional structure of a MOS control diode 2 mounted in a power conversion device according to a second embodiment of the present invention.

[0086] The MOS controlled diode 2 of the second embodiment has a structure composed of n + Layer 11, n - Layer 12, p - Layers 13, 130 and p + The layer structure is composed of the layer 14. In addition, the MOS control diode 2 includes a cathode electrode 21, anode electrodes 22 and 220, and a gate electrode 23 as electrodes, similarly to the first embodiment.

[0087] On the other hand, MOS control diode 2 is at p - The p-layer 15 is formed on at least a portion of the layer 130. The p-layer 15 is an example of a fifth semiconductor layer of the second conductivity type. The p-layer 15 sandwiches the anode electrode 220 in the above-mentioned intersecting direction and is provided on the p-layer 130. - In the illustrated case, by providing a p layer 15, the p - Layer 130 is divided into two layers, one above the other. That is, in this case, n layers are stacked in sequence. + Layer 11, n - Layer 12, p - Layer 13, p- Layer 130, p + Layer 14 and p layer 15, p - Layer 130. And, p - Layer 130 becomes p located on one surface side - layer 130 and the p - The impurity concentration of the p layer 15 is higher than that of the p layer 130. - Layer 13, 130 is higher than p + Therefore, the p layer 15 suppresses the flow of forward current from the p - Layer 13 flows to p - The current of the electrons in layer 130 comes from p + The hole injection into the p-layer 14 and the p-layer 15 increases. As a result, the forward voltage further decreases.

[0088] exist Figure 2 In (a), the p-layer 15 is also shown. Figure 2 In the equivalent circuit shown in (a), the p-layer 15 operates as follows.

[0089] That is, for p - Layer 13 flows into p - The electrons in the p-layer 130 are inserted into the p-layer 15, and the potential barrier becomes higher. + The forward bias effect of layer 14 increases the height of the barrier (potential difference), promoting the forward bias from p layer 15 and p + Holes are injected into layer 14. As a result, the forward voltage is further reduced.

[0090] Furthermore, by adjusting the concentration of the p-layer 15 , the gate threshold voltage of the n-channel MOSFET can be adjusted to a desired value.

[0091] In order to improve the utilization of p layer 15 to suppress the - Layer 13 to p - The effect of the electron current flowing through layer 130 is preferably to + The p-layer 15 is formed so as to extend across the gate insulating film 32. This can also be said to be preferably formed by using the p-layer 14. + The p-layer 15 is formed so as to connect the p-layer 14 and the gate insulating film 32. - Layer 13 and p - The entire area of ​​the layer 130 over the boundary region suppresses the detour of the electron current, so the forward voltage is further reduced.

[0092] It is desirable that the impurity concentration of the p-layer 15 be less than 100% when a gate voltage (V GA), an n inversion layer is formed at the interface of the gate insulating film 32 in contact with the p-layer 15. By doing so, the reduction of the accumulated charge immediately before the reverse recovery and the reduction of the reverse recovery loss during the reverse recovery are not impaired.

[0093] In addition, the structure of the gate electrode 23 of the MOS control diode 2 is different from that of the MOS control diode 1. In this case, the gate electrode 23 becomes thicker relative to the above-mentioned intersection direction as it goes to the other surface side. This can also be said that the thickness of the gate electrode 23 increases in the direction from one surface side toward the other surface side. Thereby, the gate capacity is halved, for example, and it is easy to drive the MOS control diode 2. This gate structure is called a sidewall gate structure. It should be noted that, needless to say, the sidewall gate structure can also be used for the MOS control diode 1. On the other hand, the gate structure of the MOS control diode 1 is called a trench gate structure. That is, the thickness of the gate electrode of the trench gate structure is approximately constant in the up and down directions in the figure. And, of course, the trench gate structure of the MOS control diode 1 can also be applied to the MOS control diode 2.

[0094] <Third Embodiment>

[0095] Next, the MOS control diode 3 of the third embodiment is described. In the third embodiment, as in the first and second embodiments, the MOS control diode 3 is configured by connecting a pn diode and an n-channel MOSFET in parallel between the anode (A) and the cathode (K) in the equivalent circuit. In addition, the source (S) of the MOSFET uses an n-layer 131 with a low impurity concentration. And, in the third embodiment, a third example of this structure is described.

[0096] Fig.10 It is a diagram showing an example of a cross-sectional structure of a MOS control diode 3 mounted in a power conversion device according to a third embodiment of the present invention.

[0097] The MOS controlled diode 3 of the third embodiment has a structure composed of n + Layer 11, n - Layer 12, p - Layer 13 and p + The layer structure is composed of the layer 14. In addition, the MOS control diode 3 includes a cathode electrode 21, anode electrodes 22, 220, and a gate electrode 23 as electrodes, similarly to the first and second embodiments.

[0098] On the other hand, in the MOS control diode 3 of the third embodiment, compared with the MOS control diode 2, the p layer 15 located on one surface side is replaced with the p layer 15. -In this case, it can be said that the n layer 131 is formed on one surface side with respect to the p layer 15. That is, in this case, n layers 131 are sequentially stacked. + Layer 11, n - Layer 12, p - Layer 13, p + The n-layer 131 is an example of the sixth semiconductor layer of the first conductivity type. Therefore, just before the reverse recovery, the electrons flowing from the n-type layer and the p-type layer are connected to each other. - Compared with the case of the n layer 130, electrons are more likely to flow to the n layer 131 which is the majority carrier. As a result, in the forward direction, electrons are accumulated in the n layer 131. - The charge of layer 12 is reduced, and the reverse recovery loss is further reduced.

[0099] The impurity concentration of the n layer 131 is higher than that of the p - Layer 13 is higher than p + Furthermore, preferably, the impurity concentration of the n-layer 131 is lower than that of the p-layer 15. - Layer 13, n - Layer 12, n + The current amplification factor of the parasitic npn transistor formed by the layer 11 is reduced, and a reduction in the reverse recovery safe operating area due to the operation of the parasitic npn transistor can be prevented.

[0100] <Fourth Implementation Method>

[0101] Next, the MOS control diode 4 of the fourth embodiment will be described. In the fourth embodiment, as in the first to third embodiments, the MOS control diode 4 is configured by connecting a pn diode and an n-channel MOSFET in parallel between the anode (A) and the cathode (K) in the equivalent circuit. In addition, a pn diode with a low impurity concentration is used for the source (S) of the MOSFET. - Layer 130. In the fourth embodiment, a fourth example of this structure will be described.

[0102] Fig.11 It is a diagram showing an example of a cross-sectional structure of a MOS control diode 4 mounted in a power conversion device according to a fourth embodiment of the present invention.

[0103] The MOS controlled diode 4 of the fourth embodiment has a structure composed of n + Layer 11, n - Layer 12, p - Layer 13 and p +The layer structure is composed of the layer 14. In addition, the MOS control diode 4 includes a cathode electrode 21, anode electrodes 22 and 220, and a gate electrode 23 as electrodes, similarly to the first to third embodiments.

[0104] On the other hand, the MOS control diode 4 is Fig.10 The MOS control diode 3 has a gate electrode 23 on the other surface side. - The p-layer 151 is provided in the layer 13. The p-layer 151 is an example of a seventh semiconductor layer of the second conductivity type. The impurity concentration of the p-layer 151 is higher than that of the p-layer 151. - Therefore, it is possible to suppress the reverse recovery through the n layer 131 (or p layer 131). - The electron current from the n-type layer 130) and the n-type layer is injected from the n-type layer into the p-type layer. - Layer 13. That is, the n inversion layer, p - Layer 13, n - The parasitic npn transistor formed by layer 12 is difficult to operate, and the reverse recovery safe operating area is significantly improved. In this embodiment, p layer 151 and p layer 15 can also be formed simultaneously by the same ion implantation, and there is no need to add a new manufacturing process for forming p layer 151.

[0105] MOS control diodes 1 to 4 show p - The junction between the layer 130 (or the n-layer 131 ) and the anode electrode 220 is preferably a Schottky junction.

[0106] In p - In the case of layer 130, p - The layer 130 and the anode electrode 220 form a p-type Schottky junction. When the accumulated charge before the reverse recovery is reduced, the electrons can easily pass from the p-type Schottky junction due to the height of the potential barrier. - The layer 130 flows smoothly toward the anode electrode 220. As a result, the n - The conductivity of layer 12 is modulated.

[0107] On the other hand, in the case of the n-layer 131, the n-layer 131 and the anode electrode 220 form an n-type Schottky junction, which can reduce the flow of electrons to the n-layer 131 by the height of its barrier, thereby suppressing the operation of the parasitic npn transistor during reverse recovery. As a result, the reverse recovery safe operating area can be improved. In this embodiment, it should be noted that the p-layer 151 and the p-layer 15 can also be formed simultaneously by the same ion implantation, and there is no need to add a new manufacturing process for forming the p-layer 151.

[0108] <Fifth Implementation Method>

[0109] Fig.12It is a diagram showing an example of a cross-sectional structure of a MOS control diode 3 mounted in a power conversion device according to a fifth embodiment of the present invention.

[0110] The MOS control diode 3 of the fifth embodiment has an n layer 131 having an impurity concentration higher than that of the p layer 15 formed in place of the n layer 131 shown in the third and fourth embodiments. + In this case, it can also be said that an n layer located on one surface side with respect to the p layer 15 is formed. + Layer 132. + The layer 132 is also an example of a sixth semiconductor layer of the first conductivity type.

[0111] n + Even when the layer 132 is in ohmic contact with the anode electrode 220, it is in contact with the anode electrode 220 at a lower resistance than in the case of Schottky contact. + The layer 132 is located on one surface side relative to the p-layer 15 and is in contact with the anode electrode 220 at a lower resistance than in the case of Schottky junction. + The layer 132 is in contact with the anode electrode 220 with a lower resistance than in the case of Schottky junction, so that when the accumulated charge just before the reverse recovery is reduced, the p - Electrons flowing in the n inversion layer on the gate electrode 23 side surface of the p layer 13 and the p layer 15 can pass through the n + The layer 132 flows smoothly into the anode electrode 220. Therefore, more accumulated charge is reduced, and the output characteristics of the MOS diode 3 can be controlled to a greater extent by the gate voltage. As a result, the reverse recovery loss is further reduced.

[0112] It should be noted that by setting the impurity concentration of the n layer 131 to be higher than that of the n layer 131, + Layer 132, by n + Layer 132, p layer 15 / p - Layer 13, n - The parasitic npn transistor formed by layer 12 is easy to operate during reverse recovery, but + The miniaturization of layer 132, p layer 15, p - Properly increasing the concentration of impurities in the layer 13 can prevent the operation of the parasitic npn transistor.

[0113] Fig.13 Indicates that it is carried on Fig.12 FIG. 1 is a measurement example of the output characteristics of the MOS controlled diode 3 of the power conversion device according to the fifth embodiment of the present invention. It can be seen that by changing the gate voltage V GA , which can control the output characteristics of MOS control diode 3. In addition, V GA= -15V and 0V have roughly the same output characteristics. MOS control diode 3 has the following characteristics: not only V GA = -15V and +15V, even if V GA =0V and +15V can also control the output characteristics, without the need for V GA =-15V for gate power supply.

[0114] <Sixth Implementation Method>

[0115] Next, a sixth embodiment will be described. In the sixth embodiment, a power conversion device 1000 will be described as a first example of a power conversion device using the above-described MOS controlled diode 82 .

[0116] Fig.14 It is a diagram showing an example of a circuit configuration of a power conversion device 1000 according to a sixth embodiment of the present invention.

[0117] The power conversion device 1000 shown in the figure includes a DC-AC conversion circuit and a MOS control diode 82. The MOS control diode 82 may be any of the MOS control diodes 1 to 4 described above, and is representatively referred to as the MOS control diode 82. The DC-AC conversion circuit is formed by connecting a plurality of (in series) DC terminals 1010 and 1020. Fig.14 The power conversion device 1000 is composed of IGBTs 81 (two in total) that conduct and cut off current. In addition, AC terminals 1030, 1040, and 1050 are connected between the plurality of IGBTs 81. Furthermore, the power conversion device 1000 connects MOS control diodes 82 to the plurality of IGBTs 81 in anti-parallel.

[0118] The MOS control diode 82 of the power conversion device 1000 of this embodiment may also have Figure 1 , Figures 9-11 Any one of the MOS controlled diodes 1 to 4 of the structure shown. Fig.14 In the embodiment, the MOS control diode 82 is composed of Figure 3 The circuit symbols shown are represented.

[0119] In the power conversion device 1000, by installing the MOS control diode 82, the conduction loss and reverse loss are reduced compared to the case of using a normal pn diode. Furthermore, in addition to this, the reduction in reverse recovery current also causes the conduction current of the IGBT 81 to be reduced. As a result, the inverter can be reduced in loss, that is, the power conversion device 1000 can be made more efficient.

[0120] <Seventh Implementation Method>

[0121] Next, a seventh embodiment will be described. In the seventh embodiment, a power conversion device 1100 will be described as a second example of a power conversion device using the above-described MOS controlled diode 82 .

[0122] Fig.15 It is a diagram showing an example of a circuit configuration of a power conversion device 1100 according to the seventh embodiment of the present invention.

[0123] The power conversion device 1100 of this embodiment is Fig.14 The circuit structure of the power conversion device 1000 of the sixth embodiment shown in the figure is obtained by replacing the IGBT 81 with a dual-gate IGBT 810. Here, the dual-gate IGBT 810 refers to an IGBT having two gates capable of time-difference driving. That is, the dual-gate IGBT 810 has two gates, a first gate and a second gate, as gate electrodes that can be independently turned on and off.

[0124] Fig.16 FIG. 8 is a diagram showing an example of a cross-sectional structure of a dual-gate IGBT 810 .

[0125] The double-gate IGBT 810 shown in the figure is composed of a p-layer 41, an n-layer 42, and an n-layer 43. - layer 43, p layer 44 and n + The layer structure is composed of the layer 45. The dual-gate IGBT 810 includes a cathode electrode 51, anode electrodes 52 and 520, and Gc gate 231 and Gs gate 232 as gate electrodes as electrodes.

[0126] The anode electrodes 52 and 520 are composed of the anode electrode 52 and the anode electrode 520. The anode electrode 22 is provided on the n - The anode electrode 520 protrudes from the anode electrode 52 toward the p layer 44 and is connected to the p layer 44 and the n layer 43. + Layer 45 contacts.

[0127] The Gc gate 231 and the Gs gate 232 are connected to the p layer 41, the n layer 42, and the n - The p layer 43 and the p layer 44 are stacked in a direction intersecting each other, with the anode electrode 520 interposed therebetween. The Gc gate 231 and the Gs gate 232 are connected to the n layer 43 and the p layer 44 via the gate insulating film 321. - Layer 43, p layer 44, n + The Gc gate 231 corresponds to the first gate, and the Gs gate 232 corresponds to the second gate.

[0128] In having Fig.16In the dual-gate IGBT810 having a cross-sectional structure, the gate electrode in the unit cell is divided into two gates, Gc gate 231 and Gs gate 232, and they are driven separately. In addition, by driving Gc gate 231 and Gs gate 232 with a time difference, the turn-off loss and the conduction loss can be reduced. It should be noted that, in addition, Fig.18 The time difference driving timing of the Gc gate 231 and the Gs gate 232 and the like will be described.

[0129] Fig.16 The cross-sectional structure of the dual-gate IGBT 810 shown in FIG. 8 is similar to that of the Gc gate 231 and the Gs gate 232. Fig.10 The structure of the gate electrode 23 of the MOS control diode 2 shown in FIG. 2 is similar. However, in the MOS control diode 2, the bottom of the gate insulating film 32 surrounding the gate electrode 23 is formed by p - Layer 13 covers, not with n - layer 12. Thus, at the gate voltage (V GA ) has stable blocking characteristics even when it is +15V.

[0130] Fig.17 It shows that Fig.16 FIG. 8 is a diagram showing an example of circuit notation of a dual-gate IGBT810.

[0131] This circuit symbol is newly created for the convenience of explaining this embodiment. It should be noted that Fig.17 The cross-sectional structure of the dual-gate IGBT810 shown by the circuit symbol is not limited to Fig.16 The cross-sectional structure may also have other cross-sectional structures.

[0132] <Seventh Implementation Method>

[0133] Next, a seventh embodiment will be described. In the seventh embodiment, control of the power conversion device 1100 will be described.

[0134] Fig.18 Yes means Fig.15 An example of a drive waveform (or drive signal) of a control method of the Gc gate 231 and the Gs gate 232 of the dual-gate IGBT 810 in the upper and lower arms of the power conversion device 1100, and the Gd gate (gate electrode 23) of the MOS control diode 82.

[0135] These drive waveforms are based on a PWM signal of a pulse width A generated by a control circuit such as a microcomputer (not shown), and are generated by the control circuit while taking into account the dead time (DT) and the like. Fig.18 , for reference, a gate (G) driving waveform in a conventional general IGBT is also shown.

[0136] like Fig.18 As shown, when the control circuit turns off the dual-gate IGBT810, the Gc gate drive signal is turned off before the Gs gate drive signal by a time td_off. For example, it changes from +15V to 0V (or -15V). As a result, the charge accumulated inside the dual-gate IGBT810 can be reduced. Next, after the time td_off has passed, the control circuit turns off the Gs gate drive signal, and the accumulated charge decreases. Therefore, the current of the dual-gate IGBT810 can be cut off at a high speed, and the turn-off loss of the dual-gate IGBT810 can be reduced.

[0137] On the other hand, when turning on the dual-gate IGBT810, the control circuit turns on the Gs gate drive signal before the Gc gate drive signal by a time td_on. That is, it changes from 0V (or -15V) to +15V. Thus, the dual-gate IGBT810 can be switched slowly only through the Gc gate, and the dv / dt can be adjusted to be small. That is, the voltage change during turn-on can be further reduced. Next, the control circuit can improve the conductivity modulation of the dual-gate IGBT810 and reduce the conduction loss (on-voltage) by turning on the Gc gate drive signal. However, if the drive is performed only through the Gc gate, the switching is delayed and the conduction loss increases. In this case, the conduction loss can be reduced by driving the Gs gate and the Gc gate at the same time.

[0138] Here, the relationship between the Gc gate drive signal and the Gs gate drive signal of the dual-gate IGBT 810 and the Gd gate drive signal of the MOS control diode 82 is as follows. Here, the transition period refers to the period from when the Gd gate drive signal is switched from 0 V (or -15 V) to +15 V, maintained at +15 V, and then returned from +15 V to 0 V (or -15 V).

[0139] exist Fig.18 In the control method, before the Gs gate drive signal of the dual-gate IGBT810 of the self-arm is turned on, the Gd gate drive signal of the MOS control diode 82 of the opposite arm connected in series is set to +15V. Then, the gate drive signals of Gc and Gs of the dual-gate IGBT810 connected in parallel with the MOS control diode 82 are turned off. Thus, the pulse width A of the PWM signal can be reproduced. Through this control method, the Gd gate drive signal, the Gs gate drive signal, and the Gc gate drive signal can be generated without contradiction based on the same PWM signal as before. It should be noted that even if the circuit of the upper arm and the circuit of the lower arm are like Fig.15 Even when there are three circuits, the point that the Gd gate drive signal, the Gs gate drive signal, and the Gc gate drive signal of each circuit can be generated without contradiction based on the PWM signal remains unchanged.

[0140] The MOS control diode 82 described above is similar to the conventional diode in that it reduces the n - The life of the minority carriers in the layer 12 can reduce the reverse recovery current and the reverse recovery loss. Furthermore, the MOS control diode 82 has the effect of reducing the conduction loss in the case of a structure in which a first MOS control diode (an example of a first semiconductor device) having a longer life and a lower forward voltage and a second MOS control diode (an example of a second semiconductor device) having a shorter life and a lower reverse recovery current (reverse recovery loss) are connected in parallel.

[0141] According to this structure, in the forward direction, the gate electrodes 23 of the first MOS control diode and the second MOS control diode are kept at 0V (or -15V), and the current mainly flows in the first MOS control diode, thereby reducing the conduction loss. In addition, during reverse recovery, the gate electrode 23 of the first MOS control diode is made +15V just before the reverse recovery, and the flow of the main current is transferred to the second MOS control diode, thereby making the second MOS control diode +15V. By doing so, the accumulated charge of the second MOS control diode can be reduced, and the reverse recovery loss can be reduced by shortening the life of the second MOS control diode. The ability to obtain such a structure and effect is also a new effect of the MOS control diode 82 in this embodiment that can utilize the current of the gate electrode control diode.

[0142] Therefore, according to the above-described structure in which the first MOS control diode and the second MOS control diode are connected in parallel, a composite MOS control diode can be realized that simultaneously utilizes the low conduction loss of the first MOS control diode and the low reverse recovery loss of the second MOS control diode.

[0143] In addition, the MOS control diode 82 and the dual-gate IGBT 810 described above can be integrated into one semiconductor chip. By integrating them into one semiconductor substrate, the mounting area of ​​the MOS control diode 82 and the dual-gate IGBT 810 as a whole can be reduced, thereby miniaturizing the power conversion device 1100.

[0144] in particular, Figures 9 to 11 The MOS controlled diodes 2, 3, and 4 shown are MOS controlled diodes 82, Fig.16 The dual-gate IGBTs 810 shown have the same side-gate structure. Therefore, if they are combined, they can be easily integrated as one semiconductor chip. Of course, even the conventional single-gate IGBT 81 can be integrated into the MOS control diode 82 of this embodiment and the same semiconductor chip.

[0145] like Figure 2 As shown in (b), as a MOS control diode proposed in the past, there is a diode in which a p-channel MOSFET is connected in series to the p-layer of a pn diode. In this MOS control diode, in the forward direction, a negative gate voltage (e.g., -15V) lower than the threshold voltage is applied to the p-channel MOSFET, so that the p-channel MOSFET is turned on, and a forward current flows through the pn junction. On the other hand, in the reverse recovery, a gate voltage higher than the threshold voltage (e.g., 0V or +15V) is applied immediately before the reverse recovery, so that the p-channel MOSFET is turned off, thereby reducing the excess charge accumulated in the pn diode in the forward direction before the reverse recovery.

[0146] However, in this MOS control diode, a negative gate voltage (e.g., -15V) is required in the forward direction. That is, a negative gate power supply needs to be newly prepared. In order to operate this MOS control diode, a new -15V power supply is required, which becomes three power supplies. As a result, the cost increases and the gate circuit becomes larger. In addition, since the p-channel MOSFET is connected in series with the pn diode, in the forward direction, in addition to the forward voltage drop of the pn diode, the on-resistance of the p-channel MOSFET is also superimposed, so the conduction loss of the MOS control diode increases.

[0147] In contrast, in the MOS control diode 82 of the present embodiment, in the equivalent circuit, the pn diode and the n-channel MOSFET are connected in parallel between the anode (A) and the cathode (K). In this case, the MOS control diode 82 does not necessarily require a negative gate voltage. That is, in the power conversion device, the gate power supply of the parallel IGBT does not necessarily require a negative gate voltage. Therefore, it can be driven with the same gate power supply of 0V and +15V as the IGBT81 and the dual-gate IGBT810. That is, the number of voltages of the gate power supply can be reduced. Therefore, compared with the case where a negative gate voltage is required, it has the advantages of easy control and the ability to simplify and miniaturize the gate circuit.

[0148] In addition, as a MOS control diode proposed in the past, an n-channel MOSFET similar to an IGBT is used. In this case, it has the following characteristics: the gate voltage is set to 0V in the forward direction, and to +15V in the reverse recovery, and the gate power supply voltage is the same as the IGBT. In addition, the MOS control diode has the following characteristics: an n-channel MOSFET is formed in parallel with a pn diode, and the forward voltage drop of the pn diode in the forward direction is not superimposed on the on-resistance of the n-channel MOSFET, and a low forward voltage drop is easily obtained.

[0149] However, this MOS control diode uses an n-channel MOSFET with a high impurity concentration at the source (S). +In addition, just before and during reverse recovery, the gate voltage must be higher than the threshold voltage of the n-channel MOSFET (for example, +15V). Therefore, an n-channel MOSFET is also formed on the Si interface of the MOS gate surface. + Inversion layer, with high concentration n + The layers together form a wide n + The parasitic npn transistor of the layer. This parasitic npn transistor is easy to operate at high voltage, large current and high temperature, but there is a problem that the switching tolerance during reverse recovery, that is, the reverse recovery safe operating area, is reduced.

[0150] On the other hand, in the MOS control diode 82 of the present embodiment, the source (S) of the n-channel MOSFET uses a p-type transistor with a low impurity concentration. - Layer 130. As a result, the forward voltage drop is reduced and the reverse recovery safe operating area is expanded.

[0151] In addition, the dual-gate IGBT 810 and the MOS control diode 82 described above can be easily manufactured by a semiconductor manufacturing process using silicon. Fig.18 The drive shown can operate the power conversion device 1100 such as the inverter efficiently and safely with low loss. As a result, without using high-cost SiC, it is possible to achieve high efficiency in the use of electricity in the power conversion device 1100 such as the inverter. Therefore, it is possible to promote the popularization of the power conversion device 1100 and promote energy conservation and new energy for a decarbonized society. It should be noted that the same can also be said for the power conversion device 1000 using the IGBT810 and the MOS control diode 82.

[0152] It should be noted that the present invention is not limited to the above-described embodiments and examples, but also includes various modified examples. For example, in order to easily understand the present invention, the above-mentioned embodiments and examples are described in detail, and are not necessarily limited to having all the structures described. In addition, a part of the structure of a certain embodiment or example can be replaced with the structure of other embodiments or examples, and in addition, the structure of other embodiments or examples can be added to the structure of a certain embodiment or example. In addition, for a part of the structure of each embodiment or example, the structure included in other embodiments or examples can also be added, deleted, or replaced.

[0153] Description of Reference Numerals

[0154] 1, 2, 3, 4, 82...MOS controlled diode, 11...n + Layer, 12…n - Layer, 13, 130…p - Layer, 14…p+ layer, 15, 151...p layer, 21...cathode electrode, 22, 220...anode electrode, 23...gate electrode, 31, 31...insulating film, 32...gate insulating film, 131...n layer, 132...n + Layer, 81…IGBT, 231…Gc gate, 232…Gs gate, 810…dual gate IGBT, 1000, 1100…power conversion device.

Claims

1. A power conversion device, which uses a semiconductor device to convert power, characterized in that: The power conversion device includes a semiconductor device and a voltage applying means, wherein the semiconductor device has: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is provided on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductivity type, provided on one surface side of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is provided in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer; a cathode electrode disposed on the other surface side of the first semiconductor layer; an anode electrode provided on one surface side of the third semiconductor layer and having a protruding portion in contact with the fourth semiconductor layer; as well as a gate electrode disposed across the protrusion in a direction intersecting a direction in which the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are stacked, and in contact with the third semiconductor layer via a gate insulating film, The voltage applying means applies a forward voltage between the anode electrode and the cathode electrode in a forward direction, and applies a reverse voltage between the anode electrode and the cathode electrode in a reverse recovery. Before the reverse recovery, the potential of the gate electrode is set to a potential at which an inversion layer is formed in the third semiconductor layer with respect to the potential of the anode electrode.

2. The power conversion device according to claim 1, characterized in that: Also available: A pair of DC terminals; a DC-AC conversion circuit, which is formed by connecting a plurality of insulated gate bipolar transistors in series between the pair of DC terminals for conducting and cutting off current; and an AC terminal connected between the plurality of the insulated gate bipolar transistors, The semiconductor device is connected in reverse parallel to each of the plurality of insulated gate bipolar transistors.

3. The power conversion device according to claim 2, characterized in that: The insulated gate bipolar transistor includes a first gate and a second gate as the gate electrodes, which can be independently controlled to be turned on and off.

4. The power conversion device according to any one of claims 1 to 3, characterized in that: The semiconductor device has a structure in which a first semiconductor device having a longer life and a lower forward voltage and a second semiconductor device having a shorter life and a lower reverse recovery current are connected in parallel.

5. A method for controlling a power conversion device, wherein the method is to operate the power conversion device using a semiconductor device to convert power, characterized in that: The power conversion device is operated by controlling a semiconductor device, wherein the semiconductor device has: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is provided on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductivity type, provided on one surface side of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is provided in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer; a cathode electrode disposed on the other surface side of the first semiconductor layer; an anode electrode provided on one surface side of the third semiconductor layer and having a protruding portion in contact with the fourth semiconductor layer; as well as a gate electrode disposed across the protrusion in a direction intersecting a direction in which the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are stacked, and in contact with the third semiconductor layer via a gate insulating film, The control is to apply a forward voltage between the anode electrode and the cathode electrode in the forward direction, and to apply a reverse voltage between the anode electrode and the cathode electrode in the reverse recovery. Before the reverse recovery, the potential of the gate electrode is set to a potential at which an inversion layer is formed in the third semiconductor layer with respect to the potential of the anode electrode.

6. The control method of the power conversion device according to claim 5, characterized in that: The power conversion device further comprises: A pair of DC terminals; a DC-AC conversion circuit, which is formed by connecting a plurality of insulated gate bipolar transistors in series between the pair of DC terminals for conducting and cutting off current; and an AC terminal connected between the plurality of the insulated gate bipolar transistors, The semiconductor device is connected in reverse parallel to the plurality of insulated gate bipolar transistors, respectively. The insulated gate bipolar transistor has two gates, a first gate and a second gate, as gate electrodes. The first gate and the second gate are controlled to be on and off independently of each other.

7. The control method of the power conversion device according to claim 6, characterized in that: When the insulated gate bipolar transistor is turned off, the driving signal of the first gate is turned off before the driving signal of the second gate, and when the insulated gate bipolar transistor is turned on, the driving signal of the second gate is turned on before the driving signal of the first gate.

8. The control method of the power conversion device according to claim 6, characterized in that: When the insulated gate bipolar transistor is turned on and off, the first gate and the second gate are driven simultaneously.

9. A semiconductor device, characterized in that: The semiconductor device comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is provided on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductivity type, provided on one surface side of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is provided in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer; a cathode electrode disposed on the other surface side of the first semiconductor layer; an anode electrode provided on one surface side of the third semiconductor layer and having a protruding portion in contact with the fourth semiconductor layer; as well as A gate electrode is provided across the protruding portion in a direction intersecting a direction in which the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are stacked, and is in contact with the third semiconductor layer via a gate insulating film.

10. The semiconductor device according to claim 9, wherein: The present invention further comprises a fifth semiconductor layer of the second conductivity type, which is provided in the third semiconductor layer across the protruding portion in the intersecting direction and has an impurity concentration higher than that of the third semiconductor layer and lower than that of the fourth semiconductor layer.

11. The semiconductor device according to claim 10, wherein: The fifth semiconductor layer is provided so as to extend from the fourth semiconductor layer to the gate insulating film.

12. The semiconductor device according to claim 10 or 11, characterized in that: A sixth semiconductor layer of the first conductivity type is provided, the sixth semiconductor layer being located on the one surface side relative to the fifth semiconductor layer and having a higher impurity concentration than the fifth semiconductor layer.

13. The semiconductor device according to claim 10 or 11, characterized in that: A sixth semiconductor layer of the first conductivity type is provided, which is located on the one surface side with respect to the fifth semiconductor layer and is in contact with the protruding portion of the anode electrode with a lower resistance than in the case of Schottky junction.

14. The semiconductor device according to claim 10 or 11, characterized in that: A sixth semiconductor layer of the first conductivity type is provided, which is located on the one surface side with respect to the fifth semiconductor layer and has an impurity concentration higher than that of the third semiconductor layer and lower than that of the fourth semiconductor layer.

15. The semiconductor device according to claim 14, wherein: The sixth semiconductor layer has an impurity concentration lower than that of the fifth semiconductor layer.

16. The semiconductor device according to claim 14 or 15, characterized in that: At least one of the third semiconductor layer and the sixth semiconductor layer forms a Schottky junction with the protruding portion of the anode electrode.

17. The semiconductor device according to any one of claims 9 to 16, wherein: A seventh semiconductor layer of the second conductivity type is further provided in the third semiconductor layer and is provided on the other surface side of the gate electrode, and has an impurity concentration higher than that of the third semiconductor layer.

18. The semiconductor device according to any one of claims 9 to 17, wherein: The gate electrode becomes thicker in the direction of the intersection as going toward the other surface side.

19. The semiconductor device according to any one of claims 9 to 18, characterized in that The fourth semiconductor layer is provided so as to be within a distance that the gate insulating film protrudes toward the third semiconductor layer.

20. The semiconductor device according to any one of claims 9 to 19, wherein: The distance between the third semiconductor layer provided between the two adjacent gate electrodes and the gate insulating film sandwiching the protrusion in the intersecting direction is smaller than the distance between the two adjacent gate electrodes and the gate insulating film not sandwiching the protrusion.

21. The semiconductor device according to claim 9, wherein: The gate electrode and the third semiconductor layer function as a metal oxide semiconductor field effect transistor.

22. The semiconductor device according to claim 21, wherein: When the semiconductor device is set as an equivalent circuit, a pn diode composed of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer and the metal oxide film semiconductor field effect transistor are connected in parallel between the anode electrode and the cathode electrode.

23. A semiconductor device, characterized in that: The semiconductor device comprises: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is provided on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductivity type, provided on one surface side of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is provided in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer; a cathode electrode disposed on the other surface side of the first semiconductor layer; an anode electrode provided on one surface side of the third semiconductor layer and in contact with the fourth semiconductor layer; as well as A gate electrode is provided adjacent to the anode electrode and the fourth semiconductor layer.

24. The semiconductor device according to claim 23, wherein: The gate electrode and the third semiconductor layer function as a metal oxide semiconductor field effect transistor. When the device is set as an equivalent circuit, a pn diode composed of the first semiconductor layer, the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer and the metal oxide film semiconductor field effect transistor are connected in parallel between the anode electrode and the cathode electrode.

25. A control method for a semiconductor device, characterized in that: A semiconductor device is controlled, the semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type, which is provided on one surface side of the first semiconductor layer and has a lower impurity concentration than the first semiconductor layer; a third semiconductor layer of the second conductivity type, provided on one surface side of the second semiconductor layer; a fourth semiconductor layer of the second conductivity type, which is provided in contact with the third semiconductor layer and has a higher impurity concentration than the third semiconductor layer; a cathode electrode disposed on the other surface side of the first semiconductor layer; an anode electrode provided on one surface side of the third semiconductor layer and having a protruding portion in contact with the fourth semiconductor layer; as well as a gate electrode disposed across the protrusion in a direction intersecting a direction in which the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are stacked, and in contact with the third semiconductor layer via a gate insulating film, The control is to apply a forward voltage between the anode electrode and the cathode electrode in the forward direction, and to apply a reverse voltage between the anode electrode and the cathode electrode in the reverse recovery. Before the reverse recovery, the potential of the gate electrode is set to a potential at which an inversion layer is formed in the third semiconductor layer with respect to the potential of the anode electrode.

26. The control method of a semiconductor device according to claim 25, characterized in that: During the reverse recovery, the potential of the gate electrode is also set to a potential at which an inversion layer is formed in the third semiconductor layer with respect to the potential of the anode electrode.

27. The control method of a semiconductor device according to claim 25 or 26, characterized in that: In at least one of the forward state and the reverse blocking state after reverse recovery, the potential difference between the gate electrode and the anode electrode is made 0 V, or the potential of the gate electrode is made opposite to the potential of the anode electrode and the potential of the inversion layer formed in the third semiconductor layer.

28. The control method of a semiconductor device according to claim 27, characterized in that: A voltage having a magnitude capable of forming a storage layer is applied to the third semiconductor layer at least in one of the forward state and the reverse blocking state after reverse recovery.

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