Wafer-level packaging structure and wafer-level chip manufacturing method

Abstract

The invention provides a wafer level packaging structure, a wafer level chip and a manufacturing method thereof, the wafer level packaging structure comprises a window, a chip layer and a dielectric layer arranged between the window and the chip layer, and the window and the chip layer are respectively bonded with the corresponding side surfaces of the dielectric layer. The dielectric layer is provided with a plurality of light through holes corresponding to the functional areas on the chip layer so as to allow the window sheet to transmit light to the functional areas of the chip layer, and the dielectric layer is provided with scribing grooves which are located around the light through holes. According to the invention, the dielectric layer is additionally arranged between the window and the chip layer, so that the distance between the window and the chip layer is increased, and the problem of abnormal imaging on the chip caused by defects on the surface of the window is reduced; and three-layer bonding is carried out on the dielectric layer, the window sheet and the chip layer, so that the bonding stress is reduced, and the problems of high bonding stress, easiness in causing chip warping and high bonding difficulty of traditional two-layer chip bonding are effectively avoided.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a wafer-level packaging structure and a wafer-level chip manufacturing method. Background Art

[0002] MEMS (micro-mechanical) devices are generally required to be hermetically packaged due to their fragile structure to ensure the stability of the MEMS structure and reliable functions. For special devices, such as MEMS infrared devices, MEMS accelerometers, MEMS gyroscopes, etc., protective gas packaging or even vacuum packaging is required.

[0003] The wafer-level packaging of MEMS infrared devices consists of the upper window layer and the bottom chip bonding, such as Figure 1 As shown in the figure, the traditional wafer-level packaging structure has the following problems: (1) The chip after bonding has a high defect rate due to the limitation of MEMS processing technology, and image abnormality problems are prone to occur when the final detector is used; (2) When assembling infrared chips, particles such as dust in the environment fall on the surface of the window piece, resulting in a low yield of the assembled finished product; (3) Due to the small distance between the upper window piece and the bottom chip of the wafer-level packaging, the surface quality requirements of the window piece are high, the process window is narrow, and the difficulty is high; (4) The bonding stress is large when the upper window piece is bonded to the bottom chip, which can easily cause chip warping during the bonding process and increase the difficulty of bonding. Summary of the invention

[0004] The purpose of the present invention is to provide a wafer-level packaging structure, which can at least solve some of the defects existing in the prior art.

[0005] To achieve the above object, the present invention adopts the following technical solution:

[0006] A wafer-level packaging structure comprises a window, a chip layer and a dielectric layer arranged between the window and the chip layer, wherein the window and the chip layer are respectively bonded to corresponding side surfaces of the dielectric layer, the dielectric layer is provided with a plurality of light-through holes corresponding to functional areas on the chip layer to allow the window to transmit light to the functional areas of the chip layer, and the dielectric layer is provided with a scribe groove, which is located around the light-through hole.

[0007] Furthermore, the thickness of the dielectric layer is 0.5-1.0 mm.

[0008] Furthermore, the surface of the dielectric layer has an alignment mark for aligning with the window sheet and the chip layer.

[0009] Furthermore, the scribe groove is arranged on a side of the dielectric layer corresponding to the chip layer.

[0010] Furthermore, a hollow hole is provided in the dicing groove.

[0011] Furthermore, the hole wall of the light-through hole is processed with a matte structure.

[0012] Furthermore, the matt structure is at least one of a light-absorbing film layer, a rough surface structure layer or a step structure.

[0013] Furthermore, the plurality of light-through holes are evenly distributed in an array.

[0014] Furthermore, a metal solder layer is plated on the surface of the dielectric layer, and is bonded to the window plate and the chip layer via the metal solder layer.

[0015] The present invention also provides a method for manufacturing a wafer-level chip, comprising the following steps:

[0016] S1. Processing a plurality of light-through holes penetrating the upper and lower surfaces of the dielectric layer, and processing dicing grooves between adjacent light-through holes on the lower surface of the dielectric layer;

[0017] S2, aligning and bonding the upper and lower surfaces of the dielectric layer processed in step S1 with the window sheet and the chip layer respectively to obtain a wafer-level packaging structure;

[0018] S3, cutting and dicing the wafer-level packaging structure bonded in step S2 from the window side at the positions of the two side walls of the dicing groove, so as to remove the window and dielectric layer portions corresponding to the dicing groove, and expose the chip layer;

[0019] S4, dicing and cutting the chip layer at the chip layer exposed in step S3 to obtain a plurality of wafer-level chips.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] (1) The present invention increases the spacing between the window sheet and the chip layer by adding a dielectric layer between the window sheet and the chip layer, thereby reducing the imaging abnormality problem on the chip caused by defects on the window sheet surface. At the same time, the dielectric layer is used to perform three-layer bonding with the window sheet and the chip layer to reduce the bonding stress, effectively avoiding the problem of high bonding stress in traditional two-layer chip bonding, which easily causes chip warping and bonding difficulty; and a dicing groove is set on the dielectric layer to reduce the resistance of cutting the dicing dielectric layer and improve the cutting and dicing processing efficiency.

[0022] (2) In the present invention, a matte structure is designed for the inner side wall of the light-through hole of the dielectric layer to reduce the reflectivity of the inner side wall of the dielectric layer, thereby reducing the influence of stray light on chip imaging and further improving product quality.

[0023] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a schematic diagram of the traditional wafer-level packaging structure;

[0025] Figure 2 is a schematic diagram of the wafer-level packaging structure in Embodiment 1 of the present invention;

[0026] Figure 3 is a schematic structural diagram of a dielectric layer in Example 1 of the present invention;

[0027] Figure 4 It is a schematic diagram of a form of the lower surface of the dielectric layer in Example 1 of the present invention;

[0028] Figure 5 is a schematic diagram of another form of the lower surface of the dielectric layer in Example 1 of the present invention;

[0029] Figure 6 It is a schematic diagram of the wafer-level chip manufacturing process in Embodiment 2 of the present invention;

[0030] Figure 7 Schematic diagram of the extinction treatment on the inner side of the light through hole of the dielectric layer in the wafer-level packaging structure in Example 1 of the present invention; wherein, (a) the inner side wall surface of the light through hole is a rough surface structure, (b) the inner side wall surface of the light through hole is coated with a light-absorbing film layer, and (c) the inner side wall surface of the light through hole is a step structure.

[0031] Explanation of the reference numerals in the accompanying drawings: 1. Window piece; 2. Metal solder layer; 3. Chip layer; 4. Dielectric layer; 5. Light-through hole; 6. Scribing groove; 7. Alignment mark; 8. Rough surface structure; 9. Light-absorbing film layer; 10. Step structure. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0033] In the description of the present invention, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0034] In the description of the present invention, it should be noted that, unless otherwise clearly stipulated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, a conflicting connection or an integral connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0035] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features; in the description of the present invention, unless otherwise specified, "multiple" and "several" mean two or more.

[0036] Embodiment 1:

[0037] like Figure 2 and Figure 3 As shown, this embodiment provides a wafer-level packaging structure, including a window piece 1, a chip layer 3 and a dielectric layer 4 arranged between the window piece 1 and the chip layer 3, the window piece 1 and the chip layer 3 are respectively bonded to the corresponding side surfaces of the dielectric layer 4, the dielectric layer 4 has a plurality of light holes 5 corresponding to the functional areas on the chip layer 3, the light holes 5 are used to allow light passing through the window piece 1 to reach the surface of the chip layer 3, and a scribe groove 6 is provided on the dielectric layer 4, and the scribe groove 6 is located around the light hole 5. Among them, the dicing groove 6 is a groove with a certain width and depth, which is used to use a dicing machine to cut and scribble along the dicing groove 6 after the three-layer bonding of the window piece 1, the dielectric layer 4, and the chip layer 3 is completed to form a final wafer-level chip. The design of the dicing groove 6 can reduce the resistance of cutting and scribing the dielectric layer 4, and improve the efficiency of the cutting and scribing process; at the same time, in this embodiment, by adding the dielectric layer 4 between the window piece 1 and the chip layer 3, the distance between the window piece 1 and the chip layer 3 is increased, and the imaging abnormality problem caused by the defects on the surface of the window piece 1 on the chip is reduced, thereby improving the product yield; at the same time, in the wafer-level packaging structure in this embodiment, the window piece 1, the dielectric layer 4, and the chip layer 3 constitute three-layer bonding, and the bonding stress is relatively small, which effectively avoids the bonding stress of the traditional two-layer chip bonding, which is large and easy to cause chip warping and bonding difficulty.

[0038] Specifically, the scribe groove 6 described in the present embodiment can be opened on the upper surface of the dielectric layer 4 (i.e., the side of the dielectric layer 4 corresponding to the window plate 1), or can be opened on the lower surface of the dielectric layer 4 (i.e., the side of the dielectric layer 4 corresponding to the chip layer 3), and the scribe groove 6 can also be opened on both the upper surface and the lower surface of the dielectric layer 4; preferably, the scribe groove 6 is arranged on the side of the dielectric layer 4 corresponding to the chip layer 3, so as to prevent the cutter wheel from cutting into the circuit elements on the chip layer 3 during subsequent cutting and scribe operation.

[0039] Furthermore, the scribe grooves 6 are designed to be arranged in a grid shape, and the center of each grid is a light-through hole 5. Preferably, a hollow hole can also be designed in the scribe grooves 6, such as Figure 5 As shown, the hollow holes are arranged on the four sides of each grid of the dicing groove 6, the hollow holes are arranged discontinuously, and the hollow holes pass through the upper and lower surfaces of the dielectric layer 4; by designing the dicing groove 6 as a hollow structure, the remaining material area of ​​the dielectric layer 4 can be further reduced, so that the dicing knife resistance is smaller during cutting and dicing, reducing the difficulty of dicing and improving the processing efficiency.

[0040] Specifically, the dielectric layer 4 can be made of a material with certain strength and thermal stability, and the material of the dielectric layer 4 can be selected from but not limited to glass, metal, ceramic, etc. As for the thickness design of the dielectric layer 4, if the thickness of the dielectric layer 4 is too small, it cannot solve the imaging abnormality and processing difficulties caused by the defects on the surface of the existing window sheet 1 on the chip, and if the thickness of the dielectric layer 4 is too thick, it will affect the size of the chip's light field angle, thereby affecting the product quality. Therefore, after multiple tests and analyses, the thickness of the dielectric layer 4 is designed to be 0.5-1.0 mm in this embodiment.

[0041] The distribution of the light-through holes 5 on the dielectric layer 4 can be designed accordingly according to the arrangement of the positions of the chips on the chip layer 3 (i.e., the functional areas). For example, when the chips on the chip layer 3 are in an array structure, the light-through holes 5 on the dielectric layer 4 are evenly distributed in an array manner, and the light-through holes 5 on the dielectric layer 4 correspond one-to-one to the chips on the chip layer 3, so that after wafer-level bonding, light can pass through the window 1 and the light-through holes 5 to reach the chips on the chip layer 3.

[0042] Optionally, a metal solder layer 2 is plated on the surface of the dielectric layer 4 for bonding with the window sheet 1 and the chip layer 3. The metal of the metal solder layer 2 can be selected from but not limited to Cu, Ni, Sn, Ag, Au, etc., and alloy materials can also be selected, and the specific selection is made according to actual conditions.

[0043] Optionally, in order to facilitate the alignment of the dielectric layer 4 with the window sheet 1 and the chip layer 3 when bonding, an alignment mark 7 for aligning with the window sheet 1 and the chip layer 3 may be provided on the surface of the dielectric layer 4. Specifically, in some embodiments, the alignment mark 7 may be provided only on the upper surface of the dielectric layer 4. When the window sheet 1, the chip layer 3 and the dielectric layer 4 are aligned, the chip layer 3 is first placed above the lens, the lens is used to identify the mark on the chip layer 3 and the mark position is recorded, and then the dielectric layer 4 is placed between the chip layer 3 and the lens, and the side of the alignment mark 7 on the dielectric layer 4 is facing the lens, and the lens is used to identify the alignment mark 7 on the dielectric layer 4, so that it is aligned with the recorded mark on the chip layer 3, and then the window sheet 1 is placed between the dielectric layer 4 and the lens, and the lens is used to identify the mark on the window sheet 1, so that it is aligned with the alignment mark 7 on the dielectric layer 4. In other embodiments, the alignment mark 7 may also be provided on both the upper and lower surfaces of the dielectric layer 4, and the alignment marks 7 on the upper and lower surfaces of the dielectric layer 4 are used to align with the marks on the window sheet 1 and the chip layer 3, respectively. The alignment mark 7 is arranged on the dielectric layer 4 in structure and position according to the alignment mark points on the window sheet 1 and the chip layer 3. In order to make the alignment mark 7 clearly visible during bonding alignment, its shape can be designed to be a cross, a circle or other easily identifiable structure. The size of the alignment mark 7 can ensure that it can be clearly identified by the lens.

[0044] In order to reduce the impact of incident light on the chip imaging area caused by reflected light generated by the inner wall of the light hole 5 of the dielectric layer 4 after adding the dielectric layer 4 between the window 1 and the chip layer 3, the inner side of the light hole 5 of the dielectric layer 4 can be subjected to low reflection extinction treatment. For example, an extinction structure can be processed inside the light hole 5 to reduce the reflectivity of the inner wall of the light hole 5 of the dielectric layer 4, thereby reducing the impact of stray light on chip imaging. In some embodiments, Figure 7 As shown, the inner surface of the light hole 5 can be roughened to form a rough surface structure 8. The irregularity of the inner wall surface of the light hole 5 causes the incident light to be diffusely reflected or scattered, thereby reducing the intensity of the reflected light. In some embodiments, a light-absorbing film layer 9 can be added to the inner wall surface of the light hole 5, and the light absorption effect of the light-absorbing film layer 9 on light is used to reduce the adverse effects of the incident light irradiating the inner wall of the light hole 5. The light-absorbing film layer 9 can be an ultra-black nano film layer or a vacuum-deposited black light-absorbing film layer. The darker the material, the wider the light absorption range. The ultra-black film layer can absorb the light incident on the surface of the material, including ultraviolet light, visible light, near-infrared light, and light in the mid- and far-infrared bands. In some embodiments, the inner wall surface of the light hole 5 can also be designed as a step structure 10, and the light irradiated on the inner wall of the light hole 5 is reflected by the side wall to the horizontal step surface, thereby eliminating the impact of the incident light irradiating the side wall to generate reflected light on the chip imaging area.

[0045] Embodiment 2:

[0046] like Figure 6 As shown, this embodiment also provides a method for manufacturing a wafer-level chip, and the specific process is as follows:

[0047] S1, processing the dielectric layer 4, processing the light through hole 5, the alignment mark 7, the dicing groove 6, and the metal solder layer 2 on the dielectric layer 4. The structure of the dielectric layer 4 after processing is the same as the structure of the dielectric layer 4 in the above-mentioned embodiment 1.

[0048] Taking a glass sheet as the dielectric layer 4 as an example, the glass sheet is first cleaned with a cleaning solution to remove dirt on the surface; then, a light hole 5 and an alignment mark 7 are etched on the glass sheet by laser cutting and wet etching technology; then, a scribe groove 6 is etched on the back of the glass sheet by laser etching; finally, a metal solder layer 2 composed of titanium, copper, nickel and gold is electroplated on the surfaces of the front and back sides of the glass sheet in sequence by an electroplating process.

[0049] S2, aligning and bonding the front and back surfaces of the dielectric layer 4 with the window sheet 1 and the chip layer 3 respectively to obtain a wafer-level packaging structure.

[0050] Specifically, the back side of the dielectric layer 4 is aligned with the surface of the chip layer 3, and the bonding is achieved by heating and pressurizing; the front side of the semi-finished dielectric layer 4 after bonding is then aligned with the window sheet 1, and the three-layer bonding is achieved by heating and pressurizing again; of course, the dielectric layer 4 can also be bonded to the window sheet 1 first, and then bonded to the chip layer 3. The wafer-level packaging structure obtained in this step is the same as the wafer-level packaging structure in the above-mentioned embodiment 1.

[0051] S3, cutting and dicing the wafer-level packaging structure bonded in step S2 from the window 1 side corresponding to the two side walls of the dicing groove 6 to remove the window 1 and the dielectric layer 4 corresponding to the dicing groove 6 to expose the chip layer.

[0052] Since the surface of the chip layer 3 is provided with circuit components, the chip layer 3 is cut from the two side walls of the dicing groove 6 to remove the window plate 1 and the dielectric layer 4 corresponding to the dicing groove 6. On the one hand, the chip layer 3 is completely exposed, which is convenient for the subsequent dicing and cutting of the chip layer 3 without damaging the circuit components on the chip layer 3. On the other hand, the shielding of the circuit components on the chip layer 3 by the window plate 1 and the dielectric layer 4 is completely removed, which is also convenient for the detection and electrical connection of the circuit components on the chip layer 3 in the subsequent application process.

[0053] S4, dicing and cutting the chip layer 3 at the chip layer 3 exposed in step S3, so as to obtain a plurality of wafer-level chips.

[0054] The above examples are merely illustrative of the present invention and do not constitute a limitation on the protection scope of the present invention. All designs that are the same or similar to the present invention fall within the protection scope of the present invention.

Claims

1. A wafer-level packaging structure, characterized in that: It includes a window piece, a chip layer and a dielectric layer arranged between the window piece and the chip layer. The window piece and the chip layer are bonded to the corresponding side surfaces of the dielectric layer respectively. The dielectric layer has a plurality of light-through holes corresponding to the functional areas on the chip layer to allow the window piece to transmit light to the functional areas of the chip layer. The dielectric layer is provided with a scribe groove, and the scribe groove is located around the light-through hole.

2. The wafer-level packaging structure according to claim 1, wherein: The thickness of the dielectric layer is 0.5-1.0 mm.

3. The wafer-level packaging structure according to claim 1, wherein: The surface of the dielectric layer has an alignment mark for aligning with the window sheet and the chip layer.

4. The wafer-level packaging structure according to claim 1, wherein: The scribe groove is arranged on a side of the dielectric layer corresponding to the chip layer.

5. The wafer-level packaging structure according to claim 1, wherein: A hollow hole is provided in the dicing groove.

6. The wafer-level packaging structure according to claim 1, wherein: The hole wall of the light-through hole is processed with a matte structure.

7. The wafer-level packaging structure according to claim 6, wherein: The matt structure is at least one of a light absorbing film layer, a rough surface structure layer or a step structure.

8. The wafer-level packaging structure according to claim 1, wherein: The plurality of light-through holes are evenly distributed in an array.

9. The wafer-level packaging structure according to claim 1, wherein: The surface of the dielectric layer is plated with a metal solder layer, and is bonded to the window sheet and the chip layer via the metal solder layer.

10. A method for manufacturing a wafer-level chip, characterized in that: The steps include: S1. Processing a plurality of light-through holes penetrating the upper and lower surfaces of the dielectric layer, and processing dicing grooves between adjacent light-through holes on the lower surface of the dielectric layer; S2, aligning and bonding the upper and lower surfaces of the dielectric layer processed in step S1 with the window sheet and the chip layer respectively to obtain a wafer-level packaging structure; S3, cutting and dicing the wafer-level packaging structure bonded in step S2 from the window side at the positions of the two side walls of the dicing groove, so as to remove the window and dielectric layer portions corresponding to the dicing groove, and expose the chip layer; S4, dicing and cutting the chip layer at the chip layer exposed in step S3 to obtain a plurality of wafer-level chips.

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