Deposition device, semiconductor structure and manufacturing method thereof

Abstract

A deposition apparatus includes a first chamber, a substrate support, a second chamber, a showerhead, a first reactant inlet, a second reactant, and a precursor inlet. The first chamber includes a diffusion region and a reaction region, the diffusion region being located above the reaction region. The substrate support is disposed within the reaction zone. The second chamber is disposed above the first chamber. The nozzle is arranged between the first chamber and the second chamber. The first reactant inlet is in communication with the second chamber. And the second reactant inlet is communicated with the reaction area of the first chamber. The precursor inlet is communicated with the spray head. The film with better quality can be deposited through the deposition device.

Description

Technical Field

[0001] The present disclosure relates to a deposition device, a semiconductor structure, and a method for manufacturing a semiconductor structure. Background Art

[0002] The integration density of various electronic components such as transistors, diodes, resistors, capacitors, etc. continues to improve in the semiconductor industry by continuously reducing the minimum feature size. As the feature size decreases, the distance between metal features also continues to decrease. As the distance between metal features decreases, the parasitic capacitance generated between metal features increases, resulting in higher power consumption and larger resistance-capacitance (RC) time delay for the integrated chip. To improve performance and reduce parasitic capacitance between metal features, materials with low dielectric constant (k) values ​​are used. However, this dielectric material encounters many processing problems that prevent further improvement of the dielectric constant.

[0003] In the process of manufacturing semiconductor devices, it is necessary to deposit low-K spacers (LKS) with good uniformity on different substrate surfaces. These different surfaces can be composed of different materials, such as metals and dielectrics. It may be beneficial to uniformly deposit a material on two or more different substrate surfaces, for example by reducing the number of steps in device manufacturing. There is also a need for dielectric materials with low dielectric constant (k) values ​​and low etching rates, for example in acid-based etching solutions such as HF. Summary of the invention

[0004] The present disclosure provides a deposition device. The deposition device includes a first chamber, a substrate support, a second chamber, a nozzle, a first reactant inlet, and a second reactant and precursor inlet. The first chamber includes a diffusion zone and a reaction zone, and the diffusion zone is located above the reaction zone. The substrate support is arranged in the reaction zone. The second chamber is arranged above the first chamber. The nozzle is arranged between the first chamber and the second chamber. The first reactant inlet is connected to the second chamber. The second reactant inlet is connected to the reaction zone of the first chamber. The precursor inlet is connected to the nozzle.

[0005] In some embodiments, the deposition apparatus further includes a first power source connected to the second chamber.

[0006] In some embodiments, the first power source includes a radio frequency source and a remote plasma generator coupled to the radio frequency source.

[0007] In some embodiments, the deposition apparatus further includes a second power source connected to the showerhead.

[0008] In some embodiments, the second power source is a radio frequency source.

[0009] In some embodiments, the deposition apparatus further comprises a fluid conduit partially covering the exterior of the showerhead.

[0010] In some embodiments, the transport fluid flowing in the fluid conduit comprises a perfluoropolyether.

[0011] In some embodiments, the deposition apparatus further includes a pump connected to the first chamber.

[0012] The present disclosure provides a method for manufacturing a semiconductor structure. The method includes the following steps. A first conductive feature structure is formed above a substrate. A first spacer is formed to cover the sidewalls of the first conductive feature structure, and the material of the first spacer includes SiCO. A second spacer is formed to cover the sidewalls of the first spacer, and the material of the second spacer is different from the material of the first spacer. A third spacer is formed to cover the sidewalls of the second spacer, and the material of the third spacer is different from the materials of the first spacer and the second spacer. A second conductive feature structure is formed adjacent to the third spacer.

[0013] In some embodiments, forming a first spacer layer to cover the sidewall of the first conductive feature structure includes the following steps. First, a structure having a first conductive feature structure above a substrate is placed on a substrate support in a deposition device. The deposition device includes a first chamber, a substrate support, a second chamber, a nozzle, a first reactant inlet, a second reactant and a precursor inlet. The first chamber includes a diffusion zone and a reaction zone, and the diffusion zone is located above the reaction zone. The substrate support is arranged in the reaction zone. The second chamber is arranged above the first chamber. The nozzle is arranged between the first chamber and the second chamber. The first reactant inlet is connected to the second chamber. The second reactant inlet is connected to the reaction zone of the first chamber. The precursor inlet is connected to the nozzle. Then, the first reaction gas is allowed to flow from the first reactant inlet into the second chamber. The second reaction gas is allowed to flow from the second reactant inlet into the first chamber. The precursor is allowed to flow from the precursor inlet into the nozzle. Next, atomic layer deposition is performed so that the first spacer layer covers the sidewall of the first conductive feature structure.

[0014] In some embodiments, the first reactant gas includes H2, He, and O2.

[0015] In some embodiments, the second reactant gas comprises NF3, Ar, and O2.

[0016] The present disclosure provides a semiconductor structure. The semiconductor structure includes a bit line structure, a first spacer, a second spacer, a third spacer, and a buried contact. The bit line structure is disposed on a substrate. The first spacer is disposed on a sidewall of the bit line structure, and the material of the first spacer includes SiCO. The second spacer is disposed on a sidewall of the first spacer. The third spacer is disposed on a sidewall of the second spacer, and the materials of the second spacer and the third spacer are different from the material of the first spacer. The buried contact is disposed adjacent to the third spacer.

[0017] In some embodiments, the semiconductor structure further includes a landing pad disposed on the bit line structure and the first spacer layer.

[0018] In some embodiments, the landing pad is in direct contact with the bit line structure, the first spacer layer, and the buried contact.

[0019] In some embodiments, the landing pad directly contacts a portion of the top surface of the first spacer layer.

[0020] In some embodiments, another portion of the top surface of the first spacer layer is exposed.

[0021] In some embodiments, another portion of the top surface of the first spacer layer that is exposed is lower than a portion of the top surface of the first spacer layer that contacts the landing pad.

[0022] It is to be understood that both the foregoing general description and the following detailed description are by way of example, and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] When reading the accompanying drawings, the various aspects of the present disclosure can be fully understood from the following detailed description. It is worth noting that, according to standard practice in the industry, the various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of the various features can be arbitrarily increased or reduced.

[0024] Figure 1 is a schematic diagram of a deposition apparatus according to some embodiments.

[0025] Figure 2 is a cross-sectional view of a semiconductor structure at one of various stages of formation in accordance with some embodiments.

[0026] Figure 3 is a cross-sectional view of a semiconductor structure at one of various stages of formation in accordance with some embodiments.

[0027] Figure 4 is a cross-sectional view of a semiconductor structure at one of various stages of formation in accordance with some embodiments.

[0028] Figure 5 is a cross-sectional view of a semiconductor structure at one of various stages of formation in accordance with some embodiments.

[0029] Figure 6 is a cross-sectional view of a semiconductor structure at one of various stages of formation in accordance with some embodiments.

[0030] Figure 7 is a cross-sectional view of a semiconductor structure at one of various stages of formation in accordance with some embodiments.

[0031] Figure 8 is a cross-sectional view of a semiconductor structure according to some embodiments. DETAILED DESCRIPTION

[0032] The following will disclose multiple embodiments of the present disclosure with the accompanying drawings. For the purpose of clear description, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. And for the sake of clarity, the size or thickness of the components may be exaggerated and not drawn according to the original size. In addition, in order to simplify the drawings, some conventional structures and components will be depicted in a simple schematic manner in the drawings.

[0033] The following disclosure provides many different embodiments or examples to realize the different features of each embodiment. The following describes specific examples of parts and arrangements to simplify the present disclosure. Of course, these examples are only examples and are not intended to be restrictive. For example, the formation of the first feature above or on the second feature in the subsequent description may include an embodiment in which the first and second features are formed as direct contacts, and may also include an embodiment in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat element symbols and / or letters in each example. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0034] Spatially relative terms such as "below", "under", "above", "on", etc. are used in this article to facilitate the description of the relative relationship between one element or feature and another element or feature, as shown in the figure. The true meaning of these spatially relative terms includes other orientations. For example, when the figure is flipped 180 degrees up and down, the relationship between one element and another element may change from "below" or "under" to "above" or "on". In addition, the spatially relative descriptions used in this article should also be interpreted in the same way.

[0035] Figure 1 1 is a schematic diagram of a deposition device 10 according to some embodiments. Specifically, the deposition device 10 is a chemical vapor deposition (CVD) device. The deposition device 10 is suitable for performing a chemical vapor deposition process (hereinafter referred to as a deposition process) on a substrate 100. The substrate 100 may include a semiconductor layer, a conductive layer and / or an insulating layer. In some embodiments, the substrate 100 includes a stack of semiconductor layers. For example, the substrate 100 includes a stack of semiconductor layers on an insulator, such as a germanium crystal structure on an insulator (SOI), a germanium crystal structure on a sapphire substrate, or a germanium structure on an insulator.

[0036] According to some embodiments, the deposition device 10 is a plasma chemical vapor deposition device, such as remote high density plasma atomic layer deposition (RHDALD). Figure 1 The deposition apparatus 10 includes a first chamber 110, a substrate support 120, a second chamber 130, a showerhead 140, a first reactant inlet 150, a second reactant inlet 160, and a precursor inlet 170. More specifically, the first chamber 110 includes a diffusion zone 114 and a reaction zone 112, and the diffusion zone 114 is located above the reaction zone 112.

[0037] Reference Figure 1 , a substrate support 120 is disposed in the reaction zone 112. The substrate support 120 is used to support the substrate 100. The substrate support 120 typically includes a heating element (not shown). Preferably, the substrate support 120 is movably disposed in the reaction zone 112 via a shaft 121, which extends through the bottom of the first chamber 110 to be connected to a drive system (not shown). Internally movable lifting pins (not shown) may be disposed in the substrate support 120 to engage the lower surface of the substrate 100. A support ring (not shown) is also disposed above the substrate support 120. The support ring may be part of a plurality of sets of substrate supports, including a cover ring and a capture ring. The lifting pins act on the ring to receive the substrate 100 before processing, or to lift the substrate 100 after deposition to be transferred to the next station.

[0038] Although not all are specifically shown in detail, when the first chamber 110 and the second chamber 130 are installed in a clean room or manufacturing facility, the first chamber 110 and the second chamber 130 are generally connected to the facility. The facility includes a piping system that provides process gases, vacuum, temperature control, and environmental particle control, etc. When installed in the target manufacturing facility, these facilities are coupled to the first chamber 110 and the second chamber 130. In addition, the first chamber 110 can be coupled to a transfer chamber that will enable a robot to transfer a substrate (e.g., a semiconductor wafer) into and out of the first chamber 110 using automation.

[0039] Reference Figure 1, the second chamber 130 is disposed above the first chamber 110. The showerhead 140 is disposed between the first chamber 110 and the second chamber 130. In some embodiments, the showerhead 140 includes aluminum, an aluminum alloy (e.g., 5083 or 6063 aluminum alloy), stainless steel (e.g., stainless steel 304 or 316), hastelloy (e.g., hastelloy C22), or titanium. In some embodiments, the showerhead 140 is heated to about 120°C-300°C, such as about 180°C, during the deposition process. In some embodiments, the temperature of the showerhead 140 can be, for example, but not limited to, about 120°C, 130°C, 140°C, 150°C, 160°C, 170°C, 180°C, 190°C, 200°C, 210°C, 220°C, 230°C, 240°C, 250°C, 260°C, 270°C, 280°C, 290°C, or 300°C, including any range between any two of the foregoing values. The showerhead 140 is provided with a plurality of distribution holes 140h through which the processing gas or the purge gas flows. In some embodiments, the distribution holes 140h are arranged in an array. Through the distribution holes 140h, the reaction gas can flow uniformly to the diffusion region 114.

[0040] See also Figure 1 , the first reactant inlet 150 is connected to the second chamber 130. In some embodiments, the first reactant gas flows from the first reactant inlet 150 into the second chamber 130. For example, the first reactant gas includes H2, He and O2. In some embodiments, the deposition apparatus 10 also includes a first power source 182 connected to the second chamber 130. For example, the first power source 182 includes a radio frequency (RF) source and a remote plasma generator coupled to the RF. In some examples, the remote plasma generator includes a microwave-based remote plasma generator, a plasma tube or other types of remote plasma generators. The first power source 182 is configured to convert the first reactant gas into high-density plasma radicals.

[0041] See also Figure 1 , the second reactant inlet 160 is connected to the reaction zone 112 of the first chamber 110. In some examples, the second reactant gas flows into the reaction zone 112 from the second reactant inlet 160. For example, the second reactant gas includes NF3, Ar and O2. The precursor inlet 170 is connected to the shower head 140. In some embodiments, the deposition apparatus 10 also includes a second power source 184 connected to the shower head 140. For example, the second power source 184 includes a radio frequency (RF) source. The second power source 184 is configured to convert the precursor into plasma radicals.

[0042] In some embodiments, the deposition apparatus 10 further includes a fluid conduit 192 that partially covers the exterior of the showerhead 140. More specifically, the delivery fluid flowing in the fluid conduit 192 includes perfluoropolyether. The fluid conduit 192 has a serpentine shape in a top view and is composed of a series of parallel and equally spaced pipes. In other words, the fluid conduit 192 is defined by a continuous pipe that forms a back-and-forth path on the processing area.

[0043] In some embodiments, the deposition apparatus 10 further includes a pump 194 connected to the first chamber 110. The pump 194 may be used to control pressure and / or exhaust reactants from the first chamber 110. More specifically, gases (e.g., process gases, inert gases, reaction byproducts, etc.) are exhausted from the diffusion zone 114 by the vacuum pump 194. It should be understood that the diffusion zone 114 and the reaction zone 112 may be maintained under vacuum by the vacuum pump 194.

[0044] According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor structure (e.g., Figure 8 The method of the semiconductor structure 20 shown in FIG. Figures 2 to 8 are cross-sectional views of a semiconductor structure at various stages of formation according to some embodiments.

[0045] Various operations of the embodiments are provided herein. The order of describing some or all operations should not be interpreted as implying that these operations must rely on the order. With the benefit of this description, alternative sequencing will be understood. In addition, it should be understood that not all operations must be present in each embodiment provided herein. Moreover, it should be understood that not all operations are required in some embodiments.

[0046] Reference Figure 2 , a first conductive feature structure 210 is formed above the substrate 200. In some embodiments, the first conductive feature structure 210 may be a bit line structure. In some embodiments, a plurality of bit line structures 210 protrude from the substrate 200, such as Figure 2 shown.

[0047] The substrate 200 may include a plurality of isolation regions (not shown) and a plurality of active regions (not shown). More specifically, the active regions are separated by isolation regions. The substrate 200 may include, for example, silicon (e.g., polycrystalline silicon, crystalline silicon, or amorphous silicon). In some embodiments, the substrate 200 may include other elemental semiconductors, such as germanium. In some embodiments, the substrate 200 may include alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium indium phosphide, etc. In some embodiments, the substrate 200 may include compound semiconductors, such as silicon carbide, gallium arsenide, indium phosphide, indium arsenide, etc. In addition, the substrate 200 may optionally include a semiconductor-on-insulator (SOI) structure.

[0048] In some embodiments, the isolation region may be formed by a shallow trench isolation (STI) process. The isolation region may include, for example, a material including at least one of silicon oxide, silicon nitride, and silicon oxynitride. The isolation region may be a single layer including one insulator, a double layer including two insulators, or a multilayer including a combination of at least three insulators. For example, the isolation region may include silicon oxide and silicon nitride. For example, the isolation region may include three layers, the three layers including silicon oxide, silicon nitride, and silicon oxynitride.

[0049] In some embodiments, an insulating layer 204 is formed over the substrate 200 to cover the top surface of the active region and the isolation region in the substrate 200. The insulating layer 204 is made of any suitable dielectric material, such as silicon oxide, boro-phospho silicate glass (BPSG), or traethylorthosilicate (TEOS), but the present disclosure is not limited to the above materials.

[0050] During the formation of the insulating layer 204, an opening (not shown) may expose a portion of the active region of the substrate 200 and define a direct contact 206. The opening (not shown) is then filled with a conductive material to form the direct contact 206. The direct contact 206 directly contacts a portion of the active region of the substrate 200, resulting in an electrical connection between the direct contact 206 and the active region.

[0051] In some embodiments, a plurality of first conductive features 210 (eg, bit line structures) protrude from the substrate 200, such as Figure 2As shown. The first conductive feature structures 210 may be regularly arranged above the substrate 200 at substantially equal intervals. The first conductive feature structure 210 may also include two parts along a vertical direction substantially perpendicular to the substrate 200 (for example, along the Z direction): a conductive layer 212 located at a lower portion and an insulating layer 214 located at an upper portion.

[0052] The formation of the conductive layer 212 and the insulating layer 214 may include sequentially forming a conductive material layer and an insulating material layer above the substrate 200. The insulating material layer may be formed on the conductive material layer. In one embodiment, the conductive material layer and the insulating material layer may be etched substantially simultaneously to form the conductive layer 212 and the insulating layer 214. Therefore, the first conductive feature structure 210 including the conductive layer 212 and the insulating layer 214 may be spaced apart from each other in a first direction (e.g., X direction) and extend parallel to each other along a second direction (e.g., Y direction). In another embodiment, the insulating material layer is etched into a desired pattern and used as a mask pattern on the conductive material layer. Using the patterned insulating material layer as an etching mask, the conductive material layer is etched to form the conductive layer 212.

[0053] In some embodiments, the conductive layer 212 includes at least one material selected from a semiconductor doped with impurities, a metal, a conductive metal nitride, and a metal silicide. In some embodiments, the conductive layer 212 may have a stacked structure. For example, the conductive layer 212 may be stacked with a material including doped polysilicon and a metal nitride or a metal such as tungsten, tungsten nitride, and / or titanium nitride.

[0054] In some embodiments, the insulating layer 214 includes silicon nitride. A vertical length (eg, a length along the Z-axis direction) of the insulating layer 214 may be greater than a vertical length of the conductive layer 212 .

[0055] Reference Figure 3 , a first spacer 222 is formed to cover the sidewalls of the first conductive feature structure 210. Specifically, the material of the first spacer 222 includes SiCO. In one embodiment, the first spacer 222 is composed of SiCO. Then, the second spacer 224 covers the sidewalls of the first spacer 222. Specifically, the material of the second spacer 224 is different from the material of the first spacer 222. In one embodiment, the material of the second spacer 224 includes an oxide. For example, the second spacer 224 may include a silicon oxide layer. Next, a third spacer 226 covers the sidewalls of the second spacer 224. Specifically, the material of the third spacer 226 is different from the material of the first spacer 222 and the second spacer 224. In one embodiment, the material of the third spacer 226 includes a nitride. For example, the third spacer 226 may include silicon nitride.

[0056] It should be noted that the first spacer layer 222 is composed of SiCO, and the dielectric constant (k) of SiCO is about 4.3, which reduces the first conductive feature structure 210 and the second conductive feature structure 230 (such as Figure 6 The parasitic capacitance between the first spacer layer 222 and the first spacer layer 222 formed by the deposition device 10 disclosed in the present invention can reduce plasma induced damage (PID), thereby preventing damage to the semiconductor structure and reducing film pinholes, thereby having better consistency. The pinhole-free SiCO film has excellent wet etching selectivity, can resist subsequent processes (such as etching and / or cleaning), and has excellent air tightness to protect the underlying layer (such as metal oxidation). Replacing the original SiN film (k value of about 7.6) with a SiCO low-k film not only has a lower k (about 4.3) to reduce parasitic capacitance, but also has better film quality.

[0057] The first spacer layer 222 is formed by the aforementioned deposition device 10 (such as Figure 1 First, a structure having a first conductive feature structure 210 above a substrate 200 is placed on a substrate support 120 in a deposition apparatus 10. The deposition apparatus 10 is already in Figure 1 10. The first reaction gas flows into the second chamber 130 from the first reactant inlet 150. The first reaction gas includes H2, He and O2. The second reaction gas flows into the first chamber 110 from the second reactant inlet 160. In some embodiments, the second reaction gas includes NF3, Ar and O2. The precursor flows into the shower head 140 from the precursor inlet 170. Next, atomic layer deposition is performed in the deposition device 10 to form a first spacer layer 222 covering the sidewalls of the first conductive feature structure 210.

[0058] The second spacer layer 224 and the third spacer layer 226 may be formed by any suitable deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). In other embodiments, any suitable etching method, such as reactive ion etching (RIE), may be implemented on the first spacer layer 222, the second spacer layer 224, and / or the third spacer layer 226 to form a specific configuration according to the design of the semiconductor device. For example, the second spacer layer 224 may not be as high as the first spacer layer 222 and / or the third spacer layer 226.

[0059] Reference Figure 4 In some embodiments, the first spacer 222, the second spacer 224, and the third spacer 226 may be etched to expose a portion 210P of the first conductive feature 210. Alternatively, in other embodiments, the first spacer 222, the second spacer 224, and the third spacer 226 may be etched to expose the top surface of the first conductive feature 210. In other words, the top surfaces of the first spacer 222, the second spacer 224, and the third spacer 226 may be flush with the top surface of the first conductive feature 210.

[0060] Reference Figure 5 , a portion 210P of the first conductive feature structure 210 may form a curved surface or a relatively rounded surface after the etching process. In other words, the top surface of the first conductive feature structure 210 is not a flat surface. In some embodiments, Figure 5 The configuration of the curved surface shown is for illustration purposes only. According to some other embodiments of the present disclosure, other configurations may be formed by using different parameters in the etching process.

[0061] Reference Figure 6 , the second conductive feature structure 230 is formed adjacent to the third spacer layer 226. In some embodiments, the second conductive feature structure 230 may be a buried contact. Specifically, the second conductive feature structure 230 is disposed between adjacent first conductive feature structures 210 and is in direct contact with the third spacer layer 226. The second conductive feature structure 230 includes a silicon-containing material. In some embodiments, the second conductive feature structure 230 may include doped polysilicon.

[0062] Reference Figure 7 , landing pad material 240 is formed on first conductive feature 210 and between two adjacent first conductive feature 210. In some embodiments, a top surface of landing pad material 240 is higher than a top surface of first conductive feature 210. Specifically, landing pad material 240 covers a portion 210P of first conductive feature 210 and side surfaces and top surfaces of first spacer layer 222, second spacer layer 224, and third spacer layer 226.

[0063] In some embodiments, the landing pad material 240 includes a conductive material. For example, the conductive material is a void-free structure. To achieve a void-free structure, forming the conductive material may include multiple deposition processes and etching processes. In some embodiments, a deposition / etch-back / deposition (dep / etch / dep) process is used to deposit the conductive material into a gap (not shown) between two adjacent first conductive feature structures 210. A dep-etch-dep process involves depositing the conductive material, then etching some of the conductive material to widen the opening of the gap (not shown), and then redepositing the conductive material.

[0064] The landing pad material 240 may be deposited using CVD, ALD, PVD, or other suitable deposition processes. In some embodiments, the deposition temperature used in the deposition process is in the range of about 280° C. to about 320° C. For example, the deposition temperature used in the deposition process may be 280° C., 290° C., 300° C., 310° C., or 320° C. The etching process performed after the deposition process includes using any suitable dry etching process and / or wet etching process. The landing pad material 240 may be stacked with a material including a metal nitride or a metal such as tungsten, tungsten nitride, and / or titanium nitride.

[0065] Reference Figure 8 , at least a portion of the landing pad material 240 is removed to form the landing pad 250. A mask pattern (not shown) may be formed on the landing pad material 240. Subsequently, the landing pad material 240 is etched using the mask pattern as an etching mask. In some embodiments, a portion of the first conductive feature structure 210 and the first spacer layer 222, the second spacer layer 224, and the third spacer layer 226 disposed on the sidewalls thereof or a portion of the landing pad material 240 may also be removed. After etching, the landing pad 250 is formed and the landing pads 250 may be separated from each other by the holes 260. In addition, the landing pad 250 is formed based on the landing pad material 240. Therefore, the landing pad 250 may include a void-free structure.

[0066] According to yet another aspect of the present disclosure, a semiconductor structure 20 is provided. Figure 82 is a cross-sectional view of a semiconductor structure 20 according to some embodiments. The semiconductor structure 20 includes a substrate 200, a bit line structure 210, a first spacer 222, a second spacer 224, a third spacer 226, and a buried contact 230. The bit line structure 210 is disposed on the substrate 200. The first spacer 222 is disposed on the sidewall of the bit line structure 210. The material of the first spacer 222 includes SiCO. The second spacer 224 is disposed on the sidewall of the first spacer 222. The third spacer 226 is disposed on the sidewall of the second spacer 224. The materials of the second spacer 224 and the third spacer 226 are different from the material of the first spacer 222. The buried contact 230 is disposed adjacent to the third spacer 226.

[0067] In some embodiments, the semiconductor structure 20 further includes a landing pad 250, a first spacer 222, a second spacer 224, a third spacer 226, and a buried contact 230 disposed on the bit line structure 210. The landing pad 250 directly contacts the bit line structure 210, the first spacer 222, and the buried contact 230. More specifically, the landing pad 250 directly contacts a portion of the top surface of the first spacer 222 and exposes another portion of the top surface of the first spacer 222. In some embodiments, the exposed other portion of the top surface of the first spacer 222 is lower than the portion of the top surface of the first spacer 222 that contacts the landing pad 250. The materials and formation methods of each element have been described in detail above and will not be repeated here.

[0068] The novel deposition device disclosed herein replaces the original SiN spacer in the semiconductor structure with a SiCO spacer to reduce parasitic capacitance. In addition, the SiCO spacer formed by the novel deposition device disclosed herein can reduce damage caused by plasma, thereby preventing damage to the semiconductor structure and reducing film pinholes, thereby having better consistency and film quality.

[0069] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the following claims.

[0070]

Explanation of symbols

[0071] 10: Deposition device

[0072] 100:Substrate

[0073] 110: First chamber

[0074] 112: Reaction zone

[0075] 114: Diffusion Zone

[0076] 120: substrate support

[0077] 121: Axis

[0078] 130: Second chamber

[0079] 140: Nozzle

[0080] 140h: distribution hole

[0081] 150: First reactant inlet

[0082] 160: Second reactant inlet

[0083] 170: Precursor entrance

[0084] 182: First power source

[0085] 184: Second power source

[0086] 192: Fluid conduit

[0087] 194: Pump

[0088] 20:Semiconductor structure

[0089] 200:Substrate

[0090] 204: Insulation layer

[0091] 206: Direct contact parts

[0092] 210: first conductive characteristic structure

[0093] 210P:Part

[0094] 212: Conductive layer

[0095] 214: Insulation layer

[0096] 222: First spacer layer

[0097] 224: Second spacer layer

[0098] 226: The third compartment

[0099] 230: Second conductive characteristic structure

[0100] 240: Landing pad material

[0101] 250: Landing Pad

[0102] 260: hole.

Claims

1. A deposition device, characterized in that: Include: A first chamber comprising a diffusion zone and a reaction zone, wherein the diffusion zone is located above the reaction zone; a substrate support disposed in the reaction zone; A second chamber, disposed above the first chamber; A nozzle is disposed between the first chamber and the second chamber; A first reactant inlet communicated with the second chamber; A second reactant inlet communicates with the reaction zone of the first chamber; and The precursor inlet is connected to the nozzle.

2. The deposition device according to claim 1, wherein: Also included is a first power source connected to the second chamber. 3 . The deposition apparatus of claim 2 , wherein the first power source comprises a radio frequency source and a remote plasma generator coupled to the radio frequency source.

4. The deposition device according to claim 1, wherein: Also included is a second power source connected to the showerhead. The deposition apparatus according to claim 4 , wherein the second power source is a radio frequency source.

6. The deposition device according to claim 1, wherein: A fluid conduit is also included that partially covers the exterior of the spray head. 7 . The deposition apparatus according to claim 6 , wherein the transport fluid flowing in the fluid conduit comprises perfluoropolyether.

8. The deposition device according to claim 1, wherein: A pump is also included that is connected to the first chamber.

9. A method for manufacturing a semiconductor structure, characterized in that: Include: forming a first conductive feature structure over the substrate; Forming a first spacer layer to cover the sidewall of the first conductive feature structure, wherein the material of the first spacer layer comprises SiCO; Forming a second spacer layer to cover the sidewall of the first spacer layer, wherein the material of the second spacer layer is different from the material of the first spacer layer; Forming a third spacer layer to cover the sidewall of the second spacer layer, wherein a material of the third spacer layer is different from the materials of the first spacer layer and the second spacer layer; as well as A second conductive feature is formed adjacent to the third spacer layer.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein forming the first spacer layer to cover the sidewall of the first conductive feature structure comprises: Placing a structure having the first conductive feature above the substrate on a substrate support in a deposition apparatus, wherein the deposition apparatus comprises: A first chamber comprising a diffusion zone and a reaction zone, wherein the diffusion zone is located above the reaction zone; The substrate support is disposed in the reaction zone; A second chamber, disposed above the first chamber; A nozzle is disposed between the first chamber and the second chamber; A first reactant inlet communicated with the second chamber; A second reactant inlet communicates with the reaction zone of the first chamber; and a precursor inlet, connected to the nozzle; Allowing a first reactant gas to flow from the first reactant inlet into the second chamber; Allowing a second reactant gas to flow from the second reactant inlet into the first chamber; Allowing a precursor to flow from the precursor inlet into the nozzle; as well as Atomic layer deposition is performed so that the first spacer layer covers the sidewall of the first conductive feature structure. 11 . The method for manufacturing a semiconductor structure according to claim 10 , wherein the first reaction gas comprises H 2 , He and O 2 . 12 . The method for manufacturing a semiconductor structure according to claim 10 , wherein the second reaction gas comprises NF 3 , Ar and O 2 .

13. A semiconductor structure, characterized in that: Include: A bit line structure is disposed on a substrate; A first spacer layer is disposed on the sidewall of the bit line structure, wherein the material of the first spacer layer comprises SiCO; A second spacer layer is disposed on a side wall of the first spacer layer; A third spacer layer is disposed on the side wall of the second spacer layer, wherein the materials of the second spacer layer and the third spacer layer are different from the material of the first spacer layer; as well as A buried contact is disposed adjacent to the third spacer layer.

14. The semiconductor structure according to claim 13, wherein: The invention also comprises a landing pad which is arranged on the bit line structure and the first spacer layer. 15 . The semiconductor structure of claim 14 , wherein the landing pad directly contacts the bit line structure, the first spacer layer and the buried contact. The semiconductor structure according to claim 14 , wherein the landing pad directly contacts a portion of a top surface of the first spacer layer. 17 . The semiconductor structure according to claim 16 , wherein another portion of the top surface of the first spacer layer is exposed. 18 . The semiconductor structure according to claim 17 , wherein the other portion of the top surface of the first spacer layer exposed is lower than the portion of the top surface of the first spacer layer contacting the landing pad.

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