Epitaxial wafer and preparation method thereof

Abstract

The invention discloses an epitaxial wafer and a preparation method thereof, and belongs to the technical field of semiconductor manufacturing. The preparation method of the epitaxial wafer comprises the following steps: raising the temperature of a reaction cavity to a first annealing temperature T1; reducing the temperature of the reaction cavity from the first annealing temperature T1 to a second annealing temperature T2 so as to perform annealing treatment on the substrate in the reaction cavity; forming a buffer layer on the substrate; forming an epitaxial layer on one side, away from the substrate, of the buffer layer; wherein the first annealing temperature T1 and the second annealing temperature T2 meet the following condition: T2lt; t1. According to the invention, by annealing the substrate, part of stress in the substrate can be eliminated, and the contact surface between the substrate and the buffer layer can be improved, so that the BPD conversion rate can be improved, and the BPD defects are reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an epitaxial wafer and a method for preparing the same. Background Art

[0002] Silicon carbide (SiC) is a semiconductor material with excellent performance. It has outstanding advantages such as large bandgap, high thermal conductivity, high breakdown field strength, high electron saturation drift rate, high temperature resistance, and radiation resistance. In recent years, it has been widely used in important fields such as new energy vehicles, photovoltaic power generation, 5G communications, smart grids, and national defense. However, the generation of epitaxial layer defects restricts the improvement of product yield, thereby increasing production costs.

[0003] The defects in silicon carbide epitaxial layers mainly come from the extension of defects in the substrate (such as basal plane dislocations, screw dislocations, edge dislocations, etc.), and defects formed during the epitaxial growth process (such as triangle defects, carrot defects, drops, step aggregation, etc.). Among them, the basal plane dislocation (BPD) defect is a common linear dislocation in SiC crystals, located in the basal plane. BPD in epitaxy mainly comes from the replication of the substrate. Basal plane dislocations have a serious impact on the performance of bipolar devices, affecting the forward voltage drop of SiC bipolar devices, and providing nucleation points for the generation of stacking faults (SF), thereby causing the forward voltage of SiC bipolar devices to drift. Since most of the epitaxial wafers will eventually be used for power devices, it is very critical to control the BPD density in the epitaxial layer. Summary of the invention

[0004] The purpose of the present application is to provide a method for preparing an epitaxial wafer, which can reduce the BPD defect density of the epitaxial wafer and thus improve the product yield.

[0005] The present application provides a method for preparing an epitaxial wafer, comprising:

[0006] Raising the temperature of the reaction chamber to a first annealing temperature T1;

[0007] Lowering the temperature of the reaction chamber from the first annealing temperature T1 to a second annealing temperature T2 to perform annealing on the substrate in the reaction chamber;

[0008] forming a buffer layer on the substrate;

[0009] forming an epitaxial layer on a side of the buffer layer facing away from the substrate;

[0010] Wherein, the first annealing temperature T1 and the second annealing temperature T2 satisfy: T2 <T1。

[0011] In some embodiments, after the temperature of the reaction chamber is cooled from the first annealing temperature T1 to the second annealing temperature T2, the method further includes:

[0012] Raising the temperature of the reaction chamber from the second annealing temperature T2 to the etching temperature T3 to perform etching on the substrate;

[0013] The first annealing temperature T1, the second annealing temperature T2 and the etching temperature T3 satisfy: T2 <T3,T3≤T1。

[0014] In some embodiments, the first annealing temperature T1 satisfies: 1600°C≤T1≤1640°C.

[0015] In some embodiments, the second annealing temperature T2 satisfies: 1000°C≤T2≤1200°C.

[0016] In some embodiments, the annealing treatment lasts for 8 to 10 minutes.

[0017] In some embodiments, the etching temperature T3 satisfies: 1600°C≤T3≤1640°C.

[0018] In some embodiments, the etching process lasts for 7 to 10 minutes.

[0019] In some embodiments, a first carbon source and a first silicon source are introduced into the reaction chamber to form a buffer layer on the substrate;

[0020] A second carbon source and a second silicon source are introduced into the reaction chamber to form an epitaxial layer on a side of the buffer layer away from the substrate.

[0021] In some embodiments, before the second carbon source and the second silicon source are introduced into the reaction chamber, the method further comprises:

[0022] The flow rates of the second carbon source and the second silicon source are adjusted and stabilized to flow rates required for forming the epitaxial layer.

[0023] In some embodiments, the stabilization time is 30 to 60 seconds.

[0024] In some embodiments, the first carbon source includes a first carbon element, the second carbon source includes a second carbon element, and the ratio of the number of atoms of the first carbon element to the second carbon element is 0.1 to 0.3.

[0025] In some embodiments, the first silicon source includes a first silicon element, the second silicon source includes a second silicon element, and the ratio of the number of atoms of the first silicon element to the second silicon element is 0.25.

[0026] In some embodiments, the first carbon source includes a first carbon element, the first silicon source includes a first silicon element, the ratio of the number of atoms of the first carbon element to the first silicon element is a first carbon-silicon ratio w1, the second carbon source includes a second carbon element, the second silicon source includes a second silicon element, the ratio of the number of atoms of the first carbon element to the first silicon element is a second carbon-silicon ratio w2, and the first carbon-silicon ratio w1 and the second carbon-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1.

[0027] In some embodiments, the first carbon-to-silicon ratio w1 satisfies: 0.4≤w1≤0.6.

[0028] In some embodiments, the second carbon-to-silicon ratio w2 satisfies: 0.56≤w2≤0.96.

[0029] In some embodiments, the flow rate of the first carbon source is 15 to 22.5 sccm.

[0030] In some embodiments, the flow rate of the first silicon source is 75 sccm.

[0031] In some embodiments, the first carbon source is selected from at least one of ethylene, acetylene, methane, and propane.

[0032] In some embodiments, the first silicon source is selected from at least one of silane or silane derivatives.

[0033] In some embodiments, the flow rate of the second carbon source is 84-144 sccm.

[0034] In some embodiments, the flow rate of the second silicon source is 300 sccm.

[0035] In some embodiments, the second carbon source is selected from at least one of ethylene, acetylene, methane, and propane.

[0036] In some embodiments, the second silicon source is selected from at least one of silane or silane derivatives.

[0037] The second aspect of the present application provides an epitaxial wafer, which is prepared by the above-mentioned method for preparing an epitaxial wafer, and the epitaxial wafer comprises:

[0038] substrate;

[0039] a buffer layer, the buffer layer being located on one side of the substrate;

[0040] An epitaxial layer is located on a side of the buffer layer facing away from the substrate.

[0041] In some embodiments, the buffer layer has a first carbon-to-silicon ratio w1; the epitaxial layer has a second carbon-to-silicon ratio w2; the first carbon-to-silicon ratio w1 and the second carbon-to-silicon ratio w2 satisfy: 1.4w1 ≤ w2 ≤ 1.6w1.

[0042] In some embodiments, the first carbon-to-silicon ratio w1 satisfies: 0.4 ≤ w1 ≤ 0.6.

[0043] In some embodiments, the second carbon-to-silicon ratio w2 satisfies: 0.56 ≤ w2 ≤ 0.96.

[0044] In some embodiments, the thickness of the substrate is 340 - 360 μm.

[0045] In some embodiments, the thickness of the buffer layer is 0.8 - 1 μm.

[0046] In some embodiments, the thickness of the epitaxial layer is 9 - 13 μm.

[0047] The beneficial effects of the present application are as follows:

[0048] A method for preparing an epitaxial wafer provided by the present application includes: heating the temperature of the reaction chamber to a first annealing temperature T1; cooling the temperature of the reaction chamber from the first annealing temperature T1 to a second annealing temperature T2 to anneal the substrate located in the reaction chamber; forming a buffer layer on the substrate; forming an epitaxial layer on a side of the buffer layer facing away from the substrate; wherein, the first annealing temperature T1 and the second annealing temperature T2 satisfy: T2 < T1. By heating the temperature of the reaction chamber to the first annealing temperature T1 first and then cooling it from the first annealing temperature T1 to the second annealing temperature T2, the present application realizes annealing treatment of the substrate, can eliminate part of the stress in the substrate, and can also improve the contact surface between the substrate and the buffer layer, thereby improving the BPD conversion rate and reducing BPD defects. Description of the Drawings

[0049] Figure 1 It is a schematic structural diagram of the epitaxial wafer provided by the present application;

[0050] Figure 2 It is a flowchart of the method for preparing the epitaxial wafer provided by the embodiment of the present application;

[0051] Figure 3 It is a surface defect diagram of the epitaxial wafer provided by Embodiment 1 of the present application;

[0052] Figure 4 It is a surface defect diagram of the epitaxial wafer provided by Embodiment 2 of the present application;

[0053] Figure 5 It is a surface defect diagram of the epitaxial wafer provided by Comparative Example 1 of the present application;

[0054] Figure 6 A surface defect map of an epitaxial wafer provided for comparative example 2 of the present application;

[0055] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0056] 10. Substrate; 20. Buffer layer; 30. Epitaxial layer. DETAILED DESCRIPTION

[0057] The technical solution of the present application will be described clearly and completely below in conjunction with the embodiments and drawings of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. The various embodiments of the present application may exist in the form of a range; it should be understood that the description in the form of a range is only for convenience and simplicity, and should not be understood as a rigid limitation on the scope of the present application; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single values ​​within the range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5 and 6, which are applicable regardless of the range. In addition, whenever a numerical range is indicated in this article, it is meant to include any quoted numbers (fractions or integers) within the indicated range.

[0058] like Figure 1-Figure 2 As shown, the embodiment of the present application provides a method for preparing an epitaxial wafer, comprising:

[0059] Step S1: raising the temperature of the reaction chamber to a first annealing temperature T1;

[0060] Step S2: lowering the temperature of the reaction chamber from the first annealing temperature T1 to the second annealing temperature T2 to perform annealing on the substrate 10; wherein the first annealing temperature T1 and the second annealing temperature T2 satisfy: T2 <T1;

[0061] Step S3: forming a buffer layer 20 on the substrate 10;

[0062] Step S4 : forming an epitaxial layer 30 on the side of the buffer layer 20 facing away from the substrate 10 .

[0063] It can be understood that the present application performs annealing treatment on the substrate 10 by first raising the temperature of the reaction chamber to the first annealing temperature T1 and then cooling it from the first annealing temperature T1 to the second annealing temperature T2, thereby eliminating part of the stress in the substrate 10 and improving the contact surface between the substrate 10 and the buffer layer 20, thereby improving the BPD conversion rate, thereby reducing BPD defects and improving crystal quality.

[0064] In some embodiments, the step of raising the temperature of the reaction chamber to the first annealing temperature T1 includes:

[0065] The temperature of the reaction chamber is raised from the standby temperature T0 to the first annealing temperature T1.

[0066] In some embodiments, the standby temperature T0 satisfies: 800° C. ≤ T0 ≤ 900° C. Specifically, the standby temperature T0 may be any one of 800° C., 820° C., 840° C., 850° C., 860° C., 880° C., and 900° C., or a range consisting of any two of the values.

[0067] In some embodiments, the time for raising the temperature of the reaction chamber from the standby temperature T0 to the first annealing temperature T1 is the first heating time, and the first heating time is 10 to 13 minutes. Specifically, the first heating time can be any one of 10 minutes, 10.5 minutes, 11 minutes, 11.5 minutes, 12 minutes, 12.5 minutes, and 13 minutes, or a range consisting of any two values.

[0068] In some embodiments, after the temperature of the reaction chamber is raised to the first annealing temperature T1, the method further includes: performing a first heat preservation step to stabilize the temperature of the reaction chamber at the first annealing temperature T1.

[0069] In some embodiments, the time for performing the first insulation step is the first insulation time, and the first insulation time is 1 to 2 minutes. Specifically, the first insulation time can be any one of 1 minute, 1.5 minutes, and 2 minutes, or a range consisting of any two values.

[0070] In some embodiments, after the temperature of the reaction chamber is cooled from the first annealing temperature T1 to the second annealing temperature T2, the method further includes: performing a second heat preservation step to stabilize the temperature of the reaction chamber at the second annealing temperature T2.

[0071] In some embodiments, the time for performing the second insulation step is the second insulation time, and the second insulation time is 1 to 2 minutes. Specifically, the second insulation time can be any one of 1 minute, 1.5 minutes, and 2 minutes, or a range consisting of any two values.

[0072] In some embodiments, after the temperature of the reaction chamber is cooled from the first annealing temperature T1 to the second annealing temperature T2, the method further includes:

[0073] Raising the temperature of the reaction chamber from the second annealing temperature T2 to the etching temperature T3 to perform etching on the substrate 10;

[0074] The first annealing temperature T1, the second annealing temperature T2 and the etching temperature T3 satisfy: T2 <T3,T3≤T1。

[0075] It can be understood that by etching the substrate 10 , the contact surface between the substrate 10 and the buffer layer 20 can be cleaned and improved, thereby reducing the BPD defect density and further improving the crystal quality.

[0076] In some embodiments, the heating time for raising the temperature of the reaction chamber from the second annealing temperature T2 to the etching temperature T3 is the second heating time, and the second heating time is 10 to 13 minutes. Specifically, the second heating time can be any one of 10 minutes, 10.5 minutes, 11 minutes, 11.5 minutes, 12 minutes, 12.5 minutes, and 13 minutes, or a range consisting of any two values.

[0077] In some embodiments, an etching gas is introduced into the reaction chamber to perform an etching process on the substrate 10 .

[0078] In some embodiments, the etching gas is selected from hydrogen.

[0079] In some embodiments, after the temperature of the reaction chamber is raised from the second annealing temperature T2 to the etching temperature T3, the method further includes: performing a third heat preservation step to stabilize the temperature of the reaction chamber at the etching temperature T3.

[0080] In some embodiments, the time for performing the third insulation step is the third insulation time, and the third insulation time is 1 to 2 minutes. Specifically, the third insulation time can be any one of 1 minute, 1.5 minutes, and 2 minutes, or a range consisting of any two values.

[0081] In some embodiments, the first annealing temperature T1 satisfies: 1600° C. ≤ T1 ≤ 1640° C. Specifically, the first annealing temperature T1 may be any one of 1600° C., 1610° C., 1620° C., 1630° C., and 1640° C., or a range consisting of any two of the values.

[0082] In some embodiments, the second annealing temperature T2 satisfies: 1000° C. ≤ T2 ≤ 1200° C. Specifically, the second annealing temperature T2 may be any one of 1000° C., 1050° C., 1100° C., 1150° C., and 1200° C., or a range consisting of any two of the values.

[0083] In some embodiments, the annealing time is 8 to 10 minutes. Specifically, the annealing time can be any one of 8 minutes, 8.5 minutes, 9 minutes, 9.5 minutes, and 10 minutes, or a range consisting of any two of the values.

[0084] It can be understood that the present application achieves rapid annealing of the substrate 10 by completing the annealing treatment of the substrate 10 within 8 to 10 minutes, which can eliminate part of the stress in the substrate 10 and improve the contact surface between the substrate 10 and the buffer layer 20, thereby improving the BPD conversion rate, thereby reducing BPD defects and improving crystal quality.

[0085] In some embodiments, the etching temperature T3 satisfies: 1600° C. ≤ T3 ≤ 1640° C. Specifically, the etching temperature T3 may be any one of 1600° C., 1610° C., 1620° C., 1630° C., and 1640° C., or a range consisting of any two of the values.

[0086] In some embodiments, the etching time is 7 to 10 minutes. Specifically, the etching time can be any one of 7 minutes, 7.5 minutes, 8 minutes, 8.5 minutes, 9 minutes, 9.5 minutes, and 10 minutes, or a range consisting of any two of the values.

[0087] It can be understood that, in the present application, by etching the substrate 10 for 7 to 10 minutes, the contact surface between the substrate 10 and the buffer layer 20 can be cleaned and improved, thereby reducing the BPD defect density and further improving the crystal quality.

[0088] In some embodiments, a first carbon source and a first silicon source are introduced into the reaction chamber to form a buffer layer 20 on the substrate 10;

[0089] A second carbon source and a second silicon source are introduced into the reaction chamber to form an epitaxial layer 30 on a side of the buffer layer 20 facing away from the substrate 10 .

[0090] It can be understood that by passing the first carbon source and the first silicon source into the reaction chamber and controlling their flow rates, a buffer layer 20 is formed on the substrate 10, and by passing the second carbon source and the second silicon source into the reaction chamber and controlling their flow rates, an epitaxial layer 30 is formed on the side of the buffer layer 20 facing away from the substrate 10.

[0091] In some embodiments, before the second carbon source and the second silicon source are introduced into the reaction chamber, the method further comprises:

[0092] The flow rates of the second carbon source and the second silicon source are adjusted and stabilized to flow rates required for forming the epitaxial layer 30 .

[0093] It can be understood that by adjusting and stabilizing the flow rates of the second carbon source and the second silicon source to the flow rates required to form the epitaxial layer 30, and then introducing the second carbon source and the second silicon source into the reaction chamber to form the epitaxial layer 30, the growth rate of the epitaxial layer 30 can be kept constant, so that the conversion of BPD will also proceed stably, thereby reducing BPD defects and improving crystal quality.

[0094] In some embodiments, the stabilization time is 30 to 60 seconds. Specifically, the stabilization time can be any one of 30 seconds, 35 seconds, 40 seconds, 45 seconds, 50 seconds, 55 seconds, and 60 seconds, or a range consisting of any two of the values.

[0095] It can be understood that by adjusting the flow rates of the second carbon source and the second silicon source and then allowing the flow rates to stabilize for a certain period of time, the flow rates of the second carbon source and the second silicon source can be stabilized.

[0096] In some embodiments, the first carbon source includes a first carbon element, the second carbon source includes a second carbon element, and the ratio of the number of atoms of the first carbon element to the second carbon element is 0.1 to 0.3. Specifically, the ratio of the number of atoms of the first carbon element to the second carbon element can be any one of 0.1, 0.15, 0.2, 0.25, 0.3, or a range consisting of any two values.

[0097] It can be understood that the number of atoms of the first carbon element in the first carbon source is related to the flow rate and molecular formula of the first carbon source, and the number of atoms of the second carbon element in the second carbon source is related to the flow rate and molecular formula of the second carbon source. When the molecular formulas of the first carbon source and the second carbon source are the same, the ratio of the number of atoms of the first carbon element to the second carbon element is also the flow ratio of the first carbon source to the second carbon source.

[0098] In some embodiments, the first silicon source includes a first silicon element, the second silicon source includes a second silicon element, and the ratio of the number of atoms of the first silicon element to the second silicon element is 0.25.

[0099] It can be understood that the number of atoms of the first silicon element in the first silicon source is related to the flow rate and molecular formula of the first silicon source, and the number of atoms of the second silicon element in the second silicon source is related to the flow rate and molecular formula of the second silicon source. When the molecular formulas of the first silicon source and the second silicon source are the same, the ratio of the number of atoms of the first silicon element to the second silicon element is also the ratio of the flow rates of the first silicon source to the second silicon source.

[0100] In some embodiments, the first carbon source includes a first carbon element, the first silicon source includes a first silicon element, the ratio of the number of atoms of the first carbon element to the first silicon element is a first carbon-silicon ratio w1, the second carbon source includes a second carbon element, the second silicon source includes a second silicon element, the ratio of the number of atoms of the first carbon element to the first silicon element is a second carbon-silicon ratio w2, and the first carbon-silicon ratio w1 and the second carbon-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1. Specifically, the value of w2 / w1 can be any one of 1.4, 1.45, 1.5, 1.55, 1.6, or a range consisting of any two values.

[0101] It can be understood that the buffer layer 20 has a first carbon-to-silicon ratio w1, and the epitaxial layer 30 has a second carbon-to-silicon ratio w2. By controlling the growth process of the buffer layer 20 and the epitaxial layer 30, the first carbon-to-silicon ratio w1 and the second carbon-to-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1, which can reduce BPD defects and improve crystal quality.

[0102] In some embodiments, the first carbon-to-silicon ratio w1 satisfies: 0.4≤w1≤0.6. Specifically, the first carbon-to-silicon ratio W1 may be any one of 0.4, 0.45, 0.5, 0.55, and 0.6, or a range consisting of any two of the values.

[0103] It can be understood that the buffer layer 20 provides a flat surface during the epitaxial growth process, reducing the stress and defects of the substrate 10. The buffer layer 20 has a lower carbon-silicon ratio, which means that the silicon content in the buffer layer 20 is relatively high, while the carbon content is relatively low, which can reduce stress and BPD defects, thereby improving the crystal quality.

[0104] In some embodiments, the second carbon-to-silicon ratio w2 satisfies: 0.56≤w2≤0.96. Specifically, the second carbon-to-silicon ratio w2 may be any one of 0.56, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, and 0.96, or a range consisting of any two of the values.

[0105] It is understandable that the epitaxial layer 30 has a higher carbon-to-silicon ratio, which means that the carbon content in the epitaxial layer 30 is relatively high, while the silicon content is relatively low, which can reduce stress and BPD defects, thereby improving crystal quality.

[0106] In some embodiments, the flow rate of the first carbon source is 15 to 22.5 sccm. Specifically, the flow rate of the first carbon source can be any one of 15 sccm, 16 sccm, 17 sccm, 18 sccm, 19 sccm, 20 sccm, 21 sccm, 22 sccm, and 22.5 sccm, or a range consisting of any two of the values.

[0107] In some embodiments, the flow rate of the first silicon source is 75 sccm.

[0108] In some embodiments, the first carbon source is selected from at least one of ethylene, acetylene, methane, and propane.

[0109] In some embodiments, the first silicon source is selected from at least one of silane or silane derivatives.

[0110] In some embodiments, the silane derivative is selected from at least one of dichlorosilane, trichlorosilane, and tetrachlorosilane.

[0111] In some embodiments, the flow rate of the second carbon source is 84 to 144 sccm. Specifically, the flow rate of the second carbon source can be any one of 84 sccm, 90 sccm, 95 sccm, 100 sccm, 105 sccm, 110 sccm, 115 sccm, 120 sccm, 125 sccm, 130 sccm, 135 sccm, 140 sccm, and 145 sccm, or a range consisting of any two of the values.

[0112] In some embodiments, the flow rate of the second silicon source is 300 sccm.

[0113] In some embodiments, the second carbon source is selected from at least one of ethylene, acetylene, methane, and propane.

[0114] In some embodiments, the second silicon source is selected from at least one of silane or silane derivatives.

[0115] In some embodiments, the silane derivative is selected from at least one of dichlorosilane, trichlorosilane, and tetrachlorosilane.

[0116] In some embodiments, the first carbon source and the second carbon source can be the same or different.

[0117] In some embodiments, the first silicon source and the second silicon source can be the same or different.

[0118] In some embodiments, the formation temperature of the buffer layer 20 and the epitaxial layer 30 is the same as the etching temperature T3.

[0119] In some embodiments, after forming the epitaxial layer 30 on the side of the buffer layer 20 facing away from the substrate 10, the method further includes:

[0120] The temperature of the reaction chamber is cooled from the etching temperature T3 to the standby temperature T0.

[0121] In some embodiments, the time for cooling the temperature of the reaction chamber from the etching temperature T3 to the standby temperature T0 is the cooling time, and the cooling time is 10 to 13 minutes. Specifically, the cooling time can be any one of 10 minutes, 10.5 minutes, 11 minutes, 11.5 minutes, 12 minutes, 12.5 minutes, and 13 minutes, or a range consisting of any two values.

[0122] In some embodiments, the gas flow rate is directly controlled by a mass flow meter; the liquid flow rate is controlled by controlling the carrier gas flow rate to control the flow rate of the corresponding liquid.

[0123] The second aspect of the present application provides an epitaxial wafer, which is prepared by the above-mentioned method for preparing an epitaxial wafer, and the epitaxial wafer comprises:

[0124] Substrate 10;

[0125] A buffer layer 20, wherein the buffer layer 20 is located on one side of the substrate 10;

[0126] The epitaxial layer 30 is located on a side of the buffer layer 20 facing away from the substrate 10 .

[0127] In some embodiments, the buffer layer 20 has a first carbon-to-silicon ratio w1; the epitaxial layer 30 has a second carbon-to-silicon ratio w2; the first carbon-to-silicon ratio w1 and the second carbon-to-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1.

[0128] It can be understood that the buffer layer 20 has a first carbon-to-silicon ratio w1, and the epitaxial layer 30 has a second carbon-to-silicon ratio w2. By controlling the growth process of the buffer layer 20 and the epitaxial layer 30, the first carbon-to-silicon ratio w1 and the second carbon-to-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1, which can reduce BPD defects and improve crystal quality.

[0129] In some embodiments, the first carbon-to-silicon ratio w1 satisfies: 0.4≤w1≤0.6. Specifically, the first carbon-to-silicon ratio W1 may be any one of 0.4, 0.45, 0.5, 0.55, and 0.6, or a range consisting of any two of the values.

[0130] It can be understood that the buffer layer 20 provides a flat surface during the epitaxial growth process, reducing the stress and defects of the substrate 10. The buffer layer 20 has a lower carbon-silicon ratio, which means that the silicon content in the buffer layer 20 is relatively high, while the carbon content is relatively low, which can reduce stress and BPD defects, thereby improving the crystal quality.

[0131] In some embodiments, the second carbon-to-silicon ratio w2 satisfies: 0.56≤w2≤0.96. Specifically, the second carbon-to-silicon ratio w2 may be any one of 0.56, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, and 0.96, or a range consisting of any two of the values.

[0132] It is understandable that the epitaxial layer 30 has a higher carbon-to-silicon ratio, which means that the carbon content in the epitaxial layer 30 is relatively high, while the silicon content is relatively low, which can reduce stress and BPD defects, thereby improving crystal quality.

[0133] In one embodiment, the substrate 10 is made of silicon carbide.

[0134] In some embodiments, the thickness of the substrate 10 is 340-360 μm. Specifically, the thickness of the substrate 10 can be any one of 340 μm, 345 μm, 350 μm, 355 μm, and 360 μm, or a range consisting of any two of the values.

[0135] It is understandable that the substrate 10 is the basis for the formation of the buffer layer 20 and the epitaxial layer 30 ; the thickness of the substrate 10 is usually determined according to specific application requirements and preparation processes.

[0136] In some embodiments, the thickness of the buffer layer 20 is 0.8-1 μm. Specifically, the thickness of the buffer layer 20 can be any one of 0.8 μm, 0.85 μm, 0.9 μm, 0.95 μm, and 1 μm, or a range consisting of any two of the values.

[0137] It can be understood that the buffer layer 20 is used to reduce the defects on the substrate 10 from extending to the epitaxial layer 30. If the thickness of the buffer layer 20 is too thin, it may not be able to reduce the defects on the substrate 10. If the thickness of the buffer layer 20 is too thick, new defects may be introduced. Therefore, controlling the thickness of the buffer layer 20 to 0.8 to 1 μm can reduce the impact of the defects on the substrate 10 on the epitaxial layer 30, thereby improving the crystal quality.

[0138] In some embodiments, the thickness of the epitaxial layer 30 is 9-13 μm. Specifically, the thickness of the epitaxial layer 30 can be any one of 9 μm, 10 μm, 11 μm, 12 μm, and 13 μm, or a range consisting of any two of the values.

[0139] It is understood that the thickness of the epitaxial layer 30 has an important influence on the performance and characteristics of the semiconductor device. A thinner epitaxial layer 30 can provide better electron transport performance and higher carrier mobility, thereby improving the speed and efficiency of the device. On the other hand, a thicker epitaxial layer 30 can increase the capacity and current carrying capacity of the device; the thickness of the epitaxial layer 30 is usually determined according to the specific application requirements and the preparation process.

[0140] The present application will be described below with reference to specific embodiments.

[0141] Example 1

[0142] Step S11: placing a silicon carbide substrate in a reaction chamber of an epitaxial furnace, wherein the thickness of the silicon carbide substrate is 350 μm;

[0143] Step S12: raising the temperature of the reaction chamber from 850° C. (standby temperature T0) to 1640° C. (first annealing temperature T1) within 10 minutes, and keeping the temperature for 2 minutes;

[0144] Step S13: lowering the temperature of the reaction chamber from 1640° C. (first annealing temperature T1) to 1100° C. (second annealing temperature T2) within 9 minutes to anneal the silicon carbide substrate, and keeping the temperature for 2 minutes;

[0145] Step S14: raising the temperature of the reaction chamber from 1100° C. (second annealing temperature T2) to 1640° C. (etching temperature T3) within 10 minutes, and keeping the temperature for 2 minutes;

[0146] Step S15: introducing hydrogen (etching gas) into the reaction chamber to etch the silicon carbide substrate for 8 minutes;

[0147] Step S16: introducing ethylene (first carbon source) with a flow rate of 19 sccm and trichlorosilane (first silicon source) with a flow rate of 75 sccm into the reaction chamber to grow a silicon carbide buffer layer on the silicon carbide substrate. The growth time of the silicon carbide buffer layer is 7 min, the thickness of the silicon carbide buffer layer is 1 um, and the carbon-silicon ratio of the silicon carbide buffer layer (first carbon-silicon ratio w1) is 0.5;

[0148] Step S17: adjusting and stabilizing the flow rates of ethylene (second carbon source) and trichlorosilane (second silicon source) for 50 seconds to the flow rates required for forming the outer silicon carbide extension layer;

[0149] Step S18: Ethylene (the second carbon source) with a flow rate of 120 sccm and trichlorosilane (the second silicon source) with a flow rate of 300 sccm are introduced into the reaction chamber to form a silicon carbide epitaxial layer on the side of the silicon carbide buffer layer away from the silicon carbide substrate. The growth time of the silicon carbide epitaxial layer is 12 min, the thickness of the silicon carbide epitaxial layer is 10 um, and the carbon-silicon ratio of the silicon carbide epitaxial layer (the second carbon-silicon ratio w2) is 0.8.

[0150] Step S19: The temperature of the reaction chamber is cooled from 1640° C. (etching temperature T3) to 850° C. (standby temperature T0) within 10 minutes to obtain an epitaxial wafer.

[0151] Example 2

[0152] The preparation method of Example 2 is the same as that of Example 1, except that the flow rates of ethylene (the second carbon source) and trichlorosilane (the second silicon source) are adjusted and then directly introduced into the reaction chamber.

[0153] Comparative Example 1

[0154] The preparation method of Comparative Example 1 is the same as that of Example 1, except that the temperature of the reaction chamber is directly raised from 850° C. (standby temperature T0) to 1640° C. (etching temperature T3).

[0155] Comparative Example 2

[0156] The preparation method of Comparative Example 2 is the same as Example 2, except that the temperature of the reaction chamber is raised from 850°C (standby temperature T0) to 1640°C (etching temperature T3), and the flow rates of ethylene (the second carbon source) and trichlorosilane (the second silicon source) are adjusted and directly introduced into the reaction chamber.

[0157] Test method:

[0158] The BPD defect density of the epitaxial layer was tested using a surface defect tester (Candela8520 from KLA-Tencor). The test results are as follows: Figures 3 to 6 shown.

[0159] Table 1 shows the test results of Examples 1-2 and Comparative Examples 1-2.

[0160] Number of BPD defects Example 1 12 Example 2 23 Comparative Example 1 44 Comparative Example 2 76

[0161] Result analysis:

[0162] By comparing Example 1 with Example 2, it can be seen that by first raising the temperature of the reaction chamber to the first annealing temperature T1 and then cooling from the first annealing temperature T1 to the second annealing temperature T2, the silicon carbide substrate is annealed, part of the stress in the silicon carbide substrate can be eliminated, and the contact surface between the silicon carbide substrate and the silicon carbide buffer layer can be improved, thereby improving the BPD conversion rate and reducing BPD defects. At the same time, after the growth of the silicon carbide buffer layer is completed, the flow of ethylene (the second carbon source) and trichlorosilane (the second silicon source) is adjusted and stabilized for a certain period of time, and then ethylene (the second carbon source) and trichlorosilane (the second silicon source) are introduced into the reaction chamber to grow the silicon carbide epitaxial layer, so as to achieve a sudden change in the carbon-silicon ratio of the silicon carbide buffer layer and the silicon carbide epitaxial layer, and the growth rate of the silicon carbide epitaxial layer can be kept constant, so that the conversion of BPD will also be stable, thereby reducing BPD defects.

[0163] By comparing Example 1 with Comparative Example 1, it can be seen that by directly raising the temperature of the reaction chamber from 850°C (standby temperature T0) to 1640°C (etching temperature T3) without annealing the silicon carbide substrate, the stress in the silicon carbide substrate cannot be relieved, which reduces the conversion rate of BPD defects and increases BPD defects.

[0164] By comparing Example 1 and Comparative Example 2, it can be seen that by directly raising the temperature of the reaction chamber from 850°C (standby temperature T0) to 1640°C (etching temperature T3) without annealing the silicon carbide substrate, the stress in the silicon carbide substrate cannot be relieved, which reduces the conversion rate of BPD defects and increases the BPD defects; at the same time, since the flow rates of ethylene (the second carbon source) and trichlorosilane (the second silicon source) are adjusted and directly introduced into the reaction chamber, the flow rates of ethylene (the second carbon source) and trichlorosilane (the second silicon source) are not allowed to reach a stable state, making the growth rate of the silicon carbide epitaxial layer not constant, further reducing the conversion rate of BPD defects, thereby further increasing the BPD defects.

[0165] The above is a detailed introduction to the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for preparing an epitaxial wafer, characterized in that: include: Raising the temperature of the reaction chamber to a first annealing temperature T1; Lowering the temperature of the reaction chamber from the first annealing temperature T1 to a second annealing temperature T2 to perform annealing treatment on the substrate (10) located in the reaction chamber; forming a buffer layer (20) on the substrate (10); forming an epitaxial layer (30) on a side of the buffer layer (20) facing away from the substrate (10); Wherein, the first annealing temperature T1 and the second annealing temperature T2 satisfy: T2 <T1。 2. The method for preparing an epitaxial wafer according to claim 1, characterized in that: After the temperature of the reaction chamber is lowered from the first annealing temperature T1 to the second annealing temperature T2, the method further includes: Raising the temperature of the reaction chamber from the second annealing temperature T2 to the etching temperature T3 to perform etching on the substrate (10); The first annealing temperature T1, the second annealing temperature T2 and the etching temperature T3 satisfy: T2 <T3,T3≤T1。 3. The method for preparing an epitaxial wafer according to claim 2, characterized in that: The first annealing temperature T1 satisfies: 1600° C.≤T1≤1640° C.; and / or, The second annealing temperature T2 satisfies: 1000° C. ≤ T2 ≤ 1200° C.; and / or, The annealing treatment time is 8 to 10 minutes; and / or, The etching temperature T3 satisfies: 1600° C.≤T3≤1640° C.; and / or, The etching treatment time is 7 to 10 minutes.

4. The method for preparing an epitaxial wafer according to claim 1, characterized in that: introducing a first carbon source and a first silicon source into the reaction chamber to form a buffer layer (20) on the substrate (10); A second carbon source and a second silicon source are introduced into the reaction chamber to form an epitaxial layer (30) on a side of the buffer layer (20) facing away from the substrate (10).

5. The method for preparing an epitaxial wafer according to claim 4, characterized in that: Before introducing the second carbon source and the second silicon source into the reaction chamber, the method further comprises: The flow rates of the second carbon source and the second silicon source are adjusted and stabilized to flow rates required for forming the epitaxial layer (30).

6. The method for preparing an epitaxial wafer according to claim 5, characterized in that: The stabilization time is 30 to 60 seconds.

7. The method for preparing an epitaxial wafer according to claim 4, characterized in that: The first carbon source includes a first carbon element, the second carbon source includes a second carbon element, and the atomic ratio of the first carbon element to the second carbon element is 0.1 to 0.3; and / or, The first silicon source includes a first silicon element, the second silicon source includes a second silicon element, and the ratio of the number of atoms of the first silicon element to the number of atoms of the second silicon element is 0.

25.

8. The method for preparing an epitaxial wafer according to claim 4, characterized in that: The first carbon source includes a first carbon element, the first silicon source includes a first silicon element, the ratio of the number of atoms of the first carbon element to the first silicon element is a first carbon-silicon ratio w1, the second carbon source includes a second carbon element, the second silicon source includes a second silicon element, the ratio of the number of atoms of the first carbon element to the first silicon element is a second carbon-silicon ratio w2, and the first carbon-silicon ratio w1 and the second carbon-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1.

9. The method for preparing an epitaxial wafer according to claim 8, characterized in that: The first carbon-to-silicon ratio w1 satisfies: 0.4≤w1≤0.6; and / or, The second carbon-to-silicon ratio w2 satisfies: 0.56≤w2≤0.

96.

10. The method for preparing an epitaxial wafer according to claim 4, characterized in that: The flow rate of the first carbon source is 15 to 22.5 sccm; and / or, The flow rate of the first silicon source is 75 sccm; and / or, The first carbon source is selected from at least one of ethylene, acetylene, methane and propane; and / or, The first silicon source is selected from at least one of silane or silane derivatives; and / or, The flow rate of the second carbon source is 84 to 144 sccm; and / or, The flow rate of the second silicon source is 300 sccm; and / or, The second carbon source is selected from at least one of ethylene, acetylene, methane and propane; and / or, The second silicon source is selected from at least one of silane and silane derivatives.

11. An epitaxial wafer, characterized in that: The epitaxial wafer is prepared by the method for preparing an epitaxial wafer according to any one of claims 1 to 10, wherein the epitaxial wafer comprises: A substrate (10); A buffer layer (20), the buffer layer (20) being located on one side of the substrate (10); An epitaxial layer (30), the epitaxial layer (30) being located on a side of the buffer layer (20) facing away from the substrate (10).

12. The epitaxial wafer according to claim 11, characterized in that: The buffer layer (20) has a first carbon-to-silicon ratio w1; the epitaxial layer (30) has a second carbon-to-silicon ratio w2; the first carbon-to-silicon ratio w1 and the second carbon-to-silicon ratio w2 satisfy: 1.4w1≤w2≤1.6w1.

13. The epitaxial wafer according to claim 12, characterized in that: The first carbon-to-silicon ratio w1 satisfies: 0.4≤w1≤0.6; and / or, The second carbon-to-silicon ratio w2 satisfies: 0.56≤w2≤0.96; and / or, The thickness of the substrate (10) is 340 to 360 μm; and / or, The thickness of the buffer layer (20) is 0.8 to 1 μm; and / or, The thickness of the epitaxial layer (30) is 9-13 μm.

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