Fault detection circuit, fault detection method and fault detection system

Abstract

The invention provides a fault detection circuit, a fault detection method and a fault detection system. The circuit comprises a detected circuit which comprises a first circuit and a second circuit; the detection circuit at least comprises a first voltage dividing unit, a second voltage dividing unit, a third voltage dividing unit and a fourth voltage dividing unit, one end of the second voltage dividing unit is connected with the first circuit, and one end of the fourth voltage dividing unit is connected with the second circuit; the deserializer chip unit at least comprises a first input end, a second input end, a first data transmission interface, a second data transmission interface and an output end, the first input end and the second input end are used for receiving output signals of the detection circuit, the first data transmission interface is connected with the first circuit, and the second data transmission interface is connected with the second circuit; the output end is used for outputting a fault detection signal, and the fault detection signal is a signal representing whether the detected circuit has a fault or not. According to the invention, the problem that whether a fault occurs in the circuit cannot be detected in the prior art is solved.

Description

Technical Field

[0001] The present application relates to the technical field of fault detection, and in particular to a fault detection circuit, a fault detection method and a fault detection system. Background Art

[0002] At present, vehicle-mounted cameras are widely used, and GMSL (Gigabit Multimedia Serial Link, GMSL for short) serial link has become the mainstream method. A video input display system for a vehicle instrument is proposed in the prior art, and a video input display system for a vehicle instrument is disclosed, wherein the video fusion chip of the system is connected to the video input interface of the display screen via a data line, the control interface of the video fusion chip is connected to the instrument MCU (vehicle control unit, Main Control Unit, MCU for short) via a signal line, and the video output interface of the instrument MCU is connected to the video input interface of the video fusion chip via a signal line. In the video input display system via the FPD-Link / GMSL serial link, the video fusion chip of the system is connected to the video input interface of the display screen via a data line, but the control circuit cannot detect whether the GMSL serial link fails.

[0003] It can be seen that, in the current vehicle-mounted camera application, once the problem of being unable to recognize the camera or display screen occurs, it is impossible to determine whether it is caused by the above-mentioned GMSL serial link failure, that is, it is impossible to detect whether the GMSL serial link fails. Summary of the invention

[0004] The main purpose of the present application is to provide a fault detection circuit, a fault detection method and a fault detection system, so as to at least solve the problem in the prior art that it is impossible to detect whether a circuit has a fault.

[0005] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a fault detection circuit is provided, including: a detected circuit, including a first circuit and a second circuit; a detection circuit, including at least a first voltage divider unit, a second voltage divider unit, a third voltage divider unit and a fourth voltage divider unit, one end of the second voltage divider unit is connected to the first circuit, and one end of the fourth voltage divider unit is connected to the second circuit; a deserializer chip unit, including at least a first input end, a second input end, a first data transmission interface, a second data transmission interface and an output end, the first input end and the second input end are used to receive an output signal of the detection circuit, the first data transmission interface is connected to the first circuit, the second data transmission interface is connected to the second circuit, and the output end is used to output a fault detection signal, and the fault detection signal is a signal characterizing whether a fault occurs in the detected circuit.

[0006] Optionally, the detection circuit also includes: a fifth voltage-dividing unit, one end of the fifth voltage-dividing unit is connected to one end of the fourth voltage-dividing unit, and the other end of the fifth voltage-dividing unit is connected to the second circuit; a switching unit, including at least a first end and a second end, the first end of the switching unit is connected to an end where the fifth voltage-dividing unit and the fourth voltage-dividing unit are connected; a power supply voltage, respectively connected to one end of the first voltage-dividing unit and one end of the third voltage-dividing unit; a first capacitor, one end of the first capacitor is connected to the first circuit, and the other end of the first capacitor is connected to the first data transmission interface; a second capacitor, one end of the second capacitor is connected to the second circuit, and the other end of the second capacitor is connected to the second data transmission interface.

[0007] Optionally, the fault detection circuit also includes: an integrated chip connected to the second end of the switch unit; a serializer chip unit, including at least a serializer chip, a sixth voltage divider unit and a seventh voltage divider unit, the serializer chip being respectively connected to the first circuit and the second circuit of the detected circuit, one end of the sixth voltage divider unit being connected to the first circuit, the other end of the sixth voltage divider unit being grounded, one end of the seventh voltage divider unit being connected to the second circuit, and the other end of the seventh voltage divider unit being grounded.

[0008] Optionally, the other end of the first voltage divider unit is connected to the other end of the second voltage divider unit, and the connection port forms a first output end, the first output end is connected to the first input end, the other end of the third voltage divider unit is connected to the other end of the fourth voltage divider unit, and the connection end interface forms a second output end, and the second output end is connected to the second input end.

[0009] According to another aspect of the present application, a fault detection method is provided, which is applied to any one of the fault detection circuits, and the fault detection method includes: when the switch unit is disconnected, obtaining a first output voltage of a first output terminal and a second output voltage of a second output terminal of the detection circuit; when the first output voltage is greater than a maximum preset threshold and the second output voltage is greater than the maximum preset threshold, determining that a power short circuit fault occurs in the detected circuit; when at least the first output voltage is less than a minimum preset threshold, determining that a short circuit to ground occurs in the detected circuit; and when the first output voltage is equal to the power supply voltage and the second output voltage is equal to the power supply voltage, determining that an open circuit fault occurs in the detected circuit.

[0010] Optionally, the detected circuit has a first connection mode and a second connection mode, and at least when the first output voltage is less than a minimum preset threshold, it is determined that the detected circuit has a short-circuit fault to ground, including: when the first output voltage is less than the minimum preset threshold, it is determined that the first connection mode of the detected circuit has the short-circuit fault to ground; when the first output voltage is less than the minimum preset threshold and the second output voltage is less than the minimum preset threshold, it is determined that the second connection mode of the detected circuit has the short-circuit fault to ground.

[0011] Optionally, the method also includes: when the switch unit is turned on, obtaining a first output voltage of the first output terminal and a second output voltage of the second output terminal; when the first output voltage is less than the minimum preset threshold and the second output voltage is less than the minimum preset threshold, determining that an inter-circuit short circuit fault occurs in the detected circuit, and outputting a low-level fault detection signal, wherein the inter-circuit short circuit fault indicates that a short circuit fault occurs between the first circuit and the second circuit of the detected circuit.

[0012] Optionally, when the switch unit is turned on, the method further includes: when the first output voltage is greater than the minimum preset threshold and less than the maximum preset threshold and the second output voltage is less than the minimum preset threshold, determining that the detected circuit does not have the inter-circuit short circuit fault.

[0013] Optionally, the method further comprises: in case of the power supply short circuit fault, the ground short circuit fault and the open circuit fault, outputting a low level fault detection signal.

[0014] According to another aspect of the present application, a fault detection system is provided, comprising: any one of the fault detection circuits described above; a controller, comprising one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include methods for executing any one of the fault detection methods described above.

[0015] The technical solution of the present application is applied, the detected circuit includes a first circuit and a second circuit; the detection circuit includes at least a first voltage divider unit, a second voltage divider unit, a third voltage divider unit and a fourth voltage divider unit, one end of the second voltage divider unit is connected to the first circuit, and one end of the fourth voltage divider unit is connected to the second circuit; the deserializer chip unit includes at least a first input end, a second input end, a first data transmission interface, a second data transmission interface and an output end, the first input end and the second input end are used to receive the output signal of the detection circuit, the first data transmission interface is connected to the first circuit, the second data transmission interface is connected to the second circuit, and the output end is used to output a fault detection signal, which is a signal that characterizes whether the detected circuit has a fault. Compared with the prior art, which cannot detect whether the detected circuit has a fault, the present application detects whether the detected circuit has a fault by setting a detection circuit, and outputs a fault detection signal through the deserializer chip unit, therefore, it can solve the problem that the detected circuit cannot be detected in the prior art, and achieve the effect of accurately detecting the fault of the detected circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 A schematic diagram of the structure of a fault detection circuit provided in an embodiment of the present application is shown;

[0018] Figure 2 A schematic diagram showing the structure of another fault detection circuit provided in an embodiment of the present application is shown;

[0019] Figure 3 A hardware structure block diagram of a mobile terminal for executing a fault detection method provided in an embodiment of the present application is shown;

[0020] Figure 4 A schematic diagram of a flow chart of a fault detection method provided in an embodiment of the present application is shown;

[0021] Figure 5 An equivalent circuit diagram when a fault occurs provided by an embodiment of the present application is shown;

[0022] Figure 6 An equivalent circuit diagram provided by an embodiment of the present application when no fault occurs is shown;

[0023] Figure 7 A flowchart of a specific fault detection method provided in an embodiment of the present application is shown.

[0024] The above drawings include the following reference numerals:

[0025] 102, processor; 104, memory; 106, transmission device; 108, input and output devices. DETAILED DESCRIPTION

[0026] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] For the convenience of description, some nouns or terms involved in the embodiments of the present application are explained below:

[0030] GMSL: Gigabit Multimedia Serial Link, referred to as GMSL;

[0031] SER: Serializer, SER for short;

[0032] DES: Deserializer, Deserializeer, referred to as DES;

[0033] MIPI: Mobile Industry Processor Interface, referred to as MIPI;

[0034] CSI2: Mainly used for the connection between the camera module and the processor, Camera Serial Interface 2, referred to as CSI2;

[0035] COAX: Coaxial Cable, referred to as COAX;

[0036] STP: Shielded Twisted Pair, referred to as STP.

[0037] The vehicle-mounted high-definition camera module has a built-in SER serial chip, which is connected to the DES deserialization chip through a GMSL link (usually COAX or STP). The deserialization chip generates multiple MIPI signals and transmits them to the SOC chip (System on Chip, SOC for short, with video encoding and ISP modules). After image processing inside the SOC, the image information processed by the SOC is sent to the serial chip for video output through MIPI or LVDS signals (an electrical signal transmission technology, Low Voltage Differential Signaling, LVDS for short), and finally connected to the display screen through the GMSL link to complete the image display of the video acquisition. When the deserialization / serialization chip cannot recognize the camera or display screen, it is impossible to determine whether it is caused by a GMSL link failure.

[0038] As introduced in the background technology, the prior art is unable to detect whether a GMSL circuit has a fault. To solve the problem of being unable to detect whether a circuit has a fault, the embodiments of the present application provide a fault detection circuit, a fault detection method and a fault detection system.

[0039] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0040] This embodiment provides a fault detection circuit, such as Figure 1 As shown, including:

[0041] The detected circuit includes a first circuit and a second circuit;

[0042] Specifically, in this embodiment, the detected circuit is a GMSL (Gigabit Multimedia Serial Link, GMSL for short) serial link, such as Figure 1In the Connector part, Connector means that the link is a communication connection. The link can be a COAX (COAX: coaxial cable, Coaxial Cable, referred to as COAX) or STP (Shielded Twisted Pair, Shielded Twisted Pair, referred to as STP) twisted pair. One line in the twisted pair is the first circuit, and the other line is the second circuit.

[0043] A detection circuit, comprising at least a first voltage dividing unit, a second voltage dividing unit, a third voltage dividing unit and a fourth voltage dividing unit, wherein one end of the second voltage dividing unit is connected to the first circuit, and one end of the fourth voltage dividing unit is connected to the second circuit;

[0044] Specifically, each of the above-mentioned voltage dividing units can be a resistor, such as Figure 1 As shown, a first voltage divider unit R1, a second voltage divider unit R2, a third voltage divider unit R3 and a fourth voltage divider unit R4, wherein R1=R3=45.3kΩ, R2=4.99kΩ, R4=2kΩ, one end of R2 is connected to the first circuit, and one end of R4 is connected to the second circuit. In actual application, one end of R2 can also be connected to the second circuit, and one end of R4 can also be connected to the first circuit.

[0045] The deserializer chip unit comprises at least a first input terminal, a second input terminal, a first data transmission interface, a second data transmission interface and an output terminal, wherein the first input terminal and the second input terminal are used to receive an output signal of the detection circuit, the first data transmission interface is connected to the first circuit, the second data transmission interface is connected to the second circuit, and the output terminal is used to output a fault detection signal, wherein the fault detection signal is a signal characterizing whether a fault occurs in the detected circuit.

[0046] Specifically, the deserializer chip unit is Figure 1 In the block diagram unit where the DES chip is located, LMN0 and LMN1 are input to the first input terminal and the second input terminal respectively, and compared with the threshold value set by the output logic comparison module (OUTPUT LOGIC) in the chip. The set threshold value is output through the reference voltage module (Reference Voltage Generator), and the output threshold voltage is V OH 、V DDIO and V OL, the comparison result is output through the output terminal " / ERR". The first data transmission interface is SIOP (an interface standard for data transmission, in which non-inverted coax / twisted-pair serial data transmission is used, Noninverted Coax / Twisted-Pair Serial-Data), and the second data transmission interface is SION (refers to a method of transmitting data through an inverted twisted pair, the data signal is encoded and transmitted through a reversely twisted twisted pair to reduce electromagnetic interference and signal loss, Inverted Twisted-Pair Serial-Data). In actual application, the first data transmission interface can also be SION, and the second data transmission interface is SIOP. This circuit can detect whether the GMSL circuit is shorted to power, shorted to ground, or open circuit. When normally connected, the voltage of LMN0 and LMN1 is the detected divided voltage, which is equal to V DDIO / 2.

[0047] In some optional embodiments, the detection circuit also includes: a fifth voltage divider unit, one end of the fifth voltage divider unit is connected to one end of the fourth voltage divider unit, and the other end of the fifth voltage divider unit is connected to the second circuit; a switch unit, including at least a first end and a second end, the first end of the switch unit is connected to an end where the fifth voltage divider unit and the fourth voltage divider unit are connected; a power supply voltage, respectively connected to one end of the first voltage divider unit and one end of the third voltage divider unit; a first capacitor, one end of the first capacitor is connected to the first circuit, and the other end of the first capacitor is connected to the first data transmission interface; a second capacitor, one end of the second capacitor is connected to the second circuit, and the other end of the second capacitor is connected to the second data transmission interface.

[0048] Specifically, in order to identify whether a short circuit fault occurs between two lines when the GMSL is an STP twisted pair, Figure 1 The circuit is further improved by adding a switch unit, which can be an NMOS resistor. At the same time, the R4 resistor is changed to two resistors, namely R4 and R5, which are 2kΩ and 3.01kΩ respectively. R5 is used as the fifth voltage divider unit, such as Figure 2 When the link is COAX, a short circuit occurs between the links, and the diagnosis result is a short-to-ground fault. The optimized circuit is mainly used to diagnose whether a short circuit occurs when the GMSL link is an STP twisted pair. Figure 2 In the case of Q1, Q1 uses an NMOS resistor, including three terminals, one of which is connected to the terminal connected to R4 and R5, the other is connected to the SOC or MCU (Vehicle Control Unit, Vehicle Control Unit, referred to as MCU), and the last terminal is grounded. Power supply voltage V DDIO=1.8V, connected to one end of R1 and R3 respectively. The detection circuit also includes a first capacitor C1 and a second capacitor C2, C1=C2=100nF, C1 is connected to the SIOP port, and C2 is connected to the SION port. In actual application, C1 can also be connected to the SION port, and C2 can be connected to the SIOP port.

[0049] In some optional embodiments, the fault detection circuit also includes: an integrated chip connected to the second end of the switch unit; a serializer chip unit, including at least a serializer chip, a sixth voltage divider unit and a seventh voltage divider unit, the serializer chip being respectively connected to the first circuit and the second circuit of the detected circuit, one end of the sixth voltage divider unit being connected to the first circuit, the other end of the sixth voltage divider unit being grounded, one end of the seventh voltage divider unit being connected to the second circuit, and the other end of the seventh voltage divider unit being grounded.

[0050] Specifically, integrated chips such as Figure 2 SOC or MCU in; serializer chip unit such as Figure 2 The block diagram unit where the SER chip is located, the serializer chip SER chip has two interfaces, each interface is connected to a capacitor, and is respectively connected to the sixth voltage divider unit R6 and the seventh voltage divider unit R7, and finally connected to the first circuit and the second circuit of the GMSL. R6 = R7 = 49.9 kΩ.

[0051] In some optional embodiments, the other end of the first voltage divider unit is connected to the other end of the second voltage divider unit, and the connection port forms a first output end, the first output end is connected to the first input end, the other end of the third voltage divider unit is connected to the other end of the fourth voltage divider unit, and the connection end interface forms a second output end, and the second output end is connected to the second input end.

[0052] In the specific implementation process, the connection ports R1 and R2 serve as the first output end to output the LMN0 signal, which is input into the first input end of the deserializer chip unit; the connection ports R3 and R4 serve as the second output end to output the LMN1 signal, which is input into the second input end of the deserializer chip unit to realize the transmission of the voltage signal.

[0053] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a mobile terminal as an example, Figure 3 FIG. 1 is a hardware structure block diagram of a mobile terminal of a fault detection method according to an embodiment of the present invention. Figure 3 As shown, the mobile terminal may include one or more ( Figure 3Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 3 The structure shown is only for illustration and does not limit the structure of the mobile terminal. Figure 3 More or fewer components as shown, or with Figure 3 Different configurations shown.

[0054] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the fault detection method in the embodiment of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, the above method is implemented. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories can be connected to the mobile terminal via a network. Examples of the above network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof. The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0055] In this embodiment, a fault detection method running on a mobile terminal, a computer terminal or a similar computing device is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0056] Figure 4 FIG. 1 is a flow chart of a fault detection method according to an embodiment of the present application. Figure 4 As shown, the method comprises the following steps:

[0057] Step S201, when the switch unit is disconnected, obtaining a first output voltage of a first output terminal and a second output voltage of a second output terminal of a detection circuit;

[0058] Specifically, the solution described in this embodiment is applied to Figure 1 and Figure 2 The above fault detection circuit is shown. This circuit can detect whether a short to power supply, short to ground, or open circuit fault occurs. When connected normally, the voltage of LMN0 and LMN1 is the divided voltage of the resistor network, which is equal to V DDIO / 2. The switch unit is Q1 mentioned above. When the switch unit is disconnected, Figure 2 The detection circuit in Figure 1 The fault detection method implemented by the circuit is the same as that of FIG. 1. By obtaining LMN0 (the first output voltage) and LMN1 (the second output voltage) and comparing them with the threshold, it is determined whether a fault occurs and what kind of fault occurs.

[0059] Step S202, when the first output voltage is greater than a maximum preset threshold and the second output voltage is greater than the maximum preset threshold, determining that a power short circuit fault occurs in the detected circuit;

[0060] Specifically, when a short circuit occurs, the voltage of LMN0 and LMN1 exceeds the maximum preset threshold value V of the I / O pin of the DES chip. OH , the internal voltage monitoring circuit determines that it is shorted to the power supply, and the detection result is that the " / ERR" pin output is 0, and the internal register of the DES chip reports a short-to-power supply fault. When detecting this fault, the GMSL serial link does not distinguish whether it is COAX or STP mode.

[0061] Step S203, determining that a short circuit to ground occurs in the detected circuit at least when the first output voltage is less than a minimum preset threshold value;

[0062] Specifically, when a short-to-ground fault occurs, the voltage of LMN0 is lower than the minimum preset threshold V of the I / O pin of the DES chip. OL The internal voltage monitoring circuit determines that it is shorted to ground, and the detection result is that the / ERR pin output is 0. At the same time, the internal register of the DES chip reports a short-to-ground fault.

[0063] Step S204: when the first output voltage is equal to the power supply voltage and the second output voltage is equal to the power supply voltage, determining that an open circuit fault occurs in the detected circuit.

[0064] Specifically, when open circuit, the voltage at the LMN0 and LMN1 pins is equal to the supply voltage V DDIO, the internal voltage monitoring circuit is judged as open circuit, the detection result is that the / ERR pin output is 0, and the internal register of the DES chip reports an open circuit fault.

[0065] Through this embodiment, when the switch unit is disconnected, the first output voltage of the first output terminal and the second output voltage of the second output terminal of the detection circuit are obtained; when the first output voltage is greater than the maximum preset threshold and the second output voltage is greater than the maximum preset threshold, it is determined that a power short circuit fault occurs in the detected circuit; when at least the first output voltage is less than the minimum preset threshold, it is determined that a short circuit fault occurs to the ground in the detected circuit; when the first output voltage is equal to the power supply voltage and the second output voltage is equal to the power supply voltage, it is determined that an open circuit fault occurs in the detected circuit. Compared with the prior art, which cannot detect whether the GMSL circuit has a fault, the present application can determine whether the detected circuit has a fault by comparing the output voltage of the detection circuit with the preset threshold, and therefore, it can solve the problem in the prior art that it is impossible to detect whether the GMSL serial link has a fault, and achieve the effect of detecting the fault of the circuit.

[0066] In the specific implementation process, the detected circuit has a first connection mode and a second connection mode. The above step S203 determines that the detected circuit has a short circuit to ground fault at least when the first output voltage is less than the minimum preset threshold value. It can be implemented by the following steps: when the first output voltage is less than the minimum preset threshold value, determine that the first connection mode of the detected circuit has the short circuit to ground fault; when the first output voltage is less than the minimum preset threshold value and the second output voltage is less than the minimum preset threshold value, determine that the second connection mode of the detected circuit has the short circuit to ground fault. The method can determine whether the two connection modes have faults respectively through the above steps, so that the fault point can be determined more accurately.

[0067] Specifically, if the serial link is the first connection mode COAX, when a short circuit occurs to the ground, because LMN1 is originally grounded, only the voltage of LMN0 is detected at this time. If the voltage of LMN0 is lower than the minimum threshold voltage V of the I / O pin of the DES chip, OL , at this time, the internal register of the DES chip reports a short-to-ground fault. If the serial link is the second connection mode STP, when a short-to-ground occurs, the voltages of LMN0 and LMN1 are both lower than the minimum threshold voltage V of the DES chip I / O pin. OL The internal voltage monitoring circuit determines that it is shorted to ground, and the detection result is that the / ERR pin output is 0. At the same time, the internal register of the DES chip reports a short-to-ground fault.

[0068] In some optional implementations, the method further includes the following steps: when the switch unit is turned on, obtaining the first output voltage of the first output terminal and the second output voltage of the second output terminal; when the first output voltage is less than the minimum preset threshold and the second output voltage is less than the minimum preset threshold, determining that a short circuit fault occurs between the detected circuit, and outputting a low-level fault detection signal, wherein the short circuit fault between the circuits indicates that a short circuit fault occurs between the first circuit and the second circuit of the detected circuit. The method further determines whether a fault occurs between the two circuits through the above steps, so that the fault can be detected more comprehensively.

[0069] In the specific implementation process, when the switch unit is turned on, the following Figure 2 The detection circuit shown is mainly used to diagnose whether a short circuit occurs when the GMSL link is an STP twisted pair. The signal between Q1 and the SOC or MCU is LINE_DIAG. When the LINE_DIAG signal is low, Q1 is disconnected. When LINE_DIAG becomes high, Q1 is turned on and connects the node between R4 and R5 to the ground. The equivalent circuit diagram when a fault occurs is shown in Figure 5 As shown in the figure, when the twisted pair is short-circuited, Q1 connects the node between R4 and R5 to the ground, but due to the twisted pair short circuit, this will affect the LMN0 level. When the supply voltage is 1.8V, the voltages of LMN0 and LMN1 will be lower than the VOL threshold voltage. Detection result: / ERR output becomes low level, and the internal register reports short-circuit faults for LMN0 and LMN1.

[0070] In some optional implementations, when the switch unit is turned on, the method further includes the following steps: when the first output voltage is greater than the minimum preset threshold and less than the maximum preset threshold and the second output voltage is less than the minimum preset threshold, determining that the detected circuit does not have the inter-circuit short-circuit fault. The method determines that the inter-circuit short-circuit fault does not occur through the above steps.

[0071] Specifically, the circuit diagram when no fault occurs is as follows: Figure 6 As shown in the figure, if there is no short circuit between the twisted pairs, Q1 connects the node between R4 and R5 to the ground. Under this condition, only LMN1 is affected by Q1, and the voltage of LMN0 is still at its normal level. However, when the supply voltage is 1.8V, the voltage of LMN1 is low enough, and the LMN1 line can be detected as shorted to the ground. The detection result is that the / ERR pin output of the DES chip becomes low, but at this time only the internal register of LMN1 is abnormal, and the LMN0 register is normal, so it is considered that there is no fault.

[0072] In some optional implementations, the method further comprises the following steps: in the case of the power short circuit fault, the ground short circuit fault and the open circuit fault, outputting a low-level fault detection signal. The method outputs a low-level fault detection signal in the above cases, which can indicate that a fault has occurred in the detected circuit.

[0073] During the specific implementation, as mentioned above, in the event of a failure, the output through the " / ERR" port of the DES chip is 0.

[0074] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, the implementation process of the fault detection method of the present application will be described in detail below in conjunction with specific embodiments.

[0075] This embodiment relates to a specific fault detection method, such as Figure 7 As shown, the following steps are included:

[0076] Step S1: When a short to the power supply occurs, the voltage of LMN0 and LMN1 exceeds the threshold voltage VOH of the IO pin of the DES chip, and the internal voltage monitoring circuit determines that it is short to the power supply. The detection result is that the output of the / ERR pin is 0, and the internal register of the DES chip reports a short to power supply fault;

[0077] Step S2: If the serial link is STP, when a short to ground occurs, the voltage of LMN0 and LMN1 is lower than the minimum threshold voltage VOL of the DES chip IO pin, and the internal voltage monitoring circuit determines that it is shorted to ground. The detection result is that the / ERR pin output is 0, and the internal register of the DES chip reports a short to ground fault;

[0078] Step S3: If the serial link is COAX, when a short circuit to ground occurs, because LMN1 is originally grounded, only the voltage of LMN0 is detected at this time. If the voltage of LMN0 is lower than the minimum threshold voltage VOL of the IO pin of the DES chip, the internal register of the DES chip reports a short circuit to ground fault;

[0079] Step S4: When the circuit is open, the voltage of the LMN0 and LMN1 pins is equal to VDDIO, and the internal voltage monitoring circuit determines that the circuit is open. The detection result is that the ERR pin output is 0, and the internal register of the DES chip reports an open circuit fault;

[0080] Step S5: When the twisted pair is short-circuited, the voltages of LMN0 and LMN1 will be lower than the VOL threshold voltage. Detection result: the ERR output becomes low level, and the internal register reports a short-circuit to ground fault for both LMN0 and LMN1.

[0081] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the fault detection method.

[0082] Specifically, the fault detection method includes:

[0083] Step S201, when the switch unit is disconnected, obtaining a first output voltage of a first output terminal and a second output voltage of a second output terminal of a detection circuit;

[0084] Specifically, the solution described in this embodiment is applied to Figure 1 and Figure 2 The above fault detection circuit is shown. This circuit can detect whether a short to power supply, short to ground, or open circuit fault occurs. When connected normally, the voltage of LMN0 and LMN1 is the divided voltage of the resistor network, which is equal to V DDIO / 2. The switch unit is Q1 mentioned above. When the switch unit is disconnected, Figure 2 The detection circuit in Figure 1 The fault detection method implemented by the circuit is the same as that of FIG. 1. By obtaining LMN0 (the first output voltage) and LMN1 (the second output voltage) and comparing them with the threshold, it is determined whether a fault occurs and what kind of fault occurs.

[0085] Step S202, when the first output voltage is greater than a maximum preset threshold and the second output voltage is greater than the maximum preset threshold, determining that a power short circuit fault occurs in the detected circuit;

[0086] Specifically, when a short circuit occurs, the voltage of LMN0 and LMN1 exceeds the maximum preset threshold value V of the I / O pin of the DES chip. OH , the internal voltage monitoring circuit determines that it is shorted to the power supply, and the detection result is that the " / ERR" pin output is 0, and the internal register of the DES chip reports a short-to-power supply fault. When detecting this fault, the GMSL serial link does not distinguish whether it is COAX or STP mode.

[0087] Step S203, determining that a short circuit to ground occurs in the detected circuit at least when the first output voltage is less than a minimum preset threshold value;

[0088] Specifically, when a short-to-ground fault occurs, the voltage of LMN0 is lower than the minimum preset threshold V of the I / O pin of the DES chip. OL The internal voltage monitoring circuit determines that it is shorted to ground, and the detection result is that the / ERR pin output is 0. At the same time, the internal register of the DES chip reports a short-to-ground fault.

[0089] Step S204: when the first output voltage is equal to the power supply voltage and the second output voltage is equal to the power supply voltage, determining that an open circuit fault occurs in the detected circuit.

[0090] Specifically, when open circuit, the voltage at the LMN0 and LMN1 pins is equal to the supply voltage V DDIO , the internal voltage monitoring circuit is judged as open circuit, the detection result is that the / ERR pin output is 0, and the internal register of the DES chip reports an open circuit fault.

[0091] An embodiment of the present invention provides a fault detection system, comprising any one of a fault detection circuit; a controller, comprising one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include a method for executing any one of the fault detection methods.

[0092] Step S201, when the switch unit is disconnected, obtaining a first output voltage of a first output terminal and a second output voltage of a second output terminal of a detection circuit;

[0093] Specifically, the solution described in this embodiment is applied to Figure 1 and Figure 2 The above fault detection circuit is shown. This circuit can detect whether a short to power supply, short to ground, or open circuit fault occurs. When connected normally, the voltage of LMN0 and LMN1 is the divided voltage of the resistor network, which is equal to V DDIO / 2. The switch unit is Q1 mentioned above. When the switch unit is disconnected, Figure 2 The detection circuit in Figure 1 The fault detection method implemented by the circuit is the same as that of FIG. 1. By obtaining LMN0 (the first output voltage) and LMN1 (the second output voltage) and comparing them with the threshold, it is determined whether a fault occurs and what kind of fault occurs.

[0094] Step S202, when the first output voltage is greater than a maximum preset threshold and the second output voltage is greater than the maximum preset threshold, determining that a power short circuit fault occurs in the detected circuit;

[0095] Specifically, when a short circuit occurs, the voltage of LMN0 and LMN1 exceeds the maximum preset threshold value V of the I / O pin of the DES chip. OH , the internal voltage monitoring circuit determines that it is shorted to the power supply, and the detection result is that the " / ERR" pin output is 0, and the internal register of the DES chip reports a short-to-power supply fault. When detecting this fault, the GMSL serial link does not distinguish whether it is COAX or STP mode.

[0096] Step S203, determining that a short circuit to ground occurs in the detected circuit at least when the first output voltage is less than a minimum preset threshold value;

[0097] Specifically, when a short circuit to ground occurs, the voltage of LMN0 is lower than the minimum preset threshold V of the I / O pin of the DES chip. OL The internal voltage monitoring circuit determines that it is shorted to ground, and the detection result is that the / ERR pin output is 0. At the same time, the internal register of the DES chip reports a short-to-ground fault.

[0098] Step S204: when the first output voltage is equal to the power supply voltage and the second output voltage is equal to the power supply voltage, determining that an open circuit fault occurs in the detected circuit.

[0099] Specifically, when open circuit, the voltage at the LMN0 and LMN1 pins is equal to the supply voltage V DDIO , the internal voltage monitoring circuit is judged as open circuit, the detection result is that the / ERR pin output is 0, and the internal register of the DES chip reports an open circuit fault.

[0100] The present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the method described in each embodiment of the present application:

[0101] Step S201, when the switch unit is disconnected, obtaining a first output voltage of a first output terminal and a second output voltage of a second output terminal of a detection circuit;

[0102] Specifically, the solution described in this embodiment is applied to Figure 1 and Figure 2 The fault detection circuit is shown in the figure. This circuit can detect whether a short to power, short to ground, or open circuit fault occurs. When connected normally, the voltage of LMN0 and LMN1 is the voltage divided by the resistor network, which is equal to VDDIO / 2. The switch unit is Q1 mentioned above. When the switch unit is disconnected, Figure 2 The detection circuit in Figure 1 The fault detection method implemented by the circuit is the same as that of FIG. 1. By obtaining LMN0 (the first output voltage) and LMN1 (the second output voltage) and comparing them with the threshold, it is determined whether a fault occurs and what kind of fault occurs.

[0103] Step S202, when the first output voltage is greater than a maximum preset threshold and the second output voltage is greater than the maximum preset threshold, determining that a power short circuit fault occurs in the detected circuit;

[0104] Specifically, when a short circuit occurs, the voltage of LMN0 and LMN1 exceeds the maximum preset threshold value VOH of the DES chip I / O pin, and the internal voltage monitoring circuit determines that it is shorted to the power supply. The detection result is that the " / ERR" pin output is 0, and the internal register of the DES chip reports a short circuit to the power supply fault. When detecting this fault, the GMSL serial link does not distinguish whether it is COAX or STP mode.

[0105] Step S203, determining that a short circuit to ground occurs in the detected circuit at least when the first output voltage is less than a minimum preset threshold value;

[0106] Specifically, when a short circuit to ground occurs, the voltage of LMN0 is lower than the minimum preset threshold VOL of the DES chip I / O pin, and the internal voltage monitoring circuit determines that it is shorted to ground. The detection result is that the / ERR pin output is 0, and the internal register of the DES chip reports a short circuit to ground fault.

[0107] Step S204: when the first output voltage is equal to the power supply voltage and the second output voltage is equal to the power supply voltage, determining that an open circuit fault occurs in the detected circuit.

[0108] Specifically, when the circuit is open, the voltage of the LMN0 and LMN1 pins is equal to the power supply voltage VDDIO, the internal voltage monitoring circuit determines that it is an open circuit, the detection result is that the / ERR pin output is 0, and the internal register of the DES chip reports an open circuit fault.

[0109] Obviously, those skilled in the art should understand that the above modules or steps of the present invention can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order than here, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0110] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0111] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0112] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0113] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0114] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0115] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0116] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0117] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0118] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0119] 1) The fault detection circuit of the present application includes a detected circuit, including a first circuit and a second circuit; the detection circuit includes at least a first voltage divider unit, a second voltage divider unit, a third voltage divider unit and a fourth voltage divider unit, one end of the second voltage divider unit is connected to the first circuit, and one end of the fourth voltage divider unit is connected to the second circuit; the deserializer chip unit includes at least a first input end, a second input end, a first data transmission interface, a second data transmission interface and an output end, the first input end and the second input end are used to receive the output signal of the detection circuit, the first data transmission interface is connected to the first circuit, the second data transmission interface is connected to the second circuit, and the output end is used to output a fault detection signal, which is a signal that characterizes whether the detected circuit has a fault. Compared with the prior art, which cannot detect whether the detected circuit has a fault, the present application detects whether the detected circuit has a fault by setting a detection circuit, and outputs a fault detection signal through the deserializer chip unit, therefore, it can solve the problem that the detected circuit cannot be detected in the prior art, and achieve the effect of accurately detecting the fault of the detected circuit.

[0120] 2) The fault detection method of the present application obtains the first output voltage of the first output terminal and the second output voltage of the second output terminal of the detection circuit when the switch unit is disconnected; when the first output voltage is greater than the maximum preset threshold and the second output voltage is greater than the maximum preset threshold, it is determined that a power short circuit fault occurs in the detected circuit; when at least the first output voltage is less than the minimum preset threshold, it is determined that a short circuit to ground occurs in the detected circuit; when the first output voltage is equal to the power supply voltage and the second output voltage is equal to the power supply voltage, it is determined that an open circuit fault occurs in the detected circuit. Compared with the prior art, which is unable to detect whether a GMSL circuit has a fault, the present application can determine whether a detected circuit has a fault by comparing the output voltage of the detection circuit with the preset threshold, thereby solving the problem in the prior art that it is unable to detect whether a GMSL serial link has a fault, and achieving the effect of detecting the fault of the circuit.

[0121] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A fault detection circuit, characterized in that: include: The detected circuit includes a first circuit and a second circuit; A detection circuit, comprising at least a first voltage dividing unit, a second voltage dividing unit, a third voltage dividing unit and a fourth voltage dividing unit, wherein one end of the second voltage dividing unit is connected to the first circuit, and one end of the fourth voltage dividing unit is connected to the second circuit; The deserializer chip unit comprises at least a first input terminal, a second input terminal, a first data transmission interface, a second data transmission interface and an output terminal, wherein the first input terminal and the second input terminal are used to receive an output signal of the detection circuit, the first data transmission interface is connected to the first circuit, the second data transmission interface is connected to the second circuit, and the output terminal is used to output a fault detection signal, wherein the fault detection signal is a signal characterizing whether a fault occurs in the detected circuit.

2. The fault detection circuit according to claim 1, characterized in that: The detection circuit also includes: a fifth voltage dividing unit, one end of the fifth voltage dividing unit being connected to one end of the fourth voltage dividing unit, and the other end of the fifth voltage dividing unit being connected to the second circuit; a switch unit, comprising at least a first end and a second end, wherein the first end of the switch unit is connected to an end where the fifth voltage dividing unit and the fourth voltage dividing unit are connected; a power supply voltage, connected to one end of the first voltage dividing unit and one end of the third voltage dividing unit respectively; a first capacitor, one end of the first capacitor being connected to the first circuit, and the other end of the first capacitor being connected to the first data transmission interface; A second capacitor, one end of the second capacitor is connected to the second circuit, and the other end of the second capacitor is connected to the second data transmission interface.

3. The fault detection circuit according to claim 1, characterized in that: The fault detection circuit also includes: An integrated chip connected to the second end of the switch unit; A serializer chip unit at least includes a serializer chip, a sixth voltage divider unit and a seventh voltage divider unit, wherein the serializer chip is respectively connected to the first circuit and the second circuit of the detected circuit, one end of the sixth voltage divider unit is connected to the first circuit, and the other end of the sixth voltage divider unit is grounded, one end of the seventh voltage divider unit is connected to the second circuit, and the other end of the seventh voltage divider unit is grounded.

4. The fault detection circuit according to claim 1, characterized in that: The other end of the first voltage divider unit is connected to the other end of the second voltage divider unit, and the connection port forms a first output end, the first output end is connected to the first input end, the other end of the third voltage divider unit is connected to the other end of the fourth voltage divider unit, and the connection end interface forms a second output end, and the second output end is connected to the second input end.

5. A fault detection method, characterized in that: Applied to the fault detection circuit according to any one of claims 1 to 4, the fault detection method comprising: When the switch unit is disconnected, obtaining a first output voltage at the first output terminal and a second output voltage at the second output terminal of the detection circuit; When the first output voltage is greater than a maximum preset threshold and the second output voltage is greater than the maximum preset threshold, determining that a power short circuit fault occurs in the detected circuit; At least when the first output voltage is less than a minimum preset threshold, determining that a short circuit to ground occurs in the detected circuit; When the first output voltage is equal to the power supply voltage and the second output voltage is equal to the power supply voltage, it is determined that an open circuit fault occurs in the detected circuit.

6. The fault detection method according to claim 5, characterized in that: The detected circuit has a first connection mode and a second connection mode, and at least when the first output voltage is less than a minimum preset threshold, determining that the detected circuit has a short circuit to ground fault includes: When the first output voltage is less than the minimum preset threshold, determining that the short-circuit fault to ground occurs in the first connection mode of the detected circuit; When the first output voltage is less than the minimum preset threshold and the second output voltage is less than the minimum preset threshold, it is determined that the short-circuit fault to ground occurs in the second connection mode of the detected circuit.

7. The fault detection method according to claim 5, characterized in that: The method further comprises: When the switch unit is turned on, obtaining a first output voltage of the first output terminal and a second output voltage of the second output terminal; When the first output voltage is less than the minimum preset threshold and the second output voltage is less than the minimum preset threshold, it is determined that an inter-circuit short circuit fault occurs in the detected circuit, and a low-level fault detection signal is output, wherein the inter-circuit short circuit fault indicates that a short circuit fault occurs between the first circuit and the second circuit of the detected circuit.

8. The fault detection method according to claim 7, characterized in that: When the switch unit is turned on, the method further includes: When the first output voltage is greater than the minimum preset threshold and less than the maximum preset threshold and the second output voltage is less than the minimum preset threshold, it is determined that the detected circuit does not have the inter-circuit short circuit fault.

9. The fault detection method according to claim 5, characterized in that: The method further comprises: In case of the power short circuit fault, the ground short circuit fault and the open circuit fault, a low level fault detection signal is output.

10. A fault detection system, characterized in that: include: The fault detection circuit according to any one of claims 1 to 4; A controller comprising one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and the one or more programs include a method for executing the fault detection method described in any one of claims 5 to 9.

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