Semiconductor device de-embedding parameter extraction method without mesa isolation

Abstract

The invention discloses a semiconductor device de-embedding and parameter extracting method without mesa isolation, which is applied to the technical field of semiconductors, and is characterized in that a structure used by the de-embedding and parameter extracting method comprises a bottom conductive dielectric layer which is integrally arranged on the whole surface, and one side surface of the bottom conductive dielectric layer comprises an active region and a residual region; a top conductive dielectric layer is arranged at the first end of a part of the active region in the thickness direction, and a passivation isolation layer is arranged at the first end of the remaining region in the thickness direction and at least corresponds to the region where the test bonding pad is arranged; the test bonding pad is arranged on the outer side surface of the passivation isolation layer, and the test bonding pad is conductively connected with the bottom conductive medium layer in the active area through a conductive part. According to the invention, the bottom conductive dielectric layer in the active area is conductively connected with the test bonding pad, so that the capacitance between the bottom conductive dielectric layer and the bonding pad can be included, and de-embedding, parameter extraction and modeling of the intrinsic area of the device can be carried out without arranging a table top for isolation in the bottom conductive dielectric layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for de-embedding and extracting parameters of a semiconductor device without requiring table isolation. Background Art

[0002] In the preparation of existing semiconductor devices, for device structures with a conductive medium under the mesa, the traditional de-embedding structure often only removes the capacitance and inductance parameters between the large electrodes. When the de-embedding and parameter extraction structure is in a powered state, excess capacitance is generated between the conductive medium and the large electrode (pad). The traditional de-embedding method cannot effectively remove parameters such as the capacitance between the conductive medium and the large electrode, and thus cannot accurately extract the intrinsic parameters of the semiconductor device. In order to ensure the accuracy of the extraction of the intrinsic parameters of the semiconductor device, it is necessary to isolate the device from the electrical mesa. However, the electrical mesa isolation of the device involves the preparation of electrical isolation trenches at the electrical mesa, which increases the complexity of the de-embedding and parameter extraction structure preparation process.

[0003] Therefore, how to provide a de-embedding and parameter extraction method and structure that can reduce the complexity of the preparation process while removing parameters such as the capacitance between the conductive medium and the large electrode is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a method and structure for de-embedding and parameter extraction of semiconductor devices without the need for mesa isolation, which solves the problem in the prior art that in order to ensure the accuracy of the intrinsic parameter extraction of the semiconductor device, electrical mesa isolation of the device is required, but electrical mesa isolation of the device involves preparing electrical isolation grooves at the electrical mesa, which increases the complexity of the de-embedding and parameter extraction structure preparation process.

[0005] In order to solve the above technical problems, the present invention provides a method for de-embedding and extracting parameters of a semiconductor device without mesa isolation, comprising:

[0006] Provided are a de-embedding and parameter extraction structure and a complete semiconductor device prepared by the de-embedding and parameter extraction structure; the de-embedding and parameter extraction structure comprises: a bottom conductive dielectric layer arranged integrally on the entire surface, one side surface of the bottom conductive dielectric layer comprising an active region and a remaining region; a top conductive dielectric layer is arranged at a first end of a portion of the active region in a thickness direction, and a passivation isolation layer is arranged at least at the first end of the remaining region in a thickness direction corresponding to a region where a test pad is arranged; the test pad is arranged on an outer surface of the passivation isolation layer, and the test pad is conductively connected to the bottom conductive dielectric layer in the active region through a conductive component;

[0007] Using a vector network analyzer to obtain a first parameter of the de-embedding parameter extraction structure and a second parameter of the complete semiconductor device;

[0008] An intrinsic parameter of the semiconductor device is determined according to the first parameter and the second parameter.

[0009] The present invention also provides a de-embedding parameter extraction structure for a semiconductor device, comprising:

[0010] A bottom conductive dielectric layer is integrally arranged on the entire surface, wherein one side surface of the bottom conductive dielectric layer includes an active area and a remaining area;

[0011] A top conductive dielectric layer is disposed at a first end of a portion of the active area in the thickness direction, and a passivation isolation layer is disposed at the first end of the remaining area in the thickness direction, at least corresponding to an area where a test pad is disposed;

[0012] The test pad is arranged on the outer surface of the passivation isolation layer, and the test pad is conductively connected to the bottom conductive medium layer in the active area through a conductive component.

[0013] Optionally, the active region includes an unshielded sub-region and a shielded sub-region at least provided with a top conductive dielectric layer at the first end in the thickness direction;

[0014] The unshielded sub-regions and the shielded sub-regions are alternately arranged in the active region, and each of the unshielded sub-regions is conductively connected to the test pad.

[0015] Optionally, a plurality of independent test pads are provided on the outer surface of the passivation isolation layer;

[0016] Each of the unshielded sub-areas is conductively connected to the corresponding test pad.

[0017] Optionally, at least one intermediate conductive dielectric layer is included between the bottom conductive dielectric layer and the top conductive dielectric layer;

[0018] There is a step structure between every two adjacent conductive medium layers in the active region, and a step surface is formed on the conductive medium layer located on the inner side in the thickness direction between every two adjacent conductive medium layers.

[0019] Optionally, the first end of the remaining area in the thickness direction is entirely provided with the passivation isolation layer.

[0020] Optionally, the outer surface of the passivation isolation layer is further provided with a conducting pad for conductive connection to the outside.

[0021] Optionally, the first end of the active area in the thickness direction is correspondingly provided with the passivation isolation layer covering the bottom conductive dielectric layer to the top conductive dielectric layer;

[0022] The passivation isolation layer is provided with a conductive through hole for conductively leading out the bottom conductive medium layer in the active area.

[0023] Optionally, the bottom conductive dielectric layer is a collector dielectric layer, and the top conductive dielectric layer is an emitter dielectric layer;

[0024] A base dielectric layer is provided between the collector dielectric layer and the emitter dielectric layer;

[0025] A first step structure is provided between the base dielectric layer and the active region, and a second step structure is provided between the emitter dielectric layer and the base dielectric layer;

[0026] A passivation isolation layer is disposed on the surface of the first step structure, the surface of the second step structure, and the surface of the emitter dielectric layer.

[0027] The present invention also provides a semiconductor device, comprising the de-embedding and parameter extraction structure of the semiconductor device as described above;

[0028] The outer surface of the passivation isolation layer is also provided with a conducting pad which is conductively connected to the outside, and the conducting pad is conductively connected to at least the top conductive medium layer.

[0029] Optionally, the first end of the conductive medium layer corresponding to the active area in the semiconductor device in the thickness direction is provided with the passivation isolation layer;

[0030] The conductive medium layers in the active area are all conductively led out through corresponding conductive through holes in the passivation isolation layer.

[0031] It can be seen that the structure used in the method for de-embedding and parameter extraction of semiconductor devices without mesa isolation provided by the present invention includes a bottom conductive dielectric layer that is arranged integrally on the entire surface, and one side surface of the bottom conductive dielectric layer includes an active area and a remaining area, and a top conductive dielectric layer is arranged at the first end of the thickness direction of part of the active area, and a passivation isolation layer is arranged at the first end of the thickness direction of the remaining area, at least corresponding to the area where the test pad is arranged, and the test pad is arranged on the outer surface of the passivation isolation layer, and the test pad is conductively connected to the bottom conductive dielectric layer in the active area through a conductive component. The present invention can include the capacitance between the bottom conductive dielectric layer and the pad by conductively connecting the bottom conductive dielectric layer in the active area to the test pad arranged on the outer surface of the passivation isolation layer, and there is no need to set a mesa isolation in the bottom conductive dielectric layer, thereby reducing the complexity of the preparation process of the de-embedding and parameter extraction structure. The de-embedding method proposed by the present invention using this structure instead of the open circuit structure can directly remove the parasitic capacitance between the conductive medium and the large electrode, thereby realizing accurate detection of the intrinsic part. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0033] Figure 1 A schematic diagram of a top view of a de-embedding and parameter extraction structure of a semiconductor device provided in an embodiment of the present invention;

[0034] Figure 2 A schematic cross-sectional view of a de-embedding and parameter extraction structure of a semiconductor device provided by an embodiment of the present invention;

[0035] Figure 3 A schematic diagram of a top view of a de-embedding and parameter extraction structure of an existing semiconductor device;

[0036] Figure 4 A schematic cross-sectional structure diagram of a step structure formed in a de-embedding and parameter extraction structure of a semiconductor device provided by an embodiment of the present invention;

[0037] Figure 5 A schematic top view of another de-embedding and parameter extraction structure of a semiconductor device provided by an embodiment of the present invention;

[0038] Figure 6 A schematic diagram of a top view structure of a semiconductor device provided by an embodiment of the present invention;

[0039] Figure 7 A schematic cross-sectional structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0040] Figures 1 to 7 In the figure, the reference numerals are described as follows:

[0041] 10 - bottom conductive dielectric layer, 11 - active area, 12 - first conductive dielectric layer, 13 - second conductive dielectric layer, 20 - top conductive dielectric layer, 30 - passivation isolation layer, 40 - test pad, 50 - conductive component, 60 - lead pad, 70 - conductive component of top conductive dielectric layer. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] An embodiment of the present invention provides a method for de-embedding and extracting parameters of a semiconductor device without mesa isolation, which may include:

[0044] Step S11: providing a de-embedding and parameter extraction structure and a complete semiconductor device prepared by the de-embedding and parameter extraction structure; the de-embedding and parameter extraction structure comprises: a bottom conductive dielectric layer arranged integrally on the entire surface, and one side surface of the bottom conductive dielectric layer comprises an active area and a remaining area; a top conductive dielectric layer is arranged at a first end of a portion of the active area in a thickness direction, and a passivation isolation layer is arranged at a first end of the remaining area in a thickness direction, at least corresponding to an area where a test pad is arranged; the test pad is arranged on an outer surface of the passivation isolation layer, and the test pad is conductively connected to the bottom conductive dielectric layer in the active area through a conductive component;

[0045] Step S12: using a vector network analyzer to obtain a first parameter of the de-embedding structure and a second parameter of the complete semiconductor device;

[0046] Step S13: determining an intrinsic parameter of the semiconductor device according to the first parameter and the second parameter.

[0047] In this embodiment, a complete semiconductor device prepared by a de-embedded parameter extraction structure is obtained by setting a functional layer and a component connecting the functional layer to an external conductor on the basis of the above-mentioned de-embedded parameter extraction structure to obtain a semiconductor device capable of performing the function of a complete device. In this embodiment, a vector network analyzer is used to obtain the first parameter of the de-embedded parameter extraction structure and the second parameter of the complete semiconductor device, wherein the first parameter and the second parameter are both scattering parameters. When processing, the heat dissipation parameter is first converted into an admittance parameter, and then the first admittance parameter converted from the first parameter and the second admittance parameter converted from the second parameter are calculated, specifically using the second admittance parameter to subtract the first admittance parameter to obtain a final admittance parameter, and the final admittance parameter is converted to obtain a final heat dissipation parameter as an intrinsic parameter of the semiconductor device.

[0048] The structure used in the method for de-embedding and parameter extraction of semiconductor devices without mesa isolation provided by the present invention includes a bottom conductive dielectric layer arranged integrally on the entire surface, one side surface of the bottom conductive dielectric layer includes an active area and a remaining area, a top conductive dielectric layer is arranged at the first end of part of the active area in the thickness direction, and a passivation isolation layer is arranged at the first end of the remaining area in the thickness direction, at least corresponding to the area where the test pad is arranged, the test pad is arranged on the outer surface of the passivation isolation layer, and the test pad is conductively connected to the bottom conductive dielectric layer in the active area through a conductive component. The present invention can include the capacitance between the bottom conductive dielectric layer and the pad by conductively connecting the bottom conductive dielectric layer in the active area with the test pad arranged on the outer surface of the passivation isolation layer, without the need to arrange mesa isolation in the bottom conductive dielectric layer, thereby reducing the complexity of the preparation process of the de-embedding and parameter extraction structure. The de-embedding method proposed by the present invention using this structure instead of the open circuit structure can directly remove the parasitic capacitance between the conductive medium and the large electrode, thereby realizing accurate detection of the intrinsic part.

[0049] The de-embedding and parameter extraction structure of the semiconductor device provided in an embodiment of the present invention is introduced below. The de-embedding and parameter extraction structure of the semiconductor device described below and the de-embedding and parameter extraction method of the semiconductor device without mesa isolation described above can be referred to each other.

[0050] Embodiment 1:

[0051] Please refer to Figure 1 , Figure 1 A schematic diagram of a top view of a de-embedding and parameter extraction structure of a semiconductor device provided in an embodiment of the present invention. The de-embedding and parameter extraction structure of the semiconductor device may include:

[0052] A bottom conductive dielectric layer 10 is integrally provided on the entire surface, and a surface of one side of the bottom conductive dielectric layer 10 includes an active area 11 and a remaining area;

[0053] A top conductive dielectric layer 20 is disposed at a first end of a portion of the active area 11 in the thickness direction, and a passivation isolation layer 30 is disposed at a first end of the remaining area in the thickness direction, at least corresponding to an area where a test pad 40 is disposed;

[0054] The test pad 40 is disposed on the outer surface of the passivation isolation layer 30 , and the test pad 40 is conductively connected to the bottom conductive medium layer 10 in the active area 11 through the conductive component 50 .

[0055] It should be noted that in the present embodiment, the bottom conductive dielectric layer 10 is a structure in which the entire surface is integrated, that is, the active area 11 and the remaining area provided on the surface of one side of the bottom conductive dielectric layer 10 are an integrated structure, and no isolation structure is prepared between the active area 11 and the remaining area, and the mesa isolation in the conventional structure is not formed. In the present embodiment, a top conductive dielectric layer 20 is provided at the first end of the partial active area 11 in the thickness direction, and other conductive dielectric layers may be included between the partial active area 11 and the top conductive dielectric layer 20, or the top conductive dielectric layer 20 may be directly provided on the surface of the partial active area 11. In the general structure, the bottom conductive dielectric layer 10 and the top conductive dielectric layer 20 are provided in an upper and lower structure, that is, the bottom conductive dielectric layer 10 is located on the lower side, and the top conductive dielectric layer 20 is located directly above the partial active area 11 in the bottom conductive dielectric layer 10. The de-embedding and parameter extraction structure in the present embodiment can also refer to Figure 2 , Figure 2 A schematic cross-sectional structural diagram of a de-embedding and parameter extraction structure of a semiconductor device provided in an embodiment of the present invention.

[0056] In this embodiment, the remaining area is the area other than the active area 11 in the bottom conductive dielectric layer 10, and the first end of the remaining area along the thickness direction is generally provided with a test pad 40. In order to avoid short circuit between the test pad 40 and the bottom conductive dielectric layer 10, a passivation isolation layer 30 needs to be provided between the remaining area and the test pad 40. However, due to the redundant capacitance generated between the test pad 40 and the bottom conductive dielectric layer, in the case where the active area 11 and the remaining area in the bottom conductive dielectric layer are not isolated from the mesa, under the influence of the redundant capacitance, the intrinsic parameters of the semiconductor device cannot be determined. For reference, Figure 3 , Figure 3 The top view of the structure of a de-embedding and parameter extraction structure of an existing semiconductor device is shown in FIG. In the present application, the test pad 40 is conductively connected to the bottom conductive medium layer 10 in the active area 11 through the conductive component 50, which can remove the parasitic capacitance and other parameters introduced by the bottom conductive medium layer 10 without table isolation, and realize the accurate detection of the intrinsic parameters of the semiconductor device.

[0057] This embodiment does not limit the specific structure of the conductive component 50 that connects the test pad 40 and the bottom conductive dielectric layer 10 in the active area 11. For example, the conductive component 50 can be set as a metal bridge component, or can also be set as other structures. Furthermore, this embodiment does not limit the specific material of the conductive component 50. In order to ensure the conductive efficiency and preparation cost, a copper metal conductive component 50 can be selected. In this embodiment, the first end along the thickness direction, that is, the direction of the side surface of the bottom conductive dielectric layer 10 pointing outward along the thickness direction, when the direction of the side surface of the bottom conductive dielectric layer 10 pointing outward is upward, the first end is the upper end of the bottom conductive dielectric layer 10.

[0058] Further, in order to ensure the stability of the conductive connection between the test pad 40 and the bottom conductive medium layer 10 in the active area 11 and to ensure the uniformity of the conductive connection, the active area 11 may include an unshielded sub-area and a shielded sub-area having at least a top conductive medium layer 20 at the first end in the thickness direction;

[0059] The unshielded sub-regions and the shielded sub-regions are alternately arranged in the active region 11 , and each unshielded sub-region is conductively connected to the test pad 40 .

[0060] It should be noted that in this embodiment, the active area 11 includes a shielded sub-region and an unshielded sub-region, and a top conductive medium layer 20 is provided at the first end of the shielded sub-region in the thickness direction, and the present embodiment includes multiple shielded sub-regions and multiple unshielded sub-regions to form an alternatingly arranged structure in the active area 11, and each unshielded sub-region is conductively connected to the test pad 40.

[0061] Furthermore, in order to ensure that the intrinsic parameters of the semiconductor device are obtained smoothly, a plurality of independent test pads 40 may be provided on the outer surface of the passivation isolation layer 30;

[0062] Each unshielded sub-region is conductively connected to a corresponding test pad 40 .

[0063] It should be noted that in this embodiment, the test pad 40 can be set to multiple, each test pad 40 is connected to the corresponding unshielded sub-region, and a single test pad 40 can be conductively connected to multiple unshielded sub-regions. In this embodiment, two test pads 40 can be set accordingly.

[0064] Further, in order to ensure the adaptability of the de-embedding and parameter extraction structure of the above semiconductor device, reference may be made to Figure 4 , Figure 4 A schematic cross-sectional structure diagram of a step structure formed in a de-embedding and parameter extraction structure of a semiconductor device provided by an embodiment of the present invention. It can be arranged between a bottom conductive dielectric layer 10 and a top conductive dielectric layer 20, including at least one intermediate conductive dielectric layer;

[0065] There is a step structure between every two adjacent conductive dielectric layers in the active region 11 , and a step surface is formed on the conductive dielectric layer located on the inner side in the thickness direction between every two adjacent conductive dielectric layers.

[0066] It should be noted that in this embodiment, a step structure is provided between each two adjacent conductive dielectric layers in the active region 11. For example, only one intermediate conductive dielectric layer may be provided between the bottom conductive dielectric layer 10 and the top conductive dielectric layer 20. In this case, a step structure is formed between the bottom conductive dielectric layer 10 and the intermediate conductive dielectric layer, and a portion of the upper surface of the bottom conductive dielectric layer 10 forms a step surface of the step structure; and a step structure is formed between the intermediate conductive dielectric layer and the top conductive dielectric layer 20, and a portion of the upper surface of the intermediate conductive dielectric layer forms a step surface of the step structure. In this embodiment, the upper surface of the bottom conductive dielectric layer 10 and the upper surface of the intermediate conductive dielectric layer are both along the thickness direction, and the outer surface of the top conductive dielectric layer 20 is provided at the first end. Figure 4 In the embodiment, the first conductive medium layer 12 is a conductive medium layer located on the bottom side between two adjacent conductive medium layers, and the second conductive medium layer 13 is a conductive medium layer located on the top side between two adjacent conductive medium layers, wherein the first end surface of the first conductive medium layer 12 that is not blocked by the second conductive medium layer 13 in the thickness direction is the step surface of the above-mentioned step structure. When the passivation isolation layer 30 is prepared on the step structure, the passivation isolation layer 30 changes accordingly with the shape of the step structure. At the same time, in this embodiment, since there is no need to prepare a table isolation on the first end surface of the bottom conductive medium layer 10, the number of step structures formed in the device active area can be reduced, thereby improving the coverage of the passivation isolation layer 30.

[0067] Furthermore, in order to ensure the manufacturing efficiency and the protection effect on the bottom conductive medium layer 10 , the first end of the remaining area in the thickness direction may be entirely provided with a passivation isolation layer 30 .

[0068] It should be noted that, in the present embodiment, the first end of the remaining area in the thickness direction is entirely provided with a passivation isolation layer 30, and the passivation isolation layer 30 can be directly prepared on the surface of the remaining area, without the need to prepare a passivation isolation layer 30 with a graphic structure in the remaining area, thereby ensuring the convenience of preparation and enabling the passivation isolation layer 30 to completely cover the remaining area, thereby improving the protection effect on the bottom conductive medium layer 10.

[0069] Furthermore, in order to ensure the functionality of the structure, reference can be made to Figure 5 , Figure 5 A schematic top view of another de-embedding structure of a semiconductor device provided by an embodiment of the present invention. In this embodiment, a conducting pad 60 for conducting connection with the outside is also provided on the outer surface of the passivation isolation layer 30 .

[0070] In this embodiment, a conducting pad 60 for conducting connection with the outside is provided on the outer surface of the passivation isolation layer 30 to ensure that the functional end of the semiconductor device can be connected with the outside, thereby ensuring the functionality of the semiconductor device.

[0071] The de-embedding and parameter extraction structure of the semiconductor device provided by the embodiment of the present invention comprises a bottom conductive dielectric layer 10 which is arranged integrally on the whole surface, a side surface of the bottom conductive dielectric layer 10 comprises an active area 11 and a remaining area, a top conductive dielectric layer 20 is arranged at the first end of the part of the active area 11 in the thickness direction, and a passivation isolation layer 30 is arranged at the first end of the remaining area in the thickness direction, at least corresponding to the area where the test pad 40 is arranged, the test pad 40 is arranged on the outer surface of the passivation isolation layer 30, and the test pad 40 is conductively connected to the bottom conductive dielectric layer 10 in the active area 11 through a conductive component 50. The present invention conductively connects the bottom conductive dielectric layer 10 in the active area 11 with the test pad 40 arranged on the outer surface of the passivation isolation layer 30, so that the capacitance between the bottom conductive dielectric layer 10 and the pad can be included in the de-embedding and parameter extraction structure of the formed open circuit structure, and the intrinsic parameters of the semiconductor device can be accurately detected without setting a mesa isolation in the bottom conductive dielectric layer 10, thereby reducing the complexity of the de-embedding and parameter extraction structure preparation process.

[0072] In addition, the embodiment of the present invention ensures the stability and uniformity of the conductive connection between the test pad 40 and the bottom conductive medium layer 10 in the active area 11 by setting the active area 11 to include multiple shielded sub-areas and multiple unshielded sub-areas, and each unshielded sub-area is conductively connected to the test pad 40; the test pad 40 can be set to multiple, and each test pad 40 is connected to the corresponding unshielded sub-area, so that the intrinsic parameters of the semiconductor device can be obtained smoothly; by setting a step structure between each two adjacent conductive medium layers in the active area 11, the adaptability of the de-embedding and parameter extraction structure of the above-mentioned semiconductor device is guaranteed; by setting the first end of the remaining area in the thickness direction to be entirely provided with a passivation isolation layer 30, the convenience of preparation is guaranteed, and at the same time, the passivation isolation layer 30 can completely cover the remaining area, thereby improving the protection effect of the bottom conductive medium layer 10; by setting a conducting pad 60 conductively connected to the outside on the outer surface of the passivation isolation layer 30, it is ensured that the functional end of the semiconductor device can be connected to the outside, thereby ensuring the functionality of the semiconductor device.

[0073] Embodiment 2:

[0074] The de-embedding and parameter extraction structure of the semiconductor device provided in the embodiment of the present invention is different from that in the above-mentioned embodiment 1 in that:

[0075] A passivation isolation layer 30 covering the bottom conductive dielectric layer 10 to the top conductive dielectric layer 20 is correspondingly disposed at the first end of the active region 11 in the thickness direction;

[0076] The passivation isolation layer 30 is provided with conductive vias for conducting the bottom conductive medium layer 10 in the active region 11 .

[0077] It should be noted that, in this embodiment, since the top conductive dielectric layer 20 is provided at the first end of part of the active region 11 in the thickness direction, that is, the top conductive dielectric layer 20 covers part of the active region 11 in the thickness direction, it can be expected that a step structure is formed between the top conductive dielectric layer 20 and the bottom conductive dielectric layer 10 in the thickness direction, and part of the bottom conductive dielectric layer 10 not covered by the top conductive dielectric layer 20 serves as a step surface of the step structure. In this application, a passivation isolation layer 30 is provided on the step surface formed on the bottom conductive dielectric layer 10 and the surface of the top conductive dielectric layer 20, and the shape of the passivation isolation layer 30 changes with the step structure formed between the top conductive dielectric layer 20 and the bottom conductive dielectric layer 10. It should be noted that, since no mesa isolation structure is prepared between the active region 11 and the remaining region of the bottom conductive dielectric layer 10 in this embodiment, the prepared passivation isolation layer 30 has a flat surface at the bottom conductive dielectric layer 10, and there is no need to form an additional step structure with the mesa isolation, thereby improving the stability of the preparation of the passivation isolation layer 30.

[0078] In addition, the embodiment of the present invention is provided with a conductive through hole for conductively leading out the active area 11 , so as to realize the conductive connection between the active area 11 and the test pad 40 on the basis of providing the passivation isolation layer 30 .

[0079] Furthermore, in order to ensure the adaptability of the de-embedding and parameter extraction structure of the semiconductor device, the bottom conductive dielectric layer 10 can be set as a collector dielectric layer, and the top conductive dielectric layer 20 can be set as an emitter dielectric layer;

[0080] A base dielectric layer is provided between the collector dielectric layer and the emitter dielectric layer;

[0081] There is a first step structure between the base dielectric layer and the active region 11, and there is a second step structure between the emitter dielectric layer and the base dielectric layer;

[0082] A passivation isolation layer 30 is disposed on the surface of the first step structure, the surface of the second step structure, and the surface of the emitter dielectric layer.

[0083] It should be noted that in this embodiment, the bottom conductive dielectric layer 10 is set as the collector dielectric layer, the top conductive dielectric layer 20 is the emitter dielectric layer, and a base dielectric layer is set between the collector dielectric layer and the emitter dielectric layer, and a step structure is formed between adjacent dielectric layers, and a passivation isolation layer 30 is set on the exposed surface from the collector dielectric layer to the emitter dielectric layer, so as to ensure that the de-embedding and parameter extraction structure of the semiconductor device is suitable for the heterojunction bipolar transistor, and to ensure the stability of the passivation isolation layer 30 in terms of glue creeping.

[0084] The de-embedding and parameter extraction structure of the semiconductor device provided by the embodiment of the present invention is applied. Since the mesa isolation structure is not prepared between the active area 11 and the remaining area of ​​the bottom conductive dielectric layer 10, the prepared passivation isolation layer 30 has a flat surface at the bottom conductive dielectric layer 10, and there is no need to form an additional step structure with the mesa isolation, thereby improving the stability of the preparation of the passivation isolation layer 30. In addition, in the embodiment of the present invention, the bottom conductive dielectric layer 10 is set as the collector dielectric layer, the top conductive dielectric layer 20 is set as the emitter dielectric layer, and a base dielectric layer is set between the collector dielectric layer and the emitter dielectric layer, and a step structure is formed between adjacent dielectric layers, and the exposed surface from the collector dielectric layer to the emitter dielectric layer is provided with the passivation isolation layer 30, which ensures the adaptability of the de-embedding and parameter extraction structure of the above-mentioned semiconductor device, and at the same time ensures the stability of the passivation isolation layer 30 in the glue creeping.

[0085] In a feasible embodiment, the de-embedding and parameter extraction structure of the semiconductor device may specifically include the following structure:

[0086] A bottom conductive dielectric layer is integrally arranged on the entire surface, and a surface on one side of the bottom conductive dielectric layer includes an active area and a remaining area;

[0087] A top conductive dielectric layer is disposed at a first end of a portion of the active area in the thickness direction, and a passivation isolation layer is disposed at a first end of the remaining area in the thickness direction;

[0088] The test pad is arranged on the outer surface of the passivation isolation layer, and the test pad is conductively connected to the bottom conductive medium layer in the active area through a conductive component;

[0089] The active region includes an unshielded sub-region and a shielded sub-region at a first end in the thickness direction of which at least a top conductive dielectric layer is provided, the unshielded sub-region and the shielded sub-region are alternately arranged in the active region, each unshielded sub-region is conductively connected to a test pad, a plurality of independent test pads are provided on the outer surface of the passivation isolation layer, and each unshielded sub-region is conductively connected to a corresponding test pad;

[0090] At least one intermediate conductive dielectric layer is included between the bottom conductive dielectric layer and the top conductive dielectric layer, and a step structure is provided between each two adjacent conductive dielectric layers in the active region, and a step surface is formed on the conductive dielectric layer located on the inner side in the thickness direction between each two adjacent conductive dielectric layers;

[0091] A passivation isolation layer covering the bottom conductive medium layer to the top conductive medium layer is correspondingly arranged at the first end of the active area in the thickness direction, and the passivation isolation layer is provided with a conductive through hole that electrically leads out the bottom conductive medium layer in the active area.

[0092] The semiconductor device provided by the embodiment of the present invention is introduced below. The de-embedding and parameter extraction structures of the semiconductor device described below and the semiconductor device described above can be referred to each other.

[0093] Please refer to Figure 6 , Figure 6 A schematic diagram of a top view structure of a semiconductor device provided in an embodiment of the present invention may include a de-embedding and parameter extraction structure of the semiconductor device as described above;

[0094] The outer surface of the passivation isolation layer 30 is further provided with a conducting pad 60 conductively connected to the outside, and the conducting pad 60 is conductively connected to at least the top conductive medium layer 20 .

[0095] It should be noted that the lead pad 60 in this embodiment, which is electrically connected to the outside, can electrically lead the top conductive medium layer 20 out through the conductive connection with the top conductive medium layer 20, thereby ensuring the normal operation of the semiconductor device. In addition, the semiconductor device in this embodiment may also include a package body for packaging the device. Figure 6 As shown, the lead pad 60 is conductively connected to the top conductive dielectric layer 20 through the top conductive dielectric layer conductive component 70 .

[0096] Furthermore, in order to ensure the stability of semiconductor devices and avoid short circuits, you can refer to Figure 7 , Figure 7 A schematic cross-sectional view of a semiconductor device provided by an embodiment of the present invention. A first end of a conductive dielectric layer corresponding to an active region 11 in the semiconductor device in a thickness direction may be provided with a passivation isolation layer 30;

[0097] The conductive dielectric layers in the active region 11 are all conductively led out through corresponding conductive through holes in the passivation isolation layer 30 .

[0098] It should be noted that, in this embodiment, the passivation isolation layer 30 arranged at the first end of the conductive dielectric layer along the thickness direction may not cover the entire surface of the conductive dielectric layer, that is, the passivation isolation layer 30 is prepared only in the unobstructed area of ​​the first end of the corresponding conductive dielectric layer along the thickness direction.

[0099] The semiconductor device provided by the embodiment of the present invention includes the de-embedding and parameter extraction structure of the semiconductor device as described above, and the outer surface of the passivation isolation layer 30 is further provided with a conductive pad 60 conductively connected to the outside, and the conductive pad 60 is conductively connected to at least the top conductive dielectric layer 20. The de-embedding and parameter extraction structure of the semiconductor device can specifically include a bottom conductive dielectric layer 10 provided in an integral manner on the entire surface, a side surface of the bottom conductive dielectric layer 10 includes an active area 11 and a remaining area, a first end of a portion of the active area 11 in the thickness direction is provided with the top conductive dielectric layer 20, and a first end of the remaining area in the thickness direction is provided with a passivation isolation layer 30, at least corresponding to the area where the test pad 40 is provided, the test pad 40 is provided on the outer surface of the passivation isolation layer 30, and the test pad 40 is conductively connected to the bottom conductive dielectric layer 10 in the active area 11 through a conductive component 50. The present invention conductively connects the bottom conductive dielectric layer 10 in the active area 11 to the test pad 40 arranged on the outer surface of the passivation isolation layer 30, so that the capacitance between the bottom conductive dielectric layer 10 and the pad can be included in the de-embedding and parameter extraction structure of the formed open circuit structure. There is no need to set up a table isolation in the bottom conductive dielectric layer 10, so that the intrinsic parameters of the semiconductor device can be accurately detected, reducing the complexity of the de-embedding and parameter extraction structure preparation process.

[0100] In addition, the embodiment of the present invention provides a passivation isolation layer 30 at the first end of the conductive medium layer corresponding to the active area 11 in the semiconductor device in the thickness direction, and the conductive medium layer in the active area 11 is conductively led out through the corresponding conductive through holes in the passivation isolation layer 30, thereby ensuring the stability of the semiconductor device and avoiding short circuit of the device.

[0101] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0102] In addition, it should be noted that, in this article, relationships such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants are intended to cover non-exclusive inclusions.

[0103] The above is a detailed introduction to the semiconductor device de-embedding and parameter extraction method and structure without mesa isolation provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A method for de-embedding and extracting parameters of a semiconductor device without mesa isolation, characterized in that: include: Providing a de-embedding and parameter extraction structure and a complete semiconductor device prepared by the de-embedding and parameter extraction structure; The de-embedding and parameter extraction structure comprises: a bottom conductive dielectric layer integrally arranged on the entire surface, one side surface of the bottom conductive dielectric layer comprising an active area and a remaining area; a top conductive dielectric layer is arranged at a first end of a portion of the active area in a thickness direction, and a passivation isolation layer is arranged at least at the first end of the remaining area in the thickness direction corresponding to an area where a test pad is arranged; the test pad is arranged on an outer surface of the passivation isolation layer, and the test pad is conductively connected to the bottom conductive dielectric layer in the active area through a conductive component; Using a vector network analyzer to obtain a first parameter of the de-embedding parameter extraction structure and a second parameter of the complete semiconductor device; An intrinsic parameter of the semiconductor device is determined according to the first parameter and the second parameter.

2. A de-embedding parameter extraction structure for a semiconductor device, characterized in that: include: A bottom conductive dielectric layer is integrally arranged on the entire surface, wherein one side surface of the bottom conductive dielectric layer includes an active area and a remaining area; A top conductive dielectric layer is disposed at a first end of a portion of the active area in the thickness direction, and a passivation isolation layer is disposed at the first end of the remaining area in the thickness direction, at least corresponding to an area where a test pad is disposed; The test pad is arranged on the outer surface of the passivation isolation layer, and the test pad is conductively connected to the bottom conductive medium layer in the active area through a conductive component.

3. The de-embedding parameter extraction structure of a semiconductor device according to claim 2, characterized in that: The active region includes an unshielded sub-region and a shielded sub-region at least provided with a top conductive dielectric layer at the first end in the thickness direction; The unshielded sub-regions and the shielded sub-regions are alternately arranged in the active region, and each of the unshielded sub-regions is conductively connected to the test pad.

4. The de-embedding parameter extraction structure of a semiconductor device according to claim 3, characterized in that: A plurality of independent test pads are arranged on the outer surface of the passivation isolation layer; Each of the unshielded sub-areas is conductively connected to the corresponding test pad.

5. The de-embedding parameter extraction structure of a semiconductor device according to claim 2, characterized in that: At least one intermediate conductive medium layer is included between the bottom conductive medium layer and the top conductive medium layer; There is a step structure between every two adjacent conductive medium layers in the active region, and a step surface is formed on the conductive medium layer located on the inner side in the thickness direction between every two adjacent conductive medium layers.

6. The de-embedding parameter extraction structure of a semiconductor device according to claim 2, characterized in that: The first end of the remaining area in the thickness direction is entirely provided with the passivation isolation layer.

7. The de-embedding parameter extraction structure of a semiconductor device according to claim 6, characterized in that: The outer surface of the passivation isolation layer is also provided with a conducting pad that is conductively connected to the outside.

8. The de-embedding parameter extraction structure of a semiconductor device according to any one of claims 2 to 7, characterized in that: The first end of the active area in the thickness direction is correspondingly provided with the passivation isolation layer covering the bottom conductive dielectric layer to the top conductive dielectric layer; The passivation isolation layer is provided with a conductive through hole for conductively leading out the bottom conductive medium layer in the active area.

9. The de-embedding parameter extraction structure of a semiconductor device according to claim 8, characterized in that: The bottom conductive dielectric layer is a collector dielectric layer, and the top conductive dielectric layer is an emitter dielectric layer; A base dielectric layer is provided between the collector dielectric layer and the emitter dielectric layer; A first step structure is provided between the base dielectric layer and the active region, and a second step structure is provided between the emitter dielectric layer and the base dielectric layer; A passivation isolation layer is disposed on the surface of the first step structure, the surface of the second step structure, and the surface of the emitter dielectric layer.

10. A semiconductor device, characterized in that: A de-embedding and parameter extraction structure of a semiconductor device comprising any one of claims 2 to 9; The outer surface of the passivation isolation layer is also provided with a conducting pad which is conductively connected to the outside, and the conducting pad is conductively connected to at least the top conductive medium layer.

11. The semiconductor device according to claim 10, characterized in that The first end of the conductive medium layer corresponding to the active area in the semiconductor device in the thickness direction is provided with the passivation isolation layer; The conductive medium layers in the active area are all conductively led out through corresponding conductive through holes in the passivation isolation layer.

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