Optical proximity pre-correction method, device, medium, program product and terminal

Abstract

The present application provides an optical proximity pre-correction method, device, medium, program product and terminal, which obtains one or more layers of the layout to be corrected, extracts the corresponding graphic parameters and anchor point parameters, and pre-corrects the graphic elements in each layer of periodic graphics with bridging risks to generate a pre-corrected layout. The present application effectively avoids the bridging phenomenon, ensures the integrity of the wafer pattern and the normal function of the circuit; at the same time, it improves the OPC correction efficiency, optimizes the optical proximity effect compensation, significantly reduces the time and resources required for correction, and improves production efficiency; in addition, it also expands the process window, improves the correction accuracy and stability, and reduces the defect rate; while reducing the process risk, it improves the quality of the final product.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to an optical proximity pre-correction method, device, medium, program product and terminal. Background Art

[0002] During the semiconductor lithography process, due to the diffraction effect of ultraviolet light, when the mask pattern is projected onto the wafer, the pattern formed on the wafer surface is often distorted. This phenomenon is called the optical proximity effect (OPE). The wafer surface pattern distortion caused by the optical proximity effect is mainly manifested in the deviation of the critical dimension (CD), the shortening of the end of the line (EOL), the missing patterns (MissedPatterns) or bridging (Bridging), and the rounding of the corners (Corner Rounding). Bridging refers to the phenomenon that during the lithography process, due to the optical interaction between adjacent patterns, the lines or patterns that should have been separated appear connected or fused on the wafer surface. This phenomenon can affect the performance of the circuit and cause problems such as short circuits.

[0003] In order to compensate for the defects caused by the optical proximity effect and obtain the same pattern as the original design on the wafer surface, the optical proximity correction (OPC) technology is used. The existing OPC correction method mainly corrects the EPE (the deviation between the simulated contour edge and the target shape). However, under certain process conditions, such as Figure 1 and Figure 2 As shown, the chip design pattern may already have a bridge risk, which makes it impossible to accurately obtain EPE, thus affecting the correction effect of OPC. In addition, this also increases the time required for OPC correction and reduces production efficiency. Summary of the invention

[0004] In view of the shortcomings of the prior art mentioned above, the purpose of the present application is to provide an optical proximity pre-correction method, device, medium, program product and terminal, which are used to solve the problem in the prior art that, when performing photolithography on dense wafer patterns, due to the risk of bridging, EPE cannot be accurately obtained, which in turn affects the OPC correction effect, thereby increasing the correction time and reducing production efficiency.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a method for optical proximity pre-correction, which includes: obtaining one or more layers of a layout to be corrected, wherein each layer of the layout to be corrected contains a periodic pattern composed of multiple graphic elements; extracting graphic parameters and anchor point parameters of the corresponding periodic graphic from each layer of the layout to be corrected; based on the graphic parameters and anchor point parameters, pre-correcting each graphic element in each layer of the periodic graphic that has been identified as having a bridging risk to generate a pre-corrected layout.

[0006] In some embodiments of the first aspect of the present application, the graphic parameters of the periodic pattern include: line width and spacing of the periodic pattern.

[0007] In some embodiments of the first aspect of the present application, the anchor point parameters of the periodic pattern include: anchor point line width and anchor point spacing.

[0008] In some embodiments of the first aspect of the present application, based on the graphic parameters and anchor point parameters, the process of pre-correcting each graphic element in each layer of the periodic graphics that has been identified as having a bridging risk includes: calculating the translation distance of each point on the edge of each graphic element according to the graphic parameters and anchor point parameters; and translating the corresponding graphic element along a preset direction based on the calculated translation distance to generate a pre-corrected layout.

[0009] In some embodiments of the first aspect of the present application, pre-correcting each graphic element identified as having a bridging risk in each layer of the periodic graphic comprises the following calculation process: ; Wherein, x represents the translation distance; Width represents the line width of the periodic figure, Space represents the spacing of the periodic figure; Awidth represents the anchor point line width, and ASpace represents the anchor point spacing.

[0010] In some embodiments of the first aspect of the present application, the process of translating the corresponding graphic element along a preset direction includes: calculating the normal vector of each point on the edge of the graphic element, and translating the current point along the normal vector in a direction close to the interior of the graphic element by the translation distance.

[0011] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides an optical proximity pre-correction device, including: a layout reading module: used to obtain one or more layers of layouts to be corrected, wherein each layer of the layout to be corrected contains a periodic pattern composed of multiple graphic elements; a parameter extraction module: used to extract graphic parameters and anchor point parameters of the periodic graphics of each layer of the layout from the layout to be corrected; a graphic correction module: used to pre-correct each graphic element in the periodic graphics of each layer that has been identified as having a bridging risk based on the graphic parameters and anchor point parameters to generate a pre-corrected layout.

[0012] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the optical proximity pre-correction method when executed by a processor.

[0013] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes a computer program code. When the computer program code is run on a computer, the computer implements the optical proximity pre-correction method.

[0014] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the optical proximity pre-correction method.

[0015] As described above, the method, device, medium, program product and terminal of the present application have the following beneficial effects:

[0016] 1. Effectively avoid bridging phenomenon: By improving the pattern correction technology, this application can effectively prevent bridging from occurring on the wafer surface, ensuring the integrity of the pattern and the normal function of the circuit.

[0017] 2. Improve OPC correction efficiency: The technical solution of the present application optimizes the compensation process of the optical proximity effect, significantly reducing the time and resources required for correction, thereby improving overall production efficiency.

[0018] 3. Expanding the process window: By improving correction accuracy and stability, this application enables the process window to be expanded, allowing higher manufacturing tolerance, thereby reducing defects caused by process fluctuations.

[0019] 4. Reduce process risks: This application not only improves production efficiency, but also reduces risks in the manufacturing process, reduces potential product defect rates, and improves the quality and reliability of the final product. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1The simulated layout pattern after bridging of the optical proximity pre-correction of the present application and the prior art is shown.

[0021] Figure 2 A simulated layout diagram after bridging of another prior art optical proximity pre-correction method of the present application is shown.

[0022] Figure 3 A flow chart of an embodiment of an optical proximity pre-correction method of the present application is shown.

[0023] Figure 4 The initial layout diagram in one embodiment of the optical proximity pre-correction method of the present application is shown.

[0024] Figure 5 The figure shows a simulated layout pattern after pre-correction according to an embodiment of the optical proximity pre-correction method of the present application.

[0025] Figure 6 The figure shows the layout pattern after pre-correction according to an embodiment of the optical proximity pre-correction method of the present application.

[0026] Figure 7 A schematic structural diagram of an embodiment of an optical proximity pre-correction device of the present application is shown.

[0027] Figure 8 A schematic structural diagram of an embodiment of an optical proximity pre-correction terminal of the present application is shown. DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0029] Before further explaining the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations:

[0030] <1> Optical Proximity Correction (OPC): OPC aims to compensate for various non-ideal effects in the imaging process, such as diffraction, interference, and scattering, by pre-correcting the pattern on the mask, thereby ensuring that the pattern finally formed on the wafer surface accurately matches the design requirements.

[0031] <2> Critical Dimension (CD): CD refers to the width or length of a specific structure in the semiconductor manufacturing process, especially those tiny dimensions that have a direct impact on device performance. CD is a core indicator for evaluating the accuracy and consistency of the manufacturing process.

[0032] <3> Bridging: Bridging is a phenomenon that occurs during semiconductor manufacturing when two supposedly independent patterns are accidentally connected to each other due to process limitations. Bridging can cause electrical shorts, affecting device functionality and reliability.

[0033] <4> Edge Placement Error (EPE): EPE is a measure of the degree of positional deviation of the edge of a pattern relative to the design model during the lithography process. EPE is critical to ensuring the correct electrical connection between components in complex integrated circuits.

[0034] <5> Periodic Pattern: In semiconductor manufacturing, a periodic pattern is a pattern that repeats at regular intervals along one or more directions. This type of pattern is very important for evaluating the resolution and uniformity of lithography systems.

[0035] <6> Pattern Element: Pattern elements are the basic units that make up the layout of integrated circuits. They can be lines, holes, contact windows or any other geometric shapes. Together, they form a complex circuit design.

[0036] <7> Line Width: Line width refers to the actual width of a conductor line or isolation region in a semiconductor device. Line width control is critical to achieving high-performance and high-density integrated circuits.

[0037] <8> Spacing: Spacing refers to the minimum distance between the centers of two adjacent graphic elements, or more specifically, the shortest distance between the edges of two graphics. Maintaining proper spacing is critical to preventing bridging and other defects.

[0038] <9> Anchor Point: Anchor points are used as reference points to fix other graphic elements in layout design. They play an important role in ensuring the relative position accuracy of various parts in complex designs, especially in the process of multi-layer graphic alignment.

[0039] To facilitate understanding of the embodiments of the present application, first Figure 3 Detailed description. Figure 3The following is a flow chart of an optical proximity pre-correction method in an embodiment of the present application. The optical proximity pre-correction method in this embodiment mainly includes the following steps:

[0040] Step S31: obtaining one or more layers of a layout to be corrected, wherein each layer of the layout to be corrected contains a periodic pattern composed of a plurality of graphic elements.

[0041] In one embodiment of the present application, the file format of the to-be-revised layout includes multiple formats such as GDSII, OASIS and SDF (standard data format). GDSII and OASIS are used to describe complex two-dimensional graphics and structures, which are easy to read in a photolithography machine. SDF is used for layout description in integrated circuit design. In integrated circuit design, since the materials of the functions of each layer are different, it is necessary to explain that the metal layers that may be included include doping layers, insulating layers, metal layers, substrate layers, etc. Among them, the doping layer is used to form the source and drain of the transistor, and ion implantation technology is usually required for precise control. Insulating layers such as silicon dioxide or silicon nitride are used to isolate circuit parts to prevent short circuits and protect patterns. Metal layers such as aluminum or copper are used to make power and signal interconnections to achieve electrical connections. The design of this layer needs to pay attention to line width and spacing to prevent the risk of short circuits when improving special effects. The substrate layer is usually composed of single crystal silicon to provide support for the entire chip. Exemplarily, the number of layers of the to-be-revised version is about 5 to 50 layers, and the specific number of layers depends on the complexity and performance characteristics of the circuit.

[0042] In one embodiment of the present application, the periodic pattern generally includes repeatedly arranged graphics, such as gates, interconnects, contact holes, etc. In high-density memories, such as DRAM, the patterns of storage cells are very dense and periodic, so that the chip can use space more efficiently. The lithography resolution is directly affected by the spacing of the periodic patterns in the design. Smaller spacing can lead to too tight arrangement, which can cause diffraction problems, especially for patterns with too tight spacing, which can cause bridging after lithography. The present application proposes to improve the accuracy of the pattern after lithography by pre-correcting the layout graphics before lithography.

[0043] Step S32: extracting the graphic parameters and anchor point parameters of the corresponding periodic graphics from each layer of the layout to be corrected.

[0044] In one embodiment of the present application, the graphic parameters of the periodic pattern include: line width and spacing of the periodic pattern.

[0045] In this embodiment, line width refers to the thickness of each line in the periodic pattern, and spacing refers to the distance between adjacent lines in the periodic pattern. In the photolithography process, line width is greatly affected by the diffraction and scattering of light. Smaller line width may appear blurred or expanded during actual exposure, thereby affecting the performance of the circuit. When the spacing is too small (for example, less than the limit of the photolithography resolution), it may cause electrical short circuits or interference between lines, thereby affecting the performance of the device.

[0046] In one embodiment of the present application, the anchor point parameters of the periodic pattern include: anchor point line width and anchor point spacing.

[0047] It should be noted that in this embodiment, the anchor point is a specific point or line in the periodic figure used for alignment or reference to ensure that other design elements can maintain the correct relative position during the lithography process. The anchor point can effectively reduce the errors generated in the process of graphic transfer and alignment, and provide a stable reference for subsequent links. Furthermore, the anchor point line width refers to the thickness of the specific line of the anchor point used for alignment or reference in the periodic figure to ensure the expected positioning and proportion of the alignment reference and surrounding design elements during the lithography or other manufacturing process, thereby determining the recognizability of the figure and the molding accuracy on the wafer. The anchor point spacing is the physical distance between adjacent anchor points to define the layout and arrangement relationship of multiple anchor points in the design, and directly affects the accuracy and alignment ability of the periodic figure during the lithography process.

[0048] Step S33: Based on the graphic parameters and anchor point parameters, pre-correct each graphic element in the periodic graphics of each layer that has been identified as having a bridging risk, to generate a pre-corrected layout.

[0049] In one embodiment of the present application, each graphic element in each layer of the periodic graphics that has been identified as having a bridging risk is pre-corrected; wherein the process of identifying the graphic elements with a bridging risk in the graphic elements includes: measuring the distance between adjacent elements, if the distance is less than a set value (for example, 0.2 microns), it is identified as a bridging risk; calculating the line density in a specific area, if the number of lines exceeds the standard (such as more than 100 lines per square centimeter), it is identified as a bridging risk; analyzing complex intersections, if the number exceeds a predetermined value (such as more than 3), it is identified as a bridging risk.

[0050] In one embodiment of the present application, based on the graphic parameters and anchor point parameters, the process of pre-correcting each graphic element in each layer of the periodic graphics that has been identified as having a bridging risk includes: calculating the translation distance of each point on the edge of each graphic element according to the graphic parameters and anchor point parameters; and translating the corresponding graphic element along a preset direction according to the calculated translation distance to generate a pre-corrected layout.

[0051] In this embodiment, the preset directions for translation include, but are not limited to, normal vector translation, tangent direction translation, custom vector translation, coordinate system translation, center of gravity translation, regular grid translation, function-driven translation, and weighted translation. Among them, normal vector translation determines the translation direction by calculating the normal vector of the edge of the graphic element to ensure that the graphic element moves inward. Tangent direction translation is performed in the direction tangent to the edge of the graphic to preserve the overall shape of the element. Custom vector translation allows the definition of any translation direction. Coordinate system translation moves in the X-axis, Y-axis, and Z-axis directions of global or local coordinates to provide precise position control. Center of gravity translation is performed around the center point of the graphic to achieve the balance of the graphic. Regular grid translation moves at a certain spacing on a preset grid to ensure the neatness of the overall design. Function-driven translation uses mathematical functions to define the translation path so that the element moves along a specific curve or path. Weighted translation adjusts the translation method of different parts according to the characteristics of the graphic element.

[0052] In one embodiment of the present application, pre-correcting each graphic element identified as having a bridging risk in each layer of the periodic graphic includes the following calculation process: Pre-correcting each graphic element identified as having a bridging risk in each layer of the periodic graphic includes the following calculation process: ; Wherein, x represents the translation distance; Width represents the line width of the periodic figure, Space represents the spacing of the periodic figure; Awidth represents the anchor point line width, and ASpace represents the anchor point spacing.

[0053] In this embodiment, the pre-correction process includes: obtaining the sum of the squares of the two differences by respectively calculating the square of the difference between the line width and the anchor point line width, and the square of the difference between the spacing and the anchor point spacing. This process is necessary for each graphic element. After calculating the square root of the sum of squares, the result is divided by 2 to obtain a reasonable translation distance. Thus, the position of each graphic element is effectively adjusted to maintain the best relative relationship with the reference anchor point. This process not only improves the neatness of the design, but also improves the aesthetics and functionality of the image after lithography.

[0054] In one embodiment of the present application, the process of translating the corresponding graphic element along a preset direction includes: calculating the normal vector of each point on the edge of the graphic element, and translating the current point along the normal vector in a direction close to the interior of the graphic element by the translation distance.

[0055] In this embodiment, the normal vector of each edge point is calculated to determine its moving direction, thereby achieving accurate element positioning. First, the normal vector of each point on the edge of the graphic element is calculated. This vector is perpendicular to the tangent and effectively describes the external direction of the point. Next, these normal vectors are used to determine the translation direction according to the preset direction, so as to move the point toward the inside of the graphic along the direction of the normal vector. Finally, for each edge point, a translation operation is performed based on the normal vector, and the translation distance is determined by the graphic parameters and anchor point parameters.

[0056] Figure 4 The schematic diagram of the layout before pre-correction in an embodiment of the present application is shown. In this embodiment, the width of the anchor point is 84nm and the spacing is 76nm, while the width of the pattern used is 92nm and the spacing is 70nm. After calculation, the movement amount is 5nm, so the adjusted pattern width will become 82nm and the spacing will be adjusted to 80nm. Figure 5 and Figure 6 The schematic diagram of the graphics after simulated etching is shown. During the simulation of the target graphics, the contour state is normal and there is no risk of bridging. Through the OPC pre-correction method proposed in this application, EPE can be accurately captured and the "bridging" phenomenon can be effectively avoided, thereby improving the OPC correction efficiency, expanding the process window, and reducing process risks.

[0057] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0058] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0059] Figure 7 is a schematic block diagram of an optical proximity pre-correction device provided in an embodiment of the present application. Figure 7As shown, the device includes a layout reading module 701, a parameter extraction module 702 and a graphic correction module 703.

[0060] The layout reading module 701 is used to obtain one or more layers of the layout to be corrected, wherein each layer of the layout to be corrected contains a periodic pattern composed of multiple graphic elements.

[0061] Parameter extraction module 702: used to extract the graphic parameters and anchor point parameters of the periodic graphics of each layer of the layout from the layout to be corrected.

[0062] Graphic correction module 703: used to pre-correct each graphic element identified as having a bridging risk in the periodic graphics of each layer based on the graphic parameters and anchor point parameters, so as to generate a pre-corrected layout.

[0063] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0064] It should also be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0065] Figure 8 is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. Figure 8 As shown, the electronic terminal includes: at least one processor 801, a memory 802, at least one network interface 803 and a user interface 805. The various components in the device are coupled together through a bus system 804. It can be understood that the bus system 804 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 804 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 8 In the specification, various buses are labeled as bus systems.

[0066] The user interface 805 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0067] It is understood that the memory 802 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of exemplary but not limiting explanation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present application is intended to include but is not limited to these and any other suitable categories of memory.

[0068] The memory 802 in the embodiment of the present application is used to store various types of data to support the operation of the electronic terminal 800. Examples of these data include: any executable program for operating on the electronic terminal 800, such as an operating system 8021 and an application 8022; the operating system 8021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 8022 can include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The optical proximity pre-correction method provided in the embodiment of the present application can be included in the application 8022.

[0069] The method disclosed in the above embodiment of the present application can be applied to the processor 801, or implemented by the processor 801. The processor 801 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor 801 or an instruction in the form of software. The above processor 801 may be a general processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 801 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general processor 801 may be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present application, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0070] In an exemplary embodiment, the electronic terminal 800 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

[0071] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes: computer program code, when the computer program code is run on a computer, the computer executes the optical proximity pre-correction method of any embodiment shown in the above embodiments.

[0072] According to the method provided by the embodiments of the present application, the present application also provides a computer-readable storage medium, which stores a program code. When the program code runs on a computer, the computer executes the optical proximity pre-correction method of any one of the embodiments shown above.

[0073] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program and / or a computer running on a processor. By way of illustration, both applications and computing devices running on a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0074] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0075] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0076] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0077] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0078] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0079] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0080] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0081] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0082] In summary, the present application provides an optical proximity pre-correction method, device, medium, program product and terminal. The present application provides a method for improving the correction efficiency of dense wafer patterns in the lithography process, by obtaining one or more layers of the layout to be corrected, extracting the corresponding graphic parameters and anchor point parameters, and pre-correcting the graphic elements in each layer of periodic graphics to generate a pre-corrected layout. The present application effectively avoids the bridging phenomenon, ensures the integrity of the wafer pattern and the normal function of the circuit; at the same time, it improves the OPC correction efficiency, optimizes the optical proximity effect compensation, significantly reduces the time and resources required for correction, and improves production efficiency; in addition, it also expands the process window, improves the correction accuracy and stability, and reduces the defect rate; while reducing the process risk, it improves the quality of the final product. Therefore, the present application effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0083] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. An optical proximity pre-correction method, characterized in that: The method comprises: Obtain one or more layers of a to-be-corrected layout, wherein each layer of the to-be-corrected layout contains a periodic pattern composed of a plurality of graphic elements; Extracting the graphic parameters and anchor point parameters of the corresponding periodic graphic from each layer of the to-be-corrected layout; the graphic parameters of the periodic graphic include: line width and spacing of the periodic graphic; the anchor point parameters of the periodic graphic include: anchor point line width and anchor point spacing; Based on the graphic parameters and anchor point parameters, each graphic element in each layer of the periodic graphics that has been identified as having a bridging risk is pre-corrected, including: calculating the translation distance of each point on the edge of each graphic element according to the graphic parameters and anchor point parameters; and translating the corresponding graphic element along a preset direction according to the calculated translation distance to generate a pre-corrected layout.

2. The optical proximity pre-correction method according to claim 1, characterized in that: The pre-correction of each graphic element identified as having a bridging risk in each layer of the periodic graphic includes the following calculation process: ； Wherein, x represents the translation distance; Width represents the line width of the periodic figure, Space represents the spacing of the periodic figure; Awidth represents the anchor point line width, and ASpace represents the anchor point spacing.

3. The optical proximity pre-correction method according to claim 1, characterized in that: The process of translating the corresponding graphic element along a preset direction includes: calculating the normal vector of each point on the edge of the graphic element, and translating the current point along the normal vector toward the direction close to the inside of the graphic element by the translation distance.

4. An optical proximity pre-correction device, characterized in that: include: A layout reading module is used to obtain one or more layers of the layout to be corrected, wherein each layer of the layout to be corrected contains a periodic pattern composed of multiple graphic elements; The graphic parameters of the periodic graphic include: the line width and spacing of the periodic graphic; the anchor point parameters of the periodic graphic include: the anchor point line width and the anchor point spacing; Parameter extraction module: used to extract the graphic parameters and anchor point parameters of the periodic graphics of each layer of the layout from the layout to be corrected; Graphic correction module: used to pre-correct each graphic element in each layer of the periodic graphics that has been identified as having a bridging risk based on the graphic parameters and anchor point parameters, including: calculating the translation distance of each point on the edge of each graphic element according to the graphic parameters and anchor point parameters; and translating the corresponding graphic element along a preset direction according to the calculated translation distance to generate a pre-corrected layout.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the optical proximity pre-correction method according to any one of claims 1 to 3 is implemented.

6. A computer program product, characterized in that The computer program product comprises computer program codes, and when the computer program codes are run on a computer, the computer is enabled to implement the optical proximity pre-correction method according to any one of claims 1 to 3.

7. An electronic terminal comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the optical proximity pre-correction method according to any one of claims 1 to 3.

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