An on-chip high-bandwidth feedback loop and high-voltage LDO and voltage stabilization circuit

Abstract

The present application provides an on-chip high-bandwidth feedback loop and a high-voltage LDO and a voltage stabilizing circuit, which are applied to the technical fields of integrated circuits and high-voltage LDO voltage regulators. In the on-chip fast-response high-bandwidth feedback loop, the buck power tube steps down the input voltage at the high-voltage end, and the output power tube M11 provides a stable output voltage for an external load at the output end with the stepped-down voltage. The common-gate circuit and the current branch jointly respond to the change trend of the output voltage that may be caused by a sudden load change, and then quickly adjust the buck power tube and the output power tube after completing the current response in a timely and rapid manner, so that the output voltage can be stably output and is not easily affected by a sudden external load change.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits and high-voltage LDO voltage regulators, and in particular to an on-chip high-bandwidth feedback loop and a high-voltage LDO and voltage stabilization circuit. Background Art

[0002] In industrial and automotive chips, the power supply inside the chip is often generated from the high-voltage power pin of the chip, and the chip does not use a capacitor of more than 100pF to absorb the undershoot and overshoot of the LDO (Low Dropout Regulator) output voltage. Therefore, when the load jumps, the output voltage will have a large sudden change, causing the output voltage to be unstable.

[0003] Based on this, a new loop adjustment technical solution is needed. Summary of the invention

[0004] In view of this, the embodiments of this specification provide an on-chip high-bandwidth feedback loop and a high-voltage LDO and voltage stabilization circuit. Since the bandwidth of the feedback loop depends on the transconductance and gate parasitic capacitance of the power tube, the loop bandwidth is very wide and can respond quickly to changes in the output voltage, thereby improving the response speed.

[0005] The embodiments of this specification provide the following technical solutions:

[0006] The embodiment of the present specification provides an on-chip high-bandwidth feedback loop, including a first pull-up current branch, a first pull-down current branch, a common-gate adjustment circuit, a buck power tube and an output power tube; wherein the common-gate adjustment circuit includes a first transistor and a second transistor, the gate of the first transistor and the gate of the second transistor are connected to a first bias power supply; the source of the first transistor is connected to the drain of the output power tube; the drain of the second transistor is connected to the gate of the buck power tube; the drain of the buck power tube is connected to an input power supply terminal, the source of the buck power tube is connected to the source of the output power tube as an output terminal, and the gate of the output power tube is controlled by an error control voltage; the drain of the first transistor and the drain of the second transistor are respectively connected to the input power supply terminal through the first pull-up current branch, and the source of the second transistor and the drain of the output power tube are respectively grounded through the first pull-down current branch;

[0007] Among them, the buck power tube is used to step down the input voltage of the input power supply end and output it to the source of the output power tube to form an output voltage; under the bias of the first bias power supply, the first pull-up current branch and the first pull-down current branch are controlled proportional current sources, the first pull-up current branch is used to provide a first pull-up current for the second transistor, the first pull-up current is proportional to the working current of the first transistor, and the first pull-down current branch is used to provide a first pull-down current for the second transistor, the first pull-down current is proportional to the sum of the working current of the first transistor and the working current of the output power tube, the first pull-up current and the first pull-down current together enable the output power tube to stably obtain the corresponding working current, so that the output power tube outputs a stable output voltage at the output end.

[0008] Compared with the prior art, the at least one technical solution adopted in the embodiments of this specification can achieve the following beneficial effects:

[0009] By forming a fast-response high-bandwidth loop at the output end, when the load jumps, the loop can quickly follow the change and complete the output adjustment, reducing the impact of the load change on the on-chip circuit. Among them, the bandwidth of the fast-response feedback loop is only affected by the gate parasitic capacitance and the crossover of the power tube, so the bandwidth is very wide and can follow the rapid changes in the output voltage. Therefore, the present invention uses a fast feedback loop to improve the responsiveness of load changes, reduce the impact of load changes on the on-chip circuit, and ensure stable output. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0011] Figure 1 It is a schematic diagram of the structure of the internal circuit and external circuit of the traditional LDO;

[0012] Figure 2 is a schematic diagram of a structure of an on-chip high-bandwidth feedback loop in the present application;

[0013] Figure 3 It is a schematic diagram of the structure of an on-chip high-bandwidth feedback loop based on transistors to implement current branches in this application;

[0014] Figure 4 It is a schematic diagram of the structure of a high-voltage LDO with on-chip fast response capability in this application;

[0015] Figure 5 It is a schematic diagram of the overall circuit structure composed of various unit circuits implemented based on transistors in this application. DETAILED DESCRIPTION

[0016] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0017] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0018] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0019] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0020] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0021] like Figure 1As shown in the figure, the output voltage (Vout) of the LDO is stabilized and filtered by an external voltage stabilization filter capacitor (Cout). Since a smaller Cout has poor voltage stabilization and filtering capabilities, a larger Cout is usually used. At this time, when a larger Cout is faced with a load mutation at the output end of the LDO, the response is very slow, resulting in the operational amplifier (OP) inside the LDO being unable to amplify the error to allow the power tube to complete the adjustment in time, making the LDO unable to keep up with the load mutation.

[0022] Based on this, the embodiments of this specification propose an on-chip fast-response broadband feedback loop solution to solve the problem of the internal circuit being affected by external load changes: Figure 2 As shown, in the broadband feedback loop with fast response in the chip, the buck power tube NLD0 is used as a power tube in the output stage for stepping down the input voltage of the high-voltage input power supply end (marked as Vin in the figure), so that the internal circuit can meet the input voltage of the wide input range; the output power tube M11 is used as a power tube in the output stage to drive the load, wherein the gate of M11 can form a corresponding output voltage Vout at the output end under the control of the error control voltage Verr; then, when M11 is affected by an external load (an external load connected to the output voltage Vout of the output power tube M11, not shown in the figure) and may cause the output voltage Vout to have a changing trend, the common gate circuit (NLD1, NLD2 transistors) and the current branch (pull-up current branch, pull-down current branch) can be used together according to the changing trend of Vout to timely adjust the buck power tube NLD0 and the output power tube M11 in a fast response, so that the output voltage Vout can be output stably and not easily affected by the change of the external load.

[0023] It should be noted that the current branch is designed as a proportional current source, so when the circuit is balanced, that is, when the load does not change, the pull-up and pull-down currents provided to NLD2 by the pull-up current branch and the pull-down current branch are basically the same (or the error is within the design requirements), and NLD1 and NLD2 of the common-gate circuit operate in the constant current region. Therefore, when the circuit loses balance, that is, when the external load changes and causes the Vout at the output end to show a changing trend, the common-gate circuit and the current branch can jointly form a current fast-response adjustment circuit, and then use the current that can respond more quickly to quickly adjust the gate voltage of the buck power tube to change the working state of the buck tube, thereby changing the buck power tube after the working state adjusts the potential of the output end to achieve stable output of the output power tube.

[0024] Therefore, even if changes in the external load may cause the output voltage Vout of the output power tube M11 to change, the above-mentioned fast response loop can be used to complete the rapid adjustment of the output stage buck power tube and the output power tube, thereby avoiding the impact of external load changes on the output voltage Vout.

[0025] The principle of loop fast adjustment is as follows:

[0026] For example, when the output voltage Vout on the source of the output power tube M11 may show a downward trend due to load changes, such as Figure 2 The dotted arrow in the middle indicates that when Vout decreases, the drain potential of M11 tends to decrease (that is, the source potential of NLD1 tends to decrease), and then the gate-source voltage of NLD1 tends to increase (because Vb1 of the bias power supply in the common-gate circuit is usually set at a certain value, so the decrease in the source potential means that the gate-source voltage will increase). At this time, the working current of NLD1 will tend to increase, but because the working current provided by the pull-up current branch to NLD2 is proportional to the working current of NLD1, the working current of NLD2 also tends to increase, that is, the current flowing from the pull-up current branch to the drain of NLD2 is greater than the current pulled down by the pull-down current branch, thereby increasing the drain voltage of NLD2. The increase in the drain potential of NLD2 means that the gate voltage of NLD0 increases at the same time, so the gate-source voltage of NLD0 tends to increase. Finally, when the gate-source voltage of NLD0 increases, the source potential of NLD0 increases (that is, the potential at the output end increases) to offset the decreasing trend of the output voltage Vout. Therefore, the common gate circuit and the current branch quickly adjust the source potential of the step-down power tube NLD0 in the upward direction, which can prevent the output voltage Vout on the source of the output power tube M11 from decreasing.

[0027] For example, when the output voltage Vout on the source of the output power tube M11 may show an upward trend due to load changes, such as Figure 2The dotted arrow in the middle indicates that when Vout rises, the drain potential of M11 tends to rise (that is, the source potential of NLD1 tends to rise), and then the gate-source voltage of NLD1 tends to fall (because Vb1 of the bias power supply in the common-gate circuit is usually set at a certain value, so when the source potential rises, the gate-source voltage will fall). At this time, the working current of NLD1 will tend to decrease, but because the working current provided by the pull-up current branch to NLD2 is proportional to the working current of NLD1, the working current of NLD2 also tends to decrease, that is, the current flowing from the pull-up current branch to the drain of NLD2 is less than the current pulled down by the pull-down current branch, thereby causing the drain voltage of NLD2 to drop (that is, the gate voltage of NLD0 drops), so the gate-source voltage of NLD0 tends to decrease, and finally when the gate-source voltage of NLD0 develops in a downward direction, the source potential of NLD0 decreases (that is, the potential at the output end decreases) to offset the rising trend of the output voltage Vout. Therefore, the common gate circuit and the current branch quickly adjust the source potential of the step-down power tube NLD0 in a downward direction, thereby preventing the output voltage Vout on the source of the output power tube M11 from rising.

[0028] In other words, since the buck power tube NLD0 is used to step down the input voltage Vin of the input power supply end and output it to the source of the output power tube M11 to form the output voltage Vout, and the gate of the output power tube M11 is generally controlled by the error control voltage provided by the internal circuit to form a stable output voltage Vout at the output end; therefore, when the output voltage Vout at the output end rises due to a change in the connected external load, the gate-source voltage of NLD1 will be caused to drop, thereby causing the pull-up current provided by the pull-up current branch to NLD2 to be less than the pull-down current provided by the pull-down current branch, and then causing the gate voltage of the buck power tube NLD0 to drop, and finally causing the output voltage to drop and maintain the stability of the output voltage Vout; and, when the output voltage Vout at the output end drops due to a change in the connected external load, the gate-source voltage of NLD1 will be caused to rise, thereby causing the pull-up current provided by the pull-up current branch to NLD2 to be greater than the pull-down current provided by the pull-down current branch, causing the gate voltage of the buck power tube NLD0 to rise, and finally causing the output voltage to rise.

[0029] By using the high-voltage NLD tube (NLDMOS tube) in the output stage as a step-down power tube (such as Figure 2 The NLD0 power tube is shown in the figure), and the output end can be adjusted by quickly adjusting the buck power tube, so a high-bandwidth fast feedback loop can be set up (for example Figure 2In the circuit, a fast feedback loop is formed by transistors such as NLD0, M11, NLD1, NLD2, PLD0, and PLD1. Since the bandwidth of the fast feedback loop is only affected by the gate parasitic capacitance and transconductance of the NLD0 power tube, the bandwidth of the feedback loop can be very wide, so that the feedback loop can quickly follow the rapid changes in the output voltage to adjust the working state of the power tube, that is, the output capacity of the power tube can be adjusted more quickly according to the output voltage through the feedback loop, thereby achieving a voltage stabilization effect of reducing the sudden change of the output voltage.

[0030] In summary, the improvement ideas of this application are:

[0031] (1) Loop adjustment is achieved through rapid adjustment of pull-up and pull-down currents: the high-voltage NLD0 is used as a high-voltage step-down power tube to generate the output voltage, and NLD1 and NLD2 are used to form a common-gate circuit to adjust the current source circuit (i.e., the pull-up current branch and the pull-down current branch), so that the gate voltage of NLD0 can be quickly adjusted and controlled, and finally the output voltage can be quickly adjusted;

[0032] (2) Use a common gate structure to form a high-bandwidth fast feedback loop: A common gate structure is used at the output end to build an adjustment circuit for the fast feedback loop, so that the bandwidth of the fast feedback loop is only affected by the gate parasitic capacitance and transconductance of the output stage buck power tube NLD0. Therefore, the bandwidth of the feedback loop can be very wide, so that the output capacity of the power tube can be adjusted more quickly according to the output voltage, thereby achieving the effect of reducing the output voltage mutation.

[0033] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0034] Example 1: Fast-response on-chip high-bandwidth feedback loop

[0035] like Figure 2 As shown, an on-chip high-bandwidth feedback loop provided by an embodiment of the present specification may include the following circuit units: a first pull-up current branch, a first pull-down current branch, a common-gate adjustment circuit, a buck power tube NLD0, and an output power tube M11, wherein the first pull-up current branch and the first pull-down current branch jointly provide pull-up current and pull-down current for the common-gate adjustment circuit, so that the working state of the common-gate adjustment circuit loses a balanced state by following the change of the external load through the pull-up current and the pull-down current, and then the working point of the output stage (i.e., the buck power tube and the output power tube) is changed by utilizing the need for the common-gate adjustment circuit to maintain a balanced state, so that the output stage can quickly follow the load change for adjustment.

[0036] refer to Figure 2 The interconnection and principle of each circuit unit in the loop are as follows:

[0037] The common-gate adjustment circuit includes a first transistor NLD1 and a second transistor NLD2, wherein the gate of the first transistor NLD1 and the gate of the second transistor NLD2 are connected to a first bias power supply Vb1; the source of the first transistor NLD1 is connected to the drain of the output power tube M11; the drain of the second transistor NLD2 is connected to the gate of the buck power tube NLD0; the drain of the buck power tube NLD0 is connected to the input power supply terminal Vin, the source of the buck power tube NLD0 is connected to the source of the output power tube M11 as the output terminal Vout, and the gate of the output power tube M11 is controlled by the error control voltage Verr; the drain of the first transistor NLD1 and the drain of the second transistor NLD2 are respectively connected to the input power supply terminal Vin through a first pull-up current branch, and the source of the second transistor NLD2 and the drain of the output power tube M11 are respectively grounded through a first pull-down current branch.

[0038] Therefore, the loop of this application has the following characteristics:

[0039] On the one hand, since the buck power tube NLD0 is used to step down the input voltage of the high-voltage side input power supply terminal Vin to form a lower voltage which is output from the source of the output power tube M11, that is, the output voltage is obtained by converting the high voltage into a low voltage by the buck power tube NLD0, and the output voltage is provided to the outside through the output power tube M11 in the output stage, so after using the buck power tube NLD0 and the output power tube M11, the overall circuit can adapt to a very wide input voltage range.

[0040] Secondly, since the adjustment transistors (i.e., NLD1 and NLD2) in the common-gate adjustment circuit are stably biased by the first bias power supply Vb1, the adjustment transistors can form a stable gate voltage. Therefore, when the first pull-up current branch and the first pull-down current branch are controlled proportional current sources, the first pull-up current branch can provide the first pull-up current for the second transistor, and the first pull-down current branch can provide the first pull-down current for the second transistor. Moreover, since the first pull-up current is proportional to the operating current of the first transistor NLD1, and the first pull-down current is also proportional to the sum of the operating current of the first transistor NLD1 and the operating current of the output power tube M11, the first pull-up current and the first pull-down current together enable the output power tube M11 to stably obtain the corresponding operating current, thereby enabling the output power tube M11 to output a stable output voltage at the output terminal Vout.

[0041] Third, when the external load suddenly changes and causes the voltage change trend of the output terminal Vout, since the common gate adjustment circuit, the current branch, etc. are all fast response units, the adjustment response of the above loop depends on the buck power tube NLD0 of the output stage. Therefore, it is only necessary to use the common gate adjustment circuit and the current branch to quickly respond to the sudden change of the external load, so as to quickly adjust the buck power tube NLD0, thereby ensuring that the on-chip circuit can quickly respond to the sudden change of the external load.

[0042] In some implementations, the current branch may be a proportional current source, and the implementation of the current source may refer to related practices in the prior art, or may refer to a preferred implementation scheme provided in the following example.

[0043] refer to Figure 3 As shown, transistors are used to form a pull-up current branch and / or a pull-down current branch in the form of a proportional current source.

[0044] In an exemplary implementation, the first pull-up current branch includes a third transistor PLD0 and a fourth transistor PLD1, the source of the third transistor PLD0 and the source of the fourth transistor PLD1 are connected to the input power supply terminal Vin, the gate and drain of the third transistor PLD0 are connected to the gate of the fourth transistor PLD1, the drain of the third transistor PLD0 is connected to the drain of the first transistor NLD1, and the drain of the fourth transistor PLD1 is connected to the drain of the second transistor NLD2 and the gate of the buck power transistor NLD0. Therefore, based on the above circuit connection, the third transistor PLD0 and the fourth transistor PLD1 form a first current mirror, which provides a first pull-up current for the second transistor NLD2.

[0045] In an exemplary implementation, the first pull-down current branch includes a fifth transistor NM13 and a sixth transistor NM14, the source of the fifth transistor NM13 and the source of the sixth transistor NM14 are grounded, the gate of the fifth transistor NM13 and the gate of the sixth transistor NM14 are controlled by a proportional control current source, the drain of the fifth transistor NM13 is connected to the source of the second transistor NLD2, and the drain of the sixth transistor NM14 is connected to the source of the first transistor NLD1 and the drain of the output power tube M11. Therefore, based on the above circuit connection, the fifth transistor NM13 and the sixth transistor NM14 constitute a proportional current mirror, which is used to provide the first pull-down current for the second transistor NLD2.

[0046] Therefore, using a transistor circuit to form a current source is conducive to simplifying the overall circuit design and can also ensure circuit accuracy. It should be noted that the current source can also adopt other circuit forms, which will not be described in detail here.

[0047] In some implementations, a laterally diffused metal oxide semiconductor (LDMOS) with characteristics such as high voltage resistance, fast current response, and low on-resistance can be selected as the transistor of the current mirror. Therefore, the third transistor PLD0 and the fourth transistor PLD1 can be selected as PLDMOS transistors, so that the first current mirror formed by the PLDMOS transistors can better adapt to the current mirror application in the high voltage domain.

[0048] In some implementations, NMOS transistors with high voltage resistance, fast current response speed, and large current capacity can be selected as constant current working transistors of the pull-down current branch. Therefore, the fifth transistor NM13 and the sixth transistor NM14 can be selected as NMOS transistors.

[0049] In some embodiments, the step-down power tube NLD0 can also be selected as a NLDMOS tube that can withstand high voltage and large current, the output power tube M11 can be selected as a PMOS tube with very small on-resistance, and the first transistor NLD1 and the second transistor NLD2 can both be selected as NLDMOS tubes that can withstand high voltage and large current.

[0050] In one embodiment, the pull-down current branch may be a controlled current source, and the controlled current source is realized by setting a proportional control current, so that the current can adapt to different current adjustment requirements.

[0051] refer to Figure 3 As shown, in the pull-down current branch, the gates of the fifth transistor NM13 and the sixth transistor NM14 are controlled by the proportional control current, so the proportional control current can be flexibly set to better adapt the pull-up current branch in a balanced state, so that the pull-down current branch and the pull-up current branch can adapt to various current adjustment requirements, further improving the adaptability of the loop and facilitating the application of the loop under different adjustment requirements.

[0052] Based on the same inventive concept, the embodiments of this specification also provide an on-chip fast response high-voltage LDO (ie, an LDO chip solution).

[0053] refer to Figure 4 As shown, an on-chip fast response high-voltage LDO may include the following circuit units: an on-chip high-bandwidth feedback loop, an on-chip capacitor C0, and an operational amplifier OP.

[0054] In implementation, the on-chip high-bandwidth feedback loop is an on-chip high-bandwidth feedback loop as described in any example in this specification. For details, please refer to the aforementioned example content and will not be expanded here.

[0055] refer to Figure 4The circuit connection diagram is as follows: one input terminal of the operational amplifier OP serves as an external feedback voltage input terminal, for example, the feedback voltage input terminal is connected to an external feedback voltage (for example, a feedback voltage obtained by a voltage divider formed by resistors R1 and R2), and the other input terminal of the operational amplifier OP is connected to a reference voltage Vref, and the output terminal of the operational amplifier OP is connected to the gate of the output power tube M11 and one end of the on-chip capacitor C0, and the other end of the on-chip capacitor C0 is grounded.

[0056] Based on the above connection relationship, the working principle of the circuit is as follows: the on-chip capacitor C0 is used as the load capacitor of the operational amplifier OP to generate the main pole of the operational amplifier loop; and the operational amplifier OP is used to form an error control voltage (i.e., Verr shown in the figure) after error amplification according to the negative feedback voltage input from the external feedback voltage input terminal, so that the gate of the output power tube M11 adjusts the operating point of the transistor under the action of the error control voltage Verr to achieve the output setting of the corresponding voltage.

[0057] In summary, by using a fast response and adjustment loop inside the LDO, the output of the LDO can quickly respond to changes in the external load.

[0058] In some implementations, the implementation of the operational amplifier may refer to related practices in the prior art, or may refer to a preferred implementation scheme provided in the following example.

[0059] In an implementation example, the operational amplifier OP may include the following circuit units: a long-tail differential input stage, a common-gate differential adjustment circuit, and a common-source differential error amplifier stage. It should be noted that the specific implementation methods of the circuit units such as the long-tail differential input stage, the common-gate differential adjustment circuit, and the common-source differential error amplifier stage can refer to the relevant circuits of the prior art, and can also refer to the preferred circuit implementation methods provided by the following corresponding examples.

[0060] refer to Figure 5 For example, the design examples of each circuit unit can be as follows:

[0061] In one example, the long-tail differential input stage includes a ninth transistor M5, a tenth transistor M4, and an eleventh transistor M3, the gate of the ninth transistor M5 is connected to the external feedback voltage as one input end of the differential, the gate of the tenth transistor M4 is connected to the reference voltage Vref as another input end of the differential, the source of the ninth transistor M5, the source of the tenth transistor M4 are connected to the drain of the eleventh transistor M3, the source of the eleventh transistor M3 is connected to the internal power supply terminal V1, and the gate of the eleventh transistor M3 is controlled by the second proportional control current. The drain of the ninth transistor M5 and the drain of the tenth transistor M4 are respectively connected to the corresponding differential input end of the common-gate differential adjustment circuit of the next stage as differential output ends.

[0062] Therefore, M3 provides the current operating point during differential amplification for the differential pair tubes M4 and M5, and the current operating point can be adjusted, which is very beneficial for the differential circuit to be set according to different operating point requirements, so that it can flexibly adapt to different differential amplification requirements, improve the circuit adaptability, and be more conducive to the circuit setting and application under different circuit performances.

[0063] In one example, the common-gate differential adjustment circuit includes a common-gate amplifier circuit, a second pull-up current branch, and a second pull-down current branch. It should be noted that the common-gate amplifier circuit, the second pull-up current branch, and the second pull-down current branch can be other circuit forms in the prior art.

[0064] For the common-gate amplifier circuit, the present specification provides a circuit example of a common-gate amplifier circuit based on a transistor and a second pull-up current branch:

[0065] refer to Figure 5 Schematically, the common-gate amplifier circuit includes a twelfth transistor NM8 and a thirteenth transistor NM9, and the second pull-up current branch includes a fourteenth transistor M6 and a fifteenth transistor M8;

[0066] And, the transistor connection relationship is shown as follows: the gate of the twelfth transistor NM8 and the gate of the thirteenth transistor NM9 are connected and then connected to the second bias power supply Vb2; the drain of the twelfth transistor NM8 is connected to the drain of the fourteenth transistor M6, the drain of the thirteenth transistor NM9 is connected to the drain of the fifteenth transistor M8, the source of the fourteenth transistor M6 and the source of the fifteenth transistor M8 are connected to the internal power supply terminal V1, the drain and gate of the fourteenth transistor M6 are connected and serve as the first differential output terminal of the common-gate differential adjustment circuit, and the drain and gate of the fifteenth transistor M8 are connected and serve as the second differential output terminal of the common-gate differential adjustment circuit; the source of the twelfth transistor NM8 and the source of the thirteenth transistor NM9 are grounded after passing through the second pull-down current branch respectively; the drain of the twelfth transistor and the drain of the thirteenth transistor are respectively connected as differential input terminals to the corresponding differential output terminals of the long-tail differential input stage of the previous stage.

[0067] In implementation, the second pull-down current branch can be in the form of a current source in the prior art, or can be a preferred circuit implementation method given in subsequent examples of this application. For details, please refer to the subsequent corresponding examples.

[0068] In one example, an embodiment of the present specification provides a transistor-based common-source differential error amplifier stage circuit.

[0069] refer to Figure 5Schematically, the common-source differential error amplifier stage circuit includes the following transistors: a sixteenth transistor M7, a seventeenth transistor M9, an eighteenth transistor M10, a nineteenth transistor NM12, a twentieth transistor NM10 and a twenty-first transistor NM11;

[0070] The circuit connection relationship is shown as follows: the gate of the sixteenth transistor M7 is connected to the first differential output terminal of the common-gate differential adjustment circuit, the gate of the seventeenth transistor M9 is connected to the second differential output terminal of the common-gate differential adjustment circuit, the source of the sixteenth transistor M7 and the source of the seventeenth transistor M9 are connected to the internal power supply terminal V1; the gate and drain of the twentieth transistor NM10 are connected to the drain of the sixteenth transistor M7 and the gate of the twenty-first transistor NM11, and the source of the twentieth transistor NM10 and the source of the twenty-first transistor NM11 are connected to the ground; the drain of the seventeenth transistor M9 is connected to the source of the eighteenth transistor M10, the gate of the eighteenth transistor M10 is connected to the third bias power supply Vb3, the drain of the eighteenth transistor M10 is connected to the drain of the nineteenth transistor NM12 as the error control voltage output terminal (that is, marked as Verr in the above example), the gate of the nineteenth transistor NM12 is connected to the fourth bias power supply Vb4, and the source of the nineteenth transistor NM12 is connected to the drain of the twenty-first transistor NM11.

[0071] In some implementations, the embodiments of this specification provide a second pull-down current branch based on a transistor.

[0072] refer to Figure 5 As shown, the second pull-down current branch includes the following transistors: a twenty-second transistor NM4 and a twenty-third transistor NM6, wherein the gate of the twenty-second transistor NM4 and the gate of the twenty-third transistor NM6 are controlled by a third proportional control current, the source of the twelfth transistor NM8 is connected to the drain of the twenty-second transistor NM4, the source of the thirteenth transistor NM9 is connected to the drain of the twenty-third transistor NM6, and the source of the twenty-second transistor NM4 and the source of the twenty-third transistor NM6 are grounded.

[0073] In some implementations, a current regulating unit is added to the second pull-down current branch, so that the second pull-down current branch can better provide a pull-down current to the common-gate amplifier circuit.

[0074] refer to Figure 5As shown, the second pull-down current branch also includes a twenty-fourth transistor and a twenty-fifth transistor, wherein the gate of the twenty-fourth transistor and the gate of the twenty-fifth transistor are controlled by a fourth proportional control current, the source of the twenty-second transistor NM4 is connected to the drain of the twenty-fourth transistor NM5, the source of the twenty-third transistor NM6 is connected to the drain of the twenty-fifth transistor NM7, and the source of the twenty-fourth transistor NM5 and the source of the twenty-fifth transistor NM7 are grounded.

[0075] In some implementations, for respective reference base currents required by operational amplifier circuits, the form of a reference circuit for providing current may refer to related practices in the prior art, or may refer to a preferred implementation scheme provided in the following example.

[0076] In one implementation example, the on-chip fast response high-voltage LDO also includes a current reference circuit for providing a proportional current, the current reference circuit including a reference current source Iref and a plurality of current mirror circuits, wherein the reference current source is used to provide a reference current, and the plurality of current mirror circuits generate corresponding proportional control currents based on the reference current source.

[0077] refer to Figure 5 Schematically, the plurality of current mirror circuits include a twenty-sixth transistor M0, a twenty-seventh transistor M1, a twenty-eighth transistor M2, a twenty-ninth transistor NM1, a thirtieth transistor NM2, a thirty-first transistor NM0 and a thirty-second transistor NM3.

[0078] The connection diagram of each transistor is as follows: the gate of the twenty-sixth transistor M0 is connected to the gate of the twenty-seventh transistor M1, the source of the twenty-sixth transistor M0 and the source of the twenty-seventh transistor M1 are connected to the internal power supply terminal, the gate and drain of the twenty-sixth transistor M0 are connected to one end of the reference current source Iref, and the other end of the reference current source Iref is grounded, the gate of the twenty-eighth transistor M2 is connected to the gate of the twenty-sixth transistor M0 and the gate of the twenty-seventh transistor M1, the source of the twenty-eighth transistor M2 is connected to the internal power supply terminal V1, and the twenty-eighth transistor The drain of M2 is connected to the drain of the 30th transistor NM2 and the gate of the 32nd transistor NM3, the gate of the 29th transistor NM1 is connected to the gate of the 30th transistor NM0, the source of the 29th transistor NM1 is connected to the drain of the 31st transistor NM2, the drain of the 29th transistor NM1 is connected to the gate of the 31st transistor NM0 and the drain of the 27th transistor M1, the source of the 31st transistor NM0 is grounded, the source of the 30th transistor NM2 is connected to the drain of the 32nd transistor NM3, and the source of the 32nd transistor NM3 is grounded.

[0079] The schematic diagram of providing proportional control current to the outside is as follows: the gate of the twenty-eighth transistor M2 provides the corresponding proportional control current to the outside, the gate of the thirtieth transistor NM2 provides the corresponding proportional control current to the outside, and the gate of the thirty-second transistor NM3 provides the corresponding proportional control current to the outside.

[0080] Based on the same inventive concept, the embodiments of this specification also provide a high-voltage linear voltage regulator circuit, which is used to input a higher input voltage into the high-voltage domain and obtain a lower output voltage based on linear voltage regulation, thereby realizing the application need that the linear voltage regulator circuit can regulate a wide range of input voltages.

[0081] Refer to the above Figure 4 As shown, the high-voltage voltage stabilizing circuit includes a feedback branch and an LDO chip, wherein the feedback branch includes a first resistor R1 and a second resistor R2; the LDO chip is an on-chip fast-response high-voltage LDO as described in any example in this specification.

[0082] The circuit connection relationship is as follows: one end of the first resistor R1 is connected to the source of the output power tube M11 in the LDO chip, and the other end of the first resistor R1 is connected to one end of the second resistor R2 as a negative feedback terminal VFB, and the negative feedback terminal is connected to an input end of the operational amplifier OP in the LDO chip as an external feedback voltage input end, and the other end of the second resistor R2 is grounded. It should be noted that in the voltage stabilization circuit, filter capacitors (such as Cin and Cout shown in the figure) can also be added to the input and output ends. In addition, because the LDO chip has fast response and adjustment capabilities, the output filter capacitor Cout does not need to use a large capacitor, which effectively avoids the need to use a large capacity filter capacitor at the traditional output end, which affects the response of the internal circuit of the LDO chip to the sudden change of the external load.

[0083] A simple circuit analysis is performed below on each circuit involved in the aforementioned examples, but those skilled in the art should be able to understand that the analysis content is convenient for understanding and implementation and should not constitute a specific limitation.

[0084] refer to Figure 5 The schematic circuit and analysis contents are explained as follows:

[0085] On the one hand, the reference current Iref, the PMOS tubes M0, M1, M2, and the NMOS tubes NM0, NM1, NM2, NM3 form a current mirror bias circuit that provides a plurality of bias currents.

[0086] On the other hand, PMOS tubes M3, M4, M5, M6, M7, M8, M9, M10 and NMOS tubes NM4, NM5, NM6, NM7, NM8, NM9, NM10, NM11, and NM12 constitute an operational amplifier circuit, in which vb1, vb2, and vb3 are input bias voltages, vref is the input reference voltage, and C0 is an on-chip capacitor serving as the load capacitor of the output of the operational amplifier circuit.

[0087] On the three aspects, NMOS tubes NM13, NM14, PMOS tube M11, high-voltage NMOS tubes NLD0, NLD1, NLD2, and high-voltage PMOS tubes PLD0, PLD1 constitute a loop output stage circuit, in which vb4 is the input bias voltage, and resistors R1, R2 are the output feedback resistor network.

[0088] The gain of the op amp circuit is given by:

[0089]

[0090] in, is the transconductance of M4 and M5, and the size ratios between M7 and M6, and between M9 and M8 are all M in the gain formula (where the specific value of M can be determined according to application needs and is not limited here). , is the transconductance and small signal resistance of M10, , is the transconductance and small signal resistance of NM12, , It is the small signal resistance of M9 and NM11.

[0091] The output of the operational amplifier forms a negative feedback loop through M11 and resistors R1 and R2. The loop gain of the loop is:

[0092]

[0093] The main pole of the loop is:

[0094]

[0095] The bandwidth of the loop is:

[0096]

[0097] The output stage NLD0, M11, NLD1, PLD0, and PLD1 form a fast feedback loop, the loop gain of which is:

[0098]

[0099] in, is the small signal resistance of PLD1, , is the transconductance and small signal resistance of NLD2, is the small signal resistance of NM13, is the transconductance of the power tube NLD0.

[0100] The bandwidth of the loop is:

[0101]

[0102] Wherein, Cp is the parasitic capacitance of NLD0.

[0103] The steady-state value of the LDO output voltage is mainly determined by the feedback formed by R1 and R2. The output voltage is:

[0104]

[0105] When the load changes, the LDO output voltage mutation is mainly controlled by the fast feedback loop. Because the bandwidth of the fast feedback loop is only affected by the gate parasitic capacitance and transconductance of the power tube, the loop bandwidth is very wide, so it can follow the rapid changes in the output voltage.

[0106] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and the relevant parts can be referred to the partial description of the previous embodiments.

[0107] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An on-chip high bandwidth feedback loop, characterized in that: It includes a first pull-up current branch, a first pull-down current branch, a common-gate adjustment circuit, a buck power tube and an output power tube; wherein the common-gate adjustment circuit includes a first transistor and a second transistor, the gate of the first transistor and the gate of the second transistor are connected to a first bias power supply; the source of the first transistor is connected to the drain of the output power tube; the drain of the second transistor is connected to the gate of the buck power tube; the drain of the buck power tube is connected to the input power supply end, the source of the buck power tube is connected to the source of the output power tube as the output end, and the gate of the output power tube is controlled by an error control voltage; the drain of the first transistor and the drain of the second transistor are respectively connected to the input power supply end through the first pull-up current branch, and the source of the second transistor and the drain of the output power tube are respectively grounded through the first pull-down current branch; Among them, the buck power tube is used to step down the input voltage of the input power supply end and output it to the source of the output power tube to form an output voltage; under the bias of the first bias power supply, the first pull-up current branch and the first pull-down current branch are controlled proportional current sources, the first pull-up current branch is used to provide a first pull-up current for the second transistor, the first pull-up current is proportional to the working current of the first transistor, and the first pull-down current branch is used to provide a first pull-down current for the second transistor, the first pull-down current is proportional to the sum of the working current of the first transistor and the working current of the output power tube, the first pull-up current and the first pull-down current together enable the output power tube to stably obtain the corresponding working current, so that the output power tube outputs a stable output voltage at the output end.

2. The on-chip high bandwidth feedback loop according to claim 1, characterized in that: The first pull-up current branch includes a third transistor and a fourth transistor, wherein the source of the third transistor and the source of the fourth transistor are connected to the input power supply terminal, the gate and the drain of the third transistor are connected to the gate of the fourth transistor, the drain of the third transistor is connected to the drain of the first transistor, and the drain of the fourth transistor is connected to the drain of the second transistor and the gate of the buck power tube; the third transistor and the fourth transistor constitute a first current mirror for providing a first pull-up current; And / or, the first pull-down current branch includes a fifth transistor and a sixth transistor, wherein the source of the fifth transistor and the source of the sixth transistor are grounded, the gate of the fifth transistor and the gate of the sixth transistor are controlled by a proportional current source, the drain of the fifth transistor is connected to the source of the second transistor, and the drain of the sixth transistor is connected to the source of the first transistor and the drain of the output power tube; The fifth transistor and the sixth transistor form a proportional current mirror for providing a first pull-down current.

3. The on-chip high bandwidth feedback loop according to claim 2, characterized in that: The third transistor and the fourth transistor are PLDMOS transistors; and / or, the fifth transistor and the sixth transistor are NMOS transistors; and / or, the proportional current mirror formed by the fifth transistor and the sixth transistor is a current mirror controlled by a first proportional control current.

4. The on-chip high-bandwidth feedback loop according to any one of claims 1 to 3, characterized in that: The step-down power tube is a high-voltage-resistant NLDMOS tube, the output power tube is a PMOS tube, and the first transistor and the second transistor are NLDMOS tubes.

5. An on-chip fast response high voltage LDO, characterized in that: include: An on-chip high-bandwidth feedback loop, an on-chip capacitor and an operational amplifier, wherein the on-chip high-bandwidth feedback loop is the on-chip high-bandwidth feedback loop as claimed in any one of claims 1 to 4; one input end of the operational amplifier serves as an external feedback voltage input end, the other input end of the operational amplifier is connected to a reference voltage, the output end of the operational amplifier is connected to the gate of an output power tube and one end of an on-chip capacitor, the other end of the on-chip capacitor is grounded, the on-chip capacitor serves as a load capacitor of the operational amplifier, and is used to generate a main pole of the operational amplifier loop, and the operational amplifier is used to form an error control voltage after error amplification according to a negative feedback voltage input from the external feedback voltage input end, so that the gate of the output power tube adjusts the operating point of the transistor under the action of the error control voltage.

6. The on-chip fast response high voltage LDO according to claim 5, characterized in that: The operational amplifier comprises a long-tail differential input stage, a common-gate differential adjustment circuit and a common-source differential error amplifier stage; Wherein, the long-tail differential input stage includes a ninth transistor, a tenth transistor and an eleventh transistor, the gate of the ninth transistor is connected to the external feedback voltage as one input end of the differential, the gate of the tenth transistor is connected to the reference voltage as another input end of the differential, the source of the ninth transistor, the source of the tenth transistor and the drain of the eleventh transistor are connected, the source of the eleventh transistor is connected to the internal power supply end, and the gate of the eleventh transistor is controlled by the second proportional control current; the drain of the ninth transistor and the drain of the tenth transistor are respectively connected to the corresponding differential input end of the common-gate differential adjustment circuit of the next stage as differential output ends; The common-gate differential adjustment circuit includes a common-gate amplifier circuit, a second pull-up current branch and a second pull-down current branch; wherein the common-gate amplifier circuit includes a twelfth transistor and a thirteenth transistor, and the second pull-up current branch includes a fourteenth transistor and a fifteenth transistor; the gate of the twelfth transistor is connected to the gate of the thirteenth transistor and then connected to the second bias power supply; the drain of the twelfth transistor is connected to the drain of the fourteenth transistor, the drain of the thirteenth transistor is connected to the drain of the fifteenth transistor, the source of the fourteenth transistor and the source of the fifteenth transistor are connected to the internal power supply terminal, the drain and the gate of the fourteenth transistor are connected as the first differential output terminal of the common-gate differential adjustment circuit, and the drain and the gate of the fifteenth transistor are connected as the second differential output terminal of the common-gate differential adjustment circuit; the source of the twelfth transistor and the source of the thirteenth transistor are respectively grounded after passing through the second pull-down current branch; the drain of the twelfth transistor and the drain of the thirteenth transistor are respectively connected as differential input terminals to the corresponding differential output terminals of the long-tail differential input stage of the previous stage; The common-source differential error amplifier stage includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twentieth transistor and a twenty-first transistor; wherein the gate of the sixteenth transistor is connected to the first differential output terminal of the common-gate differential adjustment circuit, the gate of the seventeenth transistor is connected to the second differential output terminal of the common-gate differential adjustment circuit, the source of the sixteenth transistor and the source of the seventeenth transistor are connected to the internal power supply terminal; the gate and the drain of the twentieth transistor are connected to the drain of the sixteenth transistor and the gate of the twenty-first transistor, and the source of the twentieth transistor and the source of the twenty-first transistor are connected to the ground; the drain of the seventeenth transistor is connected to the source of the eighteenth transistor, the gate of the eighteenth transistor is connected to the third bias power supply, the drain of the eighteenth transistor is connected to the drain of the nineteenth transistor as the error control voltage output terminal, the gate of the nineteenth transistor is connected to the fourth bias power supply, and the source of the nineteenth transistor is connected to the drain of the twenty-first transistor.

7. The on-chip fast response high voltage LDO according to claim 6, characterized in that: The second pull-down current branch includes a twenty-second transistor and a twenty-third transistor, wherein the gate of the twenty-second transistor and the gate of the twenty-third transistor are controlled by a third proportional control current, the source of the twelfth transistor is connected to the drain of the twenty-second transistor, the source of the thirteenth transistor is connected to the drain of the twenty-third transistor, and the source of the twenty-second transistor and the source of the twenty-third transistor are grounded.

8. The on-chip fast response high voltage LDO according to claim 6, characterized in that: The second pull-down current branch includes a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor and a twenty-fifth transistor, wherein the gate of the twenty-second transistor and the gate of the twenty-third transistor are controlled by a third proportional control current, the gate of the twenty-fourth transistor and the gate of the twenty-fifth transistor are controlled by a fourth proportional control current, the source of the twelfth transistor is connected to the drain of the twenty-second transistor, the source of the thirteenth transistor is connected to the drain of the twenty-third transistor, the source of the twenty-second transistor is connected to the drain of the twenty-fourth transistor, the source of the twenty-third transistor is connected to the drain of the twenty-fifth transistor, and the source of the twenty-fourth transistor and the source of the twenty-fifth transistor are grounded.

9. The on-chip fast response high voltage LDO according to claim 5, characterized in that: The on-chip fast response high-voltage LDO further includes a current reference circuit for providing a proportional current, wherein the current reference circuit includes a reference current source and a plurality of current mirror circuits, wherein the reference current source is used to provide a reference current, and the plurality of current mirror circuits generate corresponding proportional control currents based on the reference current source; The plurality of current mirror circuits include a twenty-sixth transistor, a twenty-seventh transistor, a twenty-eighth transistor, a twenty-ninth transistor, a thirtieth transistor, a thirty-first transistor and a thirty-second transistor; wherein the gate of the twenty-sixth transistor is connected to the gate of the twenty-seventh transistor, the source of the twenty-sixth transistor and the source of the twenty-seventh transistor are connected to the internal power supply terminal, the gate and the drain of the twenty-sixth transistor are connected to one end of the reference current source, the other end of the reference current source is grounded, the gate of the twenty-eighth transistor is connected to the gate of the twenty-sixth transistor and the gate of the twenty-seventh transistor, the source of the twenty-eighth transistor is connected to the internal power supply terminal, and the twenty-eighth transistor The drain of the twenty-eighth transistor is connected to the drain of the thirtieth transistor and the gate of the thirty-second transistor, the gate of the twenty-ninth transistor is connected to the gate of the thirtieth transistor, the source of the twenty-ninth transistor is connected to the drain of the thirty-first transistor, the drain of the twenty-ninth transistor is connected to the gate of the thirty-first transistor and the drain of the twenty-seventh transistor, the source of the thirty-first transistor is grounded, the source of the thirtieth transistor is connected to the drain of the thirty-second transistor, and the source of the thirty-second transistor is grounded; wherein the gate of the twenty-eighth transistor provides a corresponding proportional control current to the outside, the gate of the thirtieth transistor provides a corresponding proportional control current to the outside, and the gate of the thirty-second transistor provides a corresponding proportional control current to the outside.

10. A high voltage stabilizing circuit, characterized in that: The high-voltage voltage stabilizing circuit includes a feedback branch and an LDO chip, wherein the feedback branch includes a first resistor and a second resistor; the LDO chip is an on-chip fast-response high-voltage LDO as described in any one of claims 5 to 9; one end of the first resistor is connected to the source of the output power tube in the LDO chip, and the other end of the first resistor is connected to one end of the second resistor as a negative feedback end, the negative feedback end is connected to an input end of an operational amplifier in the LDO chip as an external feedback voltage input end, and the other end of the second resistor is grounded.

Images