A clock frequency division processing device

Abstract

This application relates to the field of clock frequency division technology, and particularly to a processing device for clock frequency division. The device includes a fractional frequency division module and an integer frequency division module. The input of the fractional frequency division module includes an original clock and a fractional frequency division coefficient, and the output of the fractional frequency division module is the clock after fractional frequency division processing; the input of the integer frequency division module includes the clock after fractional frequency division processing and an integer frequency division coefficient, and the output of the integer frequency division module is the target clock; the obtaining process of the fractional frequency division coefficient and the integer frequency division coefficient includes: obtaining the integer frequency division coefficient r1 according to the frequency of the original clock and the frequency of the target clock, r1 = rounddown(f0 / f1), where f0 is the frequency of the original clock and f1 is the frequency of the target clock; obtaining the fractional frequency division coefficient r2 according to the frequency of the original clock, the frequency of the target clock and the integer frequency division coefficient, r2 = f1 / f0 × r1. The present invention realizes clock frequency division.

Description

Technical Field

[0001] The present invention relates to the technical field of clock frequency division, and particularly to a processing device for clock frequency division. Background Art

[0002] The resolutions of different images are different. The resolution of an image refers to the number of pixels in the image, usually represented by the number of pixels in width and height, such as 1920×1080. If a lower clock frequency is used to attempt to display an image with a higher resolution, the transmission of one frame cannot be completed within the specified time, resulting in incomplete or torn image display. On the contrary, if too high a clock frequency is used to display an image with a lower resolution, although it will not affect the image display, it may lead to unnecessary power consumption increase. To ensure the correct and timely transmission and display of image data, different resolutions of images should be matched with different clock frequencies. How to achieve clock frequency division is an urgent problem to be solved. Summary of the Invention

[0003] The object of the present invention is to provide a processing device for clock frequency division to achieve clock frequency division.

[0004] According to the present invention, a processing device for clock frequency division is provided. The processing device for clock frequency division includes a fractional frequency division module and an integer frequency division module. The input of the fractional frequency division module includes an original clock and a fractional frequency division coefficient. The fractional frequency division module is used to perform fractional frequency division processing on the original clock according to the fractional frequency division coefficient, and the output of the fractional frequency division module is the clock after fractional frequency division processing; the input of the integer frequency division module includes the clock after fractional frequency division processing and an integer frequency division coefficient. The integer frequency division module is used to perform integer frequency division processing on the clock after fractional frequency division processing, and the output of the integer frequency division module is the target clock; the obtaining process of the fractional frequency division coefficient and the integer frequency division coefficient includes:

[0005] S100, obtain the frequency of the original clock.

[0006] S200, obtain the frequency of the target clock.

[0007] S300, obtain an integer frequency division coefficient r1 according to the frequency of the original clock and the frequency of the target clock, r1 = rounddown(f0 / f1), rounddown( ) is rounding down, f0 is the frequency of the original clock, and f1 is the frequency of the target clock.

[0008] S400, obtain a fractional frequency division coefficient r2 according to the frequency of the original clock, the frequency of the target clock, and the integer frequency division coefficient, r2 = f1 / f0×r1.

[0009] The present invention has at least the following beneficial effects compared with the prior art:

[0010] The present invention provides a clock frequency division processing device, which includes a fractional frequency division module and an integer frequency division module. The fractional frequency division module is used to perform fractional frequency division processing on the original clock according to a fractional frequency division coefficient, and the integer frequency division module is used to perform integer frequency division processing on the clock after fractional frequency division processing according to an integer frequency division coefficient. The clock obtained after integer frequency division processing is the target clock, which is also the clock that is desired to be obtained. The fractional frequency division coefficient and the integer frequency division coefficient of the present invention are obtained based on the frequency of the original clock and the frequency of the target clock. Based on the fractional frequency division coefficient and the integer frequency division coefficient of the present invention, the target clock can be obtained. The clock frequency division device of the present invention has higher efficiency in obtaining the target clock and higher accuracy of the obtained target clock, and can be used to meet the display requirements of images with different resolutions. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0012] Figure 1 It is a flowchart of the process for obtaining the fractional frequency division coefficient and the integer frequency division coefficient provided by the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0013] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0014] According to this embodiment, a clock frequency division processing device is provided. The clock frequency division processing device includes a fractional frequency division module and an integer frequency division module. The input of the fractional frequency division module includes an original clock and a fractional frequency division coefficient. The fractional frequency division module is used to perform fractional frequency division processing on the original clock according to the fractional frequency division coefficient. The output of the fractional frequency division module is the clock after fractional frequency division processing. The input of the integer frequency division module includes the clock after fractional frequency division processing and an integer frequency division coefficient. The integer frequency division module is used to perform integer frequency division processing on the clock after fractional frequency division processing. The output of the integer frequency division module is the target clock.

[0015] As Figure 1 shown, the process for obtaining the fractional frequency division coefficient and the integer frequency division coefficient includes:

[0016] S100, obtain the frequency of the original clock.

[0017] As a specific embodiment, the original clock is the system's basic clock.

[0018] S200, obtain the frequency of the target clock.

[0019] As an optional specific embodiment, the frequency of the target clock is obtained according to the resolution of the target image or the sampling rate of the audio coding in the usage mode. Those skilled in the art know that any method for obtaining the corresponding clock frequency according to the resolution of the image or the sampling rate of the audio coding in the prior art falls within the protection scope of the present invention.

[0020] As an optional specific embodiment, the frequency of the target clock is the frequency given by the user in the test mode.

[0021] In this embodiment, it is intended to divide the original clock. The original clock is known, the frequencies of the original clock and the target clock are known, and this embodiment can divide the original clock according to the frequencies of the original clock and the target clock, thereby obtaining the target clock.

[0022] S300, obtain the integer division coefficient r1 according to the frequencies of the original clock and the target clock, r1 = rounddown(f0 / f1), where rounddown( ) is rounding down, f0 is the frequency of the original clock, and f1 is the frequency of the target clock.

[0023] S400, obtain the fractional division coefficient r2 according to the frequencies of the original clock, the target clock, and the integer division coefficient, r2 = f1 / f0 × r1.

[0024] As a preferred specific embodiment, the fractional division coefficient is in decimal form. When storing the decimal fractional division coefficient in binary and performing subsequent calculations, set the number of bits for binary storage to qua, where qua satisfies: when the fractional division coefficient stored in qua-bit binary form is converted back to decimal form, the converted decimal result has a difference from r2 that is less than or equal to the preset difference threshold.

[0025] As a specific embodiment, the fractional frequency division module includes a first switch, a counting module, a judging module, and a second switch. The first switch is used to control the opening or closing of the fractional frequency division module. The inputs of the first switch include an original clock and a control signal, and the control signal is used to control the opening or closing of the first switch. The output of the first switch is the input of the counting module, and the input of the counting module further includes a fractional frequency division coefficient. The counting module is used to obtain a first count value according to the original clock and the fractional frequency division coefficient when the first switch is in the open state. The input of the judging module is the first count value, and the judging module is used to judge whether the first count value is greater than or equal to 1. If the first count value is greater than or equal to 1, the output value of the judging module is 1; if the first count value is less than 1, the output value of the judging module is 0. The inputs of the second switch include the output of the first switch and the output of the judging module. If the output value of the judging module is 1, the output of the second switch is the output of the first switch; if the output value of the judging module is 0, the output of the second switch is a low level.

[0026] As a specific embodiment, if the system enters the low-power mode, the control signal is a signal that makes the first switch in the off state; if the system is in the normal mode, the control signal is a signal that makes the first switch in the on state.

[0027] As a specific embodiment, the fractional frequency division module further includes a fractional frequency division coefficient selection module. The inputs of the fractional frequency division coefficient selection module include a mode selection signal, a fractional frequency division coefficient in the test mode, and a fractional frequency division coefficient in the use mode. The fractional frequency division coefficient selection module is used to select, according to the mode selection signal, the fractional frequency division coefficient in the test mode or the fractional frequency division coefficient in the use mode as the fractional frequency division coefficient output to the counting module. Thus, the clock frequency division processing device of this embodiment supports frequency division in two modes.

[0028] As a specific embodiment, in the use mode, if the binary form of the fractional frequency division coefficient in decimal form is the maximum value (i.e., each binary bit is 1), the original clock is directly used as the output of the second switch, that is, as the clock after fractional frequency division processing; if the binary form of the fractional frequency division coefficient in decimal form is not the maximum value, the counting module and the judging module are used to obtain the clock after fractional frequency division processing. Thus, the integer frequency division module can be verified separately and quickly.

[0029] As a specific embodiment, the obtaining of the first count value according to the original clock and the fractional frequency division coefficient when the first switch is in the open state includes:

[0030] S1, obtaining a first count value c corresponding to the i-th cycle of the original clocki ; c i = i × r2 - ∑ i-1 j=1 c j , c j is the output value of the judgment module corresponding to the j-th cycle of the original clock, where the value range of j is from 1 to i - 1, i ≥ 2; c1 = 0.

[0031] In this embodiment, the integer frequency division module is used to perform integer frequency division processing on the clock after fractional frequency division processing; as a preferred specific implementation, the integer frequency division module is used to implement the following steps:

[0032] S10, if r1 = 1, then enter S11; if r1 ≠ 1, then enter S12.

[0033] S11, determine the clock after fractional frequency division processing as the target clock.

[0034] S12, if r1 is an even number, then enter S13; if r1 is an odd number, then enter S14.

[0035] S13, perform a first processing on the clock after fractional frequency division processing according to the rising edge of the clock after fractional frequency division processing to obtain the target clock.

[0036] In this embodiment, the first processing includes: starting from the rising edge cumulative number of 1 of the clock after fractional frequency division processing, every time the rising edge cumulative number of the clock after fractional frequency division processing increases by r1 / 2, perform a level inversion.

[0037] Thus, the target clock remains high after the 1st rising edge of the clock after fractional frequency division processing until the (r1 / 2 + 1)-th rising edge of the clock after fractional frequency division processing arrives; and remains low after the (r1 / 2 + 1)-th rising edge of the clock after fractional frequency division processing until the (r1 + 1)-th rising edge of the clock after fractional frequency division processing arrives; and remains high after the (r1 + 1)-th rising edge of the clock after fractional frequency division processing until the (r1 / 2 + r1 + 1)-th rising edge of the clock after fractional frequency division processing arrives; and so on.

[0038] S14, perform a second processing on the clock after fractional frequency division processing according to the rising edge and falling edge of the clock after fractional frequency division processing to obtain the target clock.

[0039] In this embodiment, the second processing includes:

[0040] S141. Perform a third process on the clock after fractional division based on the accumulated number of rising edges of the clock after fractional division to obtain a first sub-clock. The third process includes: starting from when the accumulated number of rising edges of the clock after fractional division is 1, perform a level flip once when the accumulated number of rising edges of the clock after fractional division increases by (r1 - 1) / 2, then perform a level flip once when it increases by (r1 + 1) / 2, then perform a level flip once when it increases by (r1 - 1) / 2, then perform a level flip once when it increases by (r1 + 1) / 2, and loop to perform level flips.

[0041] Thus, the first sub-clock remains high after the 1st rising edge of the clock after fractional division until the (r1 - 1) / 2 + 1st rising edge of the clock after fractional division arrives; and remains low after the (r1 - 1) / 2 + 1st rising edge of the clock after fractional division until the r1 + 1st rising edge of the clock after fractional division arrives; and remains high after the r1 + 1st rising edge of the clock after fractional division until the (r1 - 1) / 2 + r1 + 1st rising edge of the clock after fractional division arrives; and remains low after the (r1 - 1) / 2 + r1 + 1st rising edge of the clock after fractional division until the 2×r1 + 1st rising edge of the clock after fractional division arrives; and so on.

[0042] S142. Obtain a second sub-clock based on the falling edge of the clock after fractional division and the first sub-clock. The second sub-clock satisfies the following conditions: if the first moment of the first sub-clock is low, then the second moment of the second sub-clock is low; if the first moment of the first sub-clock is high, then the second moment of the second sub-clock is high. The first moment is a moment that is separated from the second moment by a target duration and is earlier than the first moment, and the target duration is the time interval between the first falling edge and the first rising edge after the first rising edge of the clock after fractional division.

[0043] In this embodiment, the second sub-clock starts to remain high at the first falling edge after the 1st rising edge of the clock after fractional division, and the level at a certain moment (i.e., the second moment) after that is the same as the level of the first sub-clock at the first moment. That is, when the level of the first sub-clock at the first moment is high, the level of the second sub-clock at the second moment is also high; when the level of the first sub-clock at the first moment is low, the level of the second sub-clock at the second moment is also low.

[0044] S143. Perform superposition processing on the first sub-clock and the second sub-clock. The superposition processing includes: if both the first sub-clock and the second sub-clock are at a low level at the target time, output the level at the target time as low; otherwise, output the level at the target time as high.

[0045] In this embodiment, superposition processing is performed on the first sub-clock and the second sub-clock to obtain a target clock. The level of the target clock at a certain moment (i.e., the target time) is related to the levels of the first sub-clock and the second sub-clock at the target time. If the levels of both the first sub-clock and the second sub-clock at the target time are low, the level of the target clock at the target time is low; otherwise, the level of the target clock at the target time is high.

[0046] This embodiment provides a clock frequency division processing device, which includes a fractional frequency division module and an integer frequency division module. The fractional frequency division module is used to perform fractional frequency division processing on the original clock according to the fractional frequency division coefficient, and the integer frequency division module is used to perform integer frequency division processing on the clock after fractional frequency division processing according to the integer frequency division coefficient. The clock obtained after integer frequency division processing is the target clock, and the target clock is also the clock that is desired to be obtained. The fractional frequency division coefficient and the integer frequency division coefficient of this embodiment are obtained based on the frequency of the original clock and the frequency of the target clock. Based on the fractional frequency division coefficient and the integer frequency division coefficient of this embodiment, the target clock can be obtained. The clock frequency division device of this embodiment has higher efficiency in obtaining the target clock and higher accuracy of the obtained target clock, and can be used to meet the display requirements of images with different resolutions.

[0047] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration and not for limiting the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A clock frequency division processing device, characterized in that, The clock division processing device includes a fractional division module and an integer division module. The input of the fractional division module includes an original clock and a fractional division coefficient. The fractional division module is used to perform fractional division processing on the original clock according to the fractional division coefficient, and the output of the fractional division module is the clock after fractional division processing. The input of the integer division module includes the clock after fractional division processing and an integer division coefficient. The integer division module is used to perform integer division processing on the clock after fractional division processing, and the output of the integer division module is the target clock. The process of obtaining the fractional division coefficient and the integer division coefficient includes: S100, obtaining the frequency of the original clock; S200, obtaining the frequency of the target clock; S300, obtaining the integer division coefficient r1 according to the frequency of the original clock and the frequency of the target clock, r1 = rounddown(f0 / f1), where rounddown( ) is rounding down, f0 is the frequency of the original clock, and f1 is the frequency of the target clock; S400, obtaining the fractional division coefficient r2 according to the frequency of the original clock, the frequency of the target clock, and the integer division coefficient, r2 = f1 / f0 × r1; The fractional division module includes a first switch, a counting module, a judgment module, and a second switch. The first switch is used to control the opening or closing of the fractional division module. The input of the first switch includes the original clock and a control signal, and the control signal is used to control the opening or closing of the first switch. The output of the first switch is the input of the counting module, and the input of the counting module also includes the fractional division coefficient. The counting module is used to obtain a first count value according to the original clock and the fractional division coefficient when the first switch is in the open state. The input of the judgment module is the first count value, and the judgment module is used to judge whether the first count value is greater than or equal to 1. If the first count value is greater than or equal to 1, the output value of the judgment module is 1; if the first count value is less than 1, the output value of the judgment module is 0. The input of the second switch includes the output of the first switch and the output of the judgment module. If the output value of the judgment module is 1, the output of the second switch is the output of the first switch; if the output value of the judgment module is 0, the output of the second switch is a low level. Among them, if the system enters the low-power mode, the control signal is a signal that makes the first switch in the closed state; if the system is in the normal mode, the control signal is a signal that makes the first switch in the open state. The obtaining of the first count value according to the original clock and the fractional division coefficient when the first switch is in the open state includes: S1. Obtain the first count value c corresponding to the i-th cycle of the original clock i ; c i = i × r2 - ∑ i-1 j=1 c j where c j is the output value of the judgment module corresponding to the j-th cycle of the original clock, the value range of j is from 1 to i - 1, i ≥ 2; c1 = 0 2. The clock division processing device according to claim 1, wherein The integer division module is used to implement the following steps: S10, if r1 = 1, enter S11; if r1 ≠ 1, enter S12; S11, determining the clock after fractional division processing as the target clock; S12, if r1 is an even number, enter S13; if r1 is an odd number, enter S14; S13. Perform a first process on the clock after fractional division processing according to the rising edge of the clock after fractional division processing to obtain a target clock; S14. Perform a second process on the clock after fractional division processing according to the rising edge and falling edge of the clock after fractional division processing to obtain a target clock.

3. The clock division processing device according to claim 2, characterized in that, The first process includes: starting from the rising edge accumulation number of 1 of the clock after fractional division processing, every time the rising edge accumulation number of the clock after fractional division processing increases by r1 / 2, perform a level inversion.

4. The clock division processing device according to claim 2, characterized in that, The second process includes: S141. Perform a third process on the clock after fractional division processing according to the rising edge accumulation number of the clock after fractional division processing to obtain a first sub-clock; the third process includes: starting from the rising edge accumulation number of 1 of the clock after fractional division processing, perform a level inversion when the rising edge accumulation number of the clock after fractional division processing increases by (r1 - 1) / 2, then perform a level inversion when it increases by (r1 + 1) / 2, then perform a level inversion when it increases by (r1 - 1) / 2, then perform a level inversion when it increases by (r1 + 1) / 2, and loop to perform level inversions; S142. Obtain a second sub-clock according to the falling edge of the clock after fractional division processing and the first sub-clock; the second sub-clock satisfies the following conditions: if the first moment of the first sub-clock is low level, then the second moment of the second sub-clock is low level; if the first moment of the first sub-clock is high level, then the second moment of the second sub-clock is high level; the first moment is a moment that is separated from the second moment by a target duration and is earlier than the first moment, and the target duration is the time interval between the first falling edge and the first rising edge after the first rising edge of the clock after fractional division processing; S143. Perform a superposition process on the first sub-clock and the second sub-clock; the superposition process includes: if both the first sub-clock and the second sub-clock are at low level at the target moment, then output the level at the target moment as low level; otherwise, output the level at the target moment as high level.

5. The clock division processing device according to claim 1, wherein The fractional division module further includes a fractional division coefficient selection module. The inputs of the fractional division coefficient selection module include a mode selection signal, the fractional division coefficient in the test mode, and the fractional division coefficient in the usage mode. The fractional division coefficient selection module is used to select, according to the mode selection signal, either the fractional division coefficient in the test mode or the fractional division coefficient in the usage mode as the fractional division coefficient output to the counting module.

6. The clock division processing device according to claim 1, characterized in that, The frequency of the target clock is obtained according to the resolution of the target image or the sampling rate of audio coding.

Images