Command processing method during abnormal power failure and processing method for recovering power-on after abnormal power failure
By extracting and sorting the key data structures of write commands, forming long arrays and writing them into single-layer storage space, the problem of low data recovery efficiency in SSDs when abnormal power outage is solved, and fast and accurate data recovery and storage space are achieved. optimization.
Patent Information
- Application Number
- CN202411096835.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2024-12-27
AI Technical Summary
When the solid-state drive is powered off abnormally, it cannot fully write user data, resulting in low data recovery efficiency when the recovery is powered on and inaccurate command recovery, and limited single-layer storage space capacity, resulting in slow efficiency and poor accuracy during recovery.
By extracting and sorting the key data structures of multiple write commands, a long array with sequence characteristics is formed, and written to a single-layer storage space, repetitive commands are eliminated, and the data recovery process is optimized.
Saves the amount of data and time during power failure, reduces the single-layer storage space and time required for power-on recovery, and ensures fast and accurate recovery of writing commands.
Smart Images
Figure CN119200960A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of data storage, and in particular to a method for processing commands during abnormal power failure and restoring power after the abnormal power failure. Background Art
[0002] When the solid-state drive (SSD) encounters an abnormal power outage, due to capacitor limitations, it is impossible to write all the user write data being processed into the three-level storage (Three Level Cell, TLC). It is necessary to store the user write data being processed / unprocessed in the faster single-level storage (Single Level Cell, SLC) space for storage, and restore these data and the L2P mapping table when the power is turned on, but the storage capacity of SLC is limited and usually only has a relatively small capacity. When the solid-state drive is powered on and restored, in order to be able to respond to commands from the host, it is necessary to re-resume the mapping table and restore the data information saved when the power was turned off.
[0003] In the related art, since there may be a sequence or dependency between write commands, when the SSD is powered on and restored after an abnormal power outage, there may be a problem that a large amount of data is saved and more SLC storage space is required, which also leads to slow efficiency in data recovery during power-on and inaccurate command recovery during power-on. Summary of the invention
[0004] In order to solve the above technical problems, the present disclosure provides a method for processing commands during abnormal power failure and restoring power after abnormal power failure.
[0005] In a first aspect, the present disclosure provides a command processing method during abnormal power failure, comprising:
[0006] In response to the received multiple write commands, extract information from the multiple write commands at different stages to obtain corresponding multiple key data structures;
[0007] The multiple key data structures are sorted into a long array with sequence characteristics, and the long array and the buffered data corresponding to the multiple write commands are written into a single-layer storage space, wherein the multiple write commands at different stages include in-transit commands and fresh commands, the in-transit commands are write commands that have been obtained and are being processed, and the fresh commands are write commands that have not yet been taken out for processing.
[0008] In some embodiments, the command processing method during abnormal power failure further includes:
[0009] The multiple write commands used to form the long array with sequence characteristics are sorted according to the dependency relationship of the commands or according to the time sequence of the commands.
[0010] In some embodiments, the key data structure includes a logical address, a buffer address and an update bitmap, wherein the logical address is the logical address corresponding to the write command, the buffer address is the address of the data storage buffer to which the write command is to be written, and the update bitmap indicates the bit that indicates that the write command requires storage space.
[0011] In some embodiments, the information extraction process is performed on multiple write commands at different stages to obtain corresponding multiple key data structures, including:
[0012] When abnormal power failure of the solid state drive is detected, classifying the plurality of in-transit commands;
[0013] If the in-transit command is an alignment write command, in response to the overlap of logical addresses hit by multiple alignment write commands, the alignment write commands are screened by comparison and exchange to obtain a final alignment write command;
[0014] Information extraction processing is performed on the last alignment write command to obtain corresponding multiple key data structures.
[0015] In some embodiments, after performing category determination on the plurality of fresh commands, the method further includes:
[0016] If the in-transit command is an unaligned write command, updating the unaligned write command through a read-modify-write operation to obtain an updated unaligned write command;
[0017] Information extraction processing is performed on the updated non-aligned write command to obtain corresponding multiple key data structures.
[0018] In some embodiments, the command processing method during abnormal power failure further includes:
[0019] Determining a dependency relationship between the aligned write command and the unaligned write command;
[0020] Based on the dependency relationship, the logic-to-physical mapping table is invalidated according to the comparison and exchange, and the aligned write command and the unaligned write command are stored in the long array.
[0021] In some embodiments, the command processing method during abnormal power failure further includes:
[0022] Determining the non-aligned write command and a dependency relationship between the non-aligned write command;
[0023] The logical-to-physical mapping table is rolled back according to the comparison and exchange based on the dependency relationship.
[0024] In a second aspect, the present disclosure provides a method for restoring power after abnormal power failure, comprising:
[0025] After detecting that the solid state drive is powered on again, restoring the long array through the single-layer storage space;
[0026] Re-processing the write commands for the multiple key data structures according to the long array;
[0027] Among them, the long array and the buffer data corresponding to multiple write commands are written into the single-layer storage space, the long array is an array with sequence characteristics composed of multiple key data structures arranged in sequence, and the multiple key data structures are obtained by extracting information from multiple write commands received at different stages.
[0028] In some embodiments, re-processing the write commands for the multiple key data structures according to the long array includes:
[0029] Actual data corresponding to a plurality of write commands contained in the long array are read from the single-layer storage space to corresponding buffer addresses.
[0030] In a third aspect, the present disclosure provides a storage device, including:
[0031] Control components and NVM chips;
[0032] The control component executes the steps of the command processing method during abnormal power failure described in the first aspect or the steps of the processing method for restoring power after abnormal power failure described in the second aspect.
[0033] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:
[0034] The command processing method for abnormal power failure and power recovery after abnormal power failure of the disclosed embodiment can extract information from multiple write commands at different stages in response to multiple write commands received, obtain multiple corresponding key data structures, and then sort the multiple key data structures into a long array with sequence characteristics, and write the long array and the buffer data corresponding to the multiple write commands into a single-layer storage space, wherein the multiple write commands at different stages include in-transit commands and fresh commands, in-transit commands are write commands that have been obtained and are being processed, and fresh commands are write commands that have not yet been taken out for processing. Thus, after an abnormal power failure, the key data structures of multiple write commands at different stages are extracted, and the multiple key data structures are sorted into a long array with sequence characteristics. On the one hand, the long array with sequence characteristics can eliminate repeated write commands, greatly save the amount of data that needs to be written when the power is off, and can save the time for power failure processing. On the other hand, after the power is restored, the power recovery time and the usage of the single-layer storage space can be saved, which is convenient for the rapid and accurate recovery of the write commands when the power is turned on again later. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. Throughout the accompanying drawings, the same or similar reference numerals represent the same or similar elements. It should be understood that the drawings are schematic and the originals and elements are not necessarily drawn to scale.
[0036] Figure 1 A flowchart of a command processing method during abnormal power failure provided by an embodiment of the present disclosure;
[0037] Figure 2 A flowchart of a method for restoring power after abnormal power failure provided by an embodiment of the present disclosure;
[0038] Figure 3 A flowchart of another command processing method during abnormal power failure provided by an embodiment of the present disclosure;
[0039] Figure 4 A flowchart of another method for processing power restoration after abnormal power failure provided by an embodiment of the present disclosure;
[0040] Figure 5 A schematic diagram of the structure of a long array provided in an embodiment of the present disclosure;
[0041] Figure 6 A flowchart of another method for processing commands during abnormal power failure provided by an embodiment of the present disclosure;
[0042] Figure 7 A flowchart of another method for processing commands during abnormal power failure provided by an embodiment of the present disclosure;
[0043] Figure 8 A flowchart of another method for processing commands during abnormal power failure provided by an embodiment of the present disclosure;
[0044] Fig. 9 A schematic diagram of the structure of a storage device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION
[0045] The following is a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.
[0046] The following specific embodiments are provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the application, various changes, modifications and equivalents of the method, device and / or system described herein will be clear. For example, the order of operations described herein is only an example, and is not limited to those orders set forth herein, but can be changed as it will be clear after understanding the disclosure of the application, except for the operations that must occur in a specific order. In addition, for increased clarity and conciseness, the description of features known after understanding the disclosure of the application can be omitted.
[0047] The features described herein can be implemented in different forms and should not be construed as being limited to the examples described herein. Rather, the examples described herein have been provided to illustrate only some of the many possible ways to implement the methods, devices, and / or systems described herein that will be clear after understanding the disclosure of the present application.
[0048] Throughout the specification, when a component is described as being "connected to" or "coupled to" another component, the component may be directly "connected to" or "coupled to" the other component, or there may be one or more other components between them. Conversely, when an element is described as being "directly connected to" or "directly coupled to" another element, there may be no other elements between them. Similarly, similar expressions (e.g., "between" versus "immediately between" and "adjacent to" versus "immediately adjacent to") should also be interpreted in the same manner. As used herein, the term "and / or" includes any one of the relevant listed items or any combination of any two or more of the relevant listed items.
[0049] Although terms such as "first", "second" and "third" may be used to describe various components, components, regions, layers or parts herein, these components, components, regions, layers or parts are not limited by these terms. Instead, these terms are only used to distinguish one component, component, region, layer or part from another component, component, region, layer or part. Therefore, without departing from the teachings of the examples described herein, the first component, first component, first region, first layer or first part referred to in the examples may also be referred to as the second component, second component, second region, second layer or second part.
[0050] The terms used herein are only used to describe various examples and will not be used to limit the disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. The terms "comprise", "include" and "have" indicate the presence of the stated features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.
[0051] It should be noted that, if there is no conflict, the various features in the embodiments of the present application can be combined with each other, all within the scope of protection of the present application. In addition, although the functional module division is performed in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a sequence different from the module division in the device or the flow chart. Furthermore, the words "first", "second", "third", etc. used in this application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and effects.
[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art based on the understanding of the disclosure of the present application and the present disclosure. Unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant field and the disclosure of the present application, and should not be interpreted in an idealized or overly formal way. The use of the term "may" with respect to an example or embodiment herein (e.g., with respect to what an example or embodiment may include or implement) indicates that there is at least one example or embodiment that includes or implements such a feature, and all examples are not limited thereto.
[0053] In order to solve the above problems, the embodiment of the present disclosure provides a method for processing commands during abnormal power failure and restoring power after abnormal power failure. Figure 1-8 The command processing method during abnormal power failure provided by the embodiment of the present disclosure is described in detail.
[0054] Figure 1 A flow chart of a command processing method during abnormal power failure provided by an embodiment of the present disclosure is shown.
[0055] In the embodiment of the present disclosure, the command processing method in the event of abnormal power failure can be executed by an electronic device, wherein the electronic device may include but is not limited to devices such as storage devices, computer devices, cloud servers or cloud server clusters.
[0056] like Figure 1 As shown, the command processing method during abnormal power failure may include the following steps.
[0057] S110 . In response to the received multiple write commands, perform information extraction processing on the multiple write commands in different stages to obtain corresponding multiple key data structures.
[0058] In an embodiment of the present disclosure, the electronic device may perform information extraction processing on multiple write commands at different stages in response to multiple write commands received, and obtain corresponding multiple key data structures.
[0059] Optionally, the solid state drive may be a computer storage device that uses flash memory technology as a storage medium.
[0060] Optionally, the write command may be a command for a user to write data.
[0061] Optionally, the multiple write commands at different stages may be commands at different processing stages of the solid state drive, wherein the multiple write commands at different stages may include in-transit commands and fresh commands.
[0062] Optionally, the flying command may be a write command that has been fetched and is being processed.
[0063] Optionally, the fresh command (Fresh Command) may be a write command that has not yet been retrieved and processed.
[0064] Optionally, the information extraction process may be to extract key information from the write command.
[0065] Optionally, the key data structure (write_cmd_t) may be a data structure including three key information. The key data structure may include a logical address (Logical Block Address, LBA), a buffer address (BufferAddr), and an update bitmap (Bitmap). The logical address is the logical address corresponding to the write command, the buffer address is the address of the data storage buffer to be written by the write command, and the update bitmap indicates the bit position that the write command requires storage space.
[0066] Specifically, the electronic device can detect the status of the solid state drive. If an abnormal power failure of the solid state drive is detected, the electronic device can extract information from multiple write commands at different stages to obtain corresponding multiple key data structures.
[0067] S120. Sort the multiple key data structures into a long array with sequence characteristics, and write the long array and the buffered data corresponding to the multiple write commands into a single-layer storage space, wherein the multiple write commands at different stages include in-transit commands and fresh commands, the in-transit commands are write commands that have been acquired and are being processed, and the fresh commands are write commands that have not yet been taken out for processing.
[0068] In an embodiment of the present disclosure, the electronic device may sort the plurality of key data structures into a long array having sequence characteristics, and write the long array and the buffer data corresponding to the plurality of write commands into a single-layer storage space.
[0069] Optionally, the long array may be an array including a plurality of key data structures, each key array in the long array has a sequence feature, and the sequence feature may be arranged according to a timeline.
[0070] Optionally, a single-layer storage space (SLC) may be a storage unit that can store 1 bit of information per unit.
[0071] Specifically, after obtaining multiple key data structures, the electronic device can sort the multiple key data structures into a long array with sequence characteristics, and then write the long array into a single-layer storage space (abbreviated as SLC space). For example, after obtaining multiple key data structures (write_cmd_t), the multiple key data structures (write_cmd_t) are sorted according to the timeline to form a long array (write_cmd_list), and the buffer data of the buffer address (Buffer Addr) in each key data structure (write_cmd_t) are written into the SLC space, and the long array (write_cmd_list) is written into the SLC space, including the corresponding data and write command array.
[0072] Thus, in the disclosed embodiment, in response to the received multiple write commands, multiple write commands at different stages can be processed for information extraction, and multiple corresponding key data structures can be obtained. Then, the multiple key data structures are sorted to form a long array with sequence characteristics, and the long array and the buffer data corresponding to the multiple write commands are written into a single-layer storage space, wherein the multiple write commands at different stages include in-transit commands and fresh commands, in-transit commands are write commands that have been acquired and are being processed, and fresh commands are write commands that have not yet been taken out for processing. Thus, after an abnormal power failure, the key data structures of multiple write commands at different stages are extracted, and the multiple key data structures are sorted to form a long array with sequence characteristics. On the one hand, the long array with sequence characteristics can eliminate duplicate write commands, greatly save the amount of data that needs to be written when the power is off, and can save power-off time. On the other hand, after the power is restored, the power-on recovery time and the usage of the single-layer storage space can be saved, which is convenient for the rapid and accurate recovery of the write commands when the power is restored later.
[0073] Optionally, the command processing method during abnormal power failure may further include: sorting the multiple write commands used to form the long array with sequence characteristics according to command dependency or according to command time sequence.
[0074] In an embodiment of the present disclosure, after receiving multiple write commands, the electronic device can sort the multiple key data structures corresponding to the multiple write commands into a long array with sequence characteristics, for example, they can be sorted according to the write command dependency or according to the command time sequence, so as to obtain the corresponding long array.
[0075] In some embodiments, the electronic device may directly perform information extraction processing on a fresh command, regardless of an aligned write command or a non-aligned write command.
[0076] Optionally, S110 may specifically include: when an abnormal power failure of the solid state drive is detected, performing information extraction processing on a plurality of the fresh commands to obtain a corresponding plurality of the key data structures.
[0077] In the embodiment of the present disclosure, when an abnormal power failure of the solid state drive is detected, the electronic device can perform information extraction processing on the multiple in-transit commands to obtain the corresponding multiple key data structures.
[0078] Specifically, for the fresh command (Fresh Command), when the SSD experiences abnormal power failure, the electronic device directly extracts and processes the information of the fresh command (Fresh Command) regardless of the aligned write command or the unaligned write command to obtain the corresponding key data structure (write_cmd_t).
[0079] In some other embodiments, the electronic device may adopt different processing for the aligned write command and the unaligned write command respectively for the in-transit command.
[0080] Optionally, the alignment write command (Align Write) may be a write command with a length of 4K. The unalignment write command (Unalign Write) may be a write command with an alignment length less than 4K, that is, the user only modifies some 512-Byte spaces in 4K.
[0081] Optionally, S110 may specifically include: when an abnormal power failure of the solid-state hard disk is detected, performing category judgment on multiple in-transit commands; if the in-transit commands are aligned write commands, in response to overlapping logical addresses hit by multiple aligned write commands, filtering the aligned write commands by comparing and exchanging to obtain the final aligned write command; performing information extraction processing on the final aligned write command to obtain the corresponding multiple key data structures.
[0082] In an embodiment of the present disclosure, when an abnormal power failure of the solid state drive is detected, the electronic device may perform category determination on a plurality of the in-transit commands.
[0083] Specifically, when an abnormal power failure of the solid state drive is detected, the electronic device may perform category determination on the plurality of in-transit commands, that is, determine whether the in-transit command is an aligned write command or an unaligned write command.
[0084] Further, if the in-transit command is an alignment write command, in response to the overlap of logical addresses hit by multiple alignment write commands, the alignment write commands are screened by comparison and exchange to obtain a final alignment write command.
[0085] Specifically, if the in-transit command is an alignment write command, the electronic device can, in response to the overlap of the logical addresses hit by multiple alignment write commands, filter the alignment write commands by comparison and swapping to obtain the final alignment write command. For example, in-transit commands, multiple overlapping alignment write commands may hit the same logical address (LBA). The electronic device can filter the alignment write commands by comparison and swap (CAS for short), modify the mapping of LBA to PBA corresponding to the overlapped write commands pointing to the same LBA except for the last write command, and obtain the final alignment write command.
[0086] Furthermore, the electronic device may perform information extraction processing on the last alignment write command to obtain the corresponding multiple key data structures.
[0087] Optionally, S110 may specifically include: if the in-transit command is an unaligned write command, updating the unaligned write command through a read-modify-write operation to obtain an updated unaligned write command; performing information extraction processing on the updated unaligned write command to obtain corresponding multiple key data structures.
[0088] In the embodiment of the present disclosure, if the in-transit command is an unaligned write command, the electronic device may update the unaligned write command through a read-modify-write operation to obtain an updated unaligned write command.
[0089] Specifically, if the in-transit command is an unaligned write command, the electronic device can update the unaligned write command through a read-modify-write operation. For example, for the unaligned write command, the user only wants to update part of the data in the 4K LBA. To perform a read-modify-write operation on the unaligned write command, it is necessary to first read out the 4K in the current LBA, and after updating the part of the data that the user needs to update, it becomes new 4K data, that is, the updated unaligned write command is obtained.
[0090] Furthermore, the electronic device may perform information extraction processing on the updated non-aligned write command to obtain the corresponding multiple key data structures.
[0091] Optionally, the command processing method during abnormal power failure may also include: determining the dependency relationship between the aligned write command and the unaligned write command; invalidating the logical to physical mapping table based on the comparison and exchange, and storing the aligned write command and the unaligned write command in the long array.
[0092] In an embodiment of the present disclosure, the electronic device can determine the dependency between the aligned write command and the unaligned write command, and invalidate the logical-to-physical mapping table based on the comparison and exchange, and store the aligned write command and the unaligned write command into the long array.
[0093] For example, if multiple non-aligned write commands (such as w0, w1, and w2) hit the same LBA, and the current mapping of this LBA is already a NAND physical address (indicating that the previous 4K data has been written to the disk), but w0, w1, and w2 need to modify different parts of this 4K, then w1 must wait for w0 to merge with the data in NAND before merging with the data in w0, and w2 needs to wait for w1 to complete the merger before merging with the data in w1. At this time, a waiting queue is formed, such as NAND address ←w0←w1←w2.
[0094] Therefore, if the dependent header is a NAND address (PBA address) and a non-aligned write command has modified the L2P mapping table, the L2P table needs to be rolled back to the NAND address of this header when power is off, and a CAS operation is required for the rollback.
[0095] Optionally, the command processing method during abnormal power failure may further include: determining the dependency relationship between the non-aligned write command and the non-aligned write command; and performing rollback processing on the logical-to-physical mapping table according to the comparison and exchange based on the dependency relationship.
[0096] In the embodiment of the present disclosure, the electronic device may determine the non-aligned write command and a dependency relationship between the non-aligned write command, and perform a rollback process on the logical-to-physical mapping table according to the comparison and exchange based on the dependency relationship.
[0097] For another example, if multiple non-aligned write commands (w0, w1, w2) hit the same LBA, and the current mapping of this LBA is still a Buffer address (that is, the previous aligned write has not yet been actually written to the disk), but w0, w1, and w2 need to modify different parts of this 4K, then w1 must wait for w0 to merge with the data in the Buffer before merging with the data in w0, and w2 needs to wait for w1 to complete the merger before merging with the data in w1. At this time, a waiting queue is formed: Buffer Addr←w0←w1←w2.
[0098] Therefore, if the dependent header is a DDR address, it means that the header is actually an aligned write operation, and there is an unaligned write command in it that hits this aligned write, and the L2P mapping has been modified by the unaligned write command, but we no longer need the L2P content before the aligned write command, so we can use the CAS operation to set the L2P mapping to an invalid value, but put the aligned write command of the header together with the subsequent unaligned write command into the write command linked list.
[0099] Figure 2 A flow chart of a method for processing power restoration after abnormal power failure provided by an embodiment of the present disclosure is shown.
[0100] In the embodiment of the present disclosure, the command processing method in the event of abnormal power failure can be executed by an electronic device, wherein the electronic device may include but is not limited to devices such as storage devices, computer devices, cloud servers or cloud server clusters.
[0101] like Figure 2 As shown, the processing method for restoring power after abnormal power failure may include the following steps.
[0102] S210: After detecting that the solid state drive is powered on again, restoring the long array through the single-layer storage space.
[0103] In the disclosed embodiment, after detecting that the solid state drive is powered on again, the electronic device can restore the long array through the single-layer storage space.
[0104] The long array and buffer data corresponding to multiple write commands are written into the single-layer storage space. The long array is an array with sequence characteristics formed by sorting multiple key data structures, and the multiple key data structures are obtained by extracting information from multiple write commands received at different stages.
[0105] Specifically, the electronic device continues to detect the solid state drive, and if the solid state drive is powered on again, the electronic device can restore the long array through the single-layer storage space.
[0106] S220. Re-process write commands for multiple key data structures according to the long array; wherein the long array and buffer data corresponding to the multiple write commands are written into the single-layer storage space, the long array is an array with sequence characteristics formed by sorting multiple key data structures, and the multiple key data structures are obtained by extracting information from multiple write commands received at different stages.
[0107] In the embodiment of the present disclosure, the electronic device may re-process the write commands for the plurality of key data structures according to the long array.
[0108] Specifically, the electronic device can re-process the write commands for the multiple key data structures according to the long array. For example, when the solid-state drive is powered on again, the firmware will first restore the long array (write_cmd_list), and read the data in each key data structure (write_cmd_t) therein to the buffer address (Buffer Addr), and then re-process the write commands for each long array (write_cmd_list) in the long array (write_cmd_list).
[0109] Optionally, S220 may specifically include: reading actual data corresponding to a plurality of write commands included in the long array from the single-layer storage space to a corresponding buffer address.
[0110] In the embodiment of the present disclosure, the electronic device can read the actual data corresponding to the multiple write commands contained in the long array from the single-layer storage space to the corresponding buffer address.
[0111] Specifically, after the electronic device recovers the long array (write_cmd_list) in the single-layer storage space (SLC), it can read the actual data corresponding to the multiple write commands contained in the long array from the single-layer storage space (SLC) to the corresponding buffer address (Buffer Addr).
[0112] Figure 3 A flow chart of another command processing method during abnormal power failure provided by an embodiment of the present disclosure is shown.
[0113] like Figure 3 As shown, when an abnormal power failure of the solid-state drive is detected, the electronic device can shield the hardware from accepting write commands, and then process the in-transit commands as aligned write commands. After processing, the in-transit commands are processed as non-aligned write commands. After processing, the hardware is opened to accept write commands and process fresh commands, that is, information extraction processing is performed to obtain the corresponding key data structure (write_cmd_t), and multiple key data structures are sorted according to the timeline to form a long array (write_cmd_list), which is written into a single-layer storage space (SLC). Then, after detecting that the solid-state drive is powered on again, the long array (write_cmd_list) is restored through the single-layer storage space (SLC), and the data of the buffer address (Buffer Addr) in each key data structure (write_cmd_t) is written into the SLC space, and the long array (write_cmd_list) is written into the SLC space, including the corresponding data and write command array.
[0114] Figure 4A flow chart of another method for processing power restoration after abnormal power failure provided by an embodiment of the present disclosure is shown.
[0115] like Figure 4 As shown, after detecting that the solid-state drive is powered on again, the electronic device can restore the long array through the single-layer storage space (SLC). For example, when the solid-state drive is powered on again, the firmware will first restore the long array (write_cmd_list), and read the data in each key data structure (write_cmd_t) therein to the buffer address (Buffer Addr), and then re-process the write command for each long array (write_cmd_list) in the long array (write_cmd_list).
[0116] Figure 5 A schematic diagram of the structure of a long array provided by an embodiment of the present disclosure is shown.
[0117] like Figure 5 As shown, in the long array (write_cmd_list), from the head to the tail, multiple write commands are sorted according to the dependency of the commands or according to the time sequence of the commands, for example, write_cmd_t 0, write_cmd_t1, etc. Each key data structure (write_cmd_t) includes a logical address (Logical Block Address, LBA), a buffer address (Buffer Addr) and an update bitmap (Bitmap).
[0118] Figure 6 A flowchart of another method for processing commands during abnormal power failure provided by an embodiment of the present disclosure is shown.
[0119] like Figure 6 As shown, if the in-transit command is an alignment write command, the electronic device can collect all alignment write commands in the system and use its own buffer address as the old value to change the L2P table to an invalid value. For example, the atomic operation instruction set of the CPU can be used for synchronous modification or: the hardware module provided by the system-level chip can be used for atomic comparison and exchange (Compare And Swap, CAS) to modify the overlapping write command pointing to the same LBA except for the last write command. The mapping of LBA to PBA corresponding to other write commands is modified to be invalid, and the last alignment write command is obtained. If the update is successful, the last alignment write command is processed for information extraction to obtain the corresponding multiple key data structures, otherwise the write command is discarded.
[0120] Figure 7A flowchart of another method for processing commands during abnormal power failure provided by an embodiment of the present disclosure is shown.
[0121] like Figure 7 As shown, if the in-transit command is an unaligned write command, the electronic device can collect all unaligned write commands in the system. For example, if multiple unaligned write commands (w0, w1, w2) hit the same logical address LBA, establish an unaligned write dependency chain, and modify L2P in a compare and exchange manner according to the rules. If the modification is successful, all commands in the chain are pushed into the long array in sequence, otherwise all commands in the chain are discarded.
[0122] Figure 8 A flowchart of another method for processing commands during abnormal power failure provided by an embodiment of the present disclosure is shown.
[0123] like Figure 8 As shown, when the electronic device modifies L2P in a comparison and exchange manner according to the rules, for example, if multiple non-aligned write commands (w0, w1, w2) hit the same LBA, and the current mapping of this LBA is already a NAND physical address (indicating that the previous 4K data has been stored on the disk), but w0, w1, and w2 need to modify different parts of this 4K, then w1 must wait for w0 to merge with the data in NAND before merging with the data in w0, and w2 needs to wait for w1 to complete the merger before merging with the data in w1. At this time, a waiting queue such as NAND address ←w0←w1←w2 is formed.
[0124] Therefore, if the dependent header is a NAND physical address (PBA address), and there is an unaligned write command that has modified the L2P mapping table, then when the power is off, the L2P table needs to be rolled back to the NAND address of this header, and the CAS operation is required for the rollback. For example, CAS: use the buffer address (Buffer (DDR) Addressr) of 2 (i.e. w2) as the old value, update the L2P buffer to the NAND address, and if successful, push 0, 1, and 2 into the long array (write_cmd_list), otherwise all are discarded.
[0125] For another example, if multiple non-aligned write commands (w0, w1, w2) hit the same LBA, and the current mapping of this LBA is still a Buffer address (that is, the previous aligned write has not yet been actually written to the disk), but w0, w1, and w2 need to modify different parts of this 4K, then w1 must wait for w0 to merge with the data in the Buffer before merging with the data in w0, and w2 needs to wait for w1 to complete the merger before merging with the data in w1. At this time, a waiting queue is formed: Buffer Addr←w0←w1←w2.
[0126] Therefore, if the header that depends on is a DDR address, it means that the header is actually an aligned write operation, and there is an unaligned write command in the back that hits this aligned write, and the L2P mapping has been modified by the unaligned write command, but we no longer need the L2P content before the aligned write command, so we can use the CAS operation to set the L2P mapping to an invalid value, but put the aligned write command of the header together with the unaligned write command behind it into the write command linked list. For example, the buffer address (Buffer (DDR) Addr) of 5 (i.e. w5) is used as the old value to update L2P to an invalid address. If successful, OldBuf (DDR) (bitmap = 0xff) pushes 4 and 5 into the long array (write_cmd_list), otherwise all are discarded.
[0127] Therefore, when the SSD encounters an abnormal power outage, the firmware makes full use of the hardware characteristics to eliminate duplicate write commands, greatly saving the amount of data that needs to be written when the power is off, and saves the data in a long array with sequence characteristics according to the dependency or sequence of multiple write commands, thereby saving multiple write commands concisely and efficiently. After powering on again, multiple write commands can be quickly and accurately restored in sequence according to the long array with sequence characteristics, saving SLC storage space and reducing power-off time and power-on recovery time.
[0128] Fig. 9 A schematic structural diagram of a storage device provided by an embodiment of the present disclosure is shown.
[0129] In some embodiments of the present disclosure, Fig. 9 The storage device shown may be an electronic device. Specifically, the electronic device may include, but is not limited to, devices such as a solid state drive, a computer device, a cloud server, or a cloud server cluster.
[0130] like Fig. 9 As shown, the storage device may include a control component 901 and an NVM chip 902 storing computer program instructions.
[0131] Specifically, the control component 901 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or may be configured to implement one or more integrated circuits of the embodiments of the present application.
[0132] The NVM chip 902 may include a large capacity memory for information or instructions. By way of example and not limitation, the NVM chip 902 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a tape, or a universal serial bus (USB) drive or a combination of two or more of these. Where appropriate, the NVM chip 902 may include a removable or non-removable (or fixed) medium. Where appropriate, the NVM chip 902 may be inside or outside the integrated gateway device. In a particular embodiment, the NVM chip 902 is a non-volatile solid-state memory. In a particular embodiment, the NVM chip 902 includes a read-only memory (ROM). Where appropriate, the ROM may be a mask-programmed ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (Electrically Erasable Programmable ROM, EEPROM), an electrically alterable ROM (EAROM) or flash memory, or a combination of two or more of these.
[0133] The control component 901 reads and executes the computer program instructions stored in the NVM chip 902 to perform the steps of the command processing method during abnormal power failure or the steps of the processing method for restoring power after abnormal power failure provided in the embodiment of the present disclosure.
[0134] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution can be essentially or in other words, the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute various embodiments or certain parts of the embodiments.
[0135] The embodiments of the present disclosure also provide a non-volatile computer-readable storage medium, which can store a computer program. When the computer program is executed by the control component, the control component implements the command processing method for abnormal power failure or the processing method for restoring power after abnormal power failure provided by the embodiments of the present disclosure.
[0136] The above-mentioned storage medium may be, for example, an NVM chip 902 including computer program instructions, and the above-mentioned instructions may be executed by the control component 901 of the storage device to complete the command processing method for abnormal power failure provided in the embodiment of the present disclosure. Optionally, the storage medium may be a non-temporary computer-readable storage medium, for example, the non-temporary computer-readable storage medium may be a ROM, a random access NVM chip (Random Access Memory, RAM), a compact disc read-only memory (Compact Disc ROM, CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device, etc.
[0137] The above-described device or equipment embodiments are merely illustrative, wherein the unit modules described as separate components may or may not be physically separated, and the components displayed as module units may or may not be physical units, that is, they may be located in one place, or may be distributed on multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment.
[0138] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising" is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.
[0139] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
[0140] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A command processing method for abnormal power failure, characterized in that: include: In response to the received multiple write commands, extract information from the multiple write commands at different stages to obtain corresponding multiple key data structures; The multiple key data structures are sorted into a long array with sequence characteristics, and the long array and the buffered data corresponding to the multiple write commands are written into a single-layer storage space, wherein the multiple write commands at different stages include in-transit commands and fresh commands, the in-transit commands are write commands that have been obtained and are being processed, and the fresh commands are write commands that have not yet been taken out for processing.
2. The method according to claim 1, characterized in that The method further comprises: The multiple write commands used to form the long array with sequence characteristics are sorted according to the dependency relationship of the commands or according to the time sequence of the commands.
3. The method according to claim 1, characterized in that The key data structure includes a logical address, a buffer address and an update bitmap, wherein the logical address is the logical address corresponding to the write command, the buffer address is the address of the data storage buffer to be written by the write command, and the update bitmap indicates the bit position in which the write command requires storage space.
4. The method according to claim 2, characterized in that: The information extraction process is performed on multiple write commands at different stages to obtain corresponding multiple key data structures, including: When abnormal power failure of the solid state drive is detected, classifying the plurality of in-transit commands; If the in-transit command is an alignment write command, in response to the overlap of logical addresses hit by multiple alignment write commands, the alignment write commands are screened by comparison and exchange to obtain a final alignment write command; Information extraction processing is performed on the last alignment write command to obtain the corresponding multiple key data structures.
5. The method according to claim 4, characterized in that After determining the categories of the plurality of fresh commands, the method further includes: If the in-transit command is an unaligned write command, updating the unaligned write command through a read-modify-write operation to obtain an updated unaligned write command; Information extraction processing is performed on the updated non-aligned write command to obtain corresponding multiple key data structures.
6. The method according to claim 5, characterized in that The method further comprises: Determining a dependency relationship between the aligned write command and the unaligned write command; Based on the dependency relationship, the logic-to-physical mapping table is invalidated according to the comparison and exchange, and the aligned write command and the unaligned write command are stored in the long array.
7. The method according to claim 5, characterized in that The method further comprises: Determining the non-aligned write command and a dependency relationship between the non-aligned write command; The logical-to-physical mapping table is rolled back according to the comparison and exchange based on the dependency relationship.
8. A method for restoring power after abnormal power failure, characterized in that: include: After detecting that the SSD is powered on again, the long array is restored through the single-layer storage space; Re-processing the write commands for the multiple key data structures according to the long array; Among them, the long array and the buffer data corresponding to multiple write commands are written into the single-layer storage space, the long array is an array with sequence characteristics composed of multiple key data structures arranged in sequence, and the multiple key data structures are obtained by extracting information from multiple write commands received at different stages.
9. The method according to claim 8, characterized in that The re-processing of the write commands for the multiple key data structures according to the long array includes: Actual data corresponding to a plurality of write commands contained in the long array are read from the single-layer storage space to corresponding buffer addresses.
10. A storage device, characterized in that: A control component and an NVM chip, wherein the control component executes the steps of the command processing method during abnormal power failure described in any one of claims 1-7 or the steps of the processing method for restoring power after abnormal power failure described in any one of claims 8-9.