A multi-core processor and a method for centrally managing cache consistency

Abstract

The present invention proposes a multi-core processor and a method for centralized cache consistency management thereof, which relates to the field of data processing technology. Data exchange and information access between various components are performed through the connection of a central exchange block, a system main memory and a core module; cache information of each core is recorded through the core module; data read application information is obtained, core data holding information is obtained according to the data read application information, and a core that sends a data read request is converted according to the core data holding information; core update cache demand information is obtained, a cache management unit updates a memory data block, and resets a cache management table. Through a unique central exchange block and high-speed memory design, etc., a more flexible and efficient cache consistency solution is provided, which is suitable for more multi-core processor application scenarios.

Description

Technical Field

[0001] The present invention proposes a multi-core processor and a method for centrally managing cache consistency thereof, and relates to the technical field of data processing, and in particular to the technical field of centrally managing cache of core processors. Background Art

[0002] With the development of computer technology and network technology, multi-core processors have become an important direction for the development of computer hardware. Multi-core processors can improve the processing power and efficiency of computers by sharing the system main memory with multiple processing cores. However, during the use of multi-core processors, the cache consistency problem between the cores has become an important issue. Cache consistency refers to how to ensure that the data obtained by each core is consistent when multiple cores share the same data. If the cache consistency problem is not solved, data inconsistency may occur, thus affecting the normal operation of the computer system. Existing multi-core processors usually use cache consistency protocols, such as the MESI (Modified Exclusive Shared Invalid) protocol, to ensure cache consistency between the cores. The MESI protocol achieves cache consistency by maintaining a cache status register in each core to record the status of each data block. When a core needs to read or write a data block, it will first check the status of the data block and take corresponding actions according to the status. However, the existing cache consistency protocol requires a large number of communication and synchronization operations during implementation, which not only increases the complexity and overhead of the system, but also affects the performance of the system. In addition, when the existing cache consistency protocol processes multiple cores reading or writing the same data block at the same time, conflicts may occur, resulting in the inability to ensure cache consistency. Therefore, the existing cache consistency protocol has certain limitations in the application of multi-core processors. Summary of the invention

[0003] The present invention provides a multi-core processor and a method for centrally managing cache consistency thereof to solve the above problems:

[0004] The present invention proposes a multi-core processor and a method for centrally managing cache consistency. The multi-core manager includes a central switching block, a system main memory and at least one core module, wherein the central switching block is electrically coupled to the system main memory, and the central switching block is electrically coupled to the core module.

[0005] Furthermore, the central switching block includes a CROSSBAR or a routing switch.

[0006] Furthermore, a cache management unit and a cache record table are disposed inside the central switching block, and the cache management unit and the cache record table are electrically coupled to each other.

[0007] Furthermore, a high-speed memory is also arranged inside the central switching block.

[0008] Furthermore, the core module includes a computer core or a core cluster.

[0009] Further, the method comprises:

[0010] Data exchange and information access between components are carried out through the connection of the central switching block, system main memory and core modules;

[0011] Record each core cache information through the core module;

[0012] Acquire data reading application information, acquire core data holding information according to the data reading application information, and convert and send the core of the data reading request according to the core data holding information;

[0013] The core update cache requirement information is obtained, the cache management unit updates the memory data block, and resets the cache management table.

[0014] Furthermore, recording each core cache information by the core module includes:

[0015] The read and write operations of each core cache are managed and recorded through the cache management unit and cache record table of the core module to obtain management information and record information.

[0016] Further, the acquiring of data reading application information, acquiring core data holding information according to the data reading application information, and converting and sending the core of the data reading request according to the core data holding information include:

[0017] Get the core data read request information, and when any core requests to read data, determine whether the cache hits;

[0018] When the cache misses, the cache management unit in the central switching block identifies whether the read data exists in the cache record table, that is, identifies whether its core holds the corresponding read data;

[0019] When corresponding read data is identified in its core, the cache management unit converts a data read request of the read data into a data read request of the core holding the read data, performs corresponding data reading, and obtains the read data.

[0020] Furthermore, the obtaining of the core update cache requirement information, the cache management unit updating the memory data block, and resetting the cache management table, includes:

[0021] Obtaining a core update cache requirement, and sending the core update cache requirement to a cache management unit;

[0022] Recording the corresponding memory data block through the cache management unit, and invalidating the cache information in the memory data block;

[0023] The core updates the memory data block, and when the update is completed, the cache management unit resets the cache record table.

[0024] Furthermore, the acquisition of core hit data and memory update data, analysis of core hit performance and memory update performance, and then comprehensive system analysis, status determination and early warning include:

[0025] Obtain cache hit data when a core applies to read data, and calculate a cache hit rate of each core based on the cache hit data combined with a preset weight of the core;

[0026] The calculation formula of the cache hit rate of the core is:

[0027]

[0028] Among them, M z is the cache hit rate of the core, Z c is the number of successful data acquisitions, C z is the total number of core visits, Q h The preset weight value for the core;

[0029] Sort the cache hit rate of each core from large to small to obtain the core hit sequence;

[0030] Acquire updated data information of the memory data block, and calculate the data update rate of each memory data block according to the updated data information combined with the preset weight of the memory data block;

[0031] The calculation formula of the data update rate of the memory data block is:

[0032]

[0033] Among them, G n is the data update rate of the memory data block. c is the number of data updates in the memory data block, s c is the total number of data storage times in the memory data block, Q q The preset weight value of the memory data block;

[0034] Sort the data update rate of each memory data block from large to small to obtain a memory data update sequence;

[0035] Calculating a system comprehensive performance coefficient based on the core hit rate combined with the memory data block;

[0036] The calculation formula of the system comprehensive performance coefficient is:

[0037]

[0038] Among them, ZH is the system comprehensive performance coefficient, H is the total number of cores, M zi is the cache hit rate of the ith core, Q hi is the preset weight value of the ith core, H ij is the number of core hit sequences of the ith core, W1 is the category preset weight of the core hit rate, N is the total number of memory data blocks, G no is the data update rate of the oth memory data block, Q qo is the preset weight value of the oth memory data block, N oj is the memory data update sequence of the oth memory data block, and W2 is the preset weight value of the category of the memory data block;

[0039] The system comprehensive performance coefficient is compared with the preset coefficient threshold, and the system status is judged and warned based on the comparison results.

[0040] Beneficial effects of the present invention: The present invention adopts an independent cache management unit and a cache record table, and avoids the complex cache consistency protocol between multi-core processors through centralized management. This not only reduces the complexity and overhead of the system, but also improves the performance of the system. The present invention realizes centralized management of cache data through the cooperation of the central exchange block and the high-speed storage body block. This design ensures better cache consistency between each core and avoids the problem of data inconsistency. The present invention records the state of each data block in the cache management table and takes corresponding operations according to the different states. This design makes the reading and writing of cache data more efficient and reduces the delay of the system. The present invention realizes centralized management of cache data through an independent cache management unit and a cache record table, and avoids the conflict problem of cache consistency protocol between multi-core processors. This further improves the performance of the system. The design of the present invention effectively solves the cache consistency problem between multi-core processors, thereby improving the availability and reliability of the system. This is of great significance for computer systems that require high availability and high reliability. In general, compared with the prior art, the present invention not only simplifies the design and implementation of the system, improves the performance of the system, but also improves the availability and reliability of the system, and has significant advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of a method for centrally managing cache consistency of a multi-core processor;

[0042] Figure 2 A schematic diagram of the central switching block connecting all core modules and system main memory;

[0043] Figure 3 Express intent for cache management;

[0044] Figure 4 A flow chart of cache management when the core reads main memory;

[0045] Figure 5 The figure is a flow chart of cache management when the core needs to update the data in the cache. DETAILED DESCRIPTION

[0046] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0047] One embodiment of the present invention is a multi-core processor, wherein the multi-core manager includes a central switching block, a system main memory and at least one core module, wherein the central switching block is electrically coupled to the system main memory, and the central switching block is electrically coupled to the core module.

[0048] The central switching block includes a CROSSBAR or a routing switch.

[0049] A cache management unit and a cache record table are disposed inside the central switching block, and the cache management unit and the cache record table are electrically coupled.

[0050] A high-speed memory is also arranged inside the central switching block.

[0051] The core module includes a computer core or a core cluster.

[0052] The working principle of the above technical solution is: the design of the central switching block, which is any form of multi-path bus, can be a CROSSBAR, or a switch with routing function. The central switching block connects all computer cores or core clusters and system main memory, such as Figure 2 As shown, data exchange and access between various components are realized. The design of the central switching block makes data exchange and access more efficient, avoiding conflicts when multiple cores read or write the same data block at the same time, thereby ensuring cache consistency. Design of independent cache management unit and cache record table. The central switching block has an independent cache management unit and cache record table, such as Figure 3 As shown, it is used to manage and record the read and write operations of each core cache. This design ensures better cache consistency, while also avoiding the large amount of communication and synchronization operations required in the implementation of the cache consistency protocol, thereby improving the performance and efficiency of the system. The high-speed memory inside the central switching block is used to accelerate data read and write operations. The design of this high-speed memory makes data exchange and access more efficient, further improving the performance and efficiency of the system. When any core applies to read data, if a cache miss occurs, the cache management unit in the central switching block will check the cache management table to see if any other core already holds the data. If another core already holds the data, the buffer management unit will convert the data read request into a data read request to the holding core, thereby avoiding conflicts when multiple cores read or write the same data block at the same time, ensuring cache consistency, such as Figure 4As shown in the figure, when a core needs to update the data in the cache, it will send a notification message to the buffer management unit, which will record the memory block and invalidate the cache of the block in the memory. After the core that applies for modification completes the update of the memory data block, the buffer management unit will reset the dirty bit of the cache management table to 0. This design ensures better cache consistency and avoids the complexity and overhead required in the implementation of the cache consistency protocol. Figure 5 The above are the specific steps of this embodiment. Through these steps, cache consistency management based on the central switching block can be implemented to improve the performance and efficiency of the system.

[0053] The technical effect of the above technical solution is as follows: the present invention adopts an independent cache management unit and a cache record table, and avoids the complex cache consistency protocol between multi-core processors through centralized management. This not only reduces the complexity and overhead of the system, but also improves the performance of the system. The present invention realizes centralized management of cache data through the cooperation of the central exchange block and the high-speed storage body block. This design ensures better cache consistency between each core and avoids the problem of data inconsistency. The present invention records the state of each data block in the cache management table and takes corresponding operations according to the different states. This design makes the reading and writing of cache data more efficient and reduces the delay of the system. The present invention realizes centralized management of cache data through an independent cache management unit and a cache record table, and avoids the conflict problem of cache consistency protocol between multi-core processors. This further improves the performance of the system. The design of the present invention effectively solves the cache consistency problem between multi-core processors, thereby improving the availability and reliability of the system. This is of great significance for computer systems that require high availability and high reliability. In general, compared with the prior art, the present invention not only simplifies the design and implementation of the system, improves the performance of the system, but also improves the availability and reliability of the system, and has significant advantages.

[0054] Compared with the prior art, this embodiment mainly solves the following technical problems: the existing cache consistency protocol requires a large amount of communication and synchronization operations during implementation, which not only increases the complexity and overhead of the system, but also affects the performance of the system. This technical solution uses an independent cache management unit and a cache record table, and through an independent centralized management unit, it executes the program that invalidates the cache data in a directional manner, completely avoiding the interruption of the core operation by snoop, and liberating the computing power of each core wasted in cache coherence, thereby improving the performance and efficiency of the system. When the existing cache consistency protocol processes multiple cores reading or writing the same data block at the same time, conflicts may occur, resulting in the inability to ensure cache consistency. This technical solution accelerates the reading and writing of data through a central switching block and a high-speed memory, avoids conflicts when multiple cores read or write the same data block at the same time, and thus ensures cache consistency. The existing cache consistency protocol has certain limitations in the application of multi-core processors. This technical solution provides a more flexible and efficient cache consistency solution through a unique central switching block and high-speed memory design, which is suitable for more multi-core processor application scenarios.

[0055] First, in the field of computer network technology, this technical solution uses an independent centralized management unit to execute programs that invalidate cache data in a targeted manner, completely avoiding the interruption of core operations by snoop, and liberating the computing power of each core wasted in cache coherence, which will greatly improve the processing speed and efficiency of computer network equipment, reduce network latency, improve the utilization of network resources, and meet the growing demand for network traffic. Secondly, in the field of data processing systems or methods, this technical solution accelerates the reading and writing speed of data through central switching blocks and high-speed memory, improves the efficiency and accuracy of data processing, and meets the needs of modern data-intensive applications for efficient data processing, such as big data analysis, artificial intelligence computing, etc. Finally, in the field of distributed computing technology, this technical solution uses central switching blocks and high-speed memory to achieve efficient data sharing and collaboration between multiple cores, improves the performance and scalability of distributed computing systems, and meets the needs of modern distributed computing for efficient data processing and real-time collaboration, such as cloud computing and edge computing. In general, this technical solution solves the problems of existing cache consistency protocols in multi-core processors through its unique design, improves the performance and efficiency of multi-core processors, meets the needs of modern computer networks, data processing and distributed computing, and has broad application prospects and market demands.

[0056] In one embodiment of the present invention, the method comprises:

[0057] Data exchange and information access between components are carried out through the connection of the central switching block, system main memory and core modules;

[0058] Record each core cache information through the core module;

[0059] Acquire data reading application information, acquire core data holding information according to the data reading application information, and convert and send the core of the data reading request according to the core data holding information;

[0060] Obtain the core update cache requirement information, the cache management unit updates the memory data block, and resets the cache management table, such as Figure 1 shown.

[0061] The working principle of the above technical solution is: data exchange and information access between various components (such as processors, input and output devices, etc.) are realized through the central switching block. As a data transfer station, the central switching block can efficiently coordinate the flow of data and ensure the smooth transmission of data in the system. The system main memory, as the main area for data storage, stores a large amount of programs and data. When a component needs to access data, it will send a data read request to the central switching block. The core module is responsible for connecting the central switching block and the system main memory, and processing data read and write requests. It reads or writes data from the system main memory according to the instructions of the central switching block. The core module contains a cache for temporarily storing frequently accessed data to improve the data access speed. The core module records the information of each core cache, including the data blocks stored in the cache, the access frequency of the data blocks, the update time of the data blocks, etc. This information helps the core module to manage and optimize data. When a component needs to read data, it sends data read request information to the central switching block. After receiving the application, the central exchange block will query the core data holding information recorded in the core module to determine the specific location of the required data in the system main memory. The central exchange block will convert and send the data reading request to the core module according to the core data holding information. The core module reads the data from the system main memory according to the request and transmits the data to the requesting component through the central exchange block. When the system detects that a data block needs to be updated, it will send the core update cache request information to the cache management unit. After receiving the request, the cache management unit will locate the location of the data block that needs to be updated in the system main memory and read the latest data from the system main memory. The cache management unit will write the latest data to the cache of the core module and update the cache management table to reflect the latest data status. If the cache is full, the cache management unit will also select and replace the old data block according to a replacement algorithm (such as the least recently used algorithm).

[0062] The technical effect of the above technical solution is: by using the core cache, the system can reduce the number of accesses to the system main memory, thereby speeding up data access. The data blocks in the core cache are usually frequently accessed data, so storing them in the cache can significantly improve data access efficiency; the central switching block can efficiently coordinate the flow of data and reduce data transmission delays and conflicts. The core module can intelligently manage the data blocks in the cache to ensure data accuracy and consistency. By using modular design, the system can easily add new components or expand the functions of existing components. The connection between the central switching block and the core module is highly flexible and scalable, and can adapt to system requirements of different scales and complexities. By using cache technology, the system can reduce dependence on the system main memory, thereby reducing hardware costs. Cache technology can also reduce the bandwidth requirements for data transmission, further reducing system costs. Through the connection between the central switching block, the system main memory and the core module, data exchange and information access between the components are carried out, and the core module records and manages the information of each core cache, so that the system can achieve efficient data reading and cache update processes. These mechanisms and technical effects help to improve the overall performance, stability and scalability of the system while reducing system costs.

[0063] In one embodiment of the present invention, recording each core cache information by a core module includes:

[0064] The read and write operations of each core cache are managed and recorded through the cache management unit and cache record table of the core module to obtain management information and record information.

[0065] The working principle of the above technical solution is:

[0066] The cache management unit is a key component in the core module, which is responsible for managing and controlling the read and write operations of the core cache. When a component requests to read data, the cache management unit first checks the cache record table to determine whether the required data is already in the cache. If the data is in the cache and the status is valid, the cache management unit will read the data directly from the cache and update the metadata such as the access count. If the data is not in the cache or the status is invalid, the cache management unit will read the data from the system main memory, store it in the cache, and update the cache record table. When a component requests to write data, the cache management unit also first checks the cache record table. If the data is already in the cache and the status is valid, the cache management unit will update the data in the cache. If the data is not in the cache, the cache management unit needs to execute a replacement strategy to make room, then write the new data to the cache, and update the cache record table. By maintaining the cache record table and monitoring cache operations, the cache management unit can generate various management information and record information, such as cache hit rate. This information is of great significance for system performance tuning, troubleshooting, and cache strategy adjustment.

[0067] The technical effect of the above technical solution is: through the effective management of the cache management unit and the cache record table, the system can reduce the number of accesses to the system main memory, thereby significantly improving the data access speed. Through intelligent replacement strategies and metadata management, it can ensure that the most commonly used or most important data is stored in the cache, thereby improving the utilization and performance of the cache. The cache management unit can monitor the status and performance of the cache, and promptly discover and handle potential cache consistency problems or failures, thereby enhancing the stability and reliability of the system. The management information and record information generated by the cache management unit provide an important basis for system performance tuning and troubleshooting. By analyzing this information, system administrators can identify performance bottlenecks, optimize cache strategies and fix potential problems. Through efficient cache management, the system can reduce dependence on the system main memory and access frequency, thereby reducing hardware costs and energy consumption. At the same time, the cache management unit can also optimize the utilization of data transmission bandwidth, further reducing system costs.

[0068] In one embodiment of the present invention, the step of obtaining data reading application information, obtaining core data holding information according to the data reading application information, and converting and sending a core of a data reading request according to the core data holding information includes:

[0069] Get the core data read request information, and when any core requests to read data, determine whether the cache hits;

[0070] When the cache misses, the cache management unit in the central switching block identifies whether the read data exists in the cache record table, that is, identifies whether its core holds the corresponding read data;

[0071] When corresponding read data is identified in its core, the cache management unit converts a data read request of the read data into a data read request of the core holding the read data, performs corresponding data reading, and obtains the read data.

[0072] The working principle of the above technical solution is as follows: when any core in the system needs to read data, it generates a core read data request information. This information usually contains the address or identifier of the data to be read. After receiving the data read request, the core first checks its local cache to determine whether the required data is already in the cache. This process is called cache hit judgment. If the data is in the cache (cache hit), the core reads the data directly from the cache without further operation. If the data is not in the cache (cache miss), the next step is required. When the cache misses, the core sends the data read request information to the cache management unit in the central switching block. The cache management unit accesses the cache record table it maintains, which records the data block information in the cache of all cores in the system. The cache management unit determines whether other cores hold the corresponding data by comparing the address or identifier in the data read request information with the entries in the cache record table. If the cache management unit identifies that other cores hold the corresponding data in the cache record table (that is, the required data is found in the cache of other cores), it converts the original data read request into a data read request of the core holding the data. This typically involves sending a data read request to the core holding the data and waiting for the core to return the data. The core holding the data, upon receiving the read request, reads the data from its cache and returns the data to the core requesting the data through the central switch block. The core requesting the data, upon receiving the data returned from the other cores, stores it in its local cache (if possible) for later use. The core also provides the data to the processor or functional module that requested it to complete the data read operation.

[0073] The technical effect of the above technical solution is: through the use of cache hit judgment and cache record table, the system can reduce the number of accesses to the system main memory, thereby improving data access efficiency. When the data is in the cache, it can be read directly from the cache without waiting for the access of the system main memory. When the data is in the cache of other cores, unnecessary data transmission and delay can be avoided by converting the data reading requirements. The cache management unit can intelligently manage the data blocks in the cache to ensure that the most commonly used or most important data is stored in the cache. Through the conversion of data reading requirements, the system can more effectively utilize the cache resources of all cores and improve the overall cache utilization. This mechanism allows the system to expand the processing power of the system by increasing the number of cores without increasing additional hardware costs. Each core can be used as a potential source of data reading, thereby improving the parallel processing capability and scalability of the system. By directly transmitting data between cores (when the data is in the cache of other cores), the system can reduce the overhead of data transmission through the system main memory. This helps to reduce the overall energy consumption and delay of the system and improve the overall performance of the system. The mechanism encourages collaboration and data sharing between cores, thereby improving the overall efficiency and flexibility of the system. By intelligently managing data read requests and cache resources, the system can better adapt to different workloads and performance requirements.

[0074] In one embodiment of the present invention, the obtaining of core update cache requirement information, the cache management unit updating the memory data block, and resetting the cache management table include:

[0075] Obtaining a core update cache requirement, and sending the core update cache requirement to a cache management unit;

[0076] Recording the corresponding memory data block through the cache management unit, and invalidating the cache information in the memory data block;

[0077] The core updates the memory data block, and when the update is completed, the cache management unit resets the cache record table.

[0078] The working principle of the above technical solution is as follows: when a core in the system needs to update a memory data block, it generates a core update cache request. This request usually includes the address or identifier of the memory data block to be updated, as well as the new data to be written. The core sends the update request to the cache management unit in the central switching block. The cache management unit is a key component responsible for managing all cache activities in the system. After receiving the update request, the cache management unit first locates the corresponding memory data block and searches for cache entries related to the data block in the cache record table it maintains. If relevant cache entries are found, the cache management unit marks these entries as invalid to reflect that the data in the cache is outdated or no longer accurate. At the same time, the cache management unit records this update operation for subsequent cache consistency maintenance. After the cache management unit completes the invalidation of the cache information, the core begins to actually update the memory data block. This usually involves writing the data from the core back to the corresponding location in the system main memory. When the memory data block is updated, the cache management unit resets the cache record table. This process may include deleting or updating cache entries related to the update operation to ensure that the cache record table is consistent with the data in memory. The reset operation may also involve updating the cache replacement strategy, access count and other metadata to optimize subsequent cache performance.

[0079] The technical effect of the above technical solution is: by marking outdated or no longer accurate cache entries as invalid and resetting the cache record table after the memory data block is updated, the system can ensure that the data in the cache is consistent with the data in the memory. This helps prevent data inconsistency errors and program crashes. Resetting the cache record table helps the system use cache resources more efficiently. By deleting or updating outdated cache entries, the system can make room for new data requests, thereby improving the cache hit rate and performance. At the same time, updating the cache metadata can optimize the cache replacement strategy and further improve the cache utilization and performance. When the system needs to access the updated data, since the cache record table is already consistent with the data in the memory, the system can read the data directly from the cache (if the data is still in the cache) without waiting to read from the memory. This helps to improve data access speed and system responsiveness. By maintaining cache consistency, the system can reduce errors and failures caused by data inconsistency. This helps to improve the stability and reliability of the system, especially in processing critical tasks and high-availability applications. When multiple cores need to access or update the same memory data block, the cache management unit can coordinate the operations between them to ensure data consistency and synchronization. This helps improve the parallel processing capability and overall performance of the system.

[0080] In one embodiment of the present invention, the acquisition of core hit data and memory update data, analysis of core hit performance and memory update performance, and further system comprehensive analysis, status determination and early warning include:

[0081] Obtain cache hit data when a core applies to read data, and calculate a cache hit rate of each core based on the cache hit data combined with a preset weight of the core;

[0082] The calculation formula of the cache hit rate of the core is:

[0083]

[0084] Among them, M z is the cache hit rate of the core, Z c is the number of successful data acquisitions, C z is the total number of core visits, Q h The preset weight value for the core;

[0085] Sort the cache hit rate of each core from large to small to obtain the core hit sequence;

[0086] Acquire updated data information of the memory data block, and calculate the data update rate of each memory data block according to the updated data information combined with the preset weight of the memory data block;

[0087] The calculation formula of the data update rate of the memory data block is:

[0088]

[0089] Among them, G n is the data update rate of the memory data block. c is the number of data updates in the memory data block, s c is the total number of data storage times in the memory data block, Q q The preset weight value of the memory data block;

[0090] Sort the data update rate of each memory data block from large to small to obtain a memory data update sequence;

[0091] Calculating a system comprehensive performance coefficient based on the core hit rate combined with the memory data block;

[0092] The calculation formula of the system comprehensive performance coefficient is:

[0093]

[0094] Among them, ZH is the system comprehensive performance coefficient, H is the total number of cores, M zi is the cache hit rate of the ith core, Qhi is the preset weight value of the ith core, H ij is the number of core hit sequences of the ith core, W1 is the category preset weight of the core hit rate, N is the total number of memory data blocks, G no is the data update rate of the oth memory data block, Q qo is the preset weight value of the oth memory data block, N oj is the memory data update sequence of the oth memory data block, and W2 is the preset weight value of the category of the memory data block;

[0095] The system comprehensive performance coefficient is compared with the preset coefficient threshold, and the system status is judged and warned based on the comparison results.

[0096] The working principle of the above technical solution is as follows: obtain the cache hit data of the core when applying to read data, which reflects the number of times the core successfully obtains data from the cache and the total number of accesses. Obtain the updated data information of the memory data block, including the number of data updates and the total number of data storages, which reflects the activity and update frequency of the memory data. Calculate the cache hit rate of each core according to the cache hit data and the preset weight of the core. The cache hit rate is the ratio of the number of times the core successfully obtains data from the cache to the total number of accesses, reflecting the cache usage efficiency of the core. Calculate the data update rate of each memory data block according to the updated data information and preset weight of the memory data block. The data update rate is the ratio of the number of data updates of the memory data block to the total number of storages, reflecting the activity of the data and the dynamic use of the memory. Sort the cache hit rate of each core from large to small to obtain a core hit sequence. This sequence reflects the pros and cons of the cache performance of each core. Sort the data update rate of each memory data block from large to small to obtain a memory data update sequence. This sequence reflects the activity and update frequency of each memory data block. The system comprehensive performance coefficient is calculated by combining the core cache hit rate and the data update rate of the memory data block, as well as their preset weights and sequence numbers. This coefficient is a comprehensive indicator that reflects the overall cache efficiency of the system and the activity of memory data updates. The system comprehensive performance coefficient is compared with the preset coefficient threshold. If the system comprehensive performance coefficient is lower than the threshold, it is determined that the system status is poor and optimization measures or early warning signals may need to be taken.

[0097] The technical effect of the above technical solution is: by calculating the cache hit rate of the core and the data update rate of the memory data block, as well as the system comprehensive performance coefficient, the system cache efficiency and the activity of memory data update can be accurately evaluated, providing strong support for system optimization. By monitoring and early warning the system comprehensive performance coefficient, the trend of system performance degradation can be discovered in time, and preventive measures can be taken to avoid serious problems such as system crashes or data loss. According to the core hit sequence and memory data update sequence, the cores and data blocks with poor performance can be identified, thereby optimizing resource allocation and improving the overall operating efficiency of the system. The system comprehensive performance coefficient and other related indicators can provide strong data support for system administrators or decision makers, helping them make more informed decisions, such as adjusting system configuration, optimizing algorithms, etc. This method is of great significance in improving system performance, stability and resource allocation, and provides strong support for intelligent management and optimization of the system.

[0098] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A multi-core processor, characterized in that: The multi-core manager includes a central switching block, a system main memory and at least one core module, wherein the central switching block is electrically coupled to the system main memory, and the central switching block is electrically coupled to the core module; The read and write operations of each core cache are managed and recorded through the cache management unit and cache record table set inside the central switching block; Update the memory data block through the cache management unit and reset the cache management table; Obtain core hit data and memory update data, analyze core hit performance and memory update performance, and then conduct comprehensive system analysis, status determination and early warning, including: Obtain cache hit data when a core applies to read data, and calculate a cache hit rate of each core based on the cache hit data combined with a preset weight of the core; The calculation formula of the cache hit rate of the core is: Among them, M z is the cache hit rate of the core, Z c is the number of successful data acquisitions, C z is the total number of core visits, Q h The preset weight value for the core; Sort the cache hit rate of each core from large to small to obtain the core hit sequence; Acquire updated data information of the memory data block, and calculate the data update rate of each memory data block according to the updated data information combined with the preset weight of the memory data block; The calculation formula of the data update rate of the memory data block is: Among them, G n is the data update rate of the memory data block, g c is the number of data updates in the memory data block, s c is the total number of data storage times in the memory data block, Q q The preset weight value of the memory data block; Sort the data update rate of each memory data block from large to small to obtain a memory data update sequence; Calculating a system comprehensive performance coefficient based on the core hit rate combined with the memory data block; The calculation formula of the system comprehensive performance coefficient is: Among them, ZH is the system comprehensive performance coefficient, H is the total number of cores, M zi is the cache hit rate of the ith core, Q hi is the preset weight value of the ith core, H ij is the number of core hit sequences of the ith core, W1 is the category preset weight of the core hit rate, N is the total number of memory data blocks, G no is the data update rate of the oth memory data block, Q qo is the preset weight value of the oth memory data block, N oj is the memory data update sequence of the oth memory data block, and W2 is the class preset weight value of the memory data block; The system comprehensive performance coefficient is compared with the preset coefficient threshold, and the system status is judged and warned based on the comparison results.

2. A multi-core processor according to claim 1, characterized in that: The central switching block includes a CROSSBAR or a routing switch, the cache management unit and the cache record table are electrically coupled and connected, a high-speed memory is also arranged inside the central switching block, and the core module includes a computer core or a core cluster.

3. A method for implementing a centralized cache coherence management method for a multi-core processor as claimed in claim 1, characterized in that: The method comprises: Data exchange and information access between components are carried out through the connection of the central switching block, system main memory and core modules; Record each core cache information through the core module; Acquire data reading application information, acquire core data holding information according to the data reading application information, and convert and send the core of the data reading request according to the core data holding information; The core update cache requirement information is obtained, the cache management unit updates the memory data block, and resets the cache management table.

4. The method for centrally managing cache coherence of a multi-core processor according to claim 3, characterized in that: The recording of each core cache information by the core module includes: The read and write operations of each core cache are managed and recorded through the cache management unit and cache record table of the core module to obtain management information and record information.

5. The method for centrally managing cache coherence of a multi-core processor according to claim 3, characterized in that: The step of obtaining data reading application information, obtaining core data holding information according to the data reading application information, and converting and sending the core of the data reading request according to the core data holding information includes: Get the core data read request information, and when any core requests to read data, determine whether the cache hits; When the cache misses, the cache management unit in the central switching block identifies whether the read data exists in the cache record table, that is, identifies whether other cores hold the corresponding read data; When corresponding read data is identified in other cores, the cache management unit converts the data read request of the read data into a data read request of the core holding the read data, performs corresponding data reading, and obtains the read data.

6. The method for centrally managing cache coherence of a multi-core processor according to claim 3, characterized in that: The obtaining of the core update cache requirement information, the cache management unit updating the memory data block, and resetting the cache management table, includes: Obtaining a core update cache requirement, and sending the core update cache requirement to a cache management unit; Recording the corresponding memory data block through the cache management unit, and invalidating the cache information in the memory data block; The core updates the memory data block, and when the update is completed, the cache management unit resets the cache record table.

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