Floating point addition implementation method, device and electronic device for mixed precision calculation

Abstract

The present application discloses a method, device and electronic device for implementing mixed-precision floating-point addition, the method comprising: lightly preprocessing two low-precision operands of floating-point addition; if the improved near-path condition is met, performing leading zero prediction and mantissa addition operations on the two operands in parallel to obtain a near-path operation result, the number of leading zeros including the number of leading zeros offset by the high-bit of the mantissa of the floating-point addition and the number of denormalized leading zeros; if the improved near-path condition is not met, performing far-path shift and mantissa addition operations on the two operands to obtain a far-path operation result; selecting one of them as the operation result to perform mantissa rounding and normalization shift to obtain a high-precision floating-point addition operation result. Through the above manner, the embodiment of the present invention can combine the normalized calculation with increased precision with the existing near-path calculation, realize floating-point addition operation resource reuse and delay elimination, and improve execution efficiency.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of floating-point operation technology, and specifically to a method, device and electronic device for implementing mixed-precision floating-point addition. Background Art

[0002] The development of floating-point algorithms has gone through a long period of development. Standard algorithms for operations in the same data format are basically mature. For standard high-performance floating-point adders, dual-path implementation is currently widely used.

[0003] RISC-V is the abbreviation of the fifth-generation reduced instruction set, which is currently the most widely used reduced instruction set. The RISC-V vector instruction set has instructions for mixed data format floating-point operations, including instructions for adding low-precision operands to obtain high-precision results. For example, in one instruction, there are two floating-point addends, one is single precision and the other is double precision, and the result of floating-point addition is double precision, or the two addends are single precision and the result is double precision. Based on this, the problem of calculating with different floating-point precisions arises. The current classical floating-point algorithm is mainly based on the logic circuit design based on the same precision of the addend and the result. The hardware design of the traditional implementation of floating-point addition only has floating-point adders with the same data format, such as single-precision adders (both addends and results are single-precision), double-precision adders, or a "mixed adder" that implements high- and low-precision single-precision in a double-precision adder. This mixed-precision adder implements two sets of single-precision additions to reuse the computing resources in the double-precision floating-point addition. Its essence is still the same-precision adder, which is not the same concept as the mixed-precision floating-point adder proposed in this article. Traditionally, there is an independent unit dedicated to implementing the precision conversion circuit of different data formats. To implement the mixed-data format floating-point addition operation, the general method is to split the floating-point addition vector instruction of the mixed data format into micro-operations, which are divided into floating-point data format conversion micro-operations and floating-point addition micro-operations of the same data format, and then perform high-precision floating-point addition operations after converting the two operands into high-precision. Its disadvantage is that it adds additional micro-operations. Another implementation method is to use an additional cycle to convert the low-precision operand to high-precision, not report the flag, retain the original mantissa of the special value, and forward it to the standard high-precision floating-point adder with the same data format for operation in the second cycle, report the flag, and process the special value.

[0004] The existing technology for adding micro-operations is that due to the limitation of write port resources, the two operands need to use one micro-operation each to improve the precision, and a mixed-precision addition adds a total of two micro-operations, which obviously reduces the execution efficiency, especially when the vector length is long and multiple additions are required. If the method of splitting micro-operations is not used, an additional precision conversion unit can be added to increase the execution cycle by one beat. The main delay is in the conversion of low-precision non-normalized numbers to high-precision normalized numbers, which will also reduce the execution efficiency. Although the floating-point addition path is reused with general floating-point addition resources, since the execution cycles of the two addition instructions using the same precision floating-point adder do not start at the same pipeline stage, a resource conflict problem will be introduced. In order to ensure the correctness of data calculation, it is necessary to implement additional emission restrictions, which will affect the execution of the same precision floating-point addition instructions. Summary of the invention

[0005] In view of the above problems, embodiments of the present invention provide a method, device and electronic device for implementing mixed-precision floating-point addition, which overcome the above problems or at least partially solve the above problems.

[0006] According to one aspect of an embodiment of the present invention, a method for implementing floating-point addition of mixed-precision operations is provided, the method comprising: improving a near-path condition, lightly preprocessing two low-precision operands of the floating-point operation, and determining whether the improved near-path condition is met; if the improved near-path condition is met, performing leading zero prediction and mantissa addition operations on the two low-precision non-normalized operands in parallel, and performing normalized full-bit-width shifting on the mantissa operation result according to the predicted number of leading zeros to obtain a near-path operation result, wherein the number of leading zeros includes the number of leading zeros that appear due to the high-bit offset of the mantissas of the floating-point addition and the number of non-normalized leading zeros, which are shifted to the left together by a full-bit-width shifter to be removed; if the near-path condition is not met, performing far-path order shifting and mantissa addition operations on the two low-precision non-normalized operands to obtain a far-path operation result; and controlling to select one of the far-path operation result and the near-path operation result as the operation result, performing mantissa rounding and 1-bit normalization shifting on the operation result to obtain a high-precision floating-point addition operation result.

[0007] Optionally, the light preprocessing of the two low-precision operands of the floating-point addition operation includes: for the two low-precision operands of the floating-point addition operation, the exponent is added with the difference of the index offset between the low-precision and high-precision precisions, and the mantissa is padded with zeros.

[0008] Optionally, the determination of whether the improved near-path condition is met includes: if the two operands are subtracted and the exponent difference is less than or equal to 1, or the two operands are added and the exponents are both 0 at low precision, i.e., denormalized numbers, then it is determined that the near-path condition is met.

[0009] Optionally, the leading zero prediction and mantissa addition operation are performed on two low-precision non-normalized operands in parallel, including: performing a 1-bit shift on the two low-precision non-normalized operands; performing a mantissa addition operation on the two low-precision non-normalized operands or performing a subtraction operation through selective complementation, and performing leading zero prediction at the same time to obtain the number of leading zeros and the mantissa operation results.

[0010] Optionally, the leading zero prediction includes: performing leading zero prediction encoding on two low-precision operands to obtain the number of leading zeros that appear when the high bits of the mantissas of the addition of the floating-point numbers are offset; calculating the sum of the number of leading zeros that appear when the high bits of the mantissas of the addition of the floating-point numbers are offset and the number of denormalized leading zeros to obtain the final predicted number of leading zeros.

[0011] Optionally, performing a far path rank shift and mantissa addition operation on two low-precision non-normalized operands to obtain a far path operation result includes: performing a full-bit width rank shift on the two low-precision non-normalized operands; performing a mantissa addition operation on the two shifted low-precision non-normalized operands to obtain a far path operation result.

[0012] Optionally, the control selects one of the far path operation result and the near path operation result as the operation result, including: determining a control signal based on two low-precision denormalized operands; and selecting one of the far path operation result and the near path operation result as the operation result based on the control signal.

[0013] Based on the same inventive concept, a floating-point addition implementation device for mixed-precision operation is provided, comprising: a preprocessing unit, used for improving the near path condition, preprocessing two low-precision operands of the floating-point operation, and determining whether the near path condition is met; a near path processing unit, used for, if the near path condition is met, performing leading zero prediction and mantissa addition operation on the two low-precision non-normalized operands in parallel, and performing normalized full-bit-width shift on the mantissa operation result according to the predicted leading zero number, to obtain the near path operation result, wherein the leading zero number includes the leading zero number that appears due to the high-bit offset of the mantissa of the floating-point addition and the non-normalized leading zero number; a far path processing unit, used for, if the near path condition is not met, performing far path order shift and mantissa addition operation on the two low-precision non-normalized operands, to obtain the far path operation result; and a result processing unit, used for controlling the selection of one of the far path operation result and the near path operation result as the operation result, performing mantissa rounding and 1-bit normalization shift on the operation result, to obtain the high-precision floating-point addition operation result.

[0014] Based on the same inventive concept, an embodiment of the present invention further proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the aforementioned method when executing the program.

[0015] Based on the same inventive concept, an embodiment of the present invention further proposes a computer storage medium, in which at least one executable instruction is stored, and the executable instruction enables a processor to execute the aforementioned method.

[0016] The beneficial effects of the present invention are as follows: the embodiment of the present invention pre-processes two low-precision operands of floating-point operation by improving the near-path condition, and determines whether the near-path condition is met; if the near-path condition is met, leading zero prediction and mantissa addition operation are performed on the two low-precision non-normalized operands in parallel, and the mantissa operation result is normalized full-bit-width shifted according to the predicted leading zero number to obtain the near-path operation result, wherein the leading zero number includes the leading zero number and the non-normalized leading zero number that appear when the high-bit of the mantissa of the floating-point addition is offset; if the near-path condition is not met, far-path shift and mantissa addition operation are performed on the two low-precision non-normalized operands to obtain the far-path operation result; one of the far-path operation result and the near-path operation result is controlled to be selected as the operation result, and the mantissa rounding and 1-bit normalization shift are performed on the operation result to obtain the high-precision floating-point addition operation result, and the normalization calculation and the near-path calculation are combined into one by reusing the data path of the standard floating-point adder, so as to achieve the purpose of resource reuse and delay elimination, and improve the execution efficiency.

[0017] The above description is only an overview of the technical solution of the embodiment of the present invention. In order to more clearly understand the technical means of the embodiment of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0019] Figure 1 A schematic flow chart of a method for implementing mixed-precision floating-point addition provided in an embodiment of the present invention is shown;

[0020] Figure 2 A schematic diagram of light preprocessing of operands according to an embodiment of the present invention is shown;

[0021] Figure 3 A schematic diagram showing an implementation method of a mantissa path according to an embodiment of the present invention is shown;

[0022] Figure 4 A schematic diagram showing the structure of a floating-point addition implementation device for mixed-precision operations provided by an embodiment of the present invention is shown;

[0023] Figure 5 A schematic diagram of an electronic device in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0024] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.

[0025] Figure 1 FIG. 1 is a flow chart showing a method for implementing a mixed precision floating point addition operation provided by an embodiment of the present invention. Figure 1 As shown, the mixed precision floating point addition implementation method is applied to the server, and the mixed precision floating point addition implementation method includes:

[0026] Step S11: improving the near-path condition, preprocessing the two low-precision operands of the floating-point addition operation, and determining whether the improved near-path condition is satisfied.

[0027] The embodiment of the present invention is to multiplex the floating-point operation function of adding low precision to low precision equal to high precision in a high-precision floating-point adder of the same precision. Improvements are made on the classic dual-path floating-point addition algorithm, mainly improving the near-path conditions and adding relevant necessary operation logic; if a normal high-precision same-precision floating-point adder operation is performed, there is no need to perform a light preprocessing operation on the two high-precision operands to be added, in order to preliminarily align the high precision, but no normalization is performed. If an addition operation is required for two low-precision operands, the two low-precision operands that need to be floated are first obtained, and the two low-precision operands are preprocessed, and then it is determined whether the improved near-path conditions are met.

[0028] Step S12: If the improved near-path condition is met, leading zero prediction and mantissa addition operations are performed on two low-precision denormalized operands in parallel, and the mantissa operation result is normalized full-bit-width shifted according to the predicted number of leading zeros to obtain a near-path operation result, wherein the leading zero number includes the leading zero number that occurs when the high-bit of the mantissa of the floating-point addition is offset and the denormalized leading zero number.

[0029] If the near path condition is met, it means that the two low-precision non-normalized operands are suitable for floating-point operations using the near path algorithm. Two low-precision non-normalized operands are input into the near path, and after leading zero prediction and mantissa addition operations, the mantissa operation result is normalized to full-bit width shift according to the predicted number of leading zeros to obtain the near path operation result. The number of leading zeros includes the number of leading zeros that appear when the high-bit of the mantissa of the floating-point addition is offset and the number of non-normalized leading zeros. The number of non-normalized leading zeros is mainly caused by the improvement of precision. The two leading zeros will be shifted left by a shifter to achieve the purpose of multiplexing and eliminating delay. Compared with the prior art that normalization requires a set of "find leading 0, then shift", and the near path also requires a set of "find leading 0, then shift", in this process, the two are merged through adaptive modification, and there is no need to convert the low-precision non-normalized number into a high-precision normalized number before performing related operations, which can reduce delay and improve algorithm execution efficiency.

[0030] Step S13: If the improved near path condition is not satisfied, a far path shift and mantissa addition operation is performed on the two low-precision denormalized operands to obtain a far path operation result.

[0031] If the improved near path condition is not met, it means that the two low-precision denormalized operands are suitable for floating-point operations using the near path algorithm. Regardless of whether the two operands are high-precision or low-precision, the same algorithm can be used for operation. In the embodiment of the present invention, the two low-precision denormalized operands are subjected to the far path order shift and mantissa addition operations to obtain the far path operation result.

[0032] Step S14: controlling to select one of the far path operation result and the near path operation result as the operation result, performing mantissa rounding and 1-bit normalization shift on the operation result, and obtaining a high-precision floating-point addition operation result.

[0033] According to the two operands to be operated, one of the far path operation result and the near path operation result is selected as the operation result. If the near path condition is met, the near path operation result is selected as the operation result; if the near path condition is not met, the far path operation result is selected as the operation result. Then the selected operation result is rounded and 1-bit normalized shifted to obtain a high-precision floating-point addition operation result.

[0034] The existing dual-path algorithm needs to determine the relationship between the exponents of the two floating-point operands to determine the direction of the near and far paths, and to obtain the exponent difference to determine the order. However, the normalized exponent of the low-precision denormalized number in the high-precision format is not intuitive, and the number of leading 0s in the mantissa must be known before it can be determined. The existing dual-path algorithm is for the same precision, so the low-precision denormalized number must be converted into a high-precision normalized number before the true exponent of the low-precision denormalized number corresponding to the higher precision can be correctly known. At the same time, the mantissa must be shifted and normalized, otherwise the classic dual-path algorithm cannot be used correctly. This conversion requires a large delay to remove the leading 0 of the low-precision mantissa and correct the exponent. The necessary operation requires the calculation circuits for the leading 0 calculation of the mantissa and the full-bit width shifter logic circuit of the mantissa, both of which are serial calculations. This operation is performed before the floating-point addition, that is, before the addition is performed, the delay of the leading 0 calculation and the large bit width shift has already occurred. The delay logic level is large and cannot be ignored, which will directly reduce the performance and significantly reduce the circuit frequency. Ultimately, it may be necessary to use a method that increases the execution pipeline cycle by one level to specifically handle these two calculation delays to offset the impact of the frequency reduction. The embodiment of the present invention improves the current mainstream dual-path floating-point adder. In a high-precision floating-point adder with the same precision, a new floating-point operation function of low-precision plus low-precision equals high-precision is multiplexed. When entering the near-path operation circuit, the mantissa enters with a non-normalized state, and does not first perform normalization processing to adapt to high precision. The leading 0 prediction and full-bit width shift of the near-path are used to complete the necessary normalization operations. At the same time, the two components of the near-path are also performing the normal floating-point calculation process. In this way, a large number of leading 0s that may be generated by the near-path and a large number of leading 0s that are converted from low-precision non-normalized numbers to high-precision normalized numbers are generated. 0, are put together and shifted away. The above delay is eliminated without increasing the pipeline cycle and almost without reducing the frequency. Only a small amount of control delay needs to be added to achieve the addition of low-precision non-normalized numbers directly in the high-precision dual-path algorithm. The embodiment of the present invention supports mixed-precision calculation by adding a small amount of logic in the standard floating-point adder without increasing the execution cycle, and the execution logic circuit delay is almost the same as that of the standard floating-point adder. Using this module at a higher level makes the calculation control processing simpler, achieves a high reuse rate, and has a faster execution efficiency, thereby improving the utilization of floating-point resources.

[0035] In the embodiment of the present invention, the preprocessing of two low-precision operands is optional. For the two low-precision operands of floating-point operation, the exponent is added with the difference between the two precisions of low precision and high precision, and the mantissa is padded with zero. Figure 2, taking the single-precision to double-precision alignment preprocessing as an example, the 32-bit original low-precision floating-point number is obtained as a 64-bit high-precision floating-point number after preprocessing. In the high-precision floating-point number after alignment preprocessing, the sign bit is directly inherited from the original low-precision floating-point number, the highest exponent bit is inherited from the highest exponent bit of the original low-precision floating-point number, the next highest three exponent bits are obtained from the highest exponent bit of the original low-precision floating-point number through a NOT gate, and the other exponent bits are directly inherited from the original low-precision floating-point number. The mantissa bits after preprocessing first directly inherit the mantissa bits of the original low-precision floating-point number, and then zero is added at the end to obtain a 64-bit high-precision floating-point number. The entire preprocessing process consumes only one NOT gate, which only brings very little resource consumption and delay, so it is called light preprocessing.

[0036] In step S11, when determining whether two low-precision denormalized operands satisfy the near-path condition, optionally, if the two operands are subtracted and the exponent difference is less than or equal to 1, or the two operands are added and the exponents are both 0 at low precision, then it is determined that the near-path condition is satisfied, and a near-path algorithm is applied to perform an addition operation of the two low-precision denormalized operands; otherwise, the near-path condition is not satisfied, and a far-path operation is applied to perform an addition operation of the two low-precision denormalized operands.

[0037] When performing near-path operations, leading zero prediction is required. Optionally, two low-precision operands are encoded with leading zero prediction to obtain the number of leading zeros that appear when the high-bits of the mantissas of the floating-point numbers are offset; the sum of the number of leading zeros that appear when the high-bits of the mantissas of the floating-point numbers are offset and the number of unnormalized leading zeros is calculated to obtain the final predicted number of leading zeros. While performing leading zero prediction, mantissa addition operation is performed, and then the mantissa operation result is normalized to full-bit width shift according to the predicted number of leading zeros to obtain the near-path operation result. Since the number of leading zeros includes the number of leading zeros that appear when the high-bits of the mantissas of the floating-point numbers are offset, and the number of unnormalized leading zeros, the leading zero prediction is calculated once to obtain two types of "superimposed" leading zeros, which are then removed together, eliminating the large delay caused by low-precision unnormalized numbers. Only a small amount of control delay needs to be added, which enables low-precision unnormalized numbers to be added directly in the high-precision dual-path algorithm.

[0038] If the near path condition is not met, a far path operation is required. Optionally, two low-precision non-normalized operands are shifted by full bit width; the mantissas of the two low-precision non-normalized operands after the shift are added to obtain the far path operation result. The far path operation can be directly performed using a high-precision floating-point adder of the same precision.

[0039] In an embodiment of the present invention, a control signal is determined according to two low-precision non-normalized operands; one of the far path operation result and the near path operation result is selected as the operation result according to the control signal. If the two low-precision non-normalized operands meet the near path condition, the determined control signal indicates to select the near path operation result; otherwise, the far path operation result is selected. In this way, the addition operation result of the two low-precision non-normalized operands is obtained. In the embodiment of the present invention, the path direction conditions of the dual paths are modified so that the above-mentioned large delay increase is merged into the near path for operation, thereby achieving the purpose of delay elimination. When entering the near path operation circuit, the mantissa enters with a non-normalized state, without first doing a normalized process adapted to high precision. Subsequently, the leading 0 prediction circuit and the large bit width shifter circuit of the near path are used to complete the necessary normalization operation, and at the same time, the two components of the near path are also performing the normal floating point calculation process, achieving the purpose of killing two birds with one stone. These two purposes are reflected in the fact that the near path was originally designed to solve the problem that a large number of leading 0s may be generated when the difference in the exponents of two floating-point additions (subtractions) is less than or equal to 1. Here, not only the situation of a large number of leading 0s generated in the original near path is handled, but also the leading 0s of the mantissa of low-precision non-normalized numbers that should have been normalized are handled at the same time. In summary, the large number of leading 0s that may be generated by the near path and the large number of leading 0s that are converted from low-precision non-normalized numbers to high-precision normalized numbers are shifted together. The value of the shift factor obtained by the large-bit width shifter of the near path is actually the sum of the number of leading 0s and non-normalized leading 0s that appear when the high bits of the mantissa of the floating-point addition (actually subtraction) cancel each other out. The two leading 0s are not merged through the adder, but the sum of the two leading 0s is implicitly obtained. The leading 0 prediction is calculated once to obtain two types of leading 0s that are "superimposed" and then removed together. The leading 0 is removed, and the subsequent rounding correction, abnormal bit judgment, etc. can be directly reused with the high-precision floating-point path. Through the above algorithm improvement, the large delay caused by low-precision denormalized numbers is eliminated. Only a small amount of control delay is added, which means that low-precision denormalized numbers can be directly added in the high-precision dual-path algorithm. The exponent path is similar to the standard floating-point addition. The specific method of the key mantissa path is as follows Figure 3As shown, first two operands are input and the calculation begins; then consider preprocessing the two operands. If the two operands are high-precision and of the same precision, no preprocessing is required. If the two operands are low-precision denormalized numbers, that is, mixed-precision calculations are performed, light preprocessing is required. Specifically, for each operand, the exponent is added with the difference in the exponent offset between the two precisions, and the mantissa is padded with zeros. The result of one of the paths is selected through MUX, and then it is determined whether the two operands meet the near-path condition. The near-path condition is as follows: in normal mode, that is, two operands of high precision and of the same precision, the two operands are subtracted and the difference in exponents is less than or equal to 1. In mixed mode, that is, two low-precision denormalized numbers, one condition is added: the two operands are added and the exponents are both 0 in low precision. If the near-path condition is met, the near-path operation is self-taught; otherwise, the far-path operation is performed. It can be seen that the near-path conditions for same-precision and mixed-precision calculations are not completely consistent.

[0040] In the near path, first use a 1-bit shifter to shift by 1 bit. If the two operands are of high precision and the same precision, the decimal mantissa is inverted bit by bit. That is, if the same precision calculation is performed, the complement code is calculated. If the two operands are of low precision and non-normalized, and if they enter the path due to addition, the complement code is not inverted, otherwise the complement code is also calculated. That is, if mixed precision calculation is performed, the complement code can be calculated or not according to different calculation situations. Similarly, MUX is used to select the result of the corresponding path. Then the leading 0 prediction module is used to predict the leading 0, and the leading 0 calculation module is used to calculate the leading 0. In normal mode, the leading 0 of the mantissa subtracted from the mantissa of the near path index is calculated. In mixed mode, low-precision unnormalized leading 0 is also included. At the same time, the mantissa adder is used to perform mantissa addition operation. Then the normalized full-bit width shifter is used to grid the mantissa addition operation result according to the number of leading zeros.

[0041] In the far path, the full-width order shifter is used to shift, whether in normal mode or mixed mode. If the exponent is 0 in the original precision, the shift position is corrected by 1. The mantissa adder is then used to add the mantissa. If it is a subtraction, the minuend is complemented and then added.

[0042] The data selector MUX is applied to select the operation result according to the control signal, and then the 1-bit planning shifter is applied to shift the operation result, including far path normalization and near path leading 0 error correction. Finally, rounding operation is performed, and special values ​​are preferentially covered to obtain the final floating-point addition operation result. If an exception is stored during the calculation process, the corresponding exception flag is output. For inputs that do not contain low-precision non-normalized numbers, the embodiment of the present invention only needs to consume 1 level of gate delay to align the difference between the low-precision exponent complement and the exponent base to high precision, the mantissa is supplemented with 0, the sign is directly inherited, and the boundary upper limit (non-number, infinity, 0) flag is inherited to the current calculation under the original precision. Subsequent calculations can fully reuse high-precision floating-point adders with the same precision. It is equivalent to the conversion from low precision to high precision consuming only 1 level of gate delay. The two calculations of floating-point precision conversion and floating-point addition are coupled together, and the critical path delay caused by the precision conversion is eliminated, so that the operation that originally required 1 cycle conversion + 2 cycle addition for a total of 3 beats becomes a 2-beat floating-point addition operation with almost no frequency reduction. At the same time, the above two shortcomings are solved. Not only does it not need to split micro-operations, but it can also align the pipelines of floating-point adders with the same precision, without increasing the execution cycle, and the execution efficiency is also improved. The embodiment of the present invention adds two low-precision floating-point operands to obtain a high-precision floating-point result, improves the classic dual-path algorithm, reuses the data path of the standard floating-point adder, combines the normalization calculation with the near-path calculation, achieves the purpose of resource reuse and delay elimination, and improves the execution efficiency and saves area.

[0043] The embodiment of the present invention improves the classic dual-path floating-point addition algorithm, modifies the near-path judgment condition, and adds relevant necessary operation logic. The two low-precision operands of the floating-point addition operation are lightly preprocessed to preliminarily align with high precision, but no normalization is performed; if the improved near-path condition is met, the leading zero prediction and mantissa addition operation are performed on the two operands in parallel, and a normalized full-bit width shift is performed to obtain a near-path operation result, the number of leading zeros includes the number of leading zeros that appear due to the high-bit offset of the mantissa of the floating-point addition and the number of non-normalized leading zeros caused by the precision improvement, and the two leading zeros will be shifted to the left by a shifter to be removed; if the improved near-path condition is not met, the two operands are subjected to a far-path order shift and mantissa addition operation to obtain a far-path operation result; the control selects one of them as the operation result, and the mantissa is rounded and 1-bit normalized shift is performed on the operation result to obtain a high-precision floating-point addition operation result. Through the above method, the embodiment of the present invention can combine the normalized calculation with increased precision with the near-path calculation of the classical algorithm, realize the resource reuse and delay elimination of the same-precision floating-point addition operation and mixed-precision floating-point addition operation, and improve the execution efficiency.

[0044] In summary, the mixed-precision floating-point addition implementation method of the present invention improves the near-path condition, pre-processes the two low-precision operands of the floating-point operation, and determines whether the near-path condition is met; if the near-path condition is met, the two low-precision non-normalized operands are predicted to have leading zeros and the mantissa addition operation is performed in parallel, and the mantissa operation result is normalized to the full bit width according to the predicted number of leading zeros to obtain the near-path operation result, wherein the number of leading zeros includes the number of leading zeros that appear in the high-bit offset of the mantissa of the floating-point addition and the number of non-normalized leading zeros. number; if the near path condition is not met, the two low-precision non-normalized operands are subjected to far path order shift and mantissa addition operations to obtain a far path operation result; control the selection of one of the far path operation result and the near path operation result as the operation result, perform mantissa rounding and 1-bit normalization shift on the operation result to obtain a high-precision floating-point addition operation result, and combine the normalization calculation with the near path calculation into one by reusing the data path of the standard floating-point adder, thereby achieving the purpose of resource reuse and delay elimination, and improving execution efficiency.

[0045] The above specific embodiments of the present invention are described. In some cases, the actions or steps recorded in the embodiments of the present invention can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the process depicted in the accompanying drawings does not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0046] Based on the same concept, the embodiment of the present invention also provides a mixed precision floating point addition implementation device. Applicable to a server. Figure 4 As shown, the floating-point addition implementation of mixed precision operation includes: a preprocessing unit, a near path processing unit, a far path processing unit and a result processing unit. Among them,

[0047] A preprocessing unit, for improving the near path condition, lightly preprocessing two low-precision operands of the floating point addition operation, and determining whether the near path condition is satisfied;

[0048] A near-path processing unit is used to perform leading zero prediction and mantissa addition operations on two low-precision non-normalized operands in parallel if the improved near-path condition is met, and to perform normalized full-bit-width shifting on the mantissa operation result according to the predicted leading zero number to obtain a near-path operation result, wherein the leading zero number includes the leading zero number and the non-normalized leading zero number that appear due to the high-bit offset of the mantissa of the floating-point addition;

[0049] A far path processing unit is used for performing far path shift and mantissa addition operations on two low-precision denormalized operands to obtain a far path operation result if the improved near path condition is not satisfied;

[0050] The result processing unit is used to control the selection of one of the far path operation result and the near path operation result as the operation result, and perform mantissa rounding and 1-bit normalization shift on the operation result to obtain a high-precision floating-point addition operation result.

[0051] For the convenience of description, the above device is described as various modules according to their functions. Of course, when implementing the embodiment of the present invention, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0052] The device of the above embodiment is applied to the corresponding method in the above embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0053] Based on the same inventive concept, an embodiment of the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method described in any one of the above embodiments is implemented.

[0054] An embodiment of the present invention provides a non-volatile computer storage medium, wherein the computer storage medium stores at least one executable instruction, and the computer executable instruction can execute the method described in any of the above embodiments.

[0055] Figure 5 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 501, a memory 502, an input / output interface 503, a communication interface 504, and a bus 505. The processor 501, the memory 502, the input / output interface 503, and the communication interface 504 are connected to each other through the bus 505 in the device.

[0056] The processor 501 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solution provided by the method embodiment of the present invention.

[0057] The memory 502 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 502 can store an operating system and other application programs. When the technical solution provided by the method embodiment of the present invention is implemented by software or firmware, the relevant program code is stored in the memory 502 and called and executed by the processor 501.

[0058] The input / output interface 503 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0059] The communication interface 504 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.).

[0060] The bus 505 includes a path for transmitting information between various components of the device (eg, the processor 501 , the memory 502 , the input / output interface 503 , and the communication interface 504 ).

[0061] It should be noted that, although the above device only shows the processor 501, the memory 502, the input / output interface 503, the communication interface 504 and the bus 505, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present invention, and does not necessarily include all the components shown in the figure.

[0062] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present invention as described above, which are not provided in detail for the sake of simplicity.

[0063] This application is intended to cover all such substitutions, modifications and variations that fall within the broad scope of all embodiments. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the scope of protection of this disclosure.

Claims

1. A method for implementing floating-point addition of mixed precision operations, characterized in that: The method comprises: Improve the near path condition, perform light preprocessing on the two low-precision operands of the floating-point addition operation, and determine whether the improved near path condition is met; If the improved near-path condition is met, leading zero prediction and mantissa addition operations are performed on two low-precision denormalized operands in parallel, and the mantissa operation result is normalized full-bit-width shifted according to the predicted leading zero number to obtain a near-path operation result, wherein the leading zero number includes the leading zero number and the denormalized leading zero number that appear due to the high-bit offset of the mantissa of the floating-point addition; If the improved near path condition is not met, the far path order shift and mantissa addition operations are performed on the two low-precision denormalized operands to obtain the far path operation result; Controlling to select one of the far path operation result and the near path operation result as the operation result, performing mantissa rounding and 1-bit normalization shift on the operation result, and obtaining a high-precision floating-point addition operation result; The determining whether the improved near path condition is met includes: If the two operands are subtracted and the exponent difference is less than or equal to 1, or the two operands are added and the exponents are both 0 at low precision, then it is determined that the improved near path condition is satisfied; The controlling step of selecting one of the far path operation result and the near path operation result as the operation result includes: determining a control signal based on two low-precision denormalized operands; One of the far path calculation result and the near path calculation result is selected as a calculation result according to the control signal.

2. The method according to claim 1, characterized in that The light preprocessing of two low-precision operands of the floating-point addition operation includes: For two low-precision operands in floating-point addition operations, the exponent is added with the difference between the low-precision and high-precision index offsets, and the mantissa is padded with zeros.

3. The method according to claim 1, characterized in that The method of performing leading zero prediction and mantissa addition operations on two low-precision denormalized operands in parallel includes: Perform 1-bit shift on two low-precision denormalized operands; Perform mantissa addition or selective complement subtraction on two low-precision denormalized operands, and perform leading zero prediction to obtain the number of leading zeros and the mantissa result.

4. The method according to claim 1, characterized in that The performing leading zero prediction comprises: Perform leading zero prediction encoding on two low-precision operands to obtain the number of leading zeros that appear when the high bits of the mantissas of the floating-point addition are offset; The sum of the number of leading zeros that appear when the high bits of the mantissas of the added floating-point numbers are offset and the number of denormalized leading zeros is calculated to obtain a final predicted number of leading zeros.

5. The method according to claim 1, characterized in that The step of performing a far path shift and a mantissa addition operation on two low-precision denormalized operands to obtain a far path operation result includes: Perform full-bit-width shift on two low-precision denormalized operands; The mantissa addition operation is performed on the two low-precision denormalized operands after the shift to obtain the far path operation result.

6. A floating-point addition implementation device based on the mixed-precision floating-point addition implementation method according to any one of claims 1 to 5, characterized in that: The device comprises: A preprocessing unit, used for improving a near path condition, lightly preprocessing two low-precision operands of a floating-point addition operation, and determining whether the improved near path condition is satisfied; A near-path processing unit is used to perform leading zero prediction and mantissa addition operations on two low-precision non-normalized operands in parallel if the improved near-path condition is met, and to perform normalized full-bit-width shifting on the mantissa operation result according to the predicted leading zero number to obtain a near-path operation result, wherein the leading zero number includes the leading zero number and the non-normalized leading zero number that appear due to the high-bit offset of the mantissa of the floating-point addition; A far path processing unit is used for performing far path shift and mantissa addition operations on two low-precision denormalized operands to obtain a far path operation result if the improved near path condition is not satisfied; The result processing unit is used to control the selection of one of the far path operation result and the near path operation result as the operation result, and perform mantissa rounding and 1-bit normalization shift on the operation result to obtain a high-precision floating-point addition operation result.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the method according to any one of claims 1 to 5 is implemented.

8. A computer storage medium, characterized in that: The storage medium stores at least one executable instruction, and the executable instruction enables the processor to execute the method as described in any one of claims 1-5.

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