Compilation optimization method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a compiling optimization method and device, electronic equipment and a readable storage medium, and the method comprises the steps: in a compiling process, if a target branch instruction is recognized, distributing a first predicate register for the target branch instruction; the first predicate register is different from a second predicate register used before entering the target branch instruction; generating a first instruction in a first basic block, wherein the first instruction is used for storing an execution mask corresponding to a first branch task of the target branch instruction into the first predicate register; and generating a second instruction in a second basic block, wherein the second instruction is used for storing an execution mask corresponding to a second branch task of the target branch instruction into the first predicate register. According to the embodiment of the invention, the instructions generated by storing and recovering the predicate register in the compiling process can be reduced, so that the program running efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a compilation optimization method, device, electronic device and readable storage medium. Background Art

[0002] SIMT (Single Instruction Multiple Thread) is a parallel computing mode mainly used in graphics processing units (GPUs) and some special accelerators. SIMT is based on threads, each thread independently executes the same instructions but may process different data to achieve parallel computing of large-scale data, especially in fields such as deep learning.

[0003] A predicate register is a special type of processor register that stores Boolean values ​​to control conditional execution in program flow. In the GPU, when a SIMT branch instruction is executed, a predicate register can be used to control the execution of the thread group to ensure that only threads that meet specific conditions execute the corresponding operation.

[0004] However, when executing a SIMT branch instruction, the data in the current predicate register needs to be saved to a general register first, and then the result generated by the branch condition is saved in the predicate register. After the branch operation is executed, the data in the previously saved predicate register needs to be restored. Therefore, during the compilation process, multiple instructions need to be generated to save and restore the predicate register, which affects the program running efficiency. Summary of the invention

[0005] In view of the above problems, an embodiment of the present invention is proposed to provide a compilation optimization method that overcomes the above problems or at least partially solves the above problems, which can reduce the instructions generated for saving and restoring predicate registers during the compilation process, thereby improving the program running efficiency.

[0006] Correspondingly, the embodiments of the present invention also provide a compilation optimization device, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0007] In a first aspect, an embodiment of the present invention discloses a compilation optimization method, which is applied to a GPU compiler. The method includes:

[0008] During the compilation process, if a target branch instruction is identified, a first predicate register is allocated to the target branch instruction; the first predicate register is different from a second predicate register used before entering the target branch instruction;

[0009] Generate a first instruction in a first basic block, the first instruction being used to store an execution mask corresponding to a first branch task of the target branch instruction into the first predicate register;

[0010] A second instruction is generated in a second basic block, where the second instruction is used to store an execution mask corresponding to a second branch task of the target branch instruction into the first predicate register.

[0011] In a second aspect, an embodiment of the present invention discloses a compilation optimization device, which is applied to a GPU compiler, and the device includes:

[0012] A register allocation module, configured to allocate a first predicate register to a target branch instruction if a target branch instruction is identified during compilation; the first predicate register is different from a second predicate register used before entering the target branch instruction;

[0013] A first optimization module, configured to generate a first instruction in a first basic block, wherein the first instruction is configured to store an execution mask corresponding to a first branch task of the target branch instruction into the first predicate register;

[0014] The second optimization module is used to generate a second instruction in a second basic block, where the second instruction is used to store the execution mask corresponding to the second branch task of the target branch instruction into the first predicate register.

[0015] In the third aspect, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of any of the compilation optimization methods described above.

[0016] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the compilation optimization method as described in any of the above can be implemented.

[0017] In a fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program, which, when executed by a processor, performs the steps of any of the compilation optimization methods described above.

[0018] The embodiments of the present invention include the following advantages:

[0019] The compilation optimization method of the embodiment of the present invention, during the compilation process of the GPU compiler, for the SIMT branch instruction, reallocates the first predicate register to save the execution mask of different branch tasks, the first predicate register is different from the second predicate register used before entering the target branch instruction, thereby saving the execution mask of different branch tasks will not modify or overwrite the data in the second register, and there is no need to generate instructions for saving and restoring the second register. Through the compilation optimization method of the embodiment of the present invention, the instructions generated for saving and restoring the predicate register during the compilation process can be reduced, thereby improving the program running efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a flowchart of the steps of an embodiment of a compilation optimization method of the present invention;

[0021] Figure 2 It is a structural block diagram of an embodiment of a compilation optimization device of the present invention;

[0022] Figure 3 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0025] Reference Figure 1 , shows a flowchart of a compilation optimization method embodiment of the present invention, the method can be applied to a GPU compiler, the method may include the following steps:

[0026] Step 101: During the compilation process, if a target branch instruction is identified, a first predicate register is allocated to the target branch instruction; the first predicate register is different from a second predicate register used before entering the target branch instruction;

[0027] Step 102: Generate a first instruction in a first basic block, where the first instruction is used to store an execution mask corresponding to a first branch task of the target branch instruction into the first predicate register;

[0028] Step 103: Generate a second instruction in the second basic block, where the second instruction is used to store the execution mask corresponding to the second branch task of the target branch instruction into the first predicate register.

[0029] The compilation optimization method provided by the embodiment of the present invention can be used to optimize the compilation process of a GPU program to reduce the instructions for saving and restoring predicate registers generated during the compilation process, thereby reducing redundant instructions and improving the running efficiency of the program.

[0030] The GPU program can be a user program (i.e., source program) written by a user in a high-level language. The compilation process is to translate the source program written in a high-level language into a target program in a binary language (assembly language or machine language) recognizable by a computer, and the functions of the target program obtained by translation are the same as those of the source program. For example, after compiling the GPU program, a target program that can be processed by the GPU is obtained.

[0031] In the compilation process, the embodiment of the present invention identifies whether the current instruction is a target branch instruction. If the target branch instruction is identified, the compilation result of the target branch instruction is optimized. The current instruction refers to a GPU instruction, and the target branch instruction refers to a SIMT branch instruction. The SIMT branch instruction is a vector instruction, which refers to a branch instruction that can be executed by multiple threads simultaneously.

[0032] The GPU adopts the SIMT computing mode in the programming model, and multiple threads can execute the same instruction at the same time. The multiple threads refer to threads in a thread group or a thread bundle. In a GPU program, multiple threads in a thread group can execute the same target branch instruction. The embodiment of the present invention does not limit the type of target branch instruction. Exemplarily, the target branch instruction can be a conditional branch instruction, such as an "if...else" instruction; the "if...else" instruction consists of a condition and two branch tasks. If the condition is met, the first branch task is executed; if the condition is not met, the second branch task is executed. For another example, the target branch instruction can be a multi-branch structure instruction, such as a "switch...case" instruction; the "switch...case" instruction needs to distinguish multiple conditions (cases), and each condition corresponds to a different branch task. For another example, the target branch instruction can also be a loop instruction, such as a while instruction.

[0033] In the embodiment of the present invention, conditional branch instructions, such as "if...else" instructions, are used as examples for explanation. Compilation optimization methods for other types of target branch instructions are similar and can be referred to each other.

[0034] For example, a source code to be compiled is as follows:

[0035]

[0036] In the above source code, “…” indicates omitted code, and the part after “ / / ” is the description part.

[0037] The target branch instruction in the above source code is an "if...else" instruction. Among them, tid represents the thread ID. Assume that a thread group includes 10 threads, and the corresponding thread IDs are tid0 to tid9. a[tid] represents an array with tid as the index. "a[tid]>0" is the condition of the target branch instruction. When the condition is met, the code of the if branch is executed; when the condition is not met, the code of the else branch is executed.

[0038] Assuming that a[tid0]~a[tid4] are all less than 0, and a[tid5]~a[tid9] are all greater than 0, then the five threads a[tid5]~a[tid9] meet the condition "a[tid]>0" and execute the code of the if branch; the five threads tid0~tid4 do not meet the condition "a[tid]>0" and execute the code of the else branch. In the embodiment of the present invention, the code of the else branch is called the first branch task, and the code of the if branch is called the second branch task.

[0039] Without using the compilation optimization method of the present invention, the compilation result of the above source code is as follows:

[0040] BB0_0:

[0041] ;using p0

[0042] cmp.lt s0,a0,1 / / Save the comparison result of "a[tid]<1" to s0

[0043] mov s1,p0 / / Save the data in p0 to s1

[0044] and p0,p0,s0 / / Calculate the execution mask of the else branch and save it to p0

[0045] xor s0,s1,s0 / / Save the execution mask of the if branch to s0

[0046] ;SIMT BR BB0_2

[0047] BB0_1:

[0048] ;using p0

[0049] … / / Omit the code for the else branch, which uses p0 as the execution mask

[0050] BB0_2:

[0051] or p0,p0,s0 / / else branch code is executed, restore the original p0 according to s0

[0052] mov s1,p0 / / Save the data in p0 to s1

[0053] and p0,p0,s0 / / Calculate the execution mask of the if branch and save it to p0

[0054] xor s0,s1,s0 / / Save the opposite result of p0 to s0, which will be used to restore p0 later

[0055] ;SIMT BR BB0_4

[0056] BB0_3:

[0057] ;using p0

[0058] … / / Omit the code for the if branch, which uses p0 as the execution mask

[0059] BB0_4:

[0060] ;using p0

[0061] or p0,p0,s0 / / The if branch and the else branch are executed, and the original p0 is restored according to s0

[0062] exit

[0063] The part after “;” is the code comment part. For example, “;using p0” means the predicate register currently used is p0.

[0064] In the case where the compilation optimization method of the present invention is not used, the compilation result of the above source code includes five basic blocks BB0_0 to BB0_4. p0 is a predicate register, and s0 and s1 are general registers.

[0065] The predicate register can have a width of N bits, where N represents the number of threads. Each bit can store a true(1) or false(0) value. Each bit corresponds to the execution mask of a thread, where 1 means execution and 0 means no execution.

[0066] For example, for a certain instruction, p0 is used as the predicate register. If the execution mask stored in p0 is 0000011111, corresponding to 10 threads, it means that the 1st to 5th (such as tid0~tid4) threads do not execute the instruction, and the 6th to 10th (such as tid5~tid9) threads execute the instruction.

[0067] In the case where the compilation optimization method of the present invention is not used, when compiling to the target branch instruction "if...else" instruction, it is necessary to save the data in the second predicate register (p0) used before entering the target branch instruction, and it is necessary to save the general registers with conditions of "true" (if branch) or "false" (else branch) respectively, and when executing the corresponding branch task, it is necessary to copy the corresponding register data to the predicate register, and restore the data in the second predicate register (p0) used before entering the target branch instruction after the branch task is executed. In this way, after exiting the target branch instruction, the data in the second predicate register (p0) can be made consistent with that before entering the target branch instruction.

[0068] It should be noted that the second predicate register (such as p0 in this example) refers to the default predicate register used by the program before entering the target branch instruction ("if...else"). In the case where the compilation optimization method of the present invention is not used, after entering the target branch instruction, the second predicate register (p0) is still needed to save the execution mask of different branch tasks.

[0069] In this example, the condition "a[tid]>0" of the "if...else" instruction is compiled into the instruction "cmp.lt s0,a0,1", that is, the compilation of "a[tid]>0" is optimized to "a[tid]<1", and the result of "a[tid]<1" is opposite to the result of "a[tid]>0". Therefore, for the "if...else" instruction, the else branch is executed first during the specific execution. Therefore, the execution mask of the else branch task (the first branch task) needs to be calculated in the basic block BB0_0. Specifically, the first instruction "cmp.lt s0,a0,1" in BB0_0 is used to save the conditional comparison result of the "if...else" instruction in the general register s0. BB0_0 also uses three instructions (the 2nd to the 4th) to perform the following operations: save the data in the current p0, that is, the data in p0 before entering the target branch instruction (called saving the original p0); calculate the execution mask of the else branch and save it to p0; and save the execution mask of the if branch to s0.

[0070] The basic block BB0_1 contains the code of the else branch. At this time, p0 stores the execution mask of the else branch, such as 1111100000, which means that the threads of tid0 to tid4 execute the code of the else branch, and the threads of tid5 to tid9 do not execute the code of the else branch.

[0071] After basic block BB0_1 (else branch) ends, it enters basic block BB0_2. Four instructions are used in basic block BB0_2 to perform the following operations: first restore the original p0 according to s0; then save the data in p0 to s1; calculate the execution mask of the if branch and save it to p0; finally save the result opposite to the data in p0 to s0 for later restoration of p0.

[0072] The basic block BB0_3 contains the code of the if branch. At this time, p0 stores the execution mask of the if branch, such as 0000011111, which means that the threads of tid0 to tid4 do not execute the code of the if branch, and the threads of tid5 to tid9 execute the code of the if branch.

[0073] Basic block BB0_4 is used to restore the original p0 and exit the "if...else" instruction after the if branch and the else branch end.

[0074] It can be seen that when the compilation optimization method of the present invention is not used, to compile the target branch instruction (such as "if...else"), three instructions are needed in BB0_0 to save the original p0 and calculate the execution mask of the else branch and save it to p0. In BB0_2, four instructions are needed to restore the original p0, save the original p0, and calculate the execution mask of the if branch and save it to p0. In BB0_4, one instruction is needed to restore the original p0. A large number of instructions are generated for saving and restoring the predicate register (p0), which will affect the program running efficiency.

[0075] The embodiment of the present invention optimizes the above compilation process to reduce the instructions for saving and restoring the predicate registers generated during the compilation process.

[0076] Specifically, during the compilation process, when the target branch instruction is identified, such as when the assembly code of the "if...else" instruction is identified, the embodiment of the present invention allocates the first predicate register. Taking the above example as an example, assuming that before entering the "if...else" instruction, the predicate register (that is, the second register) used by the program is p0, the embodiment of the present invention allocates a new predicate register (that is, the first predicate register) as p1. In this way, the first predicate register (such as p1) can be used to save the execution mask of different branch tasks without modifying or overwriting the data in the default predicate register (that is, the second register) used by the program.

[0077] A first instruction is generated in a first basic block, the first instruction being used to store an execution mask corresponding to a first branch task of the target branch instruction into the first predicate register; and a second instruction is generated in a second basic block, the second instruction being used to store an execution mask corresponding to a second branch task of the target branch instruction into the first predicate register.

[0078] The first basic block is used to calculate the execution mask of the else branch (first branch task) and save it to the first predicate register (p1). In the above example, the first basic block corresponds to the basic block BB0_0. The first branch task and the second branch task refer to the branch tasks corresponding to the target branch instruction when different conditions are met. In the above example, the first branch task is the else branch and the second branch task is the if branch.

[0079] Since p1 is a new predicate register different from p0, using p1 to save the execution mask of the else branch (the first branch task) will not overwrite the data in p0, so there is no need to perform the operation of saving p0. In the first basic block, only one instruction (called the first instruction) is needed to complete the operation of storing the execution mask corresponding to the first branch task into the first predicate register.

[0080] In an optional embodiment of the present invention, the first instruction is used to execute a first operation; the first operation performs an AND operation on the condition of the first branch task and the data in the second predicate register, and stores the result of the AND operation in the first predicate register.

[0081] For the above example, using the compilation optimization method of the present invention, the first basic block BB1_0 compiled can be as follows:

[0082] BB1_0:

[0083] cmp.lt s0,a0,1

[0084] and p1,p0,s0 / / Calculate the execution mask of the else branch and save it to p1

[0085] The first instruction is "and p1, p0, s0", which performs an AND operation on the condition (s0) of the first branch task and the data in the second predicate register (p0), and stores the result of the AND operation in the first predicate register (p1). Thus, the execution mask of the first branch task is calculated and saved in the first predicate register.

[0086] It should be noted that, for the sake of convenience, basic blocks compiled without using the compilation optimization method of the present invention are represented by BB0_0 to BB0_4, and basic blocks compiled using the compilation optimization method of the present invention are represented by BB1_0 to BB1_4.

[0087] It can be seen that, when the compilation optimization method of the present invention is not used, three instructions (the second to the fourth) are required in the compiled first basic block BB0_0 to save the original p0 and calculate the execution mask of the first branch task and save it to p0. When the compilation optimization method of the present invention is used, only one instruction is required in the compiled first basic block BB1_0. For the first basic block, the embodiment of the present invention can reduce two instructions.

[0088] The second basic block is used to calculate the execution mask of the if branch (the second branch task) and save it to the first predicate register (p1). In the above example, the second basic block corresponds to the basic block BB0_2.

[0089] Since p1 is a new predicate register different from p0, p1 can be used to save the execution mask of the if branch (the second branch task) after the else branch (the second branch task) ends, and the data in p0 will not be overwritten, so there is no need to perform the operation of saving p0. In the second basic block, only one instruction (called the second instruction) is needed to complete the operation of storing the execution mask corresponding to the second branch task into the first predicate register.

[0090] In an optional embodiment of the present invention, the second instruction is used to execute a second operation; the second operation performs an XOR operation on the condition of the first branch task and the data in the second predicate register, and stores the result of the XOR operation in the first predicate register.

[0091] For the above example, using the compilation optimization method of the present invention, the compiled second basic block BB1_2 can be as follows:

[0092] BB1_2:

[0093] xor p1,p0,s0 / / Calculate the execution mask of the if branch and save it to p1

[0094] The second instruction is "xor p1, p0, s0", which performs an exclusive OR operation on the condition (s0) of the first branch task and the data in the second predicate register (p0), and stores the result of the exclusive OR operation in the first predicate register (p1). Thus, the execution mask of the second branch task is calculated and saved in the first predicate register.

[0095] It can be seen that, without using the compilation optimization method of the present invention, four instructions are required in the compiled second basic block BB0_2 to restore the original p0, save the original p0, and calculate the execution mask of the second branch task according to the original p0 and save it to p0, etc. When using the compilation optimization method of the present invention, only one instruction is required in the compiled second basic block BB1_2. For the second basic block, the embodiment of the present invention can reduce three instructions.

[0096] For the above example, the compilation result obtained by using the compilation optimization method of the present invention may be as follows:

[0097] BB1_0:

[0098] ;using p0

[0099] cmp.lt s0,a0,1

[0100] and p1,p0,s0 / / Calculate the execution mask of the else branch and save it to p1

[0101] ;SIMT BR BB0_2

[0102] BB1_1:

[0103] ;using p1

[0104] … / / Omit the code of the else branch, the else branch uses p1 as the execution mask

[0105] BB1_2:

[0106] xor p1,p0,s0 / / Calculate the execution mask of the if branch and save it to p1

[0107] ;SIMT BR BB0_4

[0108] BB1_3:

[0109] ;using p1

[0110] … / / Omit the code for the if branch, which uses p1 as the execution mask

[0111] BB1_4:

[0112] ;using p0

[0113] exit

[0114] Furthermore, for the third basic block, i.e., the basic block for exiting the target branch instruction (such as BB0_4 and BB1_4), when the compilation optimization method of the present invention is not used, it is necessary to use an instruction (such as "orp0, p0, s0" in BB0_4) to restore the original p0, while when the compilation optimization method of the present invention is used, since the second predicate register (p0) has not been modified, it is not necessary to restore it, and BB1_4 can be directly exited. For the third basic block, the embodiment of the present invention can reduce one instruction.

[0115] In the execution phase, the instructions in BB1_0 to BB1_4 are executed in sequence. Compared with BB0_0 to BB0_4, the embodiment of the present invention reduces the instructions to be executed and can improve the program running efficiency.

[0116] In an optional embodiment of the present invention, allocating the first predicate register may include:

[0117] Step S11, query whether there is an idle predicate register;

[0118] Step S12: If there is an idle predicate register, allocate the idle predicate register;

[0119] Step S13: If there is no idle predicate register, determine a target predicate register among all used predicate registers, save the data in the target predicate register into a preset register, and allocate the target predicate register.

[0120] In a specific implementation, the number of allocatable predicate registers may be set. In an example, assuming that the number of allocatable predicate registers is 4, the allocatable predicate registers are denoted as p0 to p3.

[0121] When the target branch instruction is identified, first check whether there is an idle predicate register. If there is an idle predicate register, the idle predicate register is allocated as the first predicate register. For example, if it is found that p1 is idle, the first predicate register can be allocated as p1.

[0122] If there is no free predicate register, the target predicate register is determined from all the used predicate registers. For example, if p0 to p3 are all occupied, the target predicate register is determined from p0 to p3. Assuming that p0 is determined as the target predicate register, the data in p0 is first saved to the preset register, and the first predicate register is assigned to p0. The preset register may be a pre-set vector register.

[0123] Further, determining the target predicate register among all the predicate registers that have been used may include: determining the target predicate register among all the predicate registers that have been used according to the sequence number of the second predicate register and the number of allocatable predicate registers. The second predicate register is the predicate register used before entering the target branch instruction.

[0124] Exemplarily, assuming that all the allocatable predicate registers have been used, the target register may be determined to be p((idx+1)%n), and the data in p((idx+1)%n) may be saved in the preset register, where idx is the serial number of the second predicate register, and n is the number of allocatable predicate registers.

[0125] For example, the allocatable predicate registers include p0-p3. If all of p0-p3 are in use and there is no idle predicate register, and the predicate register used before entering the target branch instruction is p3, that is, idx=3, n=4, then the target register can be determined to be p((3+1)%4)=p0, the data in p0 is saved to the preset register, and the first predicate register is allocated to p0.

[0126] It should be noted that the above basic blocks BB1_0 to BB0_4 are compiled with free predicate registers. If there are no free predicate registers, and assuming that the target predicate register p0 is assigned as the first predicate register, and the second predicate register is p3, the compiled first basic block BB2_0 can be as follows:

[0127] BB2_0:

[0128] ;using p3

[0129] cmp.lt s0,a0,1

[0130] s2v v0,p0,zero / / Determine the target predicate register p0 and save p0 to v0

[0131] and p0,p3,s0 / / Calculate the execution mask of the else branch and save it to p0

[0132] If there is no free predicate register, the first predicate register (i.e., the target predicate register) is allocated from the used predicate registers. Therefore, an instruction for saving the target predicate register needs to be added to the first basic block, such as "s2v v0, p0, zero". This instruction is used to save the data in p0 to the vector register v0. At this time, the first predicate register allocated is the target predicate register p0, and the second predicate register is p3. The operation performed on p0 will not modify the data in p3, and the execution process of step 102 and step 103 can remain unchanged.

[0133] In an optional embodiment of the present invention, the method may further include:

[0134] After all branch tasks of the target branch instruction are completed, determining whether a recovery condition is satisfied; the recovery condition includes: when there are insufficient free predicate registers, a used target predicate register is allocated;

[0135] If the recovery condition is not met, the next instruction is used directly;

[0136] If the recovery condition is met, a copy instruction is generated, where the copy instruction is used to copy the data in the preset register to the target predicate register.

[0137] The embodiment of the present invention determines whether a recovery condition is met when the branch task of the target branch instruction ends; the recovery condition includes: when the idle predicate registers are insufficient, the used target predicate register is allocated. Because when the idle predicate registers are insufficient, a target predicate register will be determined from the used predicate registers for allocation, so it is necessary to first save the data in the target predicate register to the preset register, and then allocate the target predicate register as the first register, and after the branch task of the target branch instruction ends, it is necessary to restore the target register, and then exit the target branch instruction, so that the data in the target predicate register remains correct.

[0138] Specifically, if the recovery condition is met, a copy instruction can be generated in the third basic block to restore the data in the target register, and the compiled third basic block BB2_4 can be as follows:

[0139] BB2_4:

[0140] v2s p0,v0,zero / / Restore the original p0

[0141] ;using p0

[0142] exit

[0143] In the embodiment of the present invention, when the recovery condition is met, a copy instruction, such as “v2s p0, v0, zero”, is added to the third basic block to restore the data in the target predicate register.

[0144] Taking the above example as an example, when a target branch instruction is identified, if it is found that there is no free predicate register, and the used target predicate register is allocated as the first register, the compilation results BB2_0 to BB2_4 of the source code of the above example may be as follows:

[0145] BB2_0:

[0146] ;using p3

[0147] cmp.lt s0,a0,1

[0148] s2v v0,p0,zero / / Determine the target predicate register p0 and save p0 to v0

[0149] and p0,p3,s0 / / Calculate the execution mask of the else branch and save it to p0

[0150] ;SIMT BR BB0_2

[0151] BB2_1:

[0152] ;using p0

[0153] … / / Omit the code for the else branch, which uses p0 as the execution mask

[0154] BB2_2:

[0155] xor p0,p3,s0 / / Calculate the execution mask of the if branch and save it to p0

[0156] ;SIMT BR BB0_4

[0157] BB2_3:

[0158] ;using p0

[0159] … / / Omit the code for the if branch, which uses p0 as the execution mask

[0160] BB2_4:

[0161] v2s p0,v0,zero / / Restore the original p0

[0162] ;using p0

[0163] exit

[0164] It can be seen that in the first basic block BB2_1, a copy instruction such as "s2v v0, p0, zero" is used to save the data in the target predicate register (p0) to the preset register (v0), and then the target predicate register (p0) is used as the allocated first predicate register. After the branch task of the target branch instruction is completed, in the third basic block BB2_4, a copy instruction such as "v2s p0, v0, zero" is used to restore the target predicate register p0 from the preset register v0.

[0165] It can be understood that when the branch task of the target branch instruction ends, if it is identified that the recovery condition is not met, that is, an idle predicate register is allocated as the first predicate register, the next instruction (such as "exit" in BB1_4) can be used directly in sequence without adding other operations, as shown in BB1_4.

[0166] In an optional embodiment of the present invention, the method may further include:

[0167] Each time a free predicate register is allocated, the value of the counter is increased by 1; the value of the counter is initially 0;

[0168] The determining whether the restoration condition is met includes:

[0169] When all branch tasks of the target branch instruction are completed, reading the value of the counter;

[0170] If the value of the counter is greater than the total number of predicate registers, it is determined that the recovery condition is met;

[0171] If the value of the counter is less than or equal to the total number of predicate registers, it is determined that the recovery condition is not satisfied.

[0172] The embodiment of the present invention sets a counter to count the allocated free predicate registers. Initially, the value of the counter is 0, and each time a free predicate register is allocated, the value of the counter is increased by 1. When the branch task of the target branch instruction ends, the value of the counter is read. If the value of the counter is greater than the total number of predicate registers, it means that the free predicate registers are insufficient, and the used target predicate register is allocated as the first predicate register, and the data in the target predicate register is saved in the preset register. At this time (when the branch task ends), the recovery condition is met, and the data in the target predicate register needs to be restored. If the value of the counter is less than or equal to the total number of predicate registers, an idle predicate register is allocated, and it is determined that the recovery condition is not met.

[0173] In the case where there are free predicate registers that can be allocated, the first basic block in the embodiment of the present invention can reduce two instructions, the second basic block can reduce three instructions, and the fourth basic block can reduce one instruction. That is, when compiling a target branch instruction, through the compilation optimization method of the present invention, in the case where there are free predicate registers that can be allocated, 6 instructions can be reduced.

[0174] In the case where there is no free predicate register to allocate, the embodiment of the present invention only needs to add a copy instruction in the first basic block to save the data in the target predicate register, and add a copy instruction in the third basic block to restore the data in the target predicate register. That is, when compiling a target branch instruction, through the compilation optimization method of the present invention, 4 instructions can be reduced in the case where there is no free predicate register to allocate.

[0175] Compared with the compilation optimization method not using the present invention, the embodiment of the present invention can reduce the number of instructions generated by saving and restoring predicate registers, and can improve program running efficiency.

[0176] Furthermore, the embodiment of the present invention can release the used first predicate register after the branch task of the target branch instruction is completed. For example, for basic block BB1_4, the first predicate register p1 can be released after exiting the target branch instruction, and the released first predicate register becomes an idle predicate register. Each time a first predicate register is released, the value of the counter can be reduced by 1.

[0177] In summary, during the compilation process of the GPU compiler, the compilation optimization method of the embodiment of the present invention reallocates the first predicate register to save the execution mask of different branch tasks for the SIMT branch instruction, and the first predicate register is different from the second predicate register used before entering the target branch instruction. Therefore, saving the execution mask of different branch tasks will not modify or overwrite the data in the second register, and there is no need to generate instructions for saving and restoring the second register. Through the compilation optimization method of the embodiment of the present invention, the instructions generated for saving and restoring the predicate register during the compilation process can be reduced, thereby improving the program running efficiency.

[0178] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0179] Reference Figure 2 , shows a structural block diagram of an embodiment of a compilation optimization device of the present invention, the device is applied to a GPU compiler, and the device may include:

[0180] The register allocation module 201 is used to allocate a first predicate register to a target branch instruction if a target branch instruction is identified during the compilation process; the first predicate register is different from a second predicate register used before entering the target branch instruction;

[0181] A first optimization module 202, configured to generate a first instruction in a first basic block, wherein the first instruction is configured to store an execution mask corresponding to a first branch task of the target branch instruction into the first predicate register;

[0182] The second optimization module 203 is used to generate a second instruction in a second basic block, where the second instruction is used to store the execution mask corresponding to the second branch task of the target branch instruction into the first predicate register.

[0183] Optionally, the register allocation module includes:

[0184] A query submodule, used to query whether there are free predicate registers;

[0185] A first allocation submodule, configured to allocate an idle predicate register if there is an idle predicate register;

[0186] The second allocation submodule is used to determine a target predicate register from all used predicate registers if there is no idle predicate register, save the data in the target predicate register into a preset register, and allocate the target predicate register.

[0187] Optionally, the device further comprises:

[0188] A conditional judgment module, used to judge whether a recovery condition is met when all branch tasks of the target branch instruction are completed; the recovery condition includes: when there are insufficient free predicate registers, a used target predicate register is allocated;

[0189] The third optimization module is used to directly use the next instruction if the recovery condition is not met;

[0190] The data recovery module is used to generate a copy instruction if the recovery condition is met, wherein the copy instruction is used to copy the data in the preset register to the target predicate register.

[0191] Optionally, the device further comprises:

[0192] An allocation counting module is used to increase the value of a counter by 1 each time an idle predicate register is allocated; the value of the counter is initially 0;

[0193] The condition judgment module is specifically used for:

[0194] When all branch tasks of the target branch instruction are completed, the value of the counter is read; if the value of the counter is greater than the total number of predicate registers, it is determined that the recovery condition is met; if the value of the counter is less than or equal to the total number of predicate registers, it is determined that the recovery condition is not met.

[0195] Optionally, the first instruction is used to execute a first operation; the first operation performs an AND operation on the condition of the first branch task and the data in the second predicate register, and stores the result of the AND operation in the first predicate register.

[0196] Optionally, the second instruction is used to execute a second operation; the second operation performs an XOR operation on the condition of the first branch task and the data in the second predicate register, and stores the result of the XOR operation in the first predicate register.

[0197] The compilation optimization device of the embodiment of the present invention can be applied to a GPU compiler. In the process of the GPU compiler compiling a GPU program, for a SIMT branch instruction, the first predicate register is reallocated to save the execution mask of different branch tasks. The first predicate register is different from the second predicate register used before entering the target branch instruction. Therefore, saving the execution mask of different branch tasks will not modify or overwrite the data in the second register, and there is no need to generate instructions for saving and restoring the second register. Through the compilation optimization device of the embodiment of the present invention, the instructions generated for saving and restoring the predicate register during the compilation process can be reduced, thereby improving the program running efficiency.

[0198] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0199] Reference Figure 3 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 3 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the compilation optimization method of the aforementioned embodiment.

[0200] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or a processor of a terminal, the terminal is enabled to perform the steps of the compilation optimization method of the aforementioned embodiment.

[0201] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0202] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0203] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0204] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0205] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0206] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0207] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A compilation optimization method, characterized in that: Applied to a GPU compiler, the method comprises: During the compilation process, if a target branch instruction is identified, a first predicate register is allocated to the target branch instruction; the first predicate register is different from a second predicate register used before entering the target branch instruction; Generate a first instruction in a first basic block, the first instruction being used to store an execution mask corresponding to a first branch task of the target branch instruction into the first predicate register; A second instruction is generated in a second basic block, where the second instruction is used to store an execution mask corresponding to a second branch task of the target branch instruction into the first predicate register.

2. The method according to claim 1, characterized in that: The allocating a first predicate register comprises: Check whether there are free predicate registers; If there is a free predicate register, allocate the free predicate register; If there is no free predicate register, a target predicate register is determined among all the used predicate registers, data in the target predicate register is saved in a preset register, and the target predicate register is allocated.

3. The method according to claim 2, characterized in that The method further comprises: After all branch tasks of the target branch instruction are completed, determining whether a recovery condition is satisfied; the recovery condition includes: when there are insufficient free predicate registers, a used target predicate register is allocated; If the recovery condition is not met, the next instruction is used directly; If the recovery condition is met, a copy instruction is generated, where the copy instruction is used to copy the data in the preset register to the target predicate register.

4. The method according to claim 3, characterized in that: The method further comprises: Each time a free predicate register is allocated, the value of the counter is increased by 1; the value of the counter is initially 0; The determining whether the restoration condition is met includes: When all branch tasks of the target branch instruction are completed, reading the value of the counter; If the value of the counter is greater than the total number of predicate registers, it is determined that the recovery condition is met; If the value of the counter is less than or equal to the total number of predicate registers, it is determined that the recovery condition is not satisfied.

5. The method according to claim 1, characterized in that The first instruction is used to execute a first operation; the first operation performs an AND operation on the condition of the first branch task and the data in the second predicate register, and stores the result of the AND operation in the first predicate register.

6. The method according to claim 1, characterized in that The second instruction is used to execute a second operation; the second operation performs an exclusive OR operation on the condition of the first branch task and the data in the second predicate register, and stores the result of the exclusive OR operation in the first predicate register.

7. A compilation optimization device, characterized in that: Applied to a GPU compiler, the device comprises: A register allocation module, configured to allocate a first predicate register to a target branch instruction if a target branch instruction is identified during compilation; the first predicate register is different from a second predicate register used before entering the target branch instruction; A first optimization module, configured to generate a first instruction in a first basic block, wherein the first instruction is configured to store an execution mask corresponding to a first branch task of the target branch instruction into the first predicate register; The second optimization module is used to generate a second instruction in a second basic block, where the second instruction is used to store the execution mask corresponding to the second branch task of the target branch instruction into the first predicate register.

8. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the compilation optimization method according to any one of claims 1 to 6.

9. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the compilation optimization method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that The computer program executed by the processor is the steps of the compilation optimization method according to any one of claims 1 to 6.

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