Code processing method and device and electronic equipment

Abstract

The invention provides a code processing method and device and electronic equipment, relates to the technical field of computers, and is used for reducing operation and maintenance pressure while reducing CPU (Central Processing Unit) front-end dependence. The code processing method comprises the steps of obtaining identification information of a first code block currently executed in a target code; according to the identification information of the first code block, identification information of a second code block executed after the first code block is obtained in calling information of the target code, and the calling information comprises identification information of a plurality of code blocks in the target code and an execution sequence; and storing the second code block in a cache according to the identification information of the second code block.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a code processing method, device and electronic device. Background Art

[0002] As the development of central processing units (CPUs) slows down, the importance of hardware-software co-optimization becomes increasingly prominent. Currently, a large number of applications are prone to CPU frontend bound due to too many branches or too large binary size. CPU frontend bound means that the CPU fetches instructions slowly or the CPU takes a long time to translate complex instructions, which reduces the performance of the application. Therefore, how to reduce CPU frontend bound and improve application performance has become an urgent problem to be solved.

[0003] In the prior art, a binary optimization and layout tool (BOLT) is used to rearrange the basic blocks in an application program to reduce CPU front-end dependency and improve the performance of the application program. Specifically, each time the CPU executes an application program, BOLT rearranges the basic blocks in the order of the frequency of use of the basic blocks in the application program from high to low, and stores the rearranged basic blocks in a continuous memory to update the binary file; when the CPU executes again and obtains instructions in the memory according to the cache line size, most of the blocks obtained are hot blocks, which improves the efficiency of obtaining instructions and shortens the time it takes for the CPU to obtain instructions, thereby improving the performance of the application program.

[0004] However, each time the CPU runs an application, the basic blocks need to be rearranged and the binary files need to be updated, increasing the pressure on operation and maintenance. Summary of the invention

[0005] The present application provides a code processing method, device and electronic device for reducing CPU front-end dependence while reducing operation and maintenance pressure.

[0006] In order to achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, a binary code processing method is provided, the method comprising: obtaining identification information of a first code block currently being executed in a target code; obtaining identification information of a second code block executed after the first code block in calling information of the target code based on the identification information of the first code block; the calling information comprising identification information and an execution order of multiple code blocks in the target code; and storing the second code block in a cache according to the identification information of the second code block.

[0008] In the technical solution provided by the present application, according to the identification information of the first code block currently being executed, the identification information of the second code block executed after the first code block is obtained in the call information of the target code, and the second code block is stored in the cache. When the CPU executes the first code block, the second code block executed after the first code block is stored in the cache in advance. When the second code block is executed, the second code block can be directly obtained from the cache without having to obtain the second code block from the memory. Since the speed of obtaining instructions in the cache is faster than the speed of obtaining instructions in the memory, the speed of obtaining the second code block is improved, thereby reducing the CPU front-end dependence and improving the performance of the application; and no new code files are generated in this process. Compared with the continuous updating of code files in the prior art, memory and time are saved, operation and maintenance pressure is reduced, and the performance of the application is further improved.

[0009] In a possible implementation of the first aspect, the second code block is a code block in a next hop group of the group where the first code block is located. In the above possible implementation, the code blocks in the next hop group of the group where the first code block is located are stored in the cache in advance, and since the speed of acquiring instructions in the cache is faster than the speed of acquiring instructions in the memory, the speed of acquiring code blocks is improved.

[0010] In a possible implementation of the first aspect, the first code block is a code block in a first group of the target code, and the second code block includes the remaining code blocks in the first group and the code blocks in the next hop group of the group where the first code block is located. In the above possible implementation, the remaining code blocks in the first group and the code blocks in the next hop group of the group where the first code block is located are stored in the cache in advance, and since the speed of obtaining instructions in the cache is faster than the speed of obtaining instructions in the memory, the speed of obtaining code blocks is improved.

[0011] In a possible implementation of the first aspect, the method further includes: determining the call information according to the execution order of the code blocks included in the target code under multiple different business paths. In the above possible implementation, the call information is determined according to the execution order under multiple different business paths, which improves the accuracy of the call information.

[0012] In a possible implementation of the first aspect, the call information is determined according to the execution order of the code blocks included in the target code under multiple different business paths, including: according to the execution order, the block information of the code blocks in the target code is determined respectively, and the block information includes the identification information of the code blocks and the identification information of the next hop block; according to the block information, the code blocks that meet the conditions are taken as a group to obtain multiple code block groups; wherein the condition is used to indicate that they belong to the same business path and are called continuously; the call information is generated, and the call information includes the group information of each code block group in the multiple code block groups, and the group information includes the group identification information, the identification information of the next hop group, and the identification information of the code blocks in the code block group. In the above possible implementation, the call information includes the group information of each code block group in the multiple code block groups, and the group information includes the group identification information, the identification information of the next hop group, and the identification information of the code blocks in the code block group, which improves the efficiency of obtaining the identification information of the second code block.

[0013] In a possible implementation of the first aspect, the group information also includes a group call count, and the method further includes: deleting group information of code block groups whose group call counts in the call information are less than a first threshold. In the above possible implementation, the utilization rate of the call information is improved.

[0014] In a possible implementation of the first aspect, the second code block is a next-hop block of the first code block. In the above possible implementation, the next-hop block of the first code block is stored in a cache in advance, and when the next-hop block of the first code block is executed, it is directly obtained from the cache. Since the speed of obtaining instructions in the cache is faster than the speed of obtaining instructions in the memory, the speed of obtaining the code block is improved.

[0015] In a possible implementation of the first aspect, the respectively determining the block information of the code blocks in the target code includes: respectively determining the block information of the hot blocks in the target code, the hot blocks being code blocks in the target code whose number of calls is greater than a second threshold. In the above possible implementation, determining the block information of the hot blocks in the target code improves the utilization rate of the block information.

[0016] In a possible implementation of the first aspect, the size of the code block is an integer multiple of the cache line size of the cache. In the above possible implementation, the selectivity of dividing the target code is increased.

[0017] In a possible implementation of the first aspect, the target code includes a binary code segment. In the above possible implementation, the selectivity of the target code is increased.

[0018] In a possible implementation of the first aspect, storing the second code block in a cache according to the identification information of the second code block includes: reading the second code block that is not stored in the cache from a memory corresponding to the cache according to the identification information of the second code block. In the above possible implementation, reading the second code block that is not stored in the cache ensures that all second code blocks are stored in the cache, and when executing the second code block, the speed of obtaining the second code block is improved.

[0019] In a possible implementation of the first aspect, the second code block not stored in the cache is read from the memory corresponding to the cache according to the identification information of the second code block, including: determining the target address of the second code block not stored in the cache according to the identification information of the second code block; reading the target code block in the memory according to the target address; and storing the read target code block in the cache. In the above possible implementation, the second code block not stored in the cache is read to ensure that the second code block is stored in the cache, and when the second code block is executed, the speed of obtaining the second code block is improved.

[0020] In a second aspect, a code processing device is provided, the device comprising: an acquisition unit, used to acquire identification information of a first code block currently executed in a target code; the acquisition unit, further used to acquire identification information of a second code block executed after the first code block in calling information of the target code based on the identification information of the first code block, the calling information comprising identification information and an execution order of multiple code blocks in the target code; a storage unit, used to store the second code block in a cache according to the identification information of the second code block.

[0021] In a possible implementation manner of the second aspect, the second code block is a code block in a next hop group of the group where the first code block is located.

[0022] In a possible implementation manner of the second aspect, the first code block is a code block in a first group of the target code, and the second code block includes the remaining code blocks in the first group and a code block in a next hop group of the group where the first code block is located.

[0023] In a possible implementation manner of the second aspect, the device further includes: a determination unit, configured to determine the call information according to an execution order of code blocks included in the target code under a plurality of different service paths.

[0024] In a possible implementation manner of the second aspect, the determination unit is specifically used to: determine, according to the execution order, block information of the code blocks in the target code respectively, the block information including identification information of the code blocks and identification information of the next hop block; according to the block information, group the code blocks that meet the conditions as a group to obtain multiple code block groups; wherein the condition is used to indicate that they belong to the same service path and are called continuously; generate the call information, the call information including group information of each code block group in the multiple code block groups, the group information including group identification information, identification information of the next hop group, and identification information of the code blocks in the code block group.

[0025] In a possible implementation manner of the second aspect, the group information further includes a number of group calls, and the apparatus further includes: a deleting unit, configured to delete group information of code block groups whose number of group calls in the calling information is less than a first threshold.

[0026] In a possible implementation manner of the second aspect, the second code block is a next hop block of the first code block.

[0027] In a possible implementation manner of the second aspect, the determination unit is further used to: respectively determine the block information of the hot block in the target code, where the hot block is a code block in the target code whose number of calls is greater than a second threshold.

[0028] In a possible implementation manner of the second aspect, the size of the code block is an integer multiple of a cache line size of the cache.

[0029] In a possible implementation manner of the second aspect, the target code includes a binary code segment.

[0030] In a possible implementation manner of the second aspect, the device further includes: a reading unit, configured to read the second code block that is not stored in the cache from a memory corresponding to the cache according to identification information of the second code block.

[0031] In a possible implementation manner of the second aspect, the reading unit is specifically used to: determine a target address of the second code block not stored in the cache according to the identification information of the second code block and the initial address of the target code; read the target code block in the memory according to the target address; and store the read target code block in the cache.

[0032] According to a third aspect, an electronic device is provided, comprising a processor and a memory, wherein the memory is used to store instructions, and the processor is used to execute a code processing method provided in the first aspect or any possible implementation of the first aspect.

[0033] In a fourth aspect, a chip is provided, comprising a processor and a memory, wherein the memory is used to store instructions, and the processor is used to execute the code processing method provided in the first aspect or any possible implementation of the first aspect.

[0034] In another aspect of the present application, a computer-readable storage medium is provided, which includes computer instructions. When the computer instructions are executed on a code processing device, the code processing device executes the binary code processing method provided by the first aspect or any possible implementation of the first aspect.

[0035] In another aspect of the present application, a computer program product comprising instructions is provided. When the computer program product is run on a computer device, the computer device executes the binary code processing method provided by the first aspect or any possible implementation of the first aspect.

[0036] It can be understood that the code processing device, electronic device, chip, computer-readable storage medium and computer program product provided above can be used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A schematic diagram of a basic block arrangement;

[0038] Figure 2 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0039] Figure 3 A schematic diagram of the structure of another electronic device provided in an embodiment of the present application;

[0040] Figure 4 A flowchart of a code processing method provided in an embodiment of the present application;

[0041] Figure 5 A flowchart of another code processing method provided in an embodiment of the present application;

[0042] Figure 6 A flowchart of a method for determining call information provided in an embodiment of the present application;

[0043] Figure 7 A schematic diagram of block information provided in an embodiment of the present application;

[0044] Figure 8 A schematic diagram of a call information provided in an embodiment of the present application;

[0045] Fig. 9 A schematic diagram of the structure of a code processing device provided in an embodiment of the present application;

[0046] Fig.10 A schematic diagram of the structure of another code processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] In this application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated with each other are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple. In addition, the embodiments of the present application use words such as "first" and "second" to distinguish between the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only to distinguish different thresholds, and do not limit their order. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order.

[0048] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0049] Before introducing the embodiments of the present application, the technical terms involved in the embodiments of the present application are first introduced and explained.

[0050] Central processing unit (CPU) front-end dependency: refers to the slow speed at which the CPU obtains instructions or the long translation process of the CPU for complex instructions.

[0051] Instruction cache (iCache): used to store machine instructions that need to be executed in the CPU.

[0052] Cache line: The unit of data storage in the CPU. Usually the size of a cache line is 64 kilobytes (KB).

[0053] Binary code: refers to the code that can be directly executed by the CPU after the source code is compiled. Binary files are files used to store binary code. After disassembling a binary file, multiple binary functions will be generated. Binary functions usually consist of several basic blocks (BB). Several basic blocks BB can complete the function under the control of the control flow graph (CFG).

[0054] Before introducing the embodiments of the present application, the relevant knowledge that the CPU front end depends on is first introduced and explained.

[0055] At present, with the slowdown of CPU development, the importance of hardware and software co-optimization has become increasingly prominent. At present, a large number of applications are prone to CPU front-end dependence due to too many branches or too large binary size, which reduces the performance of the application. Therefore, how to reduce CPU front-end dependence and improve application performance has become an urgent problem to be solved.

[0056] Usually, the binary optimization and layout tool (BOLT) is used to rearrange the basic blocks in the application to reduce the CPU front-end dependency and improve the performance of the application. Specifically, assume that the application includes a binary function A, which includes 6 basic blocks (BB) and can be represented as BB1 to BB6, such as Figure 1 As shown, Figure 1 Take the binary function A including basic blocks BB1 to BB6 as an example, Figure 1 (a) in the figure shows the arrangement of basic blocks BB1 to BB6 in memory before BOLT is used. Each time the CPU runs binary function A, BOLT records the usage frequency of basic blocks BB1 to BB6, and marks basic blocks with a usage frequency greater than or equal to a first threshold as hot blocks (taking BB1, BB4 and BB5 as hot blocks as an example), and marks basic blocks with a usage frequency less than the first threshold as cold blocks (taking BB2, BB3 and BB6 as cold blocks as an example). BOLT rearranges basic blocks BB1 to BB6 in descending order of usage frequency, and stores the rearranged basic blocks in continuous memory. Figure 1As shown in (b) in the figure, the binary file is updated. When the CPU runs binary function A again and fetches instructions from the memory according to the cache line size, most of the instructions fetched are hot blocks with high usage frequency, which improves the efficiency of fetching instructions and shortens the time it takes for the CPU to fetch instructions, thereby improving the performance of the application.

[0057] However, each time the CPU runs a function, the basic blocks need to be rearranged and the binary files need to be updated, increasing the pressure on operation and maintenance.

[0058] Based on this, the present application provides a code processing method, device and electronic device, the code processing method comprising: according to the identification information of the currently executed first code block, in the call information of the target code, obtaining the identification information of the second code block executed after the first code block, and storing the second code block in the cache. When the CPU executes the first code block, the second code block executed after the first code block is stored in the cache in advance. When the CPU executes the second code block, the second code block can be directly obtained in the cache to increase the speed of the CPU to obtain the second code block, thereby reducing the CPU front-end dependence and improving the performance of the application; and no new code files are generated in this process. Compared with the prior art of constantly updating the code files in the memory, it saves memory and time, reduces the pressure of operation and maintenance, and further improves the performance of the application.

[0059] It should be noted that the code processing method provided in this embodiment can be applied to electronic devices. The electronic devices may include terminal devices. The terminal devices may include but are not limited to personal computers, server computers, mobile devices (such as mobile phones, tablet computers, media players, etc.), wearable devices, vehicle-mounted devices, consumer terminal devices, mobile robots, and drones, etc.

[0060] Combine the following Figure 2 The structure of the electronic device is introduced and described. For example, Figure 2 The electronic device 20 may include a processor 210, a bus 220, a memory 230, and a communication interface 240. The processor 210, the memory 230, and the communication interface 240 are connected via the bus 220.

[0061] It should be understood that in this embodiment, the processor 210 may be a CPU, and the processor 210 may also be other general-purpose processors, digital signal processing (DSP), (application-specific integrated circuit, ASIC), field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0062] The processor 210 may also be a graphics processing unit (GPU), a neural network processing unit (NPU), a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the program of the present application.

[0063] The communication interface 240 is used to implement communication between the electronic device 20 and an external device or component.

[0064] The bus 220 may include a path for transmitting information between the above components (such as the processor 210 and the memory 230). In addition to the data bus, the bus 220 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are labeled as bus 220 in the figure. The bus 220 may be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 220 can be divided into an address bus, a data bus, a control bus, etc.

[0065] As an example, the electronic device 20 may include multiple processors. The processor may be a multi-core (multi-CPU) processor. The processor here may refer to one or more devices, circuits, and / or computing units for processing data (such as computer program instructions).

[0066] It is worth mentioning that Figure 2In the example, an electronic device 20 including a processor 210 and a memory 230 is taken as an example. Here, the processor 210 and the memory 230 are respectively used to indicate a type of device or equipment. In a specific embodiment, the number of each type of device or equipment can be determined according to business requirements.

[0067] The memory 230 may be a volatile memory pool or a non-volatile memory pool, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM) and direct memory bus random access memory (DRRAM).

[0068] In the embodiments of the present application, for example, Figure 3As shown, the processor 210 may include a sampler 2101 , an analyzer 2102 , and an optimizer 2103 . Among them, the sampler 2101 can be used to determine information, which may include block information of a code block in the target code, and the block information may include identification information of the code block and identification information of the next-hop block. For example, the sampler 2101 can be used to determine the block information of the code block in the target code according to the execution order of the target code; the analyzer 2102 can be used to generate information, which may include calling information of the target code, and the calling information may include group information of each code block group in multiple code block groups, and the group information includes group identification information, identification information of the next-hop group and identification information of the code block in the code block group. For example, the analyzer 2102 can be used to generate calling information of the target code according to the block information; the optimizer 2103 can be used to obtain identification information, for example, the optimizer 2103 can be used to obtain identification information of the first code block currently executed in the target code, and obtain identification information of the second code block executed after the first code block; the optimizer 2103 is also used to store the second code block in the cache according to the identification information of the second code block.

[0069] Combine the following Figure 2 and Figure 3 The electronic device shown in the figure introduces and illustrates the code processing method provided in the embodiment of the present application.

[0070] Figure 4 A flowchart of a code processing method provided in an embodiment of the present application, the method comprising:

[0071] S401: Obtain identification information of a first code block currently being executed in a target code.

[0072] The target code is the code currently executed by the electronic device.

[0073] In a possible embodiment, the target code may include a binary code segment, which may also be referred to as a code segment. In practical applications, the target code may be stored in a memory of an electronic device, which may be the above-mentioned Figure 2 The memory shown in , the object code has a corresponding starting address.

[0074] In a possible embodiment, the target code includes multiple code blocks, and the multiple code blocks can be obtained by dividing the target code.

[0075] For example, Figure 5 As shown, before step S401, the code processing method provided by the present application may further include S402: dividing the target code to obtain multiple code blocks, and configuring identification information of each of the multiple code blocks.

[0076] Optionally, the target code may be divided according to a fixed size to obtain multiple code blocks of the same size; or, the target code may be divided according to a step-by-step size to obtain multiple code blocks of a step-by-step size. The embodiment of the present application does not specifically limit the method of dividing the target code.

[0077] In a possible embodiment, the target code is divided according to integer multiples of the size of a cache line to obtain multiple code blocks, and the size of each code block in the multiple code blocks is an integer multiple of the size of a cache line. In this embodiment, the target code is divided according to integer multiples of the size of a cache line, and the size of each code block is an integer multiple of the size of a cache line, which is convenient for reading the subsequent second code block.

[0078] In a possible embodiment, the above-mentioned multiple code blocks may be basic blocks in the target code.

[0079] Furthermore, the identification information of the code block may be used to uniquely identify the code block. For example, the identification information may include the number or address of the code block.

[0080] In a possible implementation, the identification information is a number of the code block, and the number may be obtained by sequentially numbering a plurality of divided code blocks.

[0081] Exemplarily, if the identification information is the number of a code block, the specific process of obtaining the number of the first code block is: obtain the address of the first code block, which is the address of the first code block in the memory, determine the difference between the address of the first code block and the starting address based on the address of the first code block and the starting address of the target code, and determine the number of the first code block based on the difference and the size of the code block.

[0082] In another possible implementation, the identification information is the address of the code block, and the address of the code block is the address of the code block in the memory, which may also be called an instruction address.

[0083] It should be noted that in the following embodiments of the present application, the identification information of the code block is taken as the number of the code block for illustration, which does not constitute a specific limitation.

[0084] In addition, the first code block is the currently executed code block in the target code. For example, the target code includes 10 code blocks and their identification information can be B1 to B10 in sequence. If the currently executed code block in the target code is code block B3, then the first code block is code block B3.

[0085] S403: According to the identification information of the first code block, obtain the identification information of the second code block executed after the first code block in the calling information of the target code; the calling information includes the identification information and the execution order of multiple code blocks in the target code.

[0086] In a possible implementation, the call information is dynamically acquired during the execution of the target code.

[0087] For example, Figure 5 As shown, after step S402, the code processing method provided by the present application further includes S404: determining the call information according to the execution order of the code blocks included in the target code under multiple different business paths.

[0088] The service path refers to multiple code blocks that need to be called in sequence to complete a service request. A service may include multiple service requests, and different service requests correspond to different service paths.

[0089] Exemplarily, a payment service may include multiple payment requests, such as payment by a first payment software, payment by a second payment software, and payment by a bank card. Alipay payment request corresponds to service path a; WeChat payment request corresponds to service path b; and bank card payment request corresponds to service path c. Service path a includes code blocks B1, B2, B3, B8, B5, and B6 executed in sequence; service path b includes code blocks B1, B2, B3, and B4 executed in sequence; service path c includes code blocks B1, B2, B3, and B7 executed in sequence.

[0090] In addition, by using the execution order of multiple code blocks under multiple different business paths, the code blocks belonging to the same business and being called continuously are grouped as a group to obtain multiple code block groups, and the call information is generated according to the group information of each code block group. Figure 6 The process of determining the calling information is illustrated and will not be described in detail here.

[0091] In another possible implementation, the call information may be pre-configured content, and the content of the call information may be configured according to actual needs. The embodiment of the present application does not limit the configuration process and the content of the configured call information.

[0092] Exemplarily, based on the business requirements, call information that meets the business requirements is determined, the determined call information is stored in the memory, and the call information can be directly obtained in the memory during use.

[0093] Furthermore, the second code block may include different contents. Three possible situations of the second code block are described below.

[0094] In the first case, the code blocks in the target code are grouped, and the second code block is a code block in the next hop group of the group where the first code block is located.

[0095] Specifically, the code blocks that belong to the same service path and are called continuously are grouped as one. For example, the code blocks B1, B2, and B3 in the service path a are grouped as the first code block group, and the code blocks B8, B5, and B6 are grouped as the second code block group. The next hop group of the first code block group is grouped as the second code block group, assuming that the first code block is code block B1, and the second code blocks are code blocks B8, B5, and B6.

[0096] In the first case, the process of obtaining the identification information of the second code block includes the following two implementation methods:

[0097] In a first implementation, the identification information is a code block number. The process of obtaining the second code block is: determining the code block group to which the first code block belongs according to the number and call information of the first code block; determining the next hop group of the group to which the first code block belongs according to the group information of the code block group, and obtaining the number of the second code block from the group information of the next hop group of the group to which the first code block belongs.

[0098] In a second implementation, the identification information is a code block address. The process of obtaining the identification information of the second code block is similar to the process of obtaining in the first implementation, and will not be described in detail here.

[0099] It should be noted that, in the first case, the first code block may be any code block in the group where the first code block is located.

[0100] In a possible embodiment, the first code block may be the first code block in the group where the first code block is located. In this embodiment, when the first code block in the group where the first code block is located is executed, the second code block is obtained and stored in the cache, thereby improving the acquisition efficiency.

[0101] In another possible embodiment, the first code block may be the last code block in the group where the first code block is located. In this embodiment, when the last code block in the group where the first code block is located is executed, the second code block is obtained and stored in the cache, thereby improving the utilization rate of the cache.

[0102] In the second case, the code blocks in the target code are grouped, the first code block is a code block in the first group of the target code, and the second code block includes the remaining code blocks in the first group and the code blocks in the next hop group of the group where the first code block is located.

[0103] The first code block may be any code block in the first group except the last code block.

[0104] Exemplarily, the code blocks B1, B2, and B3 in the service path a are taken as the first code block group, and the code blocks B8, B5, and B6 are taken as the second code block group. Assuming that the first code block group is the first group, the first code block can be any code block except the code block B3. Assuming that the first code block can be the code block B2, the second code blocks are the code blocks B3, B8, B5, and B6.

[0105] In the second case, the process of obtaining the numbering information of the second code block includes the following two implementation methods:

[0106] In a first implementation, the identification information is a code block number. The process of obtaining the second code block is as follows: determining the first code block group to which the first code block belongs according to the number of the first code block and the calling information; obtaining the numbers of the remaining code blocks after the first code block and the next hop group of the first code block group from the group information of the first code block group; and obtaining the numbers of the code blocks in the next hop group of the first code block group from the group information of the next hop group of the first code block group.

[0107] In the second implementation, the identification information is a code block address. The process of obtaining the numbering information of the second code block is similar to the process of obtaining the numbering information in the first implementation in the second case, and will not be described in detail here.

[0108] Optionally, the group information may also include the calling probability of the next hop group. The next hop group is a group of code blocks that are likely to be executed. In the first and second cases above, the group of code blocks that are likely to be executed is stored in the cache, which improves the speed of obtaining the code blocks.

[0109] In the third case, the second code block is the next hop block of the first code block.

[0110] In the third case, the process of obtaining the second code block includes the following two implementation methods:

[0111] In a first implementation, the identification information is a code block number, and the number of the next hop block of the first code block is determined according to the number of the first code block and the calling information.

[0112] In the second implementation, the identification information is a code block address. The process of obtaining the second code block is similar to the process of obtaining the second code block in the first implementation in the third case, and will not be repeated here.

[0113] In the third case, when the first code block is executed, the next hop block of the first code block is stored in the cache, and when the second code block is executed, the second code block is directly obtained from the cache, thereby improving the speed of obtaining instructions.

[0114] It should be noted that in practical applications, the content of the second code block can be configured according to actual needs. The three possible situations of the second code block shown in this application are only for reference and do not constitute specific limitations.

[0115] S405: Store the second code block in the cache according to the identification information of the second code block.

[0116] Since the second code block may include the above three different situations, the process of obtaining the second code block in the three situations is similar. The process of obtaining the second code block is described below.

[0117] In a first implementation, the identification information is a code block number. The address of the second code block is determined according to the number of the second code block, the starting address of the target code and the code block size; and the second code block is obtained in the memory corresponding to the cache according to the address of the second code block.

[0118] In a second implementation, the identification information is a code block address. According to the address of the second code block, the second code block is directly obtained in the memory corresponding to the cache.

[0119] Specifically, S405 may be implemented as follows: according to the identification information of the second code block, reading the second code block that is not stored in the cache from the memory corresponding to the cache.

[0120] Among them, reading the second code block not stored in the cache from the memory corresponding to the cache can be specifically implemented as follows: determining the target address of the second code block not stored in the cache according to the identification information of the second code block and the initial address of the target code; reading the target code block in the memory according to the target address; and storing the read target code block in the cache.

[0121] Optionally, two possible implementations of determining the second code block not stored in the cache are described below.

[0122] In a first possible implementation, the cache is traversed. Specifically, the cache is traversed according to the identification information of the second code block to determine the second code block that is not stored in the cache.

[0123] In a second possible implementation, the read information is traversed. The read information is traversed according to the identification information of the second code block, wherein the read information includes the identification information and the read time of the code block that has been read, so as to determine the second code block that is not stored in the cache. Optionally, the read information can be stored in the memory in the form of a table.

[0124] It should be noted that, in actual applications, the optimizer under the ARM architecture may use a preload instruction (prfm) to read the second code block, and the optimizer under the X86 architecture may use a prefetch instruction (prefetcht) to read the second code block.

[0125] The code processing method provided by the present application stores the second code block to be executed after the first code block in a cache in advance when executing the first code block. When executing the second code block, the second code block can be directly obtained from the cache to increase the speed of obtaining the second code block, thereby reducing the CPU front-end dependence and improving the performance of the application. In addition, no new code files are generated in this process. Compared with the prior art of constantly updating the code files in the memory, this saves memory and time, reduces the operation and maintenance pressure, and further improves the performance of the application.

[0126] Exemplarily, the present application provides a process for determining call information, such as Figure 6 As shown, the process may include S4041 to S4043. The contents of S4041 to S4043 are respectively described below.

[0127] S4041: According to the execution order of the code blocks included in the target code under multiple different service paths, block information of the code blocks in the target code is respectively determined, where the block information includes identification information of the code block and identification information of the next hop block.

[0128] Among them, the execution order can be called execution flow information, and the execution order can also be called I-Cache access flow. The execution order can be obtained by collecting instructions, and the collection instructions under different architectures can be different. For example, under the advanced RISC machine (ARM) architecture, the branch record buffer extension (BRBE) instruction is used to collect the execution order of code blocks under multiple different business paths; under the X86 architecture, the last branch record (LBR) instruction is used to collect the execution order of code blocks under multiple different business paths.

[0129] In addition, the block information may be the block information of all code blocks in the target code, in which case the call information includes the identification information and execution order of all code blocks in the target code; or the block information of some code blocks in the target code, for example, the block information may be the block information of hot blocks in the target code, in which case the call information includes the identification information and execution order of the hot blocks in the target code. For ease of understanding, the following embodiments take the case where the call information includes the identification information and execution order of all code blocks in the target code as an example.

[0130] In a possible implementation, the block information of the code blocks in the target code is determined respectively, including: determining the block information of the hot blocks in the target code respectively, and the hot blocks are code blocks in the target code whose number of calls is greater than a second threshold. Specifically, the block information of the hot blocks can be obtained by periodically collecting the execution order of the code blocks under multiple different business paths. For example, the sampler can collect once every hour. Among them, the second threshold can be set according to actual needs and the experience of relevant staff. For example, the second threshold can be 5, and the embodiment of the present application does not make specific limitations on this. In this embodiment, the block information of the hot blocks in the target code is determined, which saves sampling time and reduces the power consumption of the sampler.

[0131] In addition, the next hop block is the next code block that may be executed after the current code block. Since the execution order of the target code is different under different business paths, that is, the code blocks called under different business paths are different, for any code block, the code block may include one hop block or multiple hop blocks.

[0132] For example, Figure 7 A schematic diagram of block information provided for an embodiment of the present application, assuming that the target code includes 12 code blocks, and their identification information can be B1 to B12 in sequence, the block information includes block information of code blocks B1 to code blocks B12, for each of code blocks B1 to code blocks B12, the block information includes identification information of the code block and identification information of the next hop block, for example, the block information of code block B4 includes identification information B4, next hop block number B7 and next hop block number B8. Figure 7 In the example, the block information is the block information of all blocks in the code block, and the code block B4 includes 2 jump blocks. Figure 7 Only the block information of code block B4 is shown.

[0133] Optionally, the block information may also include the number of times the code block is called and the number of times the next hop block is called. The block information may be stored in a memory of the electronic device in the form of a table, and the table storing the block information may also be a block information table or a block mapping table.

[0134] S4042: According to the block information, the code blocks that meet the condition are grouped as one to obtain multiple code block groups; wherein the condition is used to indicate that the code blocks belong to the same service path and are called continuously.

[0135] Exemplarily, the target code includes code block B1, code block B2 and code block B3, code blocks B1 to B3 are all in the same service path, and code block B1 has one and only one next hop block, which is code block B2, and code block B2 has one and only one next hop block, which is code block B3. That is, after the CPU executes code block B1, it calls code block B2 and code block B3 in sequence, and code block B1, code block B2 and code block B3 are regarded as a code block group.

[0136] S4043: Generate calling information, the calling information including group information of each code block group in the plurality of code block groups. The group information includes group identification information, identification information of the next hop group and identification information of the code block in the code block group.

[0137] The call information may also be referred to as group call information. The next hop group is the group of code blocks that may be executed next after the group containing the currently executed code block is executed. A group may include one next hop group or multiple next hop groups. The number of next hop groups is related to the number of service paths included in the target code.

[0138] For example, Figure 8 A schematic diagram of call information provided for an embodiment of the present application, assuming that the multiple code block groups may include 5 code block groups, and their identification information may be G1 to G5 in sequence. Among them, code block group G2 and code block group G3 are the next hop groups of code block group G1, code block group G4 and code block group G5 are the next hop groups of code block group G2, and code block group G1 includes code block B1, code block B2 and code block B3. The group information of code block group G1 includes group identification information G1, identification information G2 of the next hop group, identification information G3 of the next hop group and identification information B1, B2 and B3 of the code blocks in the group. Figure 8 Only the grouping information of the code block group G1 is shown.

[0139] Optionally, the call information may be stored in a table in a memory of the electronic device, which may be the above-mentioned Figure 2 The memory shown in .

[0140] Furthermore, the group information also includes the number of times the group is called, and the code processing method provided by the present application may also include: deleting the group information of the code block group whose number of calls in the call information is less than the first threshold. In practical applications, during the execution of the target program, the number of times the code block is called can be collected and recorded to determine the number of times the group is called, thereby determining the latest group information, and according to the number of times the group is called in the latest group information being less than or equal to the first threshold, deleting the group information of the corresponding code block group.

[0141] For example, under the ARM architecture, the optimizer can delete the group information of the code block group in the call information by using the instruction cache line invalidate (Instruction Cache line Invalidate by VA to PoU, IC IVAU) instruction; under the X86 architecture, the cache line clear (clfush) instruction is used to delete the group information of the code block group in the call information. Among them, the first threshold can be set according to actual needs and the experience of relevant staff, and the embodiment of the present application does not make specific limitations on this.

[0142] In one possible implementation, the Figure 6 The illustrated process is to periodically determine the latest call information according to the latest execution order of the code block under multiple different business paths. It should be understood that in S403, the second code block is determined according to the current latest call information.

[0143] It is understandable that, in order to realize the above functions, the code processing device includes hardware structures and / or software modules corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the steps of the binary code processing methods of each example described in the embodiments herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application.

[0144] The embodiment of the present application can divide the functional modules of the code processing device according to the above method example. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0145] In the case of dividing each functional module into corresponding functional modules, Fig. 9 A possible structural schematic diagram of a code processing device involved in the above embodiment is shown, and the code processing device includes: an acquisition unit 901 and a storage unit 902, wherein the acquisition unit 901 is used to support the code processing device to execute S401 and S403 in the above method embodiment; the storage unit 902 is used to support the code processing device to execute S405 in the above method embodiment.

[0146] Optional, such as Fig.10As shown, the code processing device may further include: a determining unit 903 , a deleting unit 904 and a reading unit 905 .

[0147] The determining unit 903 is used to support the code processing device to execute S4041 to S4043 in the above method embodiment.

[0148] The deleting unit 904 is configured to delete the group information of the code block group whose group call times in the call information is less than a first threshold.

[0149] The reading unit 905 is used to support the code processing device to execute S405 in the above method embodiment.

[0150] In hardware implementation, the determination unit 903 and the deletion unit 904 may be the above Figure 3 The analyzer shown in FIG. 1 , the reading unit 905 may be the above Figure 3 For a detailed description of the analyzer and optimizer, see Figure 3 The specific description in the embodiments of the present application will not be repeated here.

[0151] It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module, which will not be repeated here. The device provided in the embodiment of the present application is used to perform the corresponding functions in the above embodiment, so it can achieve the same effect as the above control method.

[0152] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0153] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0154] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for the device to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks or optical disks.

[0155] Another aspect of the present application provides an electronic device, the electronic device includes a processor and a memory, the memory is used to store instructions, the processor is used to execute the relevant steps in the above method embodiment, the processor can be the above Figure 2 or Figure 3 The processors provided in.

[0156] Another aspect of the present application provides a chip, the chip includes a processor and a memory, the memory is used to store instructions, the processor is used to execute the relevant steps in the above method embodiment, the processor can be the above Figure 2 or Figure 3 The processors provided in.

[0157] In another aspect of the present application, a computer-readable storage medium is provided, which includes computer instructions. When the computer instructions are executed on a code processing device, the code processing device executes the relevant steps in the above method embodiment.

[0158] In yet another aspect of the present application, a computer program product comprising instructions is provided. When the computer program product is executed on a computer device, the computer device is enabled to execute the relevant steps in the above method embodiments.

[0159] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A code processing method, characterized in that: The method comprises: Obtaining identification information of a first code block currently being executed in the target code; According to the identification information of the first code block, in the calling information of the target code, obtaining the identification information of the second code block executed after the first code block; the calling information includes the identification information and the execution order of multiple code blocks in the target code; According to the identification information of the second code block, the second code block is stored in a cache.

2. The method according to claim 1, characterized in that The second code block is a code block in a next hop group of the group where the first code block is located.

3. The method according to claim 1, characterized in that The first code block is a code block in a first group of the target code, and the second code block includes the remaining code blocks in the first group and a code block in a next hop group of the group where the first code block is located.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: The calling information is determined according to the execution order of the code blocks included in the target code under a plurality of different service paths.

5. The method according to claim 4, characterized in that The determining the call information according to the execution order of the code blocks included in the target code under a plurality of different business paths includes: According to the execution order, block information of code blocks in the target code is determined respectively, wherein the block information includes identification information of the code block and identification information of a next-hop block; According to the block information, the code blocks satisfying the condition are grouped as a group to obtain a plurality of code block groups; wherein the condition is used to indicate that the code blocks belong to the same service path and are called continuously; The calling information is generated, wherein the calling information includes group information of each code block group in the plurality of code block groups, wherein the group information includes group identification information, identification information of a next hop group, and identification information of a code block in the code block group.

6. The method according to claim 5, characterized in that The group information also includes the number of times the group is called, and the method further includes: The group information of the code block group in which the number of times the group is called is less than a first threshold in the calling information is deleted.

7. The method according to claim 1, characterized in that The second code block is a next hop block of the first code block.

8. The method according to any one of claims 5 to 7, characterized in that: The respectively determining the block information of the code blocks in the target code comprises: The block information of hot blocks in the target code is determined respectively, where the hot blocks are code blocks in the target code whose number of calls is greater than a second threshold.

9. The method according to any one of claims 1 to 8, characterized in that: The size of the code block is an integer multiple of the cache line size of the cache.

10. The method according to any one of claims 1 to 9, characterized in that: The object code includes binary code segments.

11. The method according to any one of claims 1 to 10, characterized in that: The storing the second code block in a cache according to the identification information of the second code block includes: According to the identification information of the second code block, the second code block not stored in the cache is read from the memory corresponding to the cache.

12. The method according to claim 11, characterized in that The step of reading the second code block not stored in the cache from a memory corresponding to the cache according to the identification information of the second code block includes: Determining, according to the identification information of the second code block, a target address of the second code block not stored in the cache; Reading a target code block in the memory according to the target address; The read target code block is stored in the cache.

13. A code processing device, characterized in that: The device comprises: An acquisition unit, used to acquire identification information of a first code block currently being executed in the target code; The acquisition unit is further configured to acquire, according to the identification information of the first code block, identification information of a second code block executed after the first code block in the calling information of the target code, wherein the calling information includes identification information and an execution order of multiple code blocks in the target code; A storage unit is used to store the second code block in a cache according to the identification information of the second code block.

14. The device according to claim 13, characterized in that The second code block is a code block in a next hop group of the group where the first code block is located.

15. The device according to claim 13, characterized in that The first code block is a code block in a first group of the target code, and the second code block includes the remaining code blocks in the first group and a code block in a next hop group of the group where the first code block is located.

16. The device according to any one of claims 13 to 15, characterized in that: The device also includes: The determination unit is used to determine the call information according to the execution order of the code blocks included in the target code under multiple different business paths.

17. The device according to claim 16, characterized in that The determining unit is specifically used for: According to the execution order, block information of code blocks in the target code is determined respectively, wherein the block information includes identification information of the code block and identification information of a next-hop block; According to the block information, the code blocks satisfying the condition are grouped as a group to obtain a plurality of code block groups; wherein the condition is used to indicate that the code blocks belong to the same service path and are called continuously; The calling information is generated, wherein the calling information includes group information of each code block group in the plurality of code block groups, wherein the group information includes group identification information, identification information of a next hop group, and identification information of a code block in the code block group.

18. The device according to claim 17, characterized in that The group information also includes the number of times the group is called, and the device also includes: The deleting unit is used to delete the group information of the code block group in which the number of times the group is called is less than a first threshold in the calling information.

19. The device according to claim 13, characterized in that The second code block is a next hop block of the first code block.

20. The device according to any one of claims 17 to 19, characterized in that The determining unit is further configured to: The block information of hot blocks in the target code is determined respectively, where the hot blocks are code blocks in the target code whose number of calls is greater than a second threshold.

21. The device according to any one of claims 13 to 20, characterized in that: The size of the code block is an integer multiple of the cache line size of the cache.

22. The device according to any one of claims 13 to 21, characterized in that: The object code includes binary code segments.

23. The device according to any one of claims 13 to 22, characterized in that: The device also includes: A reading unit is used to read the second code block that is not stored in the cache from the memory corresponding to the cache according to the identification information of the second code block.

24. The device according to claim 23, characterized in that The reading unit is specifically used for: Determining a target address of the second code block not stored in the cache according to the identification information of the second code block and the initial address of the target code; Reading a target code block in the memory according to the target address; The read target code block is stored in the cache.

25. An electronic device, characterized in that: The electronic device comprises a processor and a memory, the memory is used to store instructions, and the processor is used to execute the code processing method according to any one of claims 1 to 12.

26. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes computer instructions, and when the computer instructions are executed on a code processing device, the code processing device executes the code processing method according to any one of claims 1 to 12.

27. A computer program product comprising instructions, characterized in that When the computer program product is run on a computer device, the computer device is caused to execute the code processing method according to any one of claims 1 to 12.

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