A discrete fourier transform implementation method and apparatus based on a matrix operation unit

Abstract

The application relates to a kind of discrete fourier transform implementation method and equipment based on matrix operation unit, the method comprises: DFT matrix is transformed arrangement and generates the DFT matrix of transformed arrangement, the DFT matrix of transformed arrangement and input data matrix are copied to equipment global memory in host end;Start computing kernel, input data matrix and the DFT matrix of transformed arrangement are read to the data on-chip cache from global memory, input data matrix and DFT matrix are multiplied by calling matrix operation unit, and the operation result of discrete fourier transform is obtained;Host end copies result data from equipment global memory to host memory, and releases computing resource.The application directly adopts matrix multiplication operation to calculate DFT, does not need additional complex imaginary-real separation combination operation, can reduce global memory access frequency, improves the execution efficiency of entire complex matrix multiplication operation, improves equipment DFT calculation efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of high-performance computing and computing power optimization, and particularly relates to a discrete Fourier transform implementation method and device based on a matrix operation unit. BACKGROUND

[0002] Discrete Fourier Transform (DFT) is a method for converting a signal from the time domain to the frequency domain. DFT has a wide range of applications in scientific computing, including molecular dynamics calculations, electronic structure calculations, digital signal processing, etc. In deep learning, DFT also has important application value. Compared with traditional convolution algorithms, DFT-based convolution algorithms have better results in network training. Since DFT has a wide range of application scenarios, DFT algorithm parallel optimization has become a research hotspot in the field of high-performance computing.

[0003] GPU has become the mainstream computing hardware in the field of artificial intelligence and scientific computing due to its powerful parallel computing capability. It is of great significance to optimize and accelerate DFT algorithms in view of the existing GPU hardware characteristics. In order to accelerate the matrix multiplication operation commonly used in artificial intelligence computing, NVIDIA designed a matrix operation core Tensor Core in its GPU to accelerate matrix computation from the hardware level. Thereafter, AMD designed the corresponding Matrix Core.

[0004] The computing capability of hardware needs to be invoked by software. If the optimization and adaptation of software are not in place, it will cause waste of hardware computing capability and computing resources, and increase the computing cost. In order to fully exert the computing capability of GPU and improve the computing efficiency of DFT on GPU, it is necessary to optimize and design the traditional DFT algorithm in combination with the characteristics of new hardware.

[0005] At present, there are many mature DFT computing libraries on GPU, typical of which are cuFFT of NVIDIA, rocFFT of AMD, and cross-platform Vulkan FFT, etc. However, these computing libraries do not fully exert the computing capability of modern GPU, and there is still a lot of optimization space for DFT algorithms based on GPU. If the matrix operation unit in modern GPU is used to accelerate DFT computation, the computing efficiency of DFT will be greatly improved, thereby providing underlying computing power support for scientific computing and deep learning.

[0006] The complex matrix multiplication used in DFT can essentially be implemented through four real matrix multiplications and two real matrix additions. However, considering that the matrix operation unit and other units on the device need to exchange data through on-chip cache, mechanically decomposing the complex matrix multiplication steps into four independent matrix multiplication processes and two independent matrix addition processes will lead to a large number of extra operations, resulting in performance degradation. This is because the matrix operation unit is responsible for matrix multiplication, while other units are responsible for element-wise matrix addition. Data exchange between the two must be handled by data transfer, which increases the burden of data transmission. Therefore, given the independent yet computationally powerful nature of the matrix operation unit, the optimization strategy should avoid overly fragmented operations in complex matrix multiplication. Instead, it should seek a method that effectively integrates the real matrix multiplication and addition processes to minimize the number of global memory accesses, thereby improving the overall execution efficiency of the complex matrix multiplication operation. Summary of the Invention

[0007] To address the technical problems existing in the prior art, this invention provides a method and device for implementing Discrete Fourier Transform (DFT) based on matrix operation units. It performs specific transformations and arrangements on the DFT matrix, utilizes high-performance matrix operation units on existing system devices for computational acceleration, and improves the device's DFT computation efficiency. It also effectively integrates the real matrix multiplication and addition processes to minimize the number of global memory accesses, thereby improving the execution efficiency of the entire complex matrix multiplication operation.

[0008] The first objective of this invention is to provide a method for implementing discrete Fourier transform based on matrix operation units.

[0009] A second objective of this invention is to provide a computer device.

[0010] The first objective of this invention can be achieved by adopting the following technical solution:

[0011] A method for implementing discrete Fourier transform based on matrix operation units, characterized by the following steps:

[0012] S1. Request computing resources, transform and arrange the DFT matrix to generate a transformed and arranged DFT matrix, and copy the transformed and arranged DFT matrix and the input data matrix to the device's global memory on the host side.

[0013] S2. Start the computing kernel, read the input data matrix and the transformed DFT matrix into the on-chip cache from global memory, and call the matrix operation unit to perform matrix multiplication between the input data matrix and the DFT matrix to obtain the result of the discrete Fourier transform.

[0014] S3. The host side copies the result data from the device's global memory to the host memory, releasing computing resources.

[0015] Specifically, step S1 includes:

[0016] On the host side, the elements of the DFT matrix are transformed and arranged, and each element of the DFT matrix is ​​transformed from a complex number into a real number submatrix, thus obtaining the transformed and arranged DFT matrix.

[0017] Treat the batch of input sequence vectors as an input data matrix in the batch direction;

[0018] The transformed DFT matrix is ​​copied from host memory to device global memory, and the input data matrix is ​​copied to device global memory.

[0019] Specifically, the step of transforming each element of the DFT matrix from a complex number into a real submatrix includes: transforming each element of the DFT matrix from a complex number into a 2*2 real submatrix.

[0020] Specifically, the DFT matrix of the transformed arrangement is represented as follows:

[0021]

[0022] Among them, F N To transform the arrangement of the DFT matrix, express The real part, express The imaginary part.

[0023] Specifically, step S2 includes:

[0024] S21. Read the input data matrix and the transformed DFT matrix into the on-chip cache from global memory, and use a heuristic strategy to optimize the amount of data read.

[0025] S22. Call the matrix operation unit to perform matrix multiplication between the input data matrix and the DFT matrix, and output the calculation result data of the Discrete Fourier Transform. The calculation result data can be represented as:

[0026]

[0027] Where X is a vector composed of the input sequences after Fourier transform, N is the length of the input sequence, and B is the batch size of the sequence.

[0028] Specifically, the process of reading the input data matrix and the transformed DFT matrix from global memory to on-chip cache, and employing a heuristic strategy to optimize data read volume, includes:

[0029] The input data matrix is ​​read from global memory and then into the on-chip cache. When the length N of the input sequence is less than or equal to a preset threshold, the data is read from the on-chip cache into the register in blocks according to the direction of the increasing batch input sequence number, and arranged in column order first.

[0030] When the length N of the input sequence is greater than the preset threshold, the data is read from the on-chip cache into the register in blocks according to the direction of the single input sequence.

[0031] The second objective of this invention can be achieved by adopting the following technical solution:

[0032] A computer device includes a processor and a memory for storing a processor-executable program. When the processor executes the program stored in the memory, it implements the above-described discrete Fourier transform implementation method based on matrix operation units.

[0033] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0034] This invention provides a method and device for implementing Discrete Fourier Transform (DFT) based on a matrix operation unit. By transforming the elements of the DFT matrix on the host side, each element of the DFT matrix is ​​transformed from a complex number into a real submatrix, resulting in the transformed DFT matrix. Direct matrix multiplication is used to calculate the DFT, eliminating the need for additional complex-to-real submatrix separation operations. The high-performance matrix operation unit on existing system devices is utilized for computational acceleration, improving the device's DFT computation efficiency. Leveraging the high computing power of the matrix operation core and reducing the interaction between global memory and on-chip cache, it features fast computation speed, low latency, and ease of batch processing, making it highly practical. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0036] Figure 1 This is a flowchart of the discrete Fourier transform implementation method based on matrix operation unit in an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of matrix multiplication operation in an embodiment of the present invention. Detailed Implementation

[0038] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the implementation of the present invention is not limited thereto. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] Example 1:

[0040] This invention proposes a method for accelerating Discrete Fourier Transform (DFT) calculations using high-performance matrix operation units on existing GPUs. It leverages the high computing power of matrix operation cores and reduces the interaction between global memory and on-chip cache, resulting in fast calculation speed, low latency, and ease of batch processing, thus possessing significant practical value. It can fully utilize GPU computing power to accelerate DFT calculations, providing computational support for fields such as deep learning and scientific computing.

[0041] Matrix operations in the Discrete Fourier Transform (DFT) are generally implemented using specific matrix multiplication methods. The matrix representation of the DFT involves the multiplication of two matrices: the vector of the input sequence multiplied by a complex exponential function matrix called the DFT matrix. The result of this matrix multiplication is a complex spectrum that contains the frequency components of the input signal.

[0042] like Figure 1 As shown, the discrete Fourier transform implementation method based on matrix operation units described in this invention includes the following steps:

[0043] S1. Request computing resources, transform and arrange the DFT matrix to generate a transformed DFT matrix, copy the transformed DFT matrix and input data to the device's global memory on the host side, and store them in the system's persistent storage space.

[0044] S11. On the host side, the elements of the DFT matrix are transformed and arranged, and each element of the DFT matrix is ​​transformed from a complex number into a real number submatrix, and the transformed and arranged DFT matrix is ​​generated on the host memory.

[0045] Let x be the vector of input sequences of length N, and let X be the vector of sequences after Fourier transform. Then we have:

[0046]

[0047] k = 0, 1, ..., n-1;

[0048] Where X[k] is the k-th frequency component of the frequency domain signal, x[n] is the n-th time point of the time domain signal, and i is the imaginary unit. As a complex exponential function, vector X can be expressed in matrix form as follows:

[0049] X = F N x;

[0050] Among them, F N The DFT matrix can be represented as follows:

[0051]

[0052] in, DFT matrix F N Each element is a complex number. The elements are transformed and arranged so that each element is transformed into a 2x2 real submatrix. The resulting DFT matrix F is the transformed arrangement. N It can be represented as:

[0053]

[0054] in, express The real part, express The imaginary part.

[0055] By transforming each element of the Discrete Fourier Transform matrix from a complex number into a 2*2 real submatrix, the complex matrix multiplication used in the DFT process is directly converted into real matrix multiplication. This avoids the redundant process of separating and combining complex and real numbers (data exchange between the two must pass through global memory, which increases the burden of data transmission), thereby minimizing the number of global memory accesses, accelerating DFT computation, and improving the execution efficiency of the entire DFT process.

[0056] The DFT matrix of length N from the original input sequence is transformed and rearranged. Therefore, in scenarios with a finite number of N choices, the transformed and rearranged DFT matrix can be generated in advance, or even stored in local persistent storage, and retrieved before computation. It's important to note that the DFT matrix is ​​N*N in size. When N is a large input, a matrix-based approach similar to FFT is more suitable.

[0057] S12. Treat the batch of input sequence vectors as an input data matrix in the batch direction. The input data matrix x can be represented as:

[0058]

[0059] Where, x0[0] r Let x0[0] represent the real part of the 0th element of the input sequence 0. iThe imaginary part of the 0th element of the input sequence 0 is represented, and so on. When transforming the input sequence vector into the input data matrix, the data is arranged in column order, with each column being a sequence. B is the batch size of the sequences.

[0060] S13. Copy the transformed DFT matrix from the host memory to the device global memory, and copy the input data matrix to the device global memory.

[0061] Assuming a batch size of 256 and a length of 64 for DFT computation, the computation data is copied to the device's global memory, and each block retrieves the corresponding data for computation. For each 64-length DFT, since the 64×64 DFT matrix is ​​identical for all sequences, it is pre-generated and transformed on the host machine before being copied to the device's global memory for direct reading by each core.

[0062] S2. Start the computing kernel, read the input data matrix and the transformed DFT matrix into the on-chip cache from global memory, and call the matrix operation unit to perform matrix multiplication between the input data matrix and the DFT matrix to obtain the calculation result data of the Discrete Fourier Transform.

[0063] S21. Read the input data matrix and the transformed DFT matrix into on-chip cache from global memory, and use a heuristic strategy to optimize the amount of data read.

[0064] On the host side, device code is invoked to start the computation kernel, and the kernel program begins execution. Before matrix multiplication, the input data matrix and DFT matrix need to be loaded into their respective on-chip caches. Then, matrix operation units such as CubeUnit, Tensor Core, or Matrix Core in the NPU / GPU are used to perform heuristically selected matrix multiplication operations between the input data matrix and the DFT matrix. Since the computation data is already in global memory from the previous step, the computation data (input data matrix) and DFT matrix are first read into device registers or shared memory to speed up data reading efficiency and reduce memory access time. Because each core computes a 128*128 sub-result matrix, each core loads its own 128*256 DFT matrix elements and 256*128 input data into the on-chip cache, and the loading process is parallel.

[0065] Specifically, the heuristic strategy for optimizing data read volume includes: reading the input data matrix from global memory to on-chip cache; when the input sequence length N is less than or equal to a preset threshold Nh, reading from the on-chip cache to the register is performed in blocks according to the increasing direction of the batch input sequence number (i.e., the sequence batch size B), prioritizing column direction. When the input sequence length N is greater than the preset threshold Nh, reading from the on-chip cache to the register is performed in blocks according to the direction of a single input sequence (i.e., N). In this embodiment, the DFT matrix multiplication is fixed as a 2*64×2*64×2*128 matrix multiplication form. Here, when the sequence length N is greater than the threshold 45, reading from the on-chip cache to the register is performed in blocks according to the arrangement of the input sequence.

[0066] The threshold Nh is determined by the on-chip cache size. Taking a radix, sequence length N, and batch size as an example: matrix multiplication (m,k,n) = (radix,radix,N*batch / radix), with the matrix kerneled in the k and n directions. The n direction requires double buffering with twice the space. When computational resources are sufficient, the number of allocated kernels is the same as the number of physical kernels. Different colored blocks are assigned to different kernels. K-axis kernel division requires atomic addition, and several kernels require atomic addition to the same position. Another matrix multiplication method is used for cases with a small radix, such as radix <= 45. In this case, the level-zero cache can completely hold the DFT matrix. The DFT matrix is ​​loaded into the level-zero cache before the loop. When the matrix multiplication (batch, M,K,N) uses the left matrix as the left matrix, the right matrix is ​​fixed, and the matrix multiplication is the input data. When N is large, two matrix blocks are read for double buffering. When N is small, two different batches are read for double buffering.

[0067] like Figure 2 The diagram illustrates matrix multiplication. To perform matrix multiplication: X = F N The pattern of DFT matrix multiplication with transformation arrangement is different from the usual matrix multiplication pattern. It is fixed as a matrix multiplication form of 2N*2N*2B, where N is the length of the original input sequence and B is the batch size of the sequence.

[0068] S22. Call the matrix operation unit to perform matrix multiplication between the input data matrix and the DFT matrix, and output the calculation result data of the Discrete Fourier Transform. The calculation result data can be represented as:

[0069]

[0070] Where X is a vector composed of the input sequences after Fourier transform, N is the length of the input sequence, B is the batch size of the sequence, and X0[0] is the vector of the input sequences after Fourier transform. r、X0[0] i These represent the real and imaginary parts of element 0 in sequence 0, respectively, and so on for the others.

[0071] Matrix operation units on GPUs have extremely high matrix computation performance, and matrix operations account for a significant portion of the computation in DFT. Therefore, using matrix operation units can improve the overall computational efficiency of DFT to a certain extent. This invention analyzes the transformation arrangement of matrix multiplication in DFT and designs the corresponding process for the transformation arrangement of matrix multiplication to reduce the amount of data read, thereby further accelerating the DFT process.

[0072] S3. The host copies the calculation result data of the Discrete Fourier Transform from the device's global memory to the host memory, releasing computing resources.

[0073] Finally, the DFT calculation result is stored in the device's global memory. The host needs to copy the calculation result from the global memory to the host memory for output or other uses. Since a lot of device global memory and host memory space is allocated before calculating the DFT, it needs to be released after the calculation to prevent memory leaks.

[0074] In summary, this invention first requests computing resources and generates the necessary pre-processed data with a transformed arrangement. Then, it starts the computing kernel, performs matrix element-wise multiplication in parallel, calls high-speed matrix operation units to complete the matrix multiplication, copies the result data to host memory, completes the computation, and releases the computing resources. Because this invention uses high-speed matrix operation units on existing GPUs to perform DFT calculations and employs a transformed arrangement, it can directly convert the complex matrix multiplications used in the DFT process into real matrix multiplications, avoiding the redundant process of separating and combining complex and real numbers, thus greatly improving the computational efficiency of the DFT. This has significant advantages over traditional DFT calculation methods.

[0075] Example 2:

[0076] This embodiment provides a computer device, which may be a server, computer, etc., including a processor, memory, input device, display, and network interface connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. When the processor executes the computer programs stored in the memory, it implements the discrete Fourier transform implementation method based on a matrix operation unit as described in Embodiment 1 above, as follows:

[0077] S1. Request computing resources, transform and arrange the DFT matrix to generate a transformed and arranged DFT matrix, and copy the transformed and arranged DFT matrix and the input data matrix to the device's global memory on the host side.

[0078] S2. Start the computing kernel, read the input data matrix and the transformed DFT matrix into the on-chip cache from global memory, and call the matrix operation unit to perform matrix multiplication between the input data matrix and the DFT matrix to obtain the result of the discrete Fourier transform.

[0079] S3. The host side copies the result data from the device's global memory to the host memory, releasing computing resources.

[0080] Specifically, step S1 includes:

[0081] On the host side, the elements of the DFT matrix are transformed and arranged, and each element of the DFT matrix is ​​transformed from a complex number into a real number submatrix, thus obtaining the transformed and arranged DFT matrix.

[0082] Transform the input sequence vector into an input data matrix;

[0083] The transformed DFT matrix is ​​copied from host memory to device global memory, and the input data matrix is ​​copied to device global memory.

[0084] Specifically, the step of transforming each element of the DFT matrix from a complex number into a real submatrix includes: transforming each element of the DFT matrix from a complex number into a 2*2 real submatrix.

[0085] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A method for implementing discrete Fourier transform based on matrix operation units, characterized in that, Includes the following steps S1. Request computing resources, transform and arrange the DFT matrix to generate a transformed and arranged DFT matrix, and copy the transformed and arranged DFT matrix and the input data matrix to the device's global memory on the host side. Step S1 includes: On the host side, the elements of the DFT matrix are transformed and arranged, and each element of the DFT matrix is ​​transformed from a complex number into a real number submatrix, thus obtaining the transformed and arranged DFT matrix. Treat the batch of input sequence vectors as an input data matrix in the batch direction; Copy the transformed DFT matrix from host memory to device global memory, and copy the input data matrix to device global memory; The DFT matrix of the transformed arrangement is represented as: ； Among them, F N To transform the arrangement of the DFT matrix, , express The real part, express The imaginary part; S2. Start the computing kernel, read the input data matrix and the transformed DFT matrix from global memory into on-chip cache, call the matrix operation unit to perform matrix multiplication between the input data matrix and the DFT matrix, and obtain the result of the discrete Fourier transform operation. S3. The host copies the result data from the device's global memory to the host memory, releasing computing resources.

2. The method for implementing discrete Fourier transform based on matrix operation units according to claim 1, characterized in that, The step of transforming each element of the DFT matrix from a complex number into a real submatrix includes: transforming each element of the DFT matrix from a complex number into a 2*2 real submatrix.

3. The method for implementing discrete Fourier transform based on matrix operation units according to claim 1, characterized in that, Step S2 includes: S21. Read the input data matrix and the transformed DFT matrix from global memory into on-chip cache, and use a heuristic strategy to optimize the amount of data read. S22. The matrix operation unit is invoked to perform matrix multiplication between the input data matrix and the DFT matrix, and the calculation result of the Discrete Fourier Transform is output. The calculation result is represented as follows: ； Where X is a vector composed of the input sequences after Fourier transform, N is the length of the input sequence, and B is the batch size of the sequence. , These represent the real and imaginary parts of the 0th element of sequence 0, respectively.

4. The method for implementing discrete Fourier transform based on matrix operation units according to claim 3, characterized in that, The process of reading the input data matrix and the transformed DFT matrix from global memory into an on-chip cache employs a heuristic strategy to optimize data read volume, including: The input data matrix is ​​read from global memory into on-chip cache. When the length N of the input sequence is less than or equal to a preset threshold, the data is read from the on-chip cache into the register in blocks according to the direction of increasing batch input sequence number, and arranged in column order first. When the length N of the input sequence is greater than the preset threshold, the data is read from the on-chip cache into the register in blocks according to the direction of the single input sequence.

5. A computer device, comprising a processor and a memory for storing a processor-executable program, characterized in that, When the processor executes the program stored in the memory, it implements the discrete Fourier transform implementation method based on matrix operation unit as described in any one of claims 1-4.

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