Processing system

Abstract

The present invention provides a neuron logic gate metal oxide semiconductor νLGMOS circuit, which can simulate the "integration and firing" behavior of neurons in a biological neural network system, and can be fabricated together with multiple digital arithmetic circuits by using industrial CMOS logic process technology. The processing system of the present invention includes an analog νLGMOS circuit, a converter circuit, and a digital processing circuit, which can optimize the power and cost of various applications and can be fabricated into an integrated circuit chip by using the same CMOS logic process technology. At the same time, the above-mentioned analog νLGMOS circuit is inspired by the biological neural network system and can be simulated, designed, and fabricated into an integrated circuit chip for applications in the biomedical field.

Description

Technical Field

[0001] The present invention relates to a neuron metal oxide semiconductor field effect transistor (vMOSFET) circuit for simulating a biological neural circuit for analog signal processing. In particular, since the neuron circuit can be designed and manufactured by using an industrial standard complementary metal oxide semiconductor (CMOS) logic process technology, an optimized information processing system with high processing efficiency includes an analog neuron circuit and a digital arithmetic circuit, which can be implemented by an integrated circuit (IC) chip. Background Art

[0002] FIG. 1(a) is a schematic diagram showing an existing neuron MOSFET device according to the published literature of Shibata et al. ("An intelligent MOS transistor featuring gate-level weighted sum and threshold operations", International Electron Devices meeting (IEDM) 1991, page 99). FIG. 1(b) shows the equivalent floating gate capacitance value of the existing neuron MOSFET device in FIG. 1(a). The voltage potential of the neuron MOSFET device 100 is calculated as follows: and, C t = C1 + … + C n ; where represents the voltage potential of the conductive floating gate 110, (C1, C2,..., C n ) represents the capacitance value of the input gate 120 relative to the conductive floating gate 110, and (V1, V2..., V n ) represents the applied voltage value of the input gate 120.

[0003] As shown in the above equation, the integral obtained by multiplying each input voltage by the weight of the individual coupling capacitance value makes the voltage potential of the conductive floating gate 110 Greater than the critical voltage of the device to turn on the neuron MOSFET device 100. Since biological neurons are also activated or turned on by a gradient voltage potential (similar to the conductive floating gate voltage potential of the neuron MOSFET device 100) greater than the neuron critical voltage (neurons are about several tens of millivolts), the above neuron MOSFET device (hereinafter referred to as the vMOS device by the inventor) can simulate the electrical activation (integrate-and-fire) behavior of a neuron; wherein, the above neuron critical voltage is obtained by integrating the neurotransmitter signals (similar to the multiple input voltage signals of the neuron MOSFET device 100) applied to multiple post-synapses (similar to the multiple input gates 120 of the neuron MOSFET device 100) and the individual synaptic strengths (similar to the multiple input gate coupling capacitance values of the neuron MOSFET device 100).

[0004] According to the integrate-and-fire neuron firing model, a neuron with multiple post-synapses (signal receptors) can have "any strong" post-synapses strong enough to fire, or "all weak" post-synapses strong enough to fire. From the mathematical concept of logic gates, since there is "any strong" input that can turn on (to fire), the former can be regarded as the "OR" gate function; since there is "all weak" input that can turn on (to fire), the latter can be regarded as the "AND" gate function. By analogy, a neuron applies its integrate-and-fire function to "analogically and logically" analyze the input nerve signals from multiple post-synaptic inputs with various synaptic connection strengths. Analogically, according to the circuit configuration, the vMOS circuit (a circuit network formed by multiple vMOS devices with different capacitance coupling strengths (weights) to perform the above integrate-and-fire function) "analogically and logically" analyzes multiple input analog voltage signals related to the output analog voltage signal.

[0005] Figure 2(a) shows a schematic diagram of an existing vMOS circuit. Figure 2(b) shows the external control signal voltage (V A , V B , V C) and the relationships between different logic functions of the input gate voltages (I1, I2). The vMOS circuit 200 includes a two-bit digital-to-analog converter (D / A converter) 210 and a neuron circuit 220; the neuron circuit 220 includes a vMOS inverter 221 with four input terminals and a conventional inverter 222. In the above-mentioned published literature, Shibata further applied the vMOS device 100 in the vMOS circuit 200, as shown in Figure 2(a), by changing the circuit amplifier reference voltage of the vMOS inverter 221 with four input terminals and fixing the circuit input coupling capacitance ratio (8:4:2:1), to demonstrate the "variable" logic gate functions of the digital logic gates in Figure 2(b), such as AND, OR, and XOR gates. The above demonstration indicates that different reference voltages (V A , V B , V C ), input voltages (V1, V2, V3, V4), and coupling strengths of the vMOS circuit 200 will change the logic functionality of the circuit. Similarly, the firing behavior of neurons is mainly controlled by the strength of the input neurotransmitter signals from the postsynaptic connections. According to the neural plasticity mechanism, during training exercises, by frequently stimulating specific locations of the biological neural network system, the synaptic strength of a neuron entity can be changed or new synapses can be formed to change the logical analysis of the neuron. However, because the input / output analog voltage signals of the vMOS circuit are inaccurate and vulnerable to environmental interference, the vMOS circuit is not suitable for replacing the basic logic circuits (AND, OR, and NOT) used in digital computing circuits, where the input / output digital voltage signals of the circuit are represented by a series of voltage signals to represent accurate voltage states, and the digital high voltage V DD represents the value 1, while the digital low voltage V SS represents the value 0. Furthermore, in addition to the analog nature of the input / output voltage signals of the vMOS circuit, for the following two reasons, using the existing vMOS circuit design as the function of a combinational logic gate circuit (a combination of AND, OR, and NOT gates) is not cost-effective: (1) The vMOS circuit 200 has more transistors and larger transistors, such as the amplifier transistors in Figure 2(a), which will occupy a larger silicon area compared to traditional logic gate circuits, so there will be a higher IC chip cost; (2) The double-gate process of the existing vMOS devices and circuits requires an additional floating gate processing step (floating gate processing module), so there will be a higher chip process cost. SUMMARY OF THE INVENTION

[0006] The present application provides a processing system to optimize the power and cost of various applications and can be fabricated into an integrated circuit chip using the same CMOS logic process technology to solve the problems existing in the prior art.

[0007] To solve the above technical problems, the present application provides the following technical solutions:

[0008] The present application provides a processing system for receiving a plurality of input analog voltages and generating one or more digital output values, including:

[0009] An analog circuit including at least one metal-oxide-semiconductor (MOS) circuit, each MOS circuit including a first single-layer gate neuron MOS device having a plurality of input gates, wherein each MOS circuit is used to model one of an S-shaped function and an inverse S-shaped function to generate an output analog voltage in response to one or more of the plurality of input analog voltages applied to the plurality of input gates;

[0010] A conversion circuit coupled to the analog circuit and including one or more analog-to-digital converters (ADCs), each ADC performing analog-to-digital conversion on a corresponding output analog voltage according to its own resolution to generate a digital value; and

[0011] A digital processor for performing digital processing operations on one or more digital values from the conversion circuit to generate the one or more digital output values;

[0012] Wherein, the analog circuit, the conversion circuit, and the digital processor are fabricated using an industrial standard complementary metal-oxide-semiconductor (CMOS) logic process technology to form one or more integrated circuit chips.

[0013] Using the present application, the power and cost of various applications can be optimized, and they can be fabricated into integrated circuit chips using the same CMOS logic process technology. At the same time, the above analog vLGMOS circuit is inspired by the biological neural network system and can be simulated, designed, and fabricated into an integrated circuit chip for applications in the biomedical field. Brief Description of the Drawings

[0014] FIG. 1(a) is a schematic diagram showing a conventional double-layer gate neuron MOS (νMOS) device according to the published literature of Shibata et al. ("An intelligent MOS transistor featuring gate-level weighted sum and threshold operations", International Electron Devices meeting (IEDM) 1991, page 99).

[0015] FIG. 1(b) shows the equivalent floating gate capacitance value of the conventional double-layer gate neuron MOSFET device in FIG. 1(a).

[0016] Figure 2(a) shows a schematic diagram of an existing vMOS circuit according to the disclosure of Shibata et al. (“An intelligent MOS transistor featuring gate-level weighted sum and threshold operations”).

[0017] Figure 2(b) shows the relationship between the external control signal voltages (V A , V B , V C ) and the analog logic functions of the input gate voltages (I1, I2) in Figure 2(a).

[0018] Figure 3(a) is a νMOS device according to Figure 1(a), showing a cross-sectional view of an existing double-gate vMOS device.

[0019] Figure 3(b) shows a cross-sectional view of the single-gate vLGMOS device of the present invention.

[0020] Figure 3(c) shows the corresponding equivalent circuit diagram of the existing double-gate νMOS device 30A in Figure 3(a).

[0021] Figure 3(d) shows the corresponding equivalent circuit diagram of the single-gate vLGMOS device 30B in Figure 3(b).

[0022] Figure 4 is a schematic circuit diagram according to the present invention, showing a suppression-type N-type νLGNMOS device and an NMOSFET device load in a diode-connected configuration to generate a reverse S-shaped voltage function.

[0023] Figure 5 Shows Figure 4 a graph of the relationship between the floating gate voltage and the output voltage of the reverse S-shaped voltage transfer function generated by the circuit device.

[0024] Figure 6 is a schematic circuit diagram according to the present invention, showing a suppression-type P-type νLGPMOS device and an NMOSFET device load in a diode-connected configuration to generate a reverse S-shaped voltage function.

[0025] Figure 7 Shows Figure 6 a graph of the relationship between the floating gate voltage and the output voltage of the reverse S-shaped voltage transfer function generated by the circuit device.

[0026] Figure 8 is a schematic circuit diagram according to the present invention, showing a suppression-type complementary νLGCMOS circuit for generating a reverse S-shaped voltage function.

[0027] Figure 9 Display Figure 8 The graph showing the relationship between the floating gate voltage and the output voltage of the reverse S-shaped voltage transfer function generated by the circuit device.

[0028] Figure 10 It is a schematic diagram showing an excitatory complementary vLGCMOS circuit for generating an S-shaped voltage function according to an embodiment of the present invention.

[0029] Figure 11 Display Figure 10 The graph showing the relationship between the floating gate voltage and the output voltage of the S-shaped voltage transfer function generated by the circuit device.

[0030] Figure 12 It is a schematic circuit diagram showing a processing system according to an embodiment of the present invention. The above processing system has an ADC circuit for connecting the output terminal of the analog vLGMOS circuit to the input terminal of the digital processing circuit.

[0031] Figure 13 It is a top view showing an inhibitory complementary vLGCMOS circuit manufactured by CMOS logic process technology and having 4 input gates according to an embodiment of the present invention.

[0032] Figure 14 It is a top view showing an excitatory complementary vLGCMOS circuit manufactured by CMOS logic process technology and having 4 input gates according to an embodiment of the present invention.

[0033] [Symbol Explanation]

[0034] 30A, 100 Double-layer gate neuron MOSFET device

[0035] 30B Single-layer gate neuron MOS device

[0036] 110, 340, 414, 614, 816, 1016, 1316, 1416 Conductive floating gate

[0037] 120, 35(1), 35(2), …, 35(n) Input gate

[0038] 200 vMOS circuit

[0039] 210 Digital-to-analog converter

[0040] 220 Neuron circuit

[0041] 221 νMOS inverter with four input terminals

[0042] 222 Conventional inverter

[0043] 300 P-type substrate

[0044] 310 Source region

[0045] 320 Drain region

[0046] 330 P-type channel region

[0047] 331 Gate dielectric layer

[0048] 341 Coupling dielectric layer

[0049] 360 Field isolation dielectric

[0050] 370 N-type semiconductor input gate

[0051] 400 Suppression type νLGNMOS circuit

[0052] 410 Single-layer gate N-type vLGNMOS device

[0053] 420, 620 Load element

[0054] 411 Source of single-layer gate N-type νLGNMOS device 410

[0055] 412, 814, 1322, 1422 P-type substrate electrode

[0056] 413 Drain of single-layer gate N-type vLGNMOS device 410

[0057] 415(1), …, 415(n), 615(1), …, 615(n) Input gate electrode

[0058] 817(1), …, 817(n), 1011(1), …, 1011(n), 1021 Input gate electrode

[0059] 1317(1), 1317(2), 1317(3), 1317(4) Input gate electrode

[0060] 1417(1), 1417(2), 1417(3), 1417(4) Input gate electrode

[0061] 421, 422, 611, 621, 622, 815, 1012, 1022, 1435, 1445 Node

[0062] 600 Suppression type vLGPMOS circuit

[0063] 610 Single-layer gate P-type νLGNMOS device

[0064] 611 Source of single-layer gate P-type νLGPMOS device 610

[0065] 612, 812, 1312, 1412 N-type well electrodes

[0066] 613 Drain of the single-layer gate P-type νLGPMOS device 610

[0067] 800, 1300 Suppression-type complementary νLGCMOS circuits

[0068] 810, 1310 Single-layer gate P-type νLGPMOS devices

[0069] 811 Source of the single-layer gate P-type νLGPMOS device 810

[0070] 813 Source of the single-layer gate N-type vLGNMOS device 820

[0071] 815N Drain of the single-layer gate N-type νLGNMOS device 820

[0072] 815P Drain of the single-layer gate P-type vLGPMOS device 810

[0073] 820, 1320 Single-layer gate N-type νLGNMOS devices

[0074] 850 Floating gate inverter device

[0075] 1000, 1400 Excitatory νLGCMOS circuits

[0076] 1010 Single-layer gate νLGCMOS device

[0077] 1020, 1440 CMOS inverter devices

[0078] 1200 Processing system

[0079] 1201 Input node

[0080] 1202, 1203 Output nodes

[0081] 1204 Digital output node

[0082] 1210 Analog vLGMOS circuit section

[0083] 1220 Digital processing circuit

[0084] 1221 Digital input terminal

[0085] 1222 Digital output terminal

[0086] 1230 Analog-to-digital converter circuit section

[0087] 1210 Analog vLGMOS circuit section

[0088] 1220 Digital Processing Circuit

[0089] Source of 1311 and 1411 single-layer gate P-type vLGPMOS devices

[0090] Source of 1321 and 1421 single-layer gate N-type vLGNMOS devices

[0091] 1330 Floating Gate Inverter Device

[0092] 1430 vLGCMOS Inverter Detailed Description of the Invention

[0093] The following detailed description of the νLGMOS circuit layout fabricated by CMOS logic process technology is only an example and not a limitation. It should be understood that other embodiments can be used, and for different CMOS devices (such as planar devices, fin field effect transistor (FinFET) devices, and gate all around devices, etc.) fabricated in different generations of CMOS logic process technology, component changes can be made, and all should fall within the scope of the claims of the present invention. More particularly, it should be understood that the phraseology and terminology used in this specification are for illustration only and not for limitation. Those skilled in the art should understand that the embodiments of the methods and diagrams in this specification are only examples and not limitations. Those skilled in the art who understand the spirit of the present invention from the disclosure of this specification can use other embodiments, and all should fall within the scope of the claims of the present invention.

[0094] From the perspective of information processing, an analog νMOS circuit can "analogically and logically" analyze multiple input analog information related to the output analog information without going through multiple computational steps, similar to the information processing of a biological nervous system, i.e., the well-known single-step feed-forward mechanism in the industry. In contrast, a digital arithmetic processor for analyzing input information relies on multiple computational steps executed by a set of program instructions (algorithm). The power consumption of information extraction performed by an analog vMOS circuit is considered to be much lower than that of a digital circuit driven by a high-frequency clock, especially for the multiple computational steps simultaneously carried out by a multi-input and multi-output information processor with high dimensions. To develop an efficient information processor with better power consumption, there is an urgent need for a vMOS circuit to process multiple input signal fields generated by multiple sensor arrays to represent a set of concise information, and this set of concise information is represented by a set of digital data (bit symbols), so that the number of computational processing steps for the final information extraction generated by the digital processor can be significantly reduced. For this purpose, the vMOS circuit should be designed to: first analyze the input analog signal field, then filter out the unwanted analog signals and noise, in order to generate a set of concise digital data of the expected information from the sensor array field, thereby minimizing the computational steps of subsequent digital processing. The significantly reduced digital processing computational steps can not only save the overall processing power consumption, but also save the huge memory space of the random access memory (RAM) in the digital arithmetic processor.

[0095] On the other hand, because the double-gate process of existing vMOS devices and circuits (developed especially for floating-gate non-volatile memories such as EEPROM, NOR flash memories, and NAND flash memories) is incompatible with the single-gate CMOS logic process developed specifically for digital circuit manufacturing, the incompatible processes are a reason hindering the idea of "combining vMOS circuit processors and digital circuit processors to pursue the best value of information processor efficiency". The ability to fabricate IC chips using the same CMOS logic process to combine digital circuits and vMOS circuits can not only provide a way to build an efficient information processor for various applications, but also reduce the overall chip manufacturing cost. This application discloses an innovative single-gate vLG (neuron logic gate) MOS device, which is fabricated using industrial-standard CMOS logic process technology for neuron circuit design. Therefore, circuit design tools, such as device SPICE models and circuit simulators developed for industrial-standard CMOS logic process technology, can be used to perform vLGMOS circuit simulation and emulation of the present invention. At the same time, use the industrial-standard CMOS logic process technology of the wafer foundry to design and manufacture an IC chip processor that can include an analog vLGMOS processor circuit and a digital processor circuit, achieving optimized power and cost to meet various applications. Meanwhile, the analog circuit processor constructed by the vLGMOS-like circuit system architecture of the present invention inspired by the biological neural circuit system architecture of "from sensing to higher-order consciousness (neural feedforward system)", together with the biological memory / biological decision-making system (neural feedback loop), can be explored, simulated, fabricated, and developed into a physical IC chip for applications in the biomedical field.

[0096] In one aspect of the present invention, a productive application of an analog processor (constructed with vLGMOS circuits) is demonstrated. The inventors apply neuron logic gate N-type metal oxide semiconductor (vLGNMOS) circuits, neuron logic gate P-type metal oxide semiconductor (vLGPMOS) circuits, and neuron logic gate complementary metal oxide semiconductor (vLGCMOS) circuits to generate a sigmoidal voltage function, which is a basic activation function when simulating neural operations in neural networks. The activation function is introduced as the neural activation behavior in neural network simulation, especially used at multiple input ends and multiple levels of training neural networks, and the training neural network is a deep neural network (DNN) in the field of machine learning of the well-known artificial neural network algorithm in the industry. In fact, Cybenko has mathematically proven the approximation function theorem: A multi-layer feedforward network with hidden layers and sigmoidal activation functions is a universal function approximator (Cybenko, G (1989). “Approximation by superpositions of a sigmoidal function”. Mathematics of Control, Signals, and Systems. 2(4): pp. 303-314). This published literature indicates that any given function can be approximated by a neural circuit network with sigmoidal activation functions. Since the numerical values of the sigmoidal function in neural network simulation are generated by digital operations, most of the computing resources need to be provided for the numerical sigmoidal function in neural network simulation. The number of bits applied to neural network simulation has always been a trade-off between numerical accuracy and computing resources. When simulating the entire neural network, increasing one bit for the numerical accuracy of the sigmoidal function will exponentially increase the burden of digital computing resources. Therefore, in an IC chip, implementing the sigmoidal voltage function with the vLGMOS circuits of the present invention to generate function values will significantly reduce the burden of digital computing resources in neural network simulation.

[0097] In another aspect of the present invention, the neural network model simulation of data analysis must include a re-normalization process for operating binary numerical values, and the re-normalization process of the digital processor consumes a large amount of computing resources. Since the analog voltage signals at all nodes of the vLGMOS circuits of the present invention will surely be limited to the high voltage rail V a and the low voltage rail V SWithin the range, the output voltage signal generated by the vLGMOS circuit of the present invention will be divided into multiple voltage levels to meet the desired bit error rate, so that when applying subsequent neural network analog data analysis, the S-shaped function values generated by the vLGMOS circuit no longer require a re-normalization process.

[0098] In another aspect of the present invention, one or more analog-to-digital converter circuits (ADCs) are used to convert the voltage levels of the output analog voltage signal generated by the vLGMOS circuit into multiple digital voltage signals of bit symbols. The above bit symbols are represented by a series of digital high voltages V DD (representing the value 1) and digital low voltages V SS (representing the value 0) for digital operations.

[0099] In another aspect of the present invention, the bit symbol representation of the output analog voltage signal generated on multiple output nodes of the vLGMOS circuit can be regarded as the response voltage state under a given state of multiple input voltage signals within a sampling time.

[0100] The relevant terms mentioned throughout the specification and claims are defined as follows, unless otherwise specifically specified in this specification. The term "double-layer gate neuron MOS device" refers to a neuron MOS device having multiple input gates and a floating gate above the substrate, such as FIGS. 1(a) and 3(a). The term "single-layer gate neuron MOS device" refers to a neuron MOS device having a floating gate above the substrate and multiple input gates embedded in the substrate, such as FIG. 3(b). Among them, the above neuron MOS device is a floating gate device, which uses multiple input gates to control the voltage on the floating gate to control the on / off state of the floating gate device. By using the above multiple input gates, the above neuron MOS device operates very similar to a biological neuron.

[0101] The existing double-layer gate N-type vMOS device shown in FIG. 1(a) was disclosed by Shibata et al., and a double-layer gate process was used to fabricate one layer of input gate 120 and another layer of floating gate 110. The main idea of converting the double-layer gate (multiple input gates and a floating gate) vMOS device 30A into a single-layer gate vLGMOS device 30B is to replace the N-type polysilicon input gate with an N-type semiconductor silicon input gate embedded in a P-type semiconductor silicon substrate, where the P-type semiconductor silicon substrate is a typical starting silicon substrate in CMOS logic process technology. FIGS. 3(a) and 3(b) respectively show schematic diagrams of the double-layer gate N-type νMOS device 30A and the single-layer gate N-type νLGMOS device 30B, where highly doped N-type (N +)A semiconductor forms a source region 310 and a drain region 320 within a P-type substrate 300, and a P-type channel region 330 located under a conductive floating gate 340 is separated by a gate dielectric 331 having a gate capacitance value C NM in the double-gate vMOS device 30A and the single-gate vLGMOS device 30B. The n input gates (35(1), 35(2),..., 35(n)) are respectively coupled to the conductive floating gate 340 through coupling dielectrics 341 having capacitance values (C1, C2,..., C n ). In the N-type vLGMOS device 30B of FIG. 3(b), the N-type semiconductor input gates (35(1), 35(2),..., 35(n)) embedded in the P-type substrate 300 are electrically insulated from each other in such a way that "they are surrounded by a field isolation dielectric 360 on the side and form an N / P junction through an N-type semiconductor and the P-type substrate at the bottom 370". FIGS. 3(c) and 3(d) respectively show schematic diagrams of the equivalent circuit topologies of the double-gate N-type vMOS device 30A and the single-gate N-type vLGMOS device 30B.

[0102] To be compatible with CMOS logic circuits, the present invention uses a single-gate N-type vLGMOS device and a pull-up loading element, a single-gate P-type vLGMOS device and a pull-down loading element, and a single-gate complementary vLGCMOS device to establish different vLGMOS circuits to generate an inverted S-shaped voltage function. The above-mentioned inverted S-shaped voltage function is regarded as an inhibitory activation function corresponding to the inhibitory firing behavior of neurons, while the S-shaped voltage function used in neural network simulation corresponds to the excitatory activation function of the excitatory firing behavior of neurons. By reversing the output voltage of the inverted S-shaped voltage function through a CMOS inverter, the inverted S-shaped voltage function can be converted into an S-shaped voltage function.

[0103] Figure 4 In, the inhibitory νLGNMOS circuit 400 includes a single-gate N-type vLGNMOS device 410 and a load element 420 connected in series, and is biased between a high voltage rail V a and a low voltage rail V S . The source 411 and the P-type substrate electrode 412 of the single-gate N-type vLGNMOS device 410 are connected to the ground potential V S(=0), and the drain 413 of the single-layer gate N-type vLGNMOS device 410 is connected to the node of the load element 420 to form an output node 422. As for the other node 421 of the load element 420, it is biased at the high voltage rail V a . The coupling capacitance value C between the floating gate 414 and the MOS device 410 NM , and the coupling capacitance values between the floating gate 414 and n input gate electrodes (415(1),..., 415(n)) are respectively (C S1 , …, C Sn ). The voltage potential V of the floating gate 414 f is calculated as follows:

[0104] V f =(C s1 / C T )V s1 +…+(C sn / C T )V sn +(C NM / C T )V S (=0),

[0105] where, (V S1 , …, V Sn ) represents the voltages applied to the n input gates, and the total coupling capacitance value C of the channel region and the input gate electrodes (415(1),..., 415(n)) with respect to the floating gate 414 T =C s1 +…+C sn +C NM . According to the floating gate voltage V of the N-type νLGNMOS device 410 in series with the load element 420 f and the voltage transfer function V O =f(V f ), the output voltage V on the node 413 or 422 can be obtained O . When the floating gate voltage V f is greater than the critical voltage V of the vLGNMOS device th0 , it will turn on the N-type νLGNMOS device 410 to pull down the output voltage V O to the ground voltage V S . The output voltage V O is between the high voltage rail V a and the ground voltage V S . For example, Figure 5 shows the critical voltages V of the N-type νLGNMOS device 410 th0 (curve 500), V th1 (curve 501) and V th2(Curve 502) floating gate voltage V f For the output voltage V O The voltage transfer function V O = f(V f ), where V th0 < V th1 < V th2 The load element 420 is implemented using an N-type MOSFET device in a diode-connected configuration and V lth represents the threshold voltage of the above N-type MOSFET device. Note that the load element 420 includes, but is not limited to, a resistor, a MOSFET device in a diode-connected configuration, or a biased MOSFET device to allow current to flow through the N-type νLGNMOS device 410 to pull down the output voltage potential V O from the high voltage (V a - V lth ) to the ground voltage V S . The voltage transfer function of the suppression type vLGNMOS circuit 400 with the diode-connected configuration MOSFET device load element 420 with pull-up is a reverse voltage transfer function with an input voltage variable, and the above input voltage variable is calculated as follows:

[0106] V f = (C s1 / C T )V s1 + … + (C sn / C T )V sn + (C NM / C T )V S (= 0).

[0107] Furthermore, since the floating gate 414 of the N-type vLGNMOS device 410 is electrically insulated from the external electrode, storing charge in the isolated floating gate 414 of the N-type νLGNMOS device 410 will cause the voltage transfer function curves (500, 501, 502) to shift parallel, as Figure 5 shown. According to the charge conservation law of the floating gate, the right shift voltage amount ΔV of the negatively charged electrons (curves 501, 502) from the intrinsic voltage transfer function curve 500 (no charge in the floating gate 414) is calculated as follows: ΔV = -q / (C s1 + … + C sn ), where q represents the amount of charge stored in the floating gate 414, and (C s1 + … + C sn) is the total coupling capacitance value of the input gate electrodes (415(1),..., 415(n)) with respect to the floating gate 414. The above-mentioned right-shift voltage amount ΔV is the function bias variable of the inverse S-shaped function.

[0108] Figure 6 In it, the inhibitory vLGPMOS circuit 600 includes a single-layer gate P-type vLGNMOS device 610 and a load element 620 connected in series, which are biased between the high voltage rail V a and the low voltage rail V S . The source 611 and the N-type well electrode 612 of the single-layer gate P-type vLGPMOS device 610 are biased to the high voltage rail V a , and the drain 613 of the single-layer gate P-type vLGPMOS device 610 is connected to the node 622 of the load element 620 to form an output node 613. As for the other node 621 of the load element 620, it is connected to the ground potential V S . The coupling capacitance value C PM between the floating gate 614 and the vLGNMOS device 610, and the coupling capacitance values between the floating gate 614 and the n input gate electrodes (615(1),..., 615(n)) are respectively (C S1 , …, C Sn ). The voltage potential V f of the floating gate 614 is calculated as follows:

[0109] V f =(C s1 / C T )V s1 +…+(C sn / C T )V sn +(C PM / C T )V a =(C s1 / C T )(V s1 -V a )+…+(C sn / C T )(V sn -V a )+V a ,

[0110] where, (V S1 , …, V Sn ) are the voltages applied to the n input gates, and the total coupling capacitance value C T of the channel region and the input gate electrodes (615(1),..., 615(n)) with respect to the floating gate 614 = C s1 +…+C sn +C PM。

[0111] According to the floating gate voltage V of the P-type vLGPMOS device 610 in series with the load element 610 f and the voltage conversion function V O = f(V f ), the output voltage V on node 613 or 622 can be obtained O . When the floating gate voltage V f is less than the voltage (V a - V th ), the P-type vLGPMOS device 610 will be turned on to pull up the output voltage V O , from the critical voltage V of the diode-connected configuration N-type MOSFET device lth pulled up to the high voltage rail V a , where V th is the critical voltage of the P-type νLGPMOS device 610. The output voltage V O is between the high voltage rail V a and the ground voltage V S . For example, Figure 7 shows the voltage transfer function V of the floating gate voltage V th0 (curve 700), V th1 (curve 701) and V th2 (curve 702) with respect to the output voltage V f , where V O = f(V O ), where V f < V th0 < V th1 < V th2 , the load element 620 is implemented using a diode-connected configuration N-type MOSFET device and V lth represents the critical voltage of the above N-type MOSFET device. Note that the load element 620 includes, but is not limited to, a resistor, a diode-connected configuration MOSFET device, or a biased MOSFET device, to allow current to flow through the P-type νLGPMOS device 610 and pull up the output voltage potential V O from the critical voltage V lth to the high voltage rail V a . The voltage transfer function of the suppression type vLGPMOS circuit 600 with a pull-down diode-connected configuration MOSFET device load element is an inverse voltage transfer function with an input voltage variable, and the above input voltage variable is calculated as follows:

[0112] V f = (C s1 / C T ) V s1+…+(C sn / C T )V sn +(C PM / C T )V a

[0113] =(C s1 / C T )(V s1 -V a )+…+(C sn / C T )(V sn -V a )+V a 。

[0114] Furthermore, since the floating gate 614 of the P-type νLGPMOS device 610 is electrically insulated from the external electrode, storing charge in the isolated floating gate 614 of the P-type vLGPMOS device 610 will cause the voltage transfer function curves (700, 701, 702) to shift parallel, as Figure 7 shown. According to the law of conservation of charge in the floating gate, the amount of voltage shift ΔV of the negatively charged electrons (curves 701, 702) from the intrinsic voltage transfer function curve 700 (no charge in the floating gate 614) to the right is calculated as follows: ΔV = -q / (C s1 +…+C sn ), where q represents the amount of charge stored in the floating gate 614, and (C s1 +…+C sn ) is the total coupling capacitance value of the input gate electrodes (615(1),..., 615(n)) with respect to the floating gate 614. The above voltage shift amount ΔV to the right is the function bias variable of the inverse S-shaped function.

[0115] Figure 8 In, the suppression-type vLGCMOS circuit 800 includes a floating gate inverter device 850, which includes a single-layer gate P-type vLGPMOS device 810 and a single-layer gate N-type vLGNMOS device 820 connected in series. The source 811 and the N-well electrode 812 of the single-layer gate P-type vLGPMOS device 810 are biased to the high voltage rail V a , while the source 813 and the P-type substrate electrode 814 of the single-layer gate N-type vLGNMOS device 820 are connected to the ground potential V S (=0). The drain 815P of the single-layer gate P-type vLGPMOS device 810 and the drain 815N of the single-layer gate N-type vLGNMOS device 820 are connected to form a node 815 to generate an output voltage V O . The conductive floating gate 816 forms a capacitive coupling with the floating gate inverter device 850 with a PMOS capacitance value C PM and an NMOS capacitance value CNM , the conductive floating gate 816 forms a capacitive coupling with the input gate electrodes (817(1),..., 817(n)) with capacitance values (C s1 ,..., C sn ). The voltage potential V f of the floating gate 816 is calculated as follows:

[0116] V f = (C s1 / C T )V s1 + … + (C sn / C T )V sn + (C PM / C T )V a + (C NM / C T )V S (=0),

[0117] where, (V S1 , …, V Sn ) is the voltage applied to the n input gates, and the total coupling capacitance value C T of the two channel regions and the input gate electrodes (817(1),..., 817(n)) with respect to the floating gate 816 s1 = C sn + … + C PM + C NM .

[0118] According to the floating gate voltage V f of the vLGCMOS inverter device 850 and the voltage transfer function V O = f(V f ), the output voltage V O on the node 815 can be obtained. The characteristic curve of the voltage transfer function (curve 900) of the vLGCMOS inverter device 850 is an inverse S-shaped voltage function, as Figure 9 shown. At the same time, because the floating gate 816 of the vLGCMOS inverter device 850 is electrically insulated from the external electrode, storing charge in the floating gate 816 of the P-type vLGCMOS inverter device 850 will cause the voltage transfer function curves (901, 902, 903) to shift parallel, as Figure 9 shown. According to the law of charge conservation of the floating gate, the voltage shift amount ΔV shifted to the right from the essential voltage transfer function curve 900 (no charge in the floating gate 816) is calculated as follows: ΔV = -q / (C s1 + … + C sn ), where q represents the amount of charge stored in the floating gate 816, and (C s1 + … + Csn ) is the total coupling capacitance value of the input gate electrodes (817(1),..., 817(n)) with respect to the floating gate 816. Figure 9 In this case, since electrons (negative charges) are stored in the floating gate 816, the voltage transfer function curve shifts from the no-charge curve 900 to the curves (901, 902, 903) to the right, where 0 < ΔV1 < ΔV2 < ΔV3 corresponds to 0 < -q1 < -q2 < -q3. The reverse S-shaped function generated by the inhibitory νLGCMOS circuit 800 is the voltage transfer function of the floating gate inverter device 850 with the input voltage variable:

[0119] V f = (C s1 / C T )V s1 + … + (C sn / C T )V sn + (C PM / C T )V a + (C NM / C T )V S ( = 0),

[0120] and the voltage bias: ΔV = -q / (C s1 + … + C sn ).

[0121] The above two voltage variables (V f , ΔV) are the function variables of the reverse S-shaped function.

[0122] To convert the inhibitory S-shaped voltage function into an excitatory S-shaped function, a CMOS inverter device is added to reverse all the output voltage signals. For example, Figure 10 shows that the excitatory vLGCMOS circuit 1000 includes a single-layer gate vLGCMOS device 1010 and a CMOS inverter device 1020. The floating gate 1016 forms a capacitive coupling with the vLGCMOS device 1010 with PMOS capacitance value C PM and NMOS capacitance value C NM , and the floating gate 1016 forms a capacitive coupling with the input gate electrodes (1011(1),..., 1011(n)) with capacitance values (C s1 ,..., C sn ). The output node 1012 of the vLGCMOS device 1010 is connected to the input gate 1021 of the CMOS inverter device 1020. Therefore, the excitatory S-shaped voltage function generated by the excitatory vLGCMOS circuit 1000 is as Figure 11 shown, where, V th0(Curve 1100) < V th1 (Curve 1101) < V th2 (Curve 1102). The voltage potential V of the floating gate 1016 f is obtained according to the function input voltage variable and is calculated as follows:

[0123] V f = (C s1 / C T ) V s1 + … + (C sn / C T ) V sn + (C PM / C T ) V a + (C NM / C T ) V S (= 0),

[0124] and the voltage bias: ΔV = -q / (C s1 + … + C sn ), where q represents the amount of electric charge stored in the floating gate 1016, and (C s1 + … + C sn ) is the total coupling capacitance value of the input gate electrodes (1011(1),..., 1011(n)) relative to the floating gate 1016. The above two voltage variables (V f , ΔV) are the function variables of the sigmoid voltage function used in neural network simulation.

[0125] Figure 12 A schematic diagram showing a processing system with a vLGMOS circuit, which is used to optimize the processing efficiency. The processing system 1200 includes an analog vLGMOS circuit section 1210, an analog-to-digital converter (ADC) circuit section 1230, a plurality of digital input terminals 1221, a digital processing circuit 1220, and a plurality of digital output terminals 1222, and can be fabricated into an IC chip using industrial standard CMOS logic process technology; wherein, the analog νLGMOS circuit section 1210 includes at least one vLGMOS circuit 400 / 600 / 800 / 1000. A plurality of analog voltage signals (V ia1 ,..., V ian ) are fed into the input node 1201 of the analog vLGMOS circuit section 1210 to generate a plurality of output analog voltage signals (V oa1 ,..., V oam), where n and m >= 1. Thereafter, the ADC circuit section 1230 includes at least one ADC that converts an analog voltage signal (V oa1 ,..., V oam ) into a plurality of bit symbols with a plurality of digital voltage signals according to a plurality of voltage signal levels or respective resolutions. Thereafter, the plurality of digital voltage signals of the above bit symbols are represented by a plurality of strings of digital high voltage V DD (representing the value 1) and digital low voltage V SS (representing the value 0), and are fed into the digital input terminal 1221. The digital processing circuit 1220 includes a digital processor and a program memory (not shown in the figure). The program memory stores a plurality of instructions / program codes for the digital processor to execute, causing the digital processor to be configured to perform digital operations on the digital data input from the digital input terminal 1221 and output the processed digital data to the digital output terminal 1222 on the output node 1202. The above digital processor includes, but is not limited to, a general-purpose processor, a special-purpose processor, or a combination of the above two processors.

[0126] Figure 13 A top view of an inhibitory complementary νLGCMOS circuit 800 fabricated with CMOS logic process technology and having 4 input gates is shown. The inhibitory complementary vLGCMOS circuit 1300 includes a single-layer gate P-type vLGPMOS device 1310 and a single-layer gate N-type vLGNMOS device 1320. The source 1311 and the N-well electrode 1312 of the single-layer gate P-type vLGPMOS device 1310 are biased to the high voltage rail V a , while the source 1321 and the P-substrate electrode 1322 of the single-layer gate N-type vLGNMOS device 1320 are connected to the ground potential V S (= 0). The drains of the single-layer gate P-type vLGPMOS device 1310 and the single-layer gate N-type vLGNMOS device 1320 are connected through a metal / contact to form a node 1315 to generate an output voltage V O . The conductive floating gate 1316 extends from the regions of the vLGPMOS device 1310 and the vLGNMOS device 1320 to the input electrode region, forming a capacitive coupling with the floating gate inverter device 1330 with a PMOS capacitance value C PM and an NMOS capacitance value C NM , and the electrical floating gate 1316 forms a capacitive coupling with a plurality of input gates (1317(1), 1317(2), 1317(3), 1317(4)) with input electrode capacitance values (C1, C2, C3, C4). The voltage potential V f of the floating gate 1316 is calculated as follows:

[0127] Vf = (C1 / C T )V1 + (C2 / C T )V2 + (C3 / C T )V3 + (C4 / C T )V4 + (C PM / C T )V a + (C NM / C T )V S ( = 0),

[0128] where (V1, V2, V3, V4) are the voltages applied to the four input gates, and the total coupling capacitance values C T = C1 + C2 + C3 + C4 + C PM + C NM .

[0129] Note that by neglecting parasitic capacitances, the capacitance value ratios can be approximately calculated according to the area overlap ratios of the floating gate region 1316 with the PMOS region (PA), NMOS region (NA), and input electrode regions (A1, A2, A3, A4).

[0130] Figure 14 Shows a top view of an excitatory complementary vLGCMOS circuit 1000 fabricated in a CMOS logic process technology and having four input gates. The excitatory complementary vLGCMOS circuit 1400 includes a single-layer gate vLGCMOS inverter 1430 and a CMOS inverter 1440. The single-layer gate vLGCMOS inverter 1430 includes a single-layer gate P-type vLGPMOS device 1410 and a single-layer gate N-type vLGNMOS device 1420 connected in series. The CMOS inverter 1440 includes an input gate 1446, a source electrode 1441 of the PMOS, and a source electrode 1442 of the NMOS, where the source electrode 1441 of the PMOS and the source electrode 1442 of the NMOS are biased to a high voltage V a and the ground potential V S . The output node 1435 of the vLGCMOS inverter 1430 is connected to the input gate 1446 of the conventional CMOS inverter 1440 to invert the output voltage signal from the vLGCMOS inverter 1430 into an output voltage signal V O at the output node 1445. The conductive floating gate 1416 extends from the regions of the vLGPMOS device 1410 and the vLGNMOS device 1420 to the input electrode region, forming a capacitive coupling with the floating gate inverter device 1430 with a PMOS capacitance value CPM and the NMOS capacitance value C NM , and the electrically floating gate 1416 forms capacitive coupling with a plurality of input gates (1417(1), 1417(2), 1417(3), 1417(4)) with input electrode capacitance values (C1, C2, C3, C4). The voltage potential V of the floating gate 1416 f is calculated as follows:

[0131] V f =(C1 / C T )V1+(C2 / C T )V2+(C3 / C T )V3+(C4 / C T )V4+(C PM / C T )V a

[0132] +(C NM / C T )V S (=0),

[0133] where (V1, V2, V3, V4) are the voltages applied to the 4 input gates, and the total coupling capacitance value C of the two channel regions and the input gate electrodes (1417(1),..., 1417(4)) with respect to the floating gate 1416 T =C1 + C2 + C3 + C4 + C PM +C NM .

[0134] Note that by ignoring the parasitic capacitance values, the capacitance value ratios can be approximately calculated according to the area overlap ratios of the floating gate region with the PMOS region (PA), NMOS region (NA), and input electrode regions (A1, A2, A3, A4).

[0135] The preferred embodiments provided above are only used to illustrate the present invention, rather than limiting the present invention to a specific type or exemplary embodiment. Therefore, this specification should be regarded as illustrative rather than restrictive. The preferred embodiments provided above are for effectively illustrating the gist of the present invention and its best mode of implementation and application, so as to enable those skilled in the art to understand the various embodiments and various modifications of the present invention to adapt to specific uses or implementation purposes. The scope of the present invention is defined by the claims and their equivalents, and all terms are intended to have the broadest reasonable meaning, unless otherwise specifically indicated. Therefore, terms such as "the present invention" do not limit the scope of the claims to a specific embodiment, and moreover, any reference to a specific preferred embodiment of the present invention does not imply a limitation of the present invention, and no such limitation is presumed. The present invention is only defined by the scope and spirit of the claims. The abstract of the present invention is provided in accordance with the requirements of the regulations so that searchers can quickly confirm the subject matter of this technical disclosure from any patent approved by this specification, and is not used to interpret or limit the scope and meaning of the claims. Any advantages and benefits may not apply to all embodiments of the present invention. It should be understood that those skilled in the art can make various deformations or changes, which should all fall within the scope of the present invention defined by the claims. Furthermore, all elements and components in this specification are not intended to be dedicated to the public, regardless of whether these elements and components are listed in the claims.

Claims

1. A processing system for receiving a plurality of input analog voltages and generating one or more digital output values, characterized in that, Comprising: An analog circuit including at least one metal-oxide-semiconductor (MOS) circuit, each MOS circuit including a first single-layer gate neuron MOS device having a plurality of input gates, wherein each MOS circuit is used to model one of a sigmoid function and a reverse sigmoid function to generate an output analog voltage in response to one or more of the plurality of input analog voltages applied to the plurality of input gates; A conversion circuit coupled to the analog circuit and including one or more analog-to-digital converters (ADCs), each ADC performing analog-to-digital conversion on a corresponding output analog voltage according to its own resolution to generate a digital value; And A digital processor for performing digital processing operations on one or more digital values from the conversion circuit to generate the one or more digital output values; Wherein, the analog circuit, the conversion circuit, and the digital processor are fabricated using an industrial standard complementary metal-oxide-semiconductor (CMOS) logic process technology to form one or more integrated circuit chips.

2. The system according to claim 1, wherein The range of the output analog voltage is limited by two different operating voltages carried by an operating voltage terminal and a ground voltage terminal, and the operating voltage terminal and the ground voltage terminal are coupled to the analog circuit.

3. The system according to claim 1, characterized in that, One of the at least one MOS circuit is used to model the reverse sigmoid function and includes: A load element; and The first single-layer gate neuron MOS device, connected in series with the load element through an output node, and generating the output analog voltage at the output node.

4. The system according to claim 3, wherein The reverse sigmoid function is equivalent to the output analog voltage at the output node being a function of a voltage potential on a floating gate of the first single-layer gate neuron MOS device in one of the at least one MOS circuit.

5. The system according to claim 4, wherein The voltage potential on the floating gate is related to one or more of the plurality of input analog voltages, two different operating voltages of the analog circuit, and a plurality of capacitance values of the plurality of input gates and a channel region relative to the floating gate in the first single-layer gate neuron MOS device.

6. The system according to claim 1, wherein One of the at least one MOS circuit is used to model the reverse sigmoid function and includes: The first single-layer gate neuron MOS device; and A second single-layer gate neuron MOS device, wherein the first single-layer gate neuron MOS device and the second single-layer gate neuron MOS device are connected in series to form a single-layer gate neuron CMOS device including the plurality of input gates, a floating gate, a first channel region, and a second channel region.

7. The system according to claim 6, wherein The reverse sigmoid function of one of the at least one MOS circuit is equivalent to the output analog voltage at an output node of the first single-layer gate neuron CMOS device being a function of a voltage potential on the floating gate.

8. The system according to claim 7, wherein The voltage potential on the floating gate is related to one or more of the plurality of input analog voltages, two different operating voltages of the analog circuit, and a plurality of capacitance values of the plurality of input gates, the first channel region, and the second channel region relative to the floating gate.

9. The system according to claim 1, wherein One of the at least one MOS circuit is used to model the S-shaped function and includes: The first single-layer gate neuron MOS device; A second single-layer gate neuron MOS device, wherein the first single-layer gate neuron MOS device and the second single-layer gate neuron MOS device are connected in series to form a single-layer gate neuron CMOS device; and A CMOS inverter, wherein an input node of the CMOS inverter is connected to an output node of the single-layer gate neuron CMOS device, and an output node of the CMOS inverter generates the output analog voltage.

10. The system according to claim 9, wherein The single-layer gate neuron CMOS device includes the plurality of input gates, a floating gate, a first channel region, and a second channel region, wherein the S-shaped function of one of the at least one MOS circuit is equivalent to the output analog voltage on the output node of the CMOS inverter being a function of a voltage potential on the floating gate, and wherein the voltage potential on the floating gate is related to one or more of the plurality of input analog voltages, two different operating voltages of the analog circuit, and a plurality of capacitance values of the plurality of input gates, the first channel region, and the second channel region with respect to the floating gate.

11. The system according to claim 1, characterized in that, The first single-layer gate neuron MOS device is formed in a substrate of a first conductivity type and includes: A source region of a second conductivity type formed in the substrate; A drain region of the second conductivity type formed in the substrate; A channel region between the source region and the drain region; The plurality of input gates of the second conductivity type formed in the substrate; and A floating gate disposed above the channel region and the plurality of input gates and insulated from the channel region and the plurality of input gates.

12. The system according to claim 11, wherein For one of the at least one MOS circuit, A right shift amount of a current voltage transfer curve relative to an intrinsic voltage transfer curve depends on the amount of charge stored in the floating gate and a total capacitance value of the plurality of input gates with respect to the floating gate; wherein the current voltage transfer curve corresponds to one of the S-shaped function and the inverse S-shaped function; and wherein the intrinsic voltage transfer curve corresponds to no electrons being stored in the floating gate of the first single-layer gate neuron MOS device included in one of the at least one MOS circuit.

13. The system according to claim 1, characterized in that, The analog circuit is simulated and fabricated into the one or more integrated circuit chips for applications in the biomedical field.

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