Path optimization method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention provides a path optimization method and device, a storage medium and electronic equipment, and the method comprises the steps: inserting a first pipeline register into a first position of a first time sequence path, so as to divide the first time sequence path into a second time sequence path and a third time sequence path, inserting the first pipeline register into a first position of the first time sequence path; under the condition that the second time sequence path and the third time sequence path have violation time sequence paths, moving the first pipeline register to a second position of the first time sequence path so as to divide the first time sequence path into a fourth time sequence path and a fifth time sequence path; determining a first number of violation time sequence paths in the fourth time sequence path and the fifth time sequence path; and determining the fourth time sequence path and the fifth time sequence path as target time sequence paths under the condition that the first number meets a preset condition.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of communications, and more specifically, to a path optimization method and device, a storage medium, and an electronic device. Background Art

[0002] At present, the most commonly used combinatorial logic optimization method is to simplify the combinatorial logic circuit by designing an algorithm to find the optimal solution between input and output, or to insert a pipe register (pipe reg) in the path that cannot be optimized to interrupt the path (path). However, in the early stage of design, the actual physical layout, the actual routing and the actual voltage drop, as well as the structure of the clock tree are unknown. Therefore, the timing obtained in the early stage of design will be different from that in the later stage. Relying on the front-end optimization algorithm to optimize the combinatorial logic is not an efficient method. It is necessary to correctly screen out the timing path caused by the excessive length of the combinatorial logic in the physical implementation stage, and optimize the combinatorial logic path in a targeted manner. In addition, the position of the pipe reg inserted by the front end cannot be determined. It is necessary to optimize the position of the pipe reg insertion in the physical implementation stage to repair as many violation paths as possible.

[0003] Therefore, in the related art, the problem that the synthesis tool cannot repair the timing path of the timing violation caused by the excessive depth of the combinational logic level has not yet been effectively solved. Summary of the invention

[0004] The embodiments of the present application provide a path optimization method and device, a storage medium, and an electronic device to at least solve the problem in the related art that the timing path with timing violations caused by too deep a combinational logic level cannot be repaired using a synthesis tool.

[0005] According to an embodiment of the present application, a path optimization method is provided, specifically comprising: performing a first path optimization on a first timing path to divide the first timing path into a second timing path and a third timing path, wherein the first path optimization on the first timing path is used to indicate that a first pipeline register is inserted into a first position of the first timing path, the second timing path is a timing path between a starting point of the first timing path and the first position, and the third timing path is a timing path between the first position and an end point of the first timing path; in the case where there is a violation timing path between the second timing path and the third timing path, performing a first path optimization on the first timing path Perform a second path optimization to divide the first timing path into a fourth timing path and a fifth timing path, wherein the second path optimization performed on the first timing path is used to indicate moving the first pipeline register to a second position of the first timing path, the fourth timing path is a timing path between a starting point of the first timing path and the second position, and the fifth timing path is a timing path from the second position to an end point of the first timing path; determine a first number of violation timing paths in the fourth timing path and the fifth timing path; and determine the fourth timing path and the fifth timing path as target timing paths when the first number meets a preset condition.

[0006] In an exemplary embodiment, before performing a first path optimization on a first timing path, the method further includes: sending a first command to the first timing path to determine whether the first timing path includes a combinational logic unit, wherein the first timing path includes: a plurality of units; in the case where it is determined that the first timing path includes the combinational logic unit, determining a delay value corresponding to each combinational logic unit, and determining a sum of delay values ​​corresponding to all combinational logic units in the first timing path; sending a second command to the first timing path to determine a violation value corresponding to the first timing path; determining a first size relationship between the sum value and the violation value; and in the case where the first size relationship indicates that the sum value is greater than the violation value, determining to perform a first path optimization on the first timing path.

[0007] In an exemplary embodiment, before performing a second path optimization on the first timing path, the method further includes: determining a second number of violation timing paths in the second timing path and the third timing path, and determining whether the second number meets the preset condition; if it is determined that the second number does not meet the preset condition, determining that there are violation timing paths in the second timing path and the third timing path; if it is determined that the second number meets the preset condition, determining that there are no violation timing paths in the second timing path and the third timing path.

[0008] In an exemplary embodiment, before determining the fourth timing path and the fifth timing path as target timing paths, the method further includes: when it is determined that the first quantity is equal to the target value, determining that the first quantity meets the preset condition; when it is determined that the first quantity is not equal to the target value, determining that the first quantity does not meet the preset condition.

[0009] In an exemplary embodiment, after determining a first number of violating timing paths in the fourth timing path and the fifth timing path, the method further includes: determining a second size relationship between the first number and the second number when it is determined that the first number does not meet the preset condition, wherein the second number is the number of violating timing paths in the second timing path and the third timing path; and determining the target timing path based on the second size relationship.

[0010] In an exemplary embodiment, determining the target timing path according to the second size relationship includes: when the second size relationship indicates that the first number is greater than the second number and the second number is not equal to the target value, performing a third path optimization on the first timing path to divide the first timing path into a sixth timing path and a seventh timing path, wherein the third path optimization performed on the first timing path is used to indicate moving the first pipeline register to a third position of the first timing path, the sixth timing path is a timing path between a starting point of the first timing path and the third position, and the seventh timing path is a timing path from the third position to an end point of the first timing path; determining a third number of violation timing paths in the sixth timing path and the seventh timing path; and determining the sixth timing path and the seventh timing path as the target timing path when it is determined that the third number meets the preset condition.

[0011] In an exemplary embodiment, determining the target timing path according to the second size relationship includes: when the second size relationship indicates that the first quantity is less than or equal to the second quantity, moving the first pipeline register to the first position, and determining the target violation timing path in the second timing path and the third timing path; performing a first path optimization on the target violation timing path to divide the target violation timing path into an eighth timing path and a ninth timing path, wherein the first path optimization performed on the target violation timing path is used to indicate that the second pipeline register is inserted into the fourth position in the target violation timing path, the eighth timing path is the timing path between the starting point of the target violation timing path and the fourth position, and the ninth timing path is the timing path between the fourth position and the end point of the target violation timing path; based on the target violation timing path The method comprises the steps of: performing a second path optimization on the first timing path to divide the target violation timing path into a tenth timing path and an eleventh timing path, wherein the second path optimization on the target violation timing path is used to indicate moving the second pipeline register to the fifth position of the target violation timing path, the tenth timing path is a timing path between a starting point of the target violation timing path and the fifth position, and the eleventh timing path is a timing path between the fifth position and an end point of the target violation timing path; determining a fourth number of violation timing paths in the tenth timing path and the eleventh timing path; and determining the tenth timing path, the eleventh timing path, and other timing paths in the second timing path and the third timing path except the target violation timing path as the target timing path when it is determined that the fourth number meets the preset condition.

[0012] According to another embodiment of the present application, a path optimization device is provided, comprising: a first optimization module, configured to perform a first path optimization on a first timing path, so as to divide the first timing path into a second timing path and a third timing path, wherein the first path optimization on the first timing path is used to indicate that a first pipeline register is inserted into a first position of the first timing path, the second timing path is a timing path between a starting point of the first timing path and the first position, and the third timing path is a timing path between the first position and an end point of the first timing path; and a second optimization module, configured to perform a first path optimization on the first timing path in the case where a violation timing path exists between the second timing path and the third timing path. A second path optimization is performed to divide the first timing path into a fourth timing path and a fifth timing path, wherein the second path optimization performed on the first timing path is used to indicate that the first pipeline register is moved to a second position of the first timing path, the fourth timing path is a timing path between a starting point of the first timing path and the second position, and the fifth timing path is a timing path from the second position to an end point of the first timing path; a first determining module is used to determine a first number of violating timing paths in the fourth timing path and the fifth timing path; and a second determining module is used to determine the fourth timing path and the fifth timing path as target timing paths when the first number meets a preset condition.

[0013] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps in the above method embodiment when running.

[0014] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in the above method embodiment.

[0015] According to another embodiment of the present application, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiment are implemented.

[0016] Through the path optimization method of the present application, the first path optimization is performed on the first timing path, that is, the first pipeline register is inserted into the first position in the first timing path to divide the first timing path into the second timing path and the third timing path; when there are violation paths in the second timing path and the third timing path, the first pipeline register is moved from the first position of the first timing path to the second position to divide the first timing path into the fourth timing path and the fifth timing path, and at this time, the first number of violation paths in the fourth timing path and the fifth timing path is determined. When it is determined that the first number meets the preset condition, the fourth timing path and the fifth timing path can be determined as the target timing paths. That is, in the present application, by inserting the first pipeline register into the first position of the first timing path, it is determined whether there is a violation path in the two timing path clocks divided after the insertion of the first position. In the case of determining that there is a violation path, it is determined that the first position may not be the best position of the first pipeline register in the first timing path. At this time, the first pipeline register can be moved from the first tail to the second position, and then it is determined whether the first number of violation paths in the fourth timing path and the fifth timing path divided when the first pipeline register is inserted into the second position meets the preset conditions. In the case of determining that the first number meets the preset conditions, the second position is determined to be the best position of the first pipeline register in the first path, and the fourth timing path and the fifth timing path can be determined as the target timing path. Through the embodiment of the present application, the position of the first pipeline register inserted into the first timing path can be accurately determined, and the problem of too deep combinational logic levels of the first timing path can be solved, that is, the embodiment of the present application can solve the problem in the related art that the timing path with timing violations caused by too deep combinational logic levels cannot be repaired using synthesis tools. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a hardware structure block diagram of a computer terminal of a path optimization method according to an embodiment of the present application;

[0018] Figure 2 is a flow chart of a path optimization method according to an embodiment of the present application;

[0019] Figure 3 is a flow chart of a dynamic timing optimization algorithm for too deep a combinational logic level according to an optional embodiment of the present application;

[0020] Figure 4 is a schematic diagram (I) after inserting a pipe reg according to an optional embodiment of the present application;

[0021] Figure 5 is a schematic diagram (II) after the pipe reg is inserted according to an optional embodiment of the present application;

[0022] Figure 6 is a schematic diagram of moving a pipe reg to further repair a timing path violation according to an optional embodiment of the present application;

[0023] Figure 7 It is a structural block diagram of a path optimization device according to an embodiment of the present application. DETAILED DESCRIPTION

[0024] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0025] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0026] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking running on a computer terminal as an example, Figure 1 1 is a hardware structure block diagram of a computer terminal of a path optimization method according to an embodiment of the present application. Figure 1 As shown, the computer terminal may include one or more ( Figure 1 Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer terminal. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0027] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for determining the interactive state in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories can be connected to the computer terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0028] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a computer terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0029] Figure 2 is a flow chart of a path optimization method according to an embodiment of the present application, which can be applied to Figure 1 In a computer terminal, such as Figure 2 As shown, the process includes the following steps:

[0030] Step S202, performing a first path optimization on the first timing path to divide the first timing path into a second timing path and a third timing path, wherein the first path optimization on the first timing path is used to indicate that a first pipeline register is inserted into a first position of the first timing path, the second timing path is a timing path between a starting point of the first timing path and the first position, and the third timing path is a timing path between the first position and an end point of the first timing path;

[0031] Among them, the above-mentioned first position can be the middle position of the first timing path, that is, the first pipeline register is inserted into the middle position of the first timing path, and the second timing path between the starting point of the first timing path and the middle position of the first timing path, and the third timing path from the middle position of the first timing path to the end point of the first timing path are determined.

[0032] Step S204: in the case where there is a violation timing path between the second timing path and the third timing path, performing a second path optimization on the first timing path to divide the first timing path into a fourth timing path and a fifth timing path, wherein the second path optimization on the first timing path is used to indicate moving the first pipeline register to a second position of the first timing path, the fourth timing path is a timing path between a starting point of the first timing path and the second position, and the fifth timing path is a timing path from the second position to an end point of the first timing path;

[0033] It can be understood that, when it is determined that there is a violation timing path in the second timing path and the third timing path, it means that the first position may not be the best position of the first pipeline register in the first timing path, and therefore, the first pipeline register can be moved from the first position to the second position. The second position can be a position that is one unit forward or one unit backward from the first position.

[0034] Step S206, determining a first number of violating timing paths in the fourth timing path and the fifth timing path;

[0035] Step S208: When the first number meets a preset condition, determine the fourth timing path and the fifth timing path as target timing paths.

[0036] It can be understood that none of the target timing paths are violating paths.

[0037] Through the path optimization method of the present application, the first path optimization is performed on the first timing path, that is, the first pipeline register is inserted into the first position in the first timing path to divide the first timing path into the second timing path and the third timing path; when there are violation paths in the second timing path and the third timing path, the first pipeline register is moved from the first position of the first timing path to the second position to divide the first timing path into the fourth timing path and the fifth timing path, and at this time, the first number of violation paths in the fourth timing path and the fifth timing path is determined. When it is determined that the first number meets the preset condition, the fourth timing path and the fifth timing path can be determined as the target timing paths. That is, in the present application, by inserting the first pipeline register into the first position of the first timing path, it is determined whether there is a violation path in the two timing path clocks divided after the insertion of the first position. In the case of determining that there is a violation path, it is determined that the first position may not be the best position of the first pipeline register in the first timing path. At this time, the first pipeline register can be moved from the first tail to the second position, and then it is determined whether the first number of violation paths in the fourth timing path and the fifth timing path divided when the first pipeline register is inserted into the second position meets the preset conditions. In the case of determining that the first number meets the preset conditions, the second position is determined to be the best position of the first pipeline register in the first path, and the fourth timing path and the fifth timing path can be determined as the target timing path. Through the embodiment of the present application, the position of the first pipeline register inserted into the first timing path can be accurately determined, and the problem of too deep combinational logic levels of the first timing path can be solved, that is, the embodiment of the present application can solve the problem in the related art that the timing path with timing violations caused by too deep combinational logic levels cannot be repaired using synthesis tools.

[0038] Optionally, before performing the first path optimization on the first timing path in the above step S202, the method further includes: sending a first command to the first timing path to determine whether the first timing path includes a combinational logic unit, wherein the first timing path includes: multiple units; in the case where it is determined that the first timing path includes the combinational logic unit, determining a delay value corresponding to each combinational logic unit, and determining a sum of the delay values ​​corresponding to all the combinational logic units in the first timing path; sending a second command to the first timing path to determine a violation value corresponding to the first timing path; determining a first size relationship between the sum value and the violation value; and in the case where the first size relationship indicates that the sum value is greater than the violation value, determining to perform the first path optimization on the first timing path.

[0039] It is understandable that before performing the first path optimization on the first timing path, it is necessary to determine whether the first timing path includes a combinational logic unit and whether the first timing path is a timing path with too many levels of combinational logic units. Specifically:

[0040] A first command is sent to a first timing path, the first command is used to determine whether the first timing path includes a combinational logic unit. When it is determined that the first timing path includes a combinational logic unit, it is necessary to determine the delay value corresponding to each combinational logic unit included in the first timing path, and whether the first timing path is a timing path with too deep a combinational logic unit level can be determined based on a first size relationship between the sum of the delay values ​​and the violation value corresponding to the first timing path. When the sum of the delay values ​​is greater than the violation value corresponding to the first timing path, it is determined that the first timing path is a timing path with too deep a combinational logic unit level; when the sum of the delay values ​​is less than or equal to the violation value corresponding to the first timing path, it is determined that the first timing path is not a timing path with too deep a combinational logic unit level.

[0041] According to the above embodiment, it is determined whether the first timing path is a timing path with too deep a number of combinational logic units, so as to determine whether the first timing path can be solved by a tool. If the tool cannot solve the problem, the first timing path is optimized by the embodiment of the present application. That is, by timely discovering and eliminating the violation path, the accuracy and efficiency of the path optimization can be improved, and the performance and reliability of the system can be finally improved.

[0042] Optionally, before performing a second path optimization on the first timing path in the above-mentioned step S204, the method further includes: determining a second number of violation timing paths in the second timing path and the third timing path, and determining whether the second number meets the preset condition; if it is determined that the second number does not meet the preset condition, determining that there are violation timing paths in the second timing path and the third timing path; if it is determined that the second number meets the preset condition, determining that there are no violation timing paths in the second timing path and the third timing path.

[0043] Optionally, before determining the fourth timing path and the fifth timing path as target timing paths in the above step S208, the method further includes: when it is determined that the first quantity is equal to the target value, determining that the first quantity meets the preset condition; when it is determined that the first quantity is not equal to the target value, determining that the first quantity does not meet the preset condition.

[0044] It is understandable that before performing the second path optimization on the first timing path, a judgment process needs to be performed, that is, judging whether the second timing path and the third timing path divided after the first path optimization on the first timing path contain a violation path. Specifically:

[0045] Determine a second number of violation timing paths in the second timing path and the third timing path, and determine whether the second timing path and the third timing path include a violation path according to whether the second number meets a preset condition. If it is determined that the second timing path and the third timing path include a violation path, it is necessary to perform a second path optimization on the first timing path.

[0046] In addition, after the second path optimization is performed on the first timing path, a judgment process needs to be performed, that is, whether the fourth timing path and the fifth timing path divided after the second path optimization contain a violation path. When it is determined that the fourth timing path and the fifth timing path do not contain a violation path, it is determined that the optimization of the first timing path is completed.

[0047] Through the above technical solution, it can be known that whether the above second number meets the preset condition, that is, whether there is a violation timing path in the second timing path and the third timing path, that is, whether the second number is 0; whether the above first number meets the preset condition, that is, whether there is a violation timing path in the fourth timing path and the fifth timing path, that is, whether the first number is 0.

[0048] Through the optional embodiments of the present application, the risk of timing urgency and timing failure can be reduced, and the problem of timing non-convergence can be solved.

[0049] Optionally, after determining the first number of violating timing paths in the fourth timing path and the fifth timing path in the above step S206, the method further includes: when it is determined that the first number does not meet the preset condition, determining a second size relationship between the first number and the second number, wherein the second number is the number of violating timing paths in the second timing path and the third timing path; and determining the target timing path based on the second size relationship.

[0050] It can be understood that after the first pipeline register is moved from the first position to the second position, it is necessary to determine a second size relationship between the first quantity and the second quantity, and determine the target timing path according to the second size relationship, specifically:

[0051] (1) determining the target timing path according to the second size relationship, comprising: when the second size relationship indicates that the first number is greater than the second number and the second number is not equal to the target value, performing a third path optimization on the first timing path to divide the first timing path into a sixth timing path and a seventh timing path, wherein the third path optimization on the first timing path is used to indicate moving the first pipeline register to a third position of the first timing path, the sixth timing path is a timing path between a starting point of the first timing path and the third position, and the seventh timing path is a timing path from the third position to an end point of the first timing path; determining a third number of violation timing paths in the sixth timing path and the seventh timing path; and determining the sixth timing path and the seventh timing path as the target timing path when it is determined that the third number meets the preset condition.

[0052] It can be known from the above technical solution that when it is determined that the first number is greater than the second number, it is determined whether the second number is 0. When it is determined that the second number is not equal to 0, the first timing path is optimized for the third time, that is, the moving direction of the first pipeline register in the first timing path is determined according to the first position and the second position, and the first pipeline register is moved one unit along the moving direction to the third position of the first pipeline register. After the first pipeline register moves to the third position, the third number of illegal disrepair paths in the sixth timing path and the seventh timing path divided by the first disrepair path is determined, and it is determined whether the third number meets the preset conditions. At this time, it can be divided into three cases:

[0053] 1) The third number meets the preset condition, that is, the third number is 0, that is, there is no violation timing path in the sixth timing path and the seventh timing path. At this time, the sixth timing path and the seventh timing path can be determined as the target timing path.

[0054] 2) The third number does not meet the preset condition, and the third number is smaller than the first number. In this case, the technical solution of (1) needs to be executed until it is determined that there is no violating path in the two divided timing paths, or the number of violating paths in the two divided timing paths is greater than the first number.

[0055] 3) The third number does not meet the preset condition and is smaller than the first number. In this case, the second position is determined to be the optimal position of the first pipeline register in the first timing path. In this case, the target timing path needs to be determined according to the method of step (1).

[0056] Through the embodiments of the present application, the moving direction of the first pipeline register in the first timing path is determined more effectively, thereby avoiding the occurrence of a violation and out-of-repair path and making the timing path converge.

[0057] (2) determining the target timing path according to the second size relationship, comprising: when the second size relationship indicates that the first quantity is less than or equal to the second quantity, moving the first pipeline register to the first position, and determining a target violation timing path in the second timing path and the third timing path; performing a first path optimization on the target violation timing path pair to divide the target violation timing path into an eighth timing path and a ninth timing path, wherein the first path optimization on the target violation timing path is used to indicate that the second pipeline register is inserted into a fourth position in the target violation timing path, the eighth timing path being a timing path between a starting point of the target violation timing path and the fourth position, and the ninth timing path being a timing path between the fourth position and an end point of the target violation timing path; optimizing the target violation timing path pair based on the target violation timing path pair. The first timing path is subjected to a second path optimization to divide the target violation timing path into a tenth timing path and an eleventh timing path, wherein the second path optimization performed on the target violation timing path is used to indicate that the second pipeline register is moved to the fifth position of the target violation timing path, the tenth timing path is a timing path between the starting point of the target violation timing path and the fifth position, and the eleventh timing path is a timing path between the fifth position and the end point of the target violation timing path; determining a fourth number of violation timing paths in the tenth timing path and the eleventh timing path; and when it is determined that the fourth number meets the preset condition, determining the tenth timing path, the eleventh timing path, and other timing paths in the second timing path and the third timing path except the target violation timing path as the target timing path.

[0058] When it is determined that the first number is less than or equal to the second number, the first position is determined to be the optimal position of the first pipeline register in the first timing path. At this time, the second pipeline register needs to be inserted into the fourth position of the target violation timing path in the second timing path and the third timing path. The fourth position can be the middle position in the target violation timing path, and the target violation timing path is optimized according to the method of step S202-step S208.

[0059] According to the embodiment of the present application, the timing is optimized by inserting pipe reg to rearrange the timing, and the interrupted path is further optimized to achieve fast iteration and reduce the running time.

[0060] In order to better understand the process of the optimization method of the above path, the implementation process of the optimization method of the above path is described below in combination with an optional embodiment, but it is not used to limit the technical solution of the embodiment of the present application.

[0061] At present, with the continuous development of process technology, the feature size continues to decrease, and the timing convergence of chips is becoming more and more difficult. Whether the timing of integrated circuits converges determines whether the circuit can work properly. In theory, timing optimization is mainly abstracted as the analysis and design of two circuits: combinational logic circuits and sequential logic circuits. As an important content in logic circuit analysis and design, one of the main research contents of combinational logic circuit optimization is to simplify the truth table or logic function expression that describes the logic circuit. Electronic design automation tools are often used in industry to optimize logic circuits, but with the advent of the big data era, circuits are more integrated and larger in scale, and the optimization algorithm of combinational logic circuits is also facing new opportunities and challenges. As a part of digital logic circuits, combinational logic circuits can only find the optimal solution between their logic input and output to ensure the lowest energy consumption when the hardware is the same, while improving the reliability of the circuit.

[0062] In the related art, relying on the front-end optimization algorithm to optimize the combinatorial logic is not an efficient method. It is necessary to correctly screen out the timing path caused by the excessively long combinatorial logic in the physical implementation stage, and optimize the combinatorial logic path in a targeted manner. In addition, the position of the pipe reg inserted by the front end cannot be determined, and it is necessary to optimize the position of the pipe reg insertion in the physical implementation stage to repair as many violation paths as possible.

[0063] In response to the above problems, an optional embodiment of the present application provides a dynamic timing optimization algorithm for combinatorial logic levels that are too deep. Specifically: a logic synthesis tool (EDA tool) is used to screen out the delay value (delay value) of the combinatorial logic unit on a specific path, and compared with the violation value of the path to screen out the path of the combinatorial logic that needs to be optimized. For these timing violation paths, the method of inserting pipe reg for timing rearrangement is used to interrupt the combinatorial logic in the path, shorten the original path, and achieve the timing optimization effect. A dynamic optimization algorithm is also proposed, which quickly updates the timing results in the physical implementation stage, dynamically adjusts the position of the pipe reg according to the timing results of the previous step, and further optimizes the timing of the interrupted path to achieve fast iteration and reduce running time. Specifically:

[0064] The optional embodiment of the present application provides a timing repair method. To solve the problem of too much combinatorial logic in the timing path and too deep logic levels, the paths with too deep combinatorial logic levels are found by calculating the levels of combinatorial logic in the timing path and the corresponding delay. In addition, timing repair is performed on these paths by inserting pipe reg and dynamically adjusting its position. The present invention has two main focuses. One is to report all illegal timing paths and locate the paths that cause violations due to too deep combinatorial logic levels. The other is to use a dynamic iterative algorithm based on the characteristics of these timing paths to insert pipe reg and dynamically adjust its position for timing repair, so as to finally meet the timing requirements.

[0065] Figure 3 is a flow chart of a dynamic timing optimization algorithm for too deep combinational logic levels according to an optional embodiment of the present application, such as Figure 3 As shown:

[0066] Step S301, calculating the sum of the combinatorial logic delay values ​​on the path.

[0067] Use the report_timing command (a command) of the synthesis tool, in conjunction with options such as {-max_paths / -slack_lesser_than (used to indicate options)}, to report all paths with timing violations. The timing report can be processed to obtain the slack ((time) relaxation) value (i.e., the delay value of this application) of each of these timing paths. Take one of them as an example for processing. Suppose this path is A, its slack value is a, and there are × cells on this path. Traverse each cell on this path, and use the get_cells-filter "is_combinational == true" (a command) command (i.e., the first command of this application) to filter whether this cell is combinatorial logic. If it is combinatorial logic, it is recorded as Ci, and if it is not combinatorial logic, it is recorded as Bi. The number of elements in set C (the elements in set C are Ci) is the depth of the combinatorial logic level on this path.

[0068] Step S302, determining whether the Delay value is greater than the slack value of the entire path.

[0069] During the process of timing optimization, the synthesis tool may add / delete buffers, adjust the placement of units, etc., but it cannot reduce the number of combinational logic units. That is, the timing violation caused by the problem of too deep combinational logic levels cannot be repaired by the tool. Use the tool to report the delay value of Ci and add all the delay values. If the combinational logic delay value is greater than the slack value a, then this path is a path that the tool cannot repair. That is, when: In this case, this path is a path that cannot be repaired by the tool. Perform the above calculation on all the paths that violate the rules. If they meet the above formula, they are marked as the target paths for optimization. So far, the timing violation paths caused by too deep combinational logic levels have been successfully screened out.

[0070] That is, when it is determined that the Delay value is greater than the slack value of the entire path, step S303 is executed; when it is determined that the Delay value is less than or equal to the slack value of the entire path, step S309 is executed.

[0071] Step S303, inserting a pipe reg (ie, the first pipe register of the present application) in the middle of the path (ie, the first timing path of the present application) (ie, the first position of the present application).

[0072] Under the premise of not affecting the logic function of the circuit, a pipe reg is inserted into the paths of these violations. The insertion position of pipereg is exactly in the middle of the path. Figure 4 is a schematic diagram (I) after inserting pipe reg according to an optional embodiment of the present application, such as Figure 4As shown, inserting pipe reg will interrupt the original path. Figure 4 The path A in is the original path. Figure 4 Path B in the figure is the path after the pipe reg is inserted. ○ indicates the sequential logic on the original path, and the combinational logic in the middle is too long. ★ indicates the newly inserted pipe reg.

[0073] After inserting pipe reg, the original path becomes two new paths (i.e., the second timing path and the third timing path of the present application), and the originally long combinational logic is interrupted. In the same clock cycle, the number of combinational logic is less, and the introduced delay is smaller, which is conducive to timing convergence. Therefore, inserting pipe reg can effectively reduce the timing violation caused by the excessive depth of the combinational logic level.

[0074] Step S304, determining whether the timing is repaired.

[0075] After inserting pipe reg, re-analyze the timing. If the timing converges, the timing is fixed, and the optimization is complete. If the timing still does not converge, proceed to the following dynamic optimization steps.

[0076] That is, it is determined whether the timing is repaired. If it is repaired, step S310 is executed. If it is determined that the timing is not repaired, step S305 is executed.

[0077] Step S305, moving the direction of the timing violation to pipe reg.

[0078] For paths that still do not meet the timing requirements after inserting pipe reg, use the following optimization algorithm to dynamically adjust the position of pipe reg.

[0079] Figure 5 is a schematic diagram (II) after inserting pipe reg according to an optional embodiment of the present application, such as Figure 5 As shown, the method of step S302 continues to screen out the paths that cause violations due to the excessive depth of the combinational logic level. At this time, these paths should have the following two situations: ① The starting point is the newly inserted pipe reg; ② The end point is the newly inserted pipe reg. Figure 4 Path A in is divided into Figure 5 The two paths in .

[0080] Figure 6 is a schematic diagram of further repairing a timing path violation by moving a pipe reg according to an optional embodiment of the present application, such as Figure 6 As shown in the figure, ○ represents the sequential logic on the original path, and the middle is the overlong combinational logic. The dotted line ☆ represents the original position of the inserted pipe reg, and ★ represents the moved pipe reg.

[0081] Step S306, determine whether the number of violation paths decreases.

[0082] If it is determined that the number of violation paths decreases, execute Step S307. If it is determined that the number of violation paths does not decrease, return the position of the pipe reg to the position of Step S303.

[0083] Step S307, determine whether the timing is repaired.

[0084] If it is determined that the timing is repaired, end the process. If it is determined that the timing is not repaired, execute Step S308.

[0085] Step S308, continue to move the pipe reg.

[0086] That is, if a > b, it proves that moving the pipe reg is effective. At this time, the pipe reg can be moved according to Case ① and Case ② for the violation paths reported in Step S303 until a < b or all violation paths are repaired.

[0087] If a < b, it proves that moving the pipe reg will bring more violations, and the current position of the pipe reg is already optimal. Restore the moved pipe reg to the previous position. Insert the pipe reg in the middle of these a paths in the manner of Step S303, and repeat Steps S301 - S308 until all violation paths are repaired.

[0088] Step S309, non-target path, end the process.

[0089] Step S310, optimization ends.

[0090] An optional embodiment of the present application provides a timing repair method. Aiming at the problems of too much combinational logic and too deep logic levels in the timing path, by calculating the levels of combinational logic and the corresponding delays in the timing path, the paths with too deep combinational logic levels are found. Timing repair is performed on these paths by inserting and adjusting the pipe reg. And a dynamic optimization algorithm is proposed to quickly update the timing results in the physical implementation stage, dynamically adjust the position of the pipe reg according to the timing results of the previous step, and perform further timing optimization on the interrupted paths to achieve fast iteration and shorten the project cycle.

[0091] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0092] In this embodiment, a path optimization device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0093] Figure 7 is a structural block diagram of a path optimization device according to an embodiment of the present application, such as Figure 7 As shown, the device comprises:

[0094] A first optimization module 72 is used to perform a first path optimization on a first timing path to divide the first timing path into a second timing path and a third timing path, wherein the first path optimization performed on the first timing path is used to indicate that a first pipeline register is inserted into a first position of the first timing path, the second timing path is a timing path between a starting point of the first timing path and the first position, and the third timing path is a timing path between the first position and an end point of the first timing path;

[0095] A second optimization module 74 is used for performing a second path optimization on the first timing path in the case where there is a violation timing path between the second timing path and the third timing path, so as to divide the first timing path into a fourth timing path and a fifth timing path, wherein the second path optimization on the first timing path is used to indicate that the first pipeline register is moved to a second position of the first timing path, the fourth timing path is a timing path between a starting point of the first timing path and the second position, and the fifth timing path is a timing path from the second position to an end point of the first timing path;

[0096] A first determining module 76, configured to determine a first number of violating timing paths in the fourth timing path and the fifth timing path;

[0097] The second determining module 78 is configured to determine the fourth timing path and the fifth timing path as target timing paths when the first number meets a preset condition.

[0098] Through the path optimization device of the present application, the first path optimization is performed on the first timing path, that is, the first pipeline register is inserted into the first position in the first timing path to divide the first timing path into the second timing path and the third timing path; when there are violation paths in the second timing path and the third timing path, the first pipeline register is moved from the first position of the first timing path to the second position to divide the first timing path into the fourth timing path and the fifth timing path, and at this time, the first number of violation paths in the fourth timing path and the fifth timing path is determined. When it is determined that the first number meets the preset conditions, the fourth timing path and the fifth timing path can be determined as target timing paths. That is, in the present application, by inserting the first pipeline register into the first position of the first timing path, it is determined whether there is a violation path in the two timing path clocks divided after the insertion of the first position. In the case of determining that there is a violation path, it is determined that the first position may not be the best position of the first pipeline register in the first timing path. At this time, the first pipeline register can be moved from the first tail to the second position, and then it is determined whether the first number of violation paths in the fourth timing path and the fifth timing path divided when the first pipeline register is inserted into the second position meets the preset conditions. In the case of determining that the first number meets the preset conditions, the second position is determined to be the best position of the first pipeline register in the first path, and the fourth timing path and the fifth timing path can be determined as the target timing path. Through the embodiment of the present application, the position of the first pipeline register inserted into the first timing path can be accurately determined, and the problem of too deep combinational logic levels of the first timing path can be solved, that is, the embodiment of the present application can solve the problem in the related art that the timing path with timing violations caused by too deep combinational logic levels cannot be repaired using synthesis tools.

[0099] In an exemplary embodiment, the first optimization module 72 is further used to send a first command to the first timing path to determine whether the first timing path includes a combinational logic unit, wherein the first timing path includes: a plurality of units; in the case where it is determined that the first timing path includes the combinational logic unit, determining a delay value corresponding to each combinational logic unit, and determining a sum of delay values ​​corresponding to all combinational logic units in the first timing path; sending a second command to the first timing path to determine a violation value corresponding to the first timing path; determining a first size relationship between the sum value and the violation value; and in the case where the first size relationship indicates that the sum value is greater than the violation value, determining to perform a first path optimization on the first timing path.

[0100] In an exemplary embodiment, the second optimization module 74 is further used to determine a second number of violation timing paths in the second timing path and the third timing path, and determine whether the second number meets the preset condition; if it is determined that the second number does not meet the preset condition, determine that there are violation timing paths in the second timing path and the third timing path; if it is determined that the second number meets the preset condition, determine that there are no violation timing paths in the second timing path and the third timing path.

[0101] In an exemplary embodiment, the second determination module 78 is further used to determine that the first quantity meets the preset condition when it is determined that the first quantity is equal to the target value; and to determine that the first quantity does not meet the preset condition when it is determined that the first quantity is not equal to the target value.

[0102] In an exemplary embodiment, the first determination module 76 is further used to determine a second size relationship between the first number and the second number when it is determined that the first number does not meet the preset condition, wherein the second number is the number of violating timing paths in the second timing path and the third timing path; and determine the target timing path according to the second size relationship.

[0103] In an exemplary embodiment, the first determination module 76 is further used to perform a third path optimization on the first timing path when the second size relationship indicates that the first quantity is greater than the second quantity and the second quantity is not equal to the target value, so as to divide the first timing path into a sixth timing path and a seventh timing path, wherein the third path optimization performed on the first timing path is used to indicate moving the first pipeline register to a third position of the first timing path, the sixth timing path is a timing path between the starting point of the first timing path and the third position, and the seventh timing path is a timing path from the third position to the end point of the first timing path; determine a third number of violation timing paths in the sixth timing path and the seventh timing path; and determine the sixth timing path and the seventh timing path as the target timing paths when it is determined that the third number meets the preset condition.

[0104] In an exemplary embodiment, the first determination module 76 is further used to move the first pipeline register to the first position when the second size relationship indicates that the first quantity is less than or equal to the second quantity, and determine the target violation timing path in the second timing path and the third timing path; perform a first path optimization on the target violation timing path to divide the target violation timing path into an eighth timing path and a ninth timing path, wherein the first path optimization performed on the target violation timing path is used to indicate that the second pipeline register is inserted into the fourth position in the target violation timing path, the eighth timing path is the timing path between the starting point of the target violation timing path and the fourth position, and the ninth timing path is the timing path between the fourth position and the end point of the target violation timing path; based on the target violation timing path, the The first timing path is subjected to a second path optimization to divide the target violation timing path into a tenth timing path and an eleventh timing path, wherein the second path optimization performed on the target violation timing path is used to indicate moving the second pipeline register to the fifth position of the target violation timing path, the tenth timing path is a timing path between the starting point of the target violation timing path and the fifth position, and the eleventh timing path is a timing path between the fifth position and the end point of the target violation timing path; determining a fourth number of violation timing paths in the tenth timing path and the eleventh timing path; and determining the tenth timing path, the eleventh timing path, and other timing paths in the second timing path and the third timing path except the target violation timing path as the target timing path when it is determined that the fourth number meets the preset condition.

[0105] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps in the above method embodiment when running.

[0106] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0107] Optionally, in this embodiment, the storage medium may be configured to store program codes for executing the following steps:

[0108] S1, performing a first path optimization on a first timing path to divide the first timing path into a second timing path and a third timing path, wherein the first path optimization on the first timing path is used to indicate inserting a first pipeline register into a first position of the first timing path, the second timing path is a timing path between a starting point of the first timing path and the first position, and the third timing path is a timing path between the first position and an end point of the first timing path;

[0109] S2, in the case where there is a violation timing path between the second timing path and the third timing path, performing a second path optimization on the first timing path to divide the first timing path into a fourth timing path and a fifth timing path, wherein the second path optimization on the first timing path is used to indicate moving the first pipeline register to a second position of the first timing path, the fourth timing path is a timing path between a starting point of the first timing path and the second position, and the fifth timing path is a timing path from the second position to an end point of the first timing path;

[0110] S3, determining a first number of violating timing paths in the fourth timing path and the fifth timing path;

[0111] S4: When the first number meets a preset condition, determine the fourth timing path and the fifth timing path as target timing paths.

[0112] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in the above method embodiment.

[0113] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0114] Optionally, in this embodiment, the processor may be configured to perform the following steps through a computer program:

[0115] S1, performing a first path optimization on a first timing path to divide the first timing path into a second timing path and a third timing path, wherein the first path optimization on the first timing path is used to indicate inserting a first pipeline register into a first position of the first timing path, the second timing path is a timing path between a starting point of the first timing path and the first position, and the third timing path is a timing path between the first position and an end point of the first timing path;

[0116] S2, in the case where there is a violation timing path between the second timing path and the third timing path, performing a second path optimization on the first timing path to divide the first timing path into a fourth timing path and a fifth timing path, wherein the second path optimization on the first timing path is used to indicate moving the first pipeline register to a second position of the first timing path, the fourth timing path is a timing path between a starting point of the first timing path and the second position, and the fifth timing path is a timing path from the second position to an end point of the first timing path;

[0117] S3, determining a first number of violating timing paths in the fourth timing path and the fifth timing path;

[0118] S4: When the first number meets a preset condition, determine the fourth timing path and the fifth timing path as target timing paths.

[0119] An embodiment of the present application further provides a computer program product, including a computer program, which is implemented to perform the steps in the above method embodiment when executed by a processor.

[0120] Optionally, in this embodiment, the computer program product may be executed by a processor to perform the following steps:

[0121] S1, performing a first path optimization on a first timing path to divide the first timing path into a second timing path and a third timing path, wherein the first path optimization on the first timing path is used to indicate inserting a first pipeline register into a first position of the first timing path, the second timing path is a timing path between a starting point of the first timing path and the first position, and the third timing path is a timing path between the first position and an end point of the first timing path;

[0122] S2, in the case where there is a violation timing path between the second timing path and the third timing path, performing a second path optimization on the first timing path to divide the first timing path into a fourth timing path and a fifth timing path, wherein the second path optimization on the first timing path is used to indicate moving the first pipeline register to a second position of the first timing path, the fourth timing path is a timing path between a starting point of the first timing path and the second position, and the fifth timing path is a timing path from the second position to an end point of the first timing path;

[0123] S3, determining a first number of violating timing paths in the fourth timing path and the fifth timing path;

[0124] S4: When the first number meets a preset condition, determine the fourth timing path and the fifth timing path as target timing paths.

[0125] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0126] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0127] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A path optimization method, characterized in that: include: Performing a first path optimization on a first timing path to divide the first timing path into a second timing path and a third timing path, wherein the first path optimization on the first timing path is used to indicate inserting a first pipeline register into a first position of the first timing path, the second timing path is a timing path between a starting point of the first timing path and the first position, and the third timing path is a timing path between the first position and an end point of the first timing path; In the case where there is a violation timing path between the second timing path and the third timing path, performing a second path optimization on the first timing path to divide the first timing path into a fourth timing path and a fifth timing path, wherein the second path optimization on the first timing path is used to indicate moving the first pipeline register to a second position of the first timing path, the fourth timing path is a timing path between a starting point of the first timing path and the second position, and the fifth timing path is a timing path from the second position to an end point of the first timing path; determining a first number of violating timing paths in the fourth timing path and the fifth timing path; When the first number meets a preset condition, the fourth timing path and the fifth timing path are determined as target timing paths.

2. The method according to claim 1, characterized in that Before performing a first path optimization on the first timing path, the method further includes: Sending a first command to the first timing path to determine whether the first timing path includes a combinational logic unit, wherein the first timing path includes: a plurality of units; In the case where it is determined that the first timing path includes the combinational logic unit, determining a delay value corresponding to each combinational logic unit, and determining a sum of the delay values ​​corresponding to all the combinational logic units in the first timing path; Sending a second command to the first timing path to determine a violation value corresponding to the first timing path; Determine a first magnitude relationship between the sum value and the violation value; When the first size relationship indicates that the sum value is greater than the violation value, it is determined to perform a first path optimization on the first timing path.

3. The method according to claim 1, characterized in that Before performing a second path optimization on the first timing path, the method further includes: Determine a second number of violating timing paths in the second timing path and the third timing path, and determine whether the second number meets the preset condition; In the case where it is determined that the second number does not meet the preset condition, determining that there is a violation timing path between the second timing path and the third timing path; When it is determined that the second number meets the preset condition, it is determined that there is no violation timing path between the second timing path and the third timing path.

4. The method according to claim 1, characterized in that: Before determining the fourth timing path and the fifth timing path as target timing paths, the method further includes: In the case where it is determined that the first quantity is equal to the target value, determining that the first quantity meets the preset condition; When it is determined that the first quantity is not equal to the target value, it is determined that the first quantity does not meet the preset condition.

5. The method according to claim 1, characterized in that After determining a first number of violating timing paths in the fourth timing path and the fifth timing path, the method further includes: In the case where it is determined that the first number does not meet the preset condition, determining a second size relationship between the first number and the second number, wherein the second number is the number of illegal timing paths in the second timing path and the third timing path; The target timing path is determined according to the second size relationship.

6. The method according to claim 5, characterized in that Determining the target timing path according to the second size relationship includes: When the second size relationship indicates that the first quantity is greater than the second quantity, and the second quantity is not equal to the target value, performing a third path optimization on the first timing path to divide the first timing path into a sixth timing path and a seventh timing path, wherein the third path optimization on the first timing path is used to indicate moving the first pipeline register to a third position of the first timing path, the sixth timing path is a timing path between a starting point of the first timing path and the third position, and the seventh timing path is a timing path from the third position to an end point of the first timing path; determining a third number of violating timing paths in the sixth timing path and the seventh timing path; In a case where it is determined that the third number meets the preset condition, the sixth timing path and the seventh timing path are determined as the target timing paths.

7. The method according to claim 5, characterized in that Determining the target timing path according to the second size relationship includes: In a case where the second size relationship indicates that the first number is less than or equal to the second number, moving the first pipeline register to the first position, and determining a target violating timing path in the second timing path and the third timing path; Performing a first path optimization on the target violation timing path pair to divide the target violation timing path into an eighth timing path and a ninth timing path, wherein the first path optimization on the target violation timing path is used to indicate inserting the second pipeline register into a fourth position in the target violation timing path, the eighth timing path is a timing path between a starting point of the target violation timing path and the fourth position, and the ninth timing path is a timing path between the fourth position and an end point of the target violation timing path; performing a second path optimization on the first timing path based on the target violation timing path to divide the target violation timing path into a tenth timing path and an eleventh timing path, wherein the second path optimization performed on the target violation timing path is used to indicate moving the second pipeline register to a fifth position of the target violation timing path, the tenth timing path is a timing path between a starting point of the target violation timing path and the fifth position, and the eleventh timing path is a timing path between the fifth position and an end point of the target violation timing path; determining a fourth number of violating timing paths in the tenth timing path and the eleventh timing path; When it is determined that the fourth number meets the preset condition, the tenth timing path, the eleventh timing path, and other timing paths among the second timing path and the third timing path except the target violation timing path are determined as the target timing path.

8. A path optimization device, characterized in that: include: A first optimization module, configured to perform a first path optimization on a first timing path, so as to divide the first timing path into a second timing path and a third timing path, wherein the first path optimization on the first timing path is used to indicate that a first pipeline register is inserted into a first position of the first timing path, the second timing path is a timing path between a starting point of the first timing path and the first position, and the third timing path is a timing path between the first position and an end point of the first timing path; a second optimization module, configured to perform a second path optimization on the first timing path in the case where there is a violation timing path between the second timing path and the third timing path, so as to divide the first timing path into a fourth timing path and a fifth timing path, wherein the second path optimization on the first timing path is used to indicate moving the first pipeline register to a second position of the first timing path, the fourth timing path is a timing path between a starting point of the first timing path and the second position, and the fifth timing path is a timing path from the second position to an end point of the first timing path; A first determining module, configured to determine a first number of violating timing paths in the fourth timing path and the fifth timing path; The second determining module is configured to determine the fourth timing path and the fifth timing path as target timing paths when the first number meets a preset condition.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method according to any one of claims 1 to 7 when executed by a processor.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

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