Flash memory-based storage and computing method and artificial intelligence integrated memory

Abstract

The present invention relates to a flash memory-based storage and computing method and an artificial intelligence integrated memory. A flash memory-type memory is provided, which has a storage transistor array. The storage transistor array is used as a carrier of a neural network weight matrix. The input data of the neural network is set to be transmitted to a series of bit lines of the storage transistor array, and the output data of the neural network is set to be captured from a series of source lines of the storage transistor array, thereby realizing flash memory-based storage and computing. Each weight in the neural network weight matrix is ​​represented by the difference in threshold voltages of a corresponding pair of complementary transistors located in the same column but arranged in two rows in the storage transistor array. The gates of any pair of complementary transistors are coupled together, and the drains of any pair of complementary transistors are coupled to the same bit line.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of data storage, and more specifically, to a flash memory-based storage and computing method and an artificial intelligence integrated memory in the field of data storage. Background Art

[0002] In previous electronic devices, computing and storage were separate. The computing component, such as the processor, and the storage component, such as hard drives or memory, each focused on their own specific tasks, with little interference between them. Integrated storage and computing organically merges storage and computing, but this also raises concerns: artificial intelligence based on neural networks involves a large number of matrix operations and requires the use of larger operators, such as operation matrices and weight matrices, to match the high computing power and fast processing speed. However, memory is limited by semiconductor manufacturing processes and cannot achieve unlimited and flexible expansion of compatible operators. For example, a larger weight matrix requires a simultaneous increase in the number of columns or rows of the transistor arrays involved in the weight matrix. Larger arrays induce larger network parasitic parameters, and the involvement of parasitic parameters in matrix operations can cause the neural network's calculation results to deviate. Summary of the Invention

[0003] The present application relates to a storage and calculation method based on flash memory, which is characterized by comprising:

[0004] Provide a memory based on a flash memory format (such as NOR-Flash) having a storage transistor array;

[0005] Using a memory transistor array as a carrier for a neural network's weight matrix, setting the neural network's input data to be transmitted to a series of bit lines of the memory transistor array, and setting the neural network's output data to be retrieved from a series of source lines of the memory transistor array, thereby achieving integrated storage and calculation based on flash memory;

[0006] In which, each weight in the weight matrix of the neural network is represented by the difference in threshold voltages of a corresponding pair of complementary transistors located in the same column but arranged in two rows in the storage transistor array, the gates of any pair of complementary transistors are coupled together, and the drains of any pair of complementary transistors are coupled on the same bit line.

[0007] In the above method, the original input data of a neural network (such as an artificial neural network) is converted into input quantities in the form of voltage values, which are then transmitted to a series of bit lines of a storage transistor array based on the input quantities sorted into vectors; any pair of complementary transistors receives the voltage value on the bit line of their column so that the difference between the drain-source voltages of the any pair of complementary transistors is the same.

[0008] In the above method, output data of a neural network is represented by the ratio of the difference in output current at the respective source lines of two rows of transistors corresponding to a row of weights divided by a preset coefficient. Any two transistors in the two rows of transistors located in the same column and sharing the same bit line are regarded as a pair of complementary transistors; and the multiple ratios provided by a series of source lines of the memory transistor array are regarded as the output quantities provided by the memory transistor array in the form of a sorted vector.

[0009] In the above-mentioned method, the manner of adjusting any weight in the weight matrix includes: changing the floating gate injection charge of each of the pair of complementary transistors selected by the any weight, adjusting the difference in the threshold voltages of the two selected complementary transistors based on the relative change in the floating gate injection charge of the two selected complementary transistors, and further adjusting the size of the weight value at the position where the selected pair of complementary transistors are located.

[0010] In the above method, a digital-to-analog converter such as a DAC is configured at the bit line of the storage transistor array, which is used to convert the input data of the neural network (for example, a digital quantity relative to an analog quantity) into a voltage value that meets the format requirements of the input signal quantity (for example, an analog signal quantity) of the bit line of the storage transistor array.

[0011] In the above method, an analog-to-digital converter such as an ADC is configured at the source line of the storage transistor array, which is used to convert the output signal in the form of an output current at the source line (such as an analog quantity usually relative to a digital quantity) into output data that meets the format requirements of the digital output quantity (such as a digital signal quantity) of the neural network.

[0012] The above method uses the combination of every two rows of transistors in the storage transistor array to define a row of weights in the weight matrix (e.g., every two rows of transistors (i.e., one combination) determines the value of a row of weights). The multiple rows of transistors in the storage transistor array provide multiple combinations. A multiplexer (MUX) is used to time-share a set of output currents at the source lines of different combinations and transmit them to a current subtractor. The current subtractor then calculates the current difference between the output currents at the source lines of the two rows of transistors corresponding to each combination.

[0013] In the above method, the address code of the multiplexer is controlled or manipulated to determine whether any combination is selected. Only a set of output currents from the two source lines of the selected combination is delivered to the current subtractor, and a set of output currents from the two source lines of the other unselected combinations are not allowed to be delivered to the current subtractor.

[0014] In the above method, when any combination is selected, the value of the address code at this time is switched to the only enable code value that can activate any combination to a valid enable code value, and a code element with a specified weight bit is selected in the enable code value. If the code element is flipped, the source lines of the two rows of transistors belonging to any combination are transiently coupled (or coupled) once through the coupling capacitor.

[0015] The present application relates to an artificial intelligence integrated memory, characterized by comprising:

[0016] Memory in the form of flash memory with an array of memory transistors used to construct a neural network implementation;

[0017] Using a memory transistor array as a carrier of a weight matrix of a neural network, setting the input data of the neural network to be transmitted to a series of bit lines of the memory transistor array, and setting the output data of the neural network to be retrieved from a series of source lines of the memory transistor array, so that the memory integrates artificial intelligence computing functions based on the neural network;

[0018] Each weight in the weight matrix of the neural network is represented by the difference in threshold voltages of a corresponding pair of complementary transistors located in the same column but arranged in two rows in the memory transistor array, the gates of any pair of complementary transistors being coupled together, and the drains of any pair of complementary transistors being coupled to the same bit line;

[0019] Among them, the original input data of the neural network is converted into input quantities in voltage value format and then transmitted to the bit lines of the storage transistor array. The difference between the output currents at the source lines of each two rows of transistors in the storage transistor array divided by the ratio of the preset coefficient is used as an output data of the neural network.

[0020] In the aforementioned artificial intelligence integrated memory, the raw input data of the neural network is converted into input quantities in the form of voltage values, which are then transmitted to a series of bit lines of the memory transistor array based on the input quantities being sorted into vectors. Any pair of complementary transistors receives the voltage value on the bit line of their column, so that the difference between the drain-source voltages of the pair of complementary transistors is the same.

[0021] In the above-mentioned artificial intelligence integrated memory, a single output data of the neural network is represented by the ratio of the difference between the output currents at the respective source lines of the two rows of transistors corresponding to a row of weights divided by a preset coefficient. Any two transistors in the two rows of transistors located in the same column and sharing the same bit line are regarded as a pair of complementary transistors; and the multiple ratios provided by a series of source lines of the storage transistor array are regarded as the output quantities sorted into vectors provided by the storage transistor array.

[0022] In the aforementioned artificial intelligence integrated memory, the method for adjusting any weight in the weight matrix includes: changing the charge injected into the floating gates of each of the complementary transistors selected by the weight, adjusting the difference in threshold voltages of the selected pair of complementary transistors based on the relative change in the charge injected into the floating gates of the selected pair of complementary transistors, and further adjusting the size of the weight value at the location of the selected pair of complementary transistors.

[0023] In the above-mentioned artificial intelligence integrated memory, a digital-to-analog converter is configured at the bit line of the storage transistor array, which is used to convert the input data of the neural network (for example, a digital quantity relative to an analog quantity) into a voltage value that meets the format requirements of the input signal quantity (for example, an analog signal quantity) of the bit line of the storage transistor array.

[0024] In the above-mentioned artificial intelligence integrated memory, an analog-to-digital converter is configured at the source line of the storage transistor array, which is used to convert the output signal in the form of an output current at the source line (such as an analog quantity relative to a digital quantity) into output data that meets the format requirements of the digital output quantity (such as a digital signal quantity) of the neural network.

[0025] In the aforementioned artificial intelligence integrated memory, the combination of every two rows of transistors in the storage transistor array defines a row of weights in the weight matrix (every two rows of transistors (i.e., one combination) determines the value of a row of weights). Multiple rows of transistors in the storage transistor array provide multiple combinations. A multiplexer (MUX) is used to time-share a set of output currents at the source lines of different combinations and transmit them to a current subtractor. The current subtractor then calculates the current difference between the output currents at the source lines of the two rows of transistors corresponding to each combination.

[0026] The above-mentioned artificial intelligence integrated memory controls the address code or selection signal of the multiplexer to determine whether any combination is selected, and only a group of output currents at the two source lines of the selected combination are delivered to the current subtractor, and a group of output currents at the two source lines of other unselected combinations are not allowed to be delivered to the current subtractor.

[0027] In the above-mentioned artificial intelligence integrated memory, when any combination is selected, the value of the address code at this time is switched to the only enable code value that can activate any combination to a valid value. A code element with a specified weight bit is selected in the enable code value. When the code element is flipped, the source lines of the two rows of transistors belonging to any combination are transiently coupled once through the coupling capacitor.

[0028] The present application relates to an in-memory computing chip, characterized by comprising:

[0029] Memory in the form of flash memory with an array of memory transistors used to build an implementation of a neural network;

[0030] Using a memory transistor array as a carrier of a weight matrix of a neural network, setting input data of the neural network to be transmitted to a series of bit lines of the memory transistor array, and setting output data of the neural network to be retrieved from a series of source lines of the memory transistor array;

[0031] Each weight in the weight matrix of the neural network is represented by the difference in threshold voltages of a corresponding pair of complementary transistors located in the same column but arranged in two rows in the memory transistor array, the gates of any pair of complementary transistors being coupled together, and the drains of any pair of complementary transistors being coupled to the same bit line;

[0032] Among them, the original input data of the neural network is converted into input quantities in voltage value format and then transmitted to the bit lines of the storage transistor array. The difference between the output currents at the source lines of each two rows of transistors in the storage transistor array divided by the ratio of the preset coefficient is used as an output data of the neural network.

[0033] The above-mentioned in-memory computing chip also includes: a digital-to-analog converter integrated in the chip, wherein a digital-to-analog converter is configured at each bit line of the storage transistor array to convert the input data of the neural network into a voltage value that matches the input signal pattern of the bit line; an analog-to-digital converter integrated in the chip, wherein an analog-to-digital converter is configured at each source line of the storage transistor array to convert the output signal in the output current format at the source line into output data that is compatible with the digital output quantity of the neural network.

[0034] Based on the foregoing, one of the greatest advantages of this application is that the weight matrix of the neural network is directly mapped to the storage transistor array and the relative charge of the complementary transistors can be adjusted to dynamically configure the weight matrix of the neural network so as to adapt to the refresh of the weight matrix of the neural network. It is worth noting that different transistors inevitably have inconsistent process parameters in the semiconductor manufacturing process. This inconsistency will cause intrinsic errors in the weights of different transistors. The process parameters related to transistors include current or voltage amplification factor or dissipated power, frequency characteristics and current characteristics, voltage characteristics and width-to-length ratio. If a single individual transistor is used to express a weight, the weight error that naturally exists between different transistors will be caused by the inconsistent process parameters between different transistors. On the contrary, if the scheme of this article is used, instead of using a single transistor, the relative floating gate threshold relationship of a pair of complementary transistors is used to express a single weight, the weight error caused by inconsistent process parameters between different transistors can be eliminated.

[0035] Based on the above, the second biggest advantage of this application is that it adopts a non-von Neumann architecture, which can solve the compilation wall, storage wall, and power consumption wall problems under the traditional von Neumann architecture. The obvious convenience in compilation is to adjust the relative thresholds of complementary transistors to achieve weight programming, and the individual weights are based on complementary transistors. This solution only requires configuring the relative floating gate charge relationship of the complementary transistors at a pair of complementary transistors to achieve the compilation of core weight parameters. Furthermore, the floating gate storage charges originally used to store data code elements of the complementary transistors are adjusted relative to each other. The stored charge itself represents data storage, and the relative charge relationship represents weight, so the storage itself and network computing can be integrated without obstacles, which can solve the concerns about storage wall and power consumption wall, and save the intermediate transmission barriers and power consumption of moving data and performing calculations between the memory and the computing unit in the traditional computer system.

[0036] Based on the foregoing, the third greatest advantage of this application is the correction of erroneous results of neural networks. In artificial intelligence, for example, a large number of multiplication and addition convolution operations are the core components of deep learning. Storage and computing technology uses a large number of weighted portions of multiplication and addition calculations stored in storage units, and performs network calculations such as convolution operations in storage arrays. Neural networks are limited by semiconductor manufacturing processes and cannot flexibly expand operators such as increasing or decreasing weight matrices, because the larger the weight matrix, the more columns or rows of the transistor arrays involved in the weight matrix must be synchronized. Note that semiconductor manufacturing processes will inevitably give rise to many parasitic parameters in the weight array. Typically, the more transistor columns mounted on the same source line, the wider the weight matrix. Each additional column of transistors causes the source line parasitic capacitance to expand once, and the parasitic capacitance is not a simple cumulative relationship. In essence, it is a complex complex of capacitors in series and parallel, with extremely low regularity. The computational results of a neural network are closely related to the source line current. The complex parasitic capacitance of the source line can hinder the actual current of the source line. Furthermore, the charging and discharging of the parasitic capacitance can slow down the network computation and affect access to stored charge. The larger the array, the greater the parasitic capacitance of the network. The participation of parasitic parameters in matrix operations can cause the neural network computational results to shift. This application advocates actively clamping the source lines of the two rows of transistors used to define a row of weights. The key goals are to reduce the correlation between the neural network computational results and the parasitic parameters caused by the size of the transistor array, and to overcome the result shift caused by the participation of parasitic parameters in the neural network matrix operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to make the above purposes, features and advantages more understandable, the specific implementation methods are explained in detail below in conjunction with the drawings. After reading the following description and referring to the following drawings, the features and advantages of this application will become apparent.

[0038] Figure 1 A finite number of transistors are selected inside the flash memory as the weight carriers of the neural network.

[0039] Figure 2 The input data to the neural network comes from a series of bit lines in the memory transistor array.

[0040] Figure 3 Taking a picture with pixels as an example, the pixel value or grayscale value is input into the storage transistor array.

[0041] Figure 4 It is the difference in output current at the source lines of the two rows of transistors corresponding to a row of weights.

[0042] Figure 5 A multiplexer is used to time-share switch a group of output currents at the source lines of different combinations.

[0043] Figure 6 When any combination is selected, the value of the address code at this time switches to the valid enable code value.

[0044] Figure 7 This is an example of transiently coupling the source lines of the two rows of transistors belonging to the combination through coupling capacitors. DETAILED DESCRIPTION

[0045] The technical solutions disclosed in this application will be clearly and completely explained below in conjunction with specific embodiments. However, the embodiments described are only embodiments used for narration and explanation of this application and are not all embodiments.

[0046] See also Figure 1 Regarding the concepts related to storage and calculation, the storage and calculation method mentioned in the context of this application is an abbreviation for in-memory calculation or storage and calculation integrated performed inside the memory.

[0047] See also Figure 1 Regarding storage-related concepts, the flash memory-based memory mentioned in the context of this application is, for example, a NOR-Flash-based memory, or an equivalent memory.

[0048] See also Figure 1 Regarding artificial intelligence integrated memory, the artificial intelligence integrated memory mentioned in the context of this application is a type of memory that integrates artificial intelligence functions based on in-memory computing, such as an in-memory computing chip.

[0049] See also Figure 1For ease of explanation, an existing conventional NOR flash memory circuit is used as an example. The working principle is that a floating gate (Floating Gate) that stores stored charges such as electrons can be formed between the source S and drain D of the storage transistor, that is, on the current-conducting semiconductor. The floating gate is isolated by an insulating layer such as a silicon oxide film. Outside the floating gate is a selection / control gate (Control Gate) that controls the conduction current between the source and drain. The floating gate charge, such as electrons, will not disappear immediately due to power failure, so flash memory is a non-volatile memory. The write operation, such as applying a positive voltage to the control electrode, allows charges such as electrons to pass through the insulating layer into the floating gate. The erase operation, for example, is the opposite. A positive voltage can be applied to the substrate to extract electrons from the floating gate to achieve erasure. Flash memory and its data operations are prior art and will not be described separately in this article. The read, write, or erase operations of flash memory in the prior art are applicable to the flash memory of this application.

[0050] See also Figure 1 , describes flash memory in array form: the gates of each row of transistors are connected to a common word line, the drains of each column of transistors are connected to a common bit line, and the sources of each row of transistors are connected to a common source line.

[0051] See also Figure 1 Regarding the row wordline example, the gates of the transistors in the first row are connected to wordline G1, the gates of the transistors in the second row are connected to wordline G2, and the gates of the transistors in the Mth row are connected to wordline GM. The gates of the transistors in the 2Mth row are connected to wordline G2M. Further omitted rows and columns are not repeated in the figure. The total number of transistors in the Mth row is considered to be a matrix of M×N elements, and the total number of transistors in the 2Mth row is considered to be a matrix of 2M×N elements.

[0052] See also Figure 1 Regarding the row source line example, the sources of the transistors in the first row are connected to source line S1, the sources of the transistors in the second row are connected to source line S2, the sources of the transistors in the Mth row are connected to source line SM, and the sources of the transistors in the 2Mth row are connected to source line S2M. Further omitted rows are not shown repeatedly in the figure.

[0053] See also Figure 1 For example, in the column bit line example, the drains of the transistors in the first column are connected to bit line B1, the drains of the transistors in the second column are connected to bit line B2, and the drains of the transistors in the third column are connected to bit line B3. The drains of the transistors in the Nth column are connected to bit line BN. The total number of N columns of transistors is considered to be a matrix of N×2M elements.

[0054] See also Figure 1The original function of a memory's floating gate is to store a code element, 1 or 0. In other words, flash memory has no special use in traditional computers, servers, or other similar electronic devices other than storage. However, this application no longer views flash memory as simply a storage space for code elements 1 or 0. Instead, it advocates modifying the flash memory's circuit architecture to a quasi-computing unit capable of participating in artificial intelligence, with minimal changes to the flash memory's underlying physical structure.

[0055] See also Figure 4 A flash memory-based storage and computing method includes: providing a flash memory-based memory having a storage transistor array, such as a 2M×N array. Using the storage transistor array, such as the 2M×N array, as a carrier of the weight matrix of the neural network, setting the input data of the neural network to be transmitted to a series of bit lines B1-BN of the transistor array, and setting the output data of the neural network to be captured from the series of source lines S1-S2M of the storage transistor array, such as the 2M×N array, thereby realizing flash memory-based storage and computing. Each weight in the weight matrix of the neural network, such as Ma_wei, is represented by the difference in threshold voltages of a corresponding pair of complementary transistors located in the same column but arranged in two rows in the storage transistor array. The gates of any pair of complementary transistors are coupled together, and the drains of any pair of complementary transistors are coupled to the same bit line.

[0056] See also Figure 4 , the weight matrix is ​​as in Ma_wei, for example, the weight W 11 The threshold voltages (V TH11 and V TH21 ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line B1.

[0057] See also Figure 4 , the weight matrix is ​​as in Ma_wei, for example, the weight W 12 The threshold voltages (V TH12 and V TH22 ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line B2.

[0058] See also Figure 4 , the weight matrix is ​​as in Ma_wei, for example, the weight W 13The threshold voltages (V TH13 and V TH23 ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line B3.

[0059] See also Figure 4 , the weight matrix is ​​as in Ma_wei, for example, the weight W 1N The threshold voltages (V TH1N and V TH2N ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line BN.

[0060] See also Figure 4 The use of flash-based computing units (FPUs) to replace traditional computers stems from several major drawbacks when executing neural networks. Data transfer times for reading and writing data from external memory can be hundreds or thousands of times longer than computation time, resulting in inefficient energy consumption ranging from 60% to 90%. This significantly lower energy efficiency and the associated memory wall present a significant barrier to data computing applications. In particular, the most significant challenge in accelerating deep learning in neural networks is the frequent data transfer between computing units and storage. While parallel acceleration technologies such as multi-core CPUs and multi-core GPUs are being used to increase computing power, in the post-Moore era, memory bandwidth limits the practical bandwidth of computing systems, hindering overall computing power growth. The time and energy consumption associated with running neural network weight calculations or inference calculations on traditional computers is a significant manifestation of this drawback.

[0061] See also Figure 2 In the design, bit lines B1-BN are used as input and source lines S1-S2M are used as output. Figure 1 The flash memory is regarded as the physical carrier for realizing the neural network NET.

[0062] See also Figure 4 , In order to illustrate the specific implementation process, a weight matrix Ma_wei is designed as follows.

[0063]

[0064] See also Figure 4, the introduction of a large number of parameters into neural networks has caused their development to encounter a bottleneck. Each output neuron in the fully connected layer is connected to all input neurons. According to the assumptions in the figure: if the number of input neurons is N and the number of output neurons is M, then there are at least approximately N×M weights or M biases that need to be trained and calculated. For each output neuron in the convolutional layer, there are usually input neurons within the coverage of the convolution kernel connected to it, and the convolution kernel used for all outputs is the same. Although local connections and weight sharing reduce the parameters of the convolution layer, a large amount of calculation still needs to be performed under the conditions of large-scale image input and deep neural networks. The reading and calculation of large amounts of data face the memory bottleneck and computing bottleneck of the network. The power consumption and latency of the neural network have increased sharply, limiting the application of neural networks.

[0065] See also Figure 2 , bit line B1-BN input is represented by vector Ma_in = [B1, B2...BN]. For the convenience of mathematical expression, the input of bit line B1 is mapped to X1, the input of bit line B2 is mapped to X2, the input of bit line B3 is mapped to X3, ..., the input of bit line BN is mapped to X N That is, Ma_in=[X1, X2…X N ] indicates input.

[0066] See also Figure 2 , the output of source lines S1-S2M is represented by vector Ma_out = [S1 / S2, S3 / S4...S2M]. For the convenience of mathematical expression, the output of source lines S1 / S2 is mapped to Y1, the output of source lines S3 / S4 is mapped to Y2, the output of source lines S5 / S6 is mapped to Y3, ..., the output of source lines S(2M-1) / S2M is mapped to Y M That is, Ma_out=[Y1, Y2…Y M ] indicates output.

[0067] See also Figure 2 The purpose of the flash memory is to perform the computational functions of the neural network NET. The specific computational process is expressed by the following formula. In fact, this process is also a detailed example of simulating the flash memory into a computing unit or a quasi-computing unit. Figure 4 . With Y1, Y2 and Y M etc. as representatives to illustrate this spirit.

[0068] Y1=X1*W 11 +X2*W 12 +X3*W 13 +…X N *W 1N

[0069] Y2=X1*W21 +X2*W 22 +X3*W 23 +…X N *W 2N

[0070] Y M =X1*W M1 +X2*W M2 +X3*W M3 +…X N *W MN

[0071] See also Figure 2 To address these bottlenecks, the non-von Neumann architecture shown in the figure can provide greater computing power and higher energy efficiency in specific areas, surpassing existing ASIC computing chips. In-memory computing and in-memory logic, or in-memory computing, directly utilize memory for data processing or computation, integrating data storage and computation within the same chip or memory area. This can completely eliminate the bottlenecks of the von Neumann computing architecture and is particularly well-suited for large-scale, parallel applications like deep learning neural networks, which require large amounts of data.

[0072] See also Figure 2 A more intuitive expression is to use vector-matrix multiplication to show the aforementioned complex operation. The vector-matrix expression flash memory performs local data processing of the neural network NET as follows. Figure 4 .

[0073]

[0074] See also Figure 2 , if we define X1 to X N is the input layer of the neural network NET, then Y1 to Y N The corresponding is the output layer of the neural network NET. So far, it can be considered that Figure 1 The flash memory performs an entire vector operation from the input layer to the output layer. This operation differs significantly from that of a traditional von Neumann computer because it only requires measuring the individual signal quantities from source lines S1-S2M. Individual multiplications and additions do not need to be performed one by one; the final result can be fully reflected in the signal quantities from source lines S1-S2M at once. This is why it is called quasi-computing. Traditional von Neumann computers require all multiplications and additions to be performed one by one, which is the key difference.

[0075] See also Figure 4 , the combination of every two rows of transistors (such as the first row and the second row) in the memory transistor array is used to define the first row weight (W 11 -W 1N), a memory transistor array such as N×2M multi-row transistors provides multiple combinations: a combination of the first row and the second row, a combination of the third row and the fourth row, and so on.

[0076] See also Figure 4 The memory transistor array uses the combination of every two rows of transistors (row 2M-1 and row 2M) to define the weight of the Mth row in the weight matrix (W M1 -W MN ), the multiple rows of transistors in the N×2M storage transistor array provide multiple combinations: a combination of the K-1th row and the Kth row, a combination of the 2M-1th row and the 2Mth row, etc.

[0077] See also Figure 3 Flash memory-based neural networks (NETs) are suitable for image processing. Assume that data such as a video or image with pixel values ​​or grayscale values ​​(e.g., for image classification, image segmentation, autonomous driving, or object detection) is input into a flash memory-based neural network (NET). The following uses the image Gr_in as an example.

[0078] See also Figure 3 , the pixels in the image Gr_in are divided into multiple rows and columns. The pixel corresponding to the address of the 0th pixel is defined as g1, the pixel corresponding to the address of the 1st pixel is defined as g2, the pixel corresponding to the address of the 2nd pixel is defined as g3, and so on. The pixel corresponding to the last pixel address is defined as gn. According to the arrangement rule and address specification of the pixel matrix, the grayscale value of any pixel can be obtained from the captured image. The grayscale values ​​or pixel values ​​of n pixels (belonging to the image Gr_in) are allowed to be coupled to the X1 to X N The grayscale values ​​or pixel values ​​of n pixels (belonging to the image Gr_in) can be segmented and then sent to different flash memories. In other words, the grayscale values ​​or pixel values ​​of n pixels can be distributed and calculated using different flash memories. Of course, the grayscale values ​​or pixel values ​​can also be normalized or similarly processed before being sent to the memory.

[0079] See also Figure 3An important point to note is that the input format of bit lines B1-BN must conform to the inherent characteristics of flash memory. That is, the input values ​​of bit lines B1-BN are not directly equivalent to the pixel values ​​g1-gn. Therefore, in an alternative embodiment, the pixel values ​​g1-gn undergo digital-to-analog conversion using a DAC (Digital-to-Analog Converter) device, such as one packaged with the flash memory. The analog values ​​corresponding to the pixel values ​​g1-gn are then input to bit lines B1-BN. The DAC (Digital to Analog Converter) device can also be directly integrated with the flash memory during wafer fabrication. This allows the data contained in image Gr_in to be smoothly coupled with the flash memory. Another important factor is that the final storage location or space of image Gr_in is typically some type of memory. Therefore, the unique advantage of having the image Gr_in stored in the same flash memory as the matrix operations is realized. The CPU or GPU no longer needs to read data from memory to perform matrix operations. All storage and computing actions are implemented in the memory. The concerns mentioned above about reading and writing data from the processor to the memory, the time cost of data transfer, and so on (the storage wall) will no longer exist.

[0080] See also Figure 4 At this point, there is still a problem to be solved: In order to explain the specific implementation process of the neural network, the matrix Ma_wei involved in the network calculation was specially designed in the previous article. However, how to map the M*N vector matrix Ma_wei to the transistors in the flash memory? Figure 1 The 2M×N array shown still presents concerns that need to be resolved.

[0081] See also Figure 4Regarding the relationship between pixel values ​​g1-gn and bit lines B1-BN, pixel value g1 is converted into voltage value V1 through DAC digital-to-analog conversion, pixel value g2 is converted into voltage value V2 through digital-to-analog conversion, pixel value g3 is converted into voltage value V3 through digital-to-analog conversion, and so on, until pixel value gn is converted into voltage value VN through digital-to-analog conversion. According to the interface correspondence shown in the diagram, voltage value V1 is connected to bit line B1, voltage value V2 is connected to bit line B2, voltage value V3 is connected to bit line B3, and so on, until voltage value VN is connected to bit line BN. As a rule of thumb, larger pixel values ​​result in larger converted bit line voltages, while smaller pixel values ​​result in lower converted bit line voltages. If the number of transistors in the layout, i.e., the size of the 2M×N matrix, corresponds to the pixel size of image Gr_in, that is, n / N is exactly equal, then the single flash memory array shown can process exactly n pixel values. Otherwise, a larger number of n pixel values ​​would require the coordination of multiple flash memory arrays (shown in the figure) to perform the computational processing, for example, when n / N is not equal. That is, the grayscale values ​​or pixel values ​​of multiple pixels are calculated separately by different transistor arrays. Regarding the benefits of this article: Memory is limited by semiconductor manufacturing processes and cannot flexibly expand the weight matrix without limit. If N caters to n and the adaptive operator of the neural network is forcibly expanded, the larger the array (for example, as N increases), the larger the parasitic parameters of the neural network NET will be. The participation of parasitic parameters in matrix operations will cause the neural network's computational results to shift. When the matrix Ma_wei expansion faces the constraints of semiconductor manufacturing processes, how to avoid the participation of parasitic parameters in the operation is precisely the advantage of this article.

[0082] See also Figure 4 Regarding the matrix Ma_wei, the gates of the transistors in the first row are connected to the word line G1, the gates of the transistors in the second row are connected to the word line G2, and the gates of the transistors in the Mth row are connected to the word line GM. The gates of the transistors in the 2Mth row are connected to the word line G2M. For the first row weight, the corresponding weights of the transistors in the first and second rows are recorded as W. 11 、W 12 、W 13 、……W 1N The weights generated by the third and fourth rows of transistors for the second row weight are recorded as W 21 、W 22 、W 23 、……W 2N For the weight of the Mth row, the weight generated by the 2M-1th row and the 2Mth row transistors is recorded as W M1 、W M2 、W M3 、……W MN The combination of every two rows of transistors in the memory transistor array is used to define a row of weights in the weight matrix. 11-W 1N Example explanation.

[0083] See also Figure 4 , for the first row weight W 11 -W 1N , a weight W 11 The threshold voltages (V TH11 and V TH21 ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line B1.

[0084] See also Figure 4 , for the first row weight W 11 -W 1N , such as weight W 1N The threshold voltages (V TH1N and V TH2N ), note that the gates of the pair of complementary transistors are coupled together (G1 coupled to G2), and the drains of the pair of complementary transistors are coupled to the same bit line BN.

[0085] See also Figure 4 The total of 2M rows and N columns of transistors are considered to be elements of an M×N matrix. The definition of each weight value in the matrix Ma_wei is the basis for realizing the neural network NET. The figure shows that the source current of each row of transistors flows to the common source line of the transistors in that row, and the figure shows that the drain of each column of transistors is connected to the common bit line of the transistors in that column. This transistor layout will provide a feasible solution for how to define the weights of the transistors. For example, the source current convergence characteristics of each row of transistors correspond to the multiplication and accumulation calculation algorithm of the vector-matrix multiplication mentioned above. Each weight is represented by the difference in threshold voltage of a corresponding pair of complementary transistors located in the same column but arranged in two rows in the storage transistor array.

[0086] See also Figure 4 To explain how to map weights to transistors, let’s first explain the relationship between the current, threshold, and applied voltage of the storage transistor: The gate threshold voltage is V TH The process parameter K of the memory transistor related to the process is μCW / L, where W / L is the width-to-length ratio of the transistor. For a memory transistor with a certain manufacturing process and a certain size, the process parameter K is almost constant. The voltage between the gate and source is V GSand the voltage between the drain and source of the transistor, V DS Can satisfy K[(V GS -V TH )V DS -V 2 DS / 2] = I. For a row of transistors, if the source line currents I of the transistors are multiplied and the output currents I of the transistors in a row are accumulated, this is equivalent to the multiplication and accumulation calculation of the matrix multiplication, which is also the basic principle of mapping the transistor array to the weight matrix.

[0087] See also Figure 4 , first row transistor (gate coupled to G1): the current I11 of the first transistor is calculated to be approximately K[(V GS1 -V TH11 )V DS1 -V 2 DS1 / 2]=I11. Similarly, the current I12 of the second transistor can be calculated as K[(V GS1 -V TH12 )V DS2 -V 2 DS2 / 2]=I12. Similarly, the Nth transistor current I1N can be calculated to be approximately K[(V GS1 -V TH1N )V DSN -V 2 DSN / 2]=I1N. The voltage between the gate and source of the first transistor is V GS1 And the voltage between the drain and source is V DS1 , the threshold voltage is V TH11 , the voltage between the gate and source of the second transistor is V GS1 And the voltage between drain and source is V DS2 , the threshold voltage is V TH12 , the voltage between the gate and source of the Nth transistor is V GS1 And the voltage between the drain and source is V DSN , the threshold voltage is V TH1N The above is the specific situation of the first row of transistors.

[0088] See also Figure 4 , first row of transistors (gate coupled to G1): the source currents of the first transistor to the Nth transistor all flow to the common source line S1 of the transistors in the row, and the current of the source line S1 is recorded as IS1.

[0089] IS1=I11+I12+I13+…I1N

[0090] See also Figure 4, the second row of transistors (gate coupled to G2): the current I21 of the first transistor is calculated to be approximately K[(V GS2 -V TH21 )V DS1 -V 2 DS1 / 2]=I21. Similarly, the current I22 of the second transistor can be calculated as K[(V GS1 -V TH22 )V DS2 -V 2 DS2 / 2]=I22. Similarly, the Nth transistor current I2N can be calculated to be approximately K[(V GS1 -V TH2N )V DSN -V 2 DSN / 2]=I2N. The voltage between the gate and source of the first transistor is V GS2 And the voltage between the drain and source is V DS1 , the threshold voltage is V TH21 , the voltage between the gate and source of the second transistor is V GS2 And the voltage between the drain and source is V DS2 , the threshold voltage is V TH22 , the voltage between the gate and source of the Nth transistor is V GS2 And the voltage between the drain and source is V DSN , the threshold voltage is V TH2N The above is the specific situation of the second row of transistors.

[0091] See also Figure 4 , the second row of transistors (gate coupled to G2): the source currents of the first transistor to the Nth transistor all flow to the common source line S2 of the transistors in this row, and the current of the source line S2 is recorded as IS2.

[0092] IS2=I21+I22+I23+…I2N

[0093] See also Figure 4 A parameter explaining the weighting is the default coefficient K = μCW / L, where W / L is the aspect ratio of the transistor, μ is the mobility of carriers such as electrons, and C is the capacitance of the gate oxide. The default coefficient is described in the equation for transistor drain current in Jacob Baker's "CMOS Circuit Design, Layout, and Simulation," for example. The relevant equation is incorporated herein by reference.

[0094] See also Figure 4, if the first row of transistors (word line G1) and the second row of transistors (word line G2) are set to have the same potential, for example, the gate of word line G1 is coupled to the gate of word line G2. That is, the gate-source voltage of the first row of transistors is equal to the gate-source voltage of the second row of transistors, such as V GS1 Equal to V GS2 The voltages assigned to the series bit lines B1 to BN at the transistor array position can be V DS1 To V DSN For example, VN=V DSN Then, the source line current IS1 of the first row of transistors is subtracted from the source line current IS2 of the second row of transistors, which is recorded as IS12.

[0095] IS12=IS1-IS2=(I11-I21)+(I12-I22)+(I13-I23)+…(I1N-I2N)

[0096] See also Figure 4 , as previously recorded in Ma_wei, inform the weight W 11 The threshold voltages (V TH11 and V TH21 ) is characterized by the difference between the gates of the complementary transistors being coupled together (G1 coupled to G2), and the drains of the complementary transistors being coupled to the bit line B1 (V1 = V DS1 ). The complementary transistor current subtraction I11-I21=K[(V GS1 -V TH11 )V DS1 -V 2 DS1 / 2]-K[(V GS2 -V TH21 )V DS1 -V 2 DS1 / 2], the result of current subtraction is expressed as I11-I21=K[(V TH21 -V TH11 )V DS1 The voltage of bit line B1 is V1. The threshold voltages (V TH11 and V TH21 ) to represent the weight W 11 .

[0097] See also Figure 4 , as previously recorded in Ma_wei, inform the weight W 1NThe threshold voltages (V TH1N and V TH2N ), note that the gates of the complementary transistors are coupled together (G1 coupled to G2), and the drains of the complementary transistors are coupled to the bit line BN (VN = V DSN ). The complementary transistor current subtraction I1N-I2N=K[(V GS1 -V TH1N )V DSN -V 2 DSN / 2]-K[(V GS1 -V TH2N )V DSN -V 2 DSN / 2], the subtraction result is expressed as I1N-I2N=K[(V TH2N -V TH1N )V DSN The voltage of the bit line BN is VN. The threshold voltage of the complementary transistor (V TH1N and V TH2N ) to represent the weight W 1N .

[0098] See also Figure 4 If the source line current IS1 of the first row transistor (word line G1) and the source line current IS2 of the second row transistor (word line G2) are subtracted, it is recorded as IS12. Word line G1 is coupled to word line G2.

[0099] IS12=(K*W 11 *V1)+(K*W 12 *V2)+(K*W 13 *V3)+…(K*W 1N *VN)

[0100] See also Figure 4 , the first row of transistors (word line G1) and the second row of transistors (word line G2) can be expressed as the above IS12 expression after the current subtraction formula is converted (Y1=IS12 / K can also be defined). The source current IS1 convergence characteristics of the first row of transistors correspond to the multiplication and accumulation calculation algorithm of the vector-matrix multiplication; the source current IS2 convergence characteristics of the second row of transistors correspond to the multiplication and accumulation calculation algorithm of the vector-matrix multiplication. Furthermore, the subtraction of the source current of the first row of transistors and the source current of the second row of transistors, IS1-IS2=IS12, does not affect the multiplication calculation of the weight and bit line voltage, nor does it affect the accumulation calculation mechanism of the multiplication value obtained by the multiplication calculation.

[0101] See also Figure 4 In addition to its use in AI computing, flash memory technology can also be used in other computing applications, such as brain-inspired chips. It represents a future mainstream big data computing chip architecture and can also serve as the core computing module for low-energy supercomputing centers. For example, NOR FLASH in-memory computing can support approximately 300MB of deep learning weight parameters on a single chip, eliminating the need for additional memory.

[0102] See also Figure 5 The third row transistor (word line G3) and the fourth row transistor (word line G4) have their respective source line currents IS3 and IS4 subtracted from each other, which is recorded as IS34. Word line G3 is coupled to word line G4.

[0103] IS34=(K*W 21 *V1)+(K*W 22 *V2)+(K*W 23 *V3)+…(K*W 2N *VN)

[0104] See also Figure 5 , the third row of transistors (word line G3) and the fourth row of transistors (word line G4) can be expressed as the above IS34 expression through the current subtraction formula (Y2 can also be defined as IS34 / K). The source current IS3 convergence characteristics of the third row of transistors correspond to the multiplication and accumulation calculation algorithm of vector-matrix multiplication; the source current IS4 convergence characteristics of the fourth row of transistors correspond to the multiplication and accumulation calculation algorithm of vector-matrix multiplication. Furthermore, the subtraction of the source current of the third row of transistors from the source current of the fourth row of transistors, IS3-IS4=IS34, does not affect the multiplication calculation of the weight and bit line voltage, nor does it affect the accumulation calculation mechanism of the multiplication value obtained by the multiplication calculation.

[0105] See also Figure 5 , the 2M-1th row of transistors (the word line where the transistors in this row are located is represented by G(2M-1)) and the other Mth row of transistors adjacent to this row (the word line where the transistors in this row are located is represented by G2M), if the source line current IS(2M-1) and the source line current IS2M of these two rows are subtracted, it is recorded as IS2M(2M-1).

[0106] IS2M(2M-1)=(K*W M1 *V1)+(K*W M2 *V2)+…(K*W MN *VN)

[0107] See also Figure 5, word line G(2M-1) and word line G2M are set to be connected to each other and their potentials are equal.

[0108] See also Figure 5 , the 2M-1th row of transistors (the word line where the row of transistors is located is represented by G(2M-1)) and the other Mth row of transistors adjacent to the row (the word line where the row of transistors is located is represented by G2M), can be expressed as the above IS2M(2M-1) expression after current subtraction conversion (you can also define Y M =IS2M(2M-1) / K). The source current IS(2M-1) of the transistors in the 2M-1th row converges, corresponding to the multiplication and accumulation calculations of the vector-matrix multiplication; the source current IS2M of the transistors in the Mth row converges, corresponding to the multiplication and accumulation calculations of the vector-matrix multiplication. The subtraction of the source current of the transistors in the Mth row from the source current of the transistors in the 2M-1th row, IS2M-IS(2M-1)=IS2M(2M-1), does not affect the multiplication calculations of the weights and bit line voltages, nor does it affect the accumulation calculation mechanism of the multiplication values.

[0109] See also Figure 5 , follow the example shown in the figure, and combine Figure 2 As shown above, based on the mathematical expression, the source line current difference between the source line groups S1 / S2 is mapped to Y1, and for example, Y1=IS12 / K. Based on the mathematical expression, the source line current difference between the source line groups S3 / S4 is mapped to Y2, and for example, Y2=IS34 / K. Based on the mathematical expression, the source line current difference between the source line groups S(2M-1) / S2M is mapped to Y M For example, Y M =IS2M(2M-1) / K.

[0110] See also Figure 5 , follow the example shown in the figure, and combine Figure 2 As shown, the raw input data of the neural network is converted into input quantities in the form of voltage values, for example, the input data is converted into input quantities in the form of voltage values ​​V1-VN, and then transmitted to a series of bit lines B1-BN of the storage transistor array based on the input quantities sorted into vectors. In addition to pixel values, the raw input data of the neural network can also be other data suitable for neural network processing, such as speech, text, etc.

[0111] See also Figure 5 , and combined with Figure 2 As shown, the vector Ma_in=[B1, B2...BN] indicates that the input of bit line B1 is mapped to X1, the input of bit line B2 is mapped to X2, the input of bit line B3 is mapped to X3, and the input of bit line BN is mapped to X N The input quantities of bit lines B1-BN are V1-VN respectively. That is, Ma_in=[X1, X2…XN ] indicates that the input is based on the input quantities sorted into vectors [X1=V1、X2=V2、…、X N =VN].

[0112] See also Figure 5 , and combined with Figure 4 As shown, any pair of complementary transistors receives the voltage value on the bit line of the column where they are located and makes the difference between the drain-source voltages of the any pair of complementary transistors the same.

[0113] See also Figure 5 , the weight matrix is ​​as in Ma_wei, for example, the weight W 11 It is characterized by the difference in threshold voltages of two complementary transistors located in the same first column (bit line B1) but in the first row (word line G1) and the second row (word line G2) in the memory transistor array. The complementary transistors receive the voltage value V1 on the bit line B1 in the first column and make the difference in drain-source voltage V DS Same (for example, both are V DS1 ).

[0114] See also Figure 5 , the weight matrix is ​​as in Ma_wei, for example, the weight W 1N It is characterized by the difference in threshold voltages of two complementary transistors located in the same Nth column (bit line is BN) but in the first row (word line is G1) and the second row (word line is G2) in the memory transistor array. The complementary transistors receive the voltage value on the bit line BN in the Nth column, that is, VN, and make the difference in drain-source voltage of the complementary transistors V DS Same (for example, both are V DSN ).

[0115] See also Figure 5 , and combined with Figure 4 As shown, an output data of the neural network is represented by the ratio of the difference between the output currents at the respective source lines of the two rows of transistors corresponding to a row of weights divided by a preset coefficient, and any two transistors in the two rows of transistors located in the same column and sharing the same bit line are regarded as a pair of complementary transistors; and the multiple ratios provided by a series of source lines of the memory transistor array are regarded as the output quantities sorted into vectors provided by the memory transistor array.

[0116] See also Figure 5 , the output data Y1 of the neural network NET is used to define a row of weights W 11 To W 1NThe difference between the output currents IS1 and IS2 at the source lines S1 and S2 of two corresponding rows of transistors (the first and second rows) is represented by the ratio of a predetermined coefficient. IS1 - IS2 = IS12, where the predetermined coefficient is K = μCW / L, and the ratio is IS12 / K = Y1. Any two transistors in the same column and on the same bit line within the two rows are considered a pair of complementary transistors.

[0117] See also Figure 5 , the output data Y2 of the neural network NET is used to define a row of weights W 21 To W 2N The difference between the output currents IS3 and IS4 at the source lines S3 and S4 of the corresponding two rows of transistors (the third and fourth rows) is represented by the ratio of a predetermined coefficient. IS3 - IS4 = IS34, where the predetermined coefficient is K = μCW / L, and the ratio is IS34 / K = Y2. Any two transistors in the same column and on the same bit line within the two rows of transistors are considered a pair of complementary transistors.

[0118] See also Figure 5 , the neural network NET outputs data Y M To define a row weight W M1 To W MN The difference between the source line currents S(2M-1), S2M currents IS(2M-1), and IS2M of the corresponding two rows of transistors (rows 2M-1 and 2M) is represented by the ratio of the preset coefficient. IS2M-IS(2M-1)=IS2M(2M-1), the preset coefficient is K=μCW / L and the calculated ratio is IS2M(2M-1) / K=Y M Similarly, any two transistors in the 2M-1 and 2M rows that are located in the same column and share the same bit line are considered to be a pair of complementary transistors.

[0119] See also Figure 5 As mentioned above, the ratios IS12 / K, IS34 / K, ..., IS2M(2M-1) / K provided by the series of source lines S1 to S2M of the memory transistor array 2M×N are regarded as the output quantity Ma_out=[Y1, Y2...Y M ].

[0120] See also Figure 5 , as defined above, X1 to X N For the input layer of the neural network NET, define Y1 to Y N This corresponds to the output layer of the neural network NET. At this point, the first and second rows of transistors in the flash memory have completed a vector operation Y1 from the input layer to the output layer, and the result of Y1 can be directly calculated at one time by sensing the source line current of the first and second rows of transistors, without having to calculate W separately.11 ×V1 or W 12 ×V2 or W 1N ×VN, etc., belong to the class of calculations under the non-von Neumann architecture. The calculation results are not obtained through numerical calculations, but by current sensing. Similarly, the third and fourth rows of transistors in the flash memory complete a vector operation Y2 from the input layer to the output layer, the fifth and sixth rows of transistors in the flash memory complete a vector operation Y3 from the input layer to the output layer, and the 2M-1 and 2M rows of transistors complete a vector operation Y from the input layer to the output layer. M The positive integers N and M can be freely expanded to meet network requirements.

[0121] See also Figure 5 As mentioned above, the combination of every two rows of transistors in the memory transistor array is used to define a row of weights in the weight matrix. The first combination of the first and second rows of transistors defines the first row weight W 11 -W 1N , a second combination of the third and fourth rows of transistors to define the second row weight W 21 -W 2N , and so on, the 2M-1 and 2M rows of transistors and their Mth combination define the Mth row weight W M1 -W MN . The first to Mth combinations are shown.

[0122] See also Figure 5 As mentioned above, the 2M×N rows of memory transistors, such as 2M rows of transistors, provide the first through Mth combinations. Multiplexer MUX time-shares the output currents from the source lines of the different combinations and transmits them to current subtractor I_Mi. Current subtractor I_Mi calculates the current difference between the output currents from the source lines of the two rows of transistors corresponding to each combination.

[0123] See also Figure 5 Multiplexer MUX transmits the output currents IS1 and IS2 from the source lines of the first combination (the first and second rows of transistors) at time T1 to current subtractor I_Mi. Current subtractor I_Mi calculates the current difference between the output currents from the source lines S1 and S2 of the two rows of transistors corresponding to this combination, i.e., IS1 - IS2. In an alternative embodiment, the output current of current subtractor I_Mi, i.e., the current difference IS12, is converted to a digital value via an ADC.

[0124] See also Figure 5Multiplexer MUX transmits the output currents IS3 and IS4 from the source lines of the second combination (the third and fourth rows of transistors) to current subtractor I_Mi at time T2. Current subtractor I_Mi calculates the current difference between the output currents from the source lines S3 and S4 of the two rows of transistors corresponding to this combination, i.e., IS3 - IS4. In an alternative example, the output current of current subtractor I_Mi, i.e., current difference IS34, is converted to a digital value via an ADC.

[0125] See also Figure 5 Multiplexer MUX transmits the output currents IS(2M-1) and IS2M at the source lines of the Mth combination (transistors in rows 2M-1 and 2M) at time TM to current subtractor I_Mi. The current subtractor calculates the current difference between the output currents of the source lines S(2M-1) and S2M at the source lines of the transistors in rows 2M-1 and 2M, corresponding to the combination, i.e., subtracts IS2M from IS(2M-1). In an alternative embodiment, the output current of current subtractor I_Mi, i.e., the current difference IS2M(2M-1), is converted into a digital value via an ADC.

[0126] See also Figure 5 The multiplexer MUX has a time-sharing feature: the multiplexer MUX switches the output currents of different combinations of source lines to the current subtractor in a time-sharing manner. At time T1, the output currents IS1 and IS2 are delivered to the current subtractor; at time T2, the output currents IS3 and IS4 are delivered to the current subtractor; at time TM, the output currents IS(2M-1) and IS2M are delivered to the current subtractor, and so on. T1, T2, and TM are different time points, and the order of any two of them can be reversed. It is possible for T1 to be earlier or later than T2, and it is possible for T2 to be earlier or later than TM, and so on.

[0127] See also Figure 5 The source line currents of any two rows of transistors corresponding to the pair of source lines are subtracted by the current subtractor I_Mi and then combined. Figure 3 The output current of I_Mi is converted from analog to digital by an ADC (Analog-to-Digital Converter) device, such as one packaged with the flash memory. This converts the analog output current into a digital value. This digital output current is more suitable for various calculations, such as dividing it by a preset coefficient K to obtain a desired ratio. The ADC (Analog to Digital Converter) device can also be directly integrated onto the same semiconductor die as the flash memory during wafer fabrication.

[0128] See also Figure 4 One of the tasks performed by the transistor array of the flash memory is to construct the matrix Ma_wei, and each element in the matrix corresponds to the weight matrix of the neural network NET.

[0129] See also Figure 4 Taking the neural network NET input layer Lay1 / hidden layer Lay2 as an example, when input data is fed into the input layer Lay1, a matrix Ma_wei is constructed between the input layer Lay1 and the hidden layer Lay2. Furthermore, the input data is converted into a voltage V1-VN and fed to the input layer Lay1. The output of the hidden layer Lay2 is equivalent to the result of performing a matrix operation on the input data using the weight matrix Ma_wei. The input is a voltage signal, and the output data is a current signal. The effect of the weight matrix Ma_wei on the input voltage signal influences the magnitude of the output current. This is the general process of implementing artificial intelligence computing using NOR Flash memory.

[0130] See also Figure 3 In an optional embodiment, a digital-to-analog converter DAC is configured at the series bit lines B1-BN of the storage transistor array, and the digital-to-analog converter DAC is used to convert the input data of the neural network NET into a voltage value that matches the input signal pattern of the bit line (for example, the bit line requires an analog quantity such as a voltage signal as an input quantity).

[0131] See also Figure 3 In an optional embodiment, an analog-to-digital converter ADC is configured at the series source lines S1-S2M of the storage transistor array. The analog-to-digital converter ADC can be used to convert the output signal in the output current format of the source line into output data compatible with the digital output quantity of the neural network NET. For example, the analog-to-digital converters configured at the source lines S1 and S2 are used to convert the output signal in the format of the difference between their output currents IS12 into output data compatible with the digital output quantity of the neural network NET. The digital quantity of current is different from the analog quantity. For example, the analog quantity of the current difference IS12 originally output by the current subtractor I_Mi is recorded as A_IS12. The analog-to-digital converter samples and converts the current difference IS12 output by the current subtractor to obtain the digital quantity D_IS12 of the current difference IS12.

[0132] See also Figure 3 As mentioned above, a digital-to-analog converter is configured at the bit line of the storage transistor array to convert the input data of the neural network into a voltage value that meets the input signal format requirements of the bit line.

[0133] See also Figure 3As mentioned above, an analog-to-digital converter is configured at the source line of the storage transistor array, which is used to convert the output signal in the form of an output current at the source line (such as analog quantity analog) into output data that meets the digital output format (such as digital quantity digital) requirements of the neural network NET.

[0134] See also Figure 4 , the weight matrix is ​​as in Ma_wei, for example, the weight W 11 The threshold voltages of two complementary transistors (threshold values ​​V TH11 and V TH21 ), the gates of the complementary transistors are coupled together (G1 coupled to G2), and the drains of the complementary transistors are coupled to the same bit line B1. 11 The method includes: changing any weight W 11 The floating gates of the selected complementary transistors inject charge, changing the threshold voltage to V TH11 The floating gate of a transistor injects charge such as electrons and changes the threshold voltage to V TH21 The floating gate injection charge of the remaining other transistor is such as electrons. The difference between the threshold voltages of the two selected complementary transistors (the two transistors determined by G1, G2 and B1) is adjusted by the relative change of the floating gate injection charge. For example, the threshold voltage is adjusted to V TH11 The amount of charge on the floating gate of a transistor compared to the threshold voltage V TH21 The floating gate charge of the remaining transistor is more or less, and the weight W at the position of the selected pair of complementary crystals can be adjusted. 11 The size.

[0135] See also Figure 4 , the weight matrix is ​​as in Ma_wei, and the weight W 13 The threshold voltages (V TH13 and V TH23 ), note that the gates of the complementary transistors are coupled together (G1 coupled to G2), and the drains of the complementary transistors are coupled to the same bit line B3. 13 The method includes: changing any weight W 13 The floating gates of the selected complementary transistors inject charge, changing the threshold voltage to V TH13The floating gate of a transistor injects charge as the amount of charge changes the threshold voltage V TH23 The floating gate injection charge of the remaining other transistor is adjusted by the relative change of the floating gate injection charge of the selected complementary transistor (the two transistors determined by G1, G2 and B3) to adjust the difference in the threshold voltage of the two transistors, such as adjusting the threshold voltage to V TH13 The amount of charge on the floating gate of a transistor compared to the threshold voltage V TH23 The floating gate charge of the remaining transistor should be denser or sparser, and the weight W of the selected pair of complementary crystals can be adjusted. 13 The size.

[0136] See also Figure 5 , for the multiplexer MUX, the multiplexer MUX is used to time-share the output currents at the source lines of different combinations and transmit them to the current subtractor I_Mi. The current subtractor performs the current difference calculation of the output currents at the source lines of the two rows of transistors corresponding to each combination. The address code is also called the select signal or control signal at the multiplexer. In this article, the address characteristics of the code element are more utilized, so it is defined as the address code and represented by the Sel signal in the figure. In the storage transistor array, the combination of each two rows of transistors (such as the first row and the second row, the third row and the fourth row, etc.) defines a row weight. The multiple rows of transistors in the storage transistor array provide multiple combinations.

[0137] See also Figure 5 The address code Sel that controls the multiplexer MUX is used to determine whether any combination is selected and only a set of output currents at the two source lines of the selected combination is delivered to the current subtractor I_Mi, and a set of output currents at the two source lines of other unselected combinations are not allowed to be delivered to the current subtractor I_Mi.

[0138] See also Figure 5 , the first combination of the first and second row transistors defines a first row weight W 11 -W 1N , a second combination of the third and fourth rows of transistors to define the second row weight W 21 -W 2N , and so on, the 2M-1 and 2M rows of transistors and their Mth combination define the Mth row weight W M1 -W MN . The first to Mth combinations are shown.

[0139] See also Figure 5Assuming that the address code Sel satisfies Sel=

[01001] , the first combination is determined to be selected and only the output currents IS1 and IS2 at the source lines S1 and S2 of the selected first combination are delivered to the current subtractor I_Mi. The output currents at the source lines of other unselected combinations are not allowed to be delivered to the current subtractor I_Mi. When the first combination is selected, the value of the address code at this time is switched to the only enable code value that can activate the first combination to be valid (enable), such as

[01001] . If the value of the address code at this time is any value other than the enable code value corresponding to the first combination, such as

[01010] , the first combination will be inactivated and the output current at its source line cannot be delivered to the current subtractor I_Mi through the MUX.

[0140] See also Figure 5 Assuming that the address code Sel satisfies Sel=

[01010] , the second combination is determined to be selected and only the output currents IS3 and IS4 at the source lines S3 and S4 of the selected second combination are delivered to the current subtractor I_Mi. The output currents at the source lines of other unselected combinations are not allowed to be delivered to the current subtractor I_Mi. When the second combination is selected, the value of the address code at this time is switched to the only enable code value that can activate the second combination to be valid (enable), such as

[01010] . If the value of the address code at this time is any value other than the enable code value corresponding to the second combination, such as

[01011] , the second combination will be inactivated and the output current at its source line cannot be delivered to the current subtractor I_Mi through the MUX.

[0141] See also Figure 5 Assuming that the address code Sel satisfies Sel =

[01100] , the Mth combination is determined to be selected and only the output currents IS(2M-1) and IS2M of the two source lines S(2M-1) and S2M of the selected Mth combination are transmitted to the current subtractor I_Mi to perform the current calculation of the subtraction IS2M-IS(2M-1). The output currents of the source lines of other unselected combinations are not allowed to be transmitted to the current subtractor I_Mi. Similarly, when the Mth combination is selected, the value of the address code at this time is switched to the only enable code value that can activate the Mth combination to be valid (enable), such as

[01100] . If the value of the address code at this time is any value other than the enable code value corresponding to the Mth combination (active code), such as

[01101] , the Mth combination will be inactivated and the output currents of its source lines cannot be transmitted to the current subtractor I_Mi through the MUX.

[0142] See also Figure 5Continuing with the above, when any combination is selected, for example, any one of the first through Mth combinations (for example, the Kth combination), the value of the address code Sel at this time switches to the only active code value that can activate that combination (for example, the Kth combination) to a valid value. Please note that if the combination (for example, the Kth combination) cannot be activated to a valid value but is disabled, then the value of the address code at this time cannot be called an active code value but rather a non-active code value. In this embodiment, a positive integer K can be set to 1, 2, 3, ..., M. 1≤K≤M.

[0143] See also Figure 5 , as mentioned above, when any combination (taking the first combination as an example) is selected, the value of the address code at this time switches to the only enable code value that can activate any combination (such as the first combination) to be valid. Assuming that the enable code value is a certain value

[01001] , Sel =

[01001] , select a code element of a specified weight bit in the enable code value

[01001] . For example, the enable code value can be expressed as Sel[4] = 0, Sel[3] = 1, Sel[2] = 0, Sel[1] = 0, Sel[0] = 1, and let the specified weight bit selected in the enable code value be Sel[1], the highest weight bit is Sel[4] and the lowest weight bit is Sel[0]. Then the specified weight bit selected in the enable code value is the second lowest weight bit Sel[1]. Of course, the specified weight bit can also be the lowest bit, the highest bit, the second highest bit, the third highest bit, etc. Here, the second lowest weight bit Sel[1] is used as the specified weight bit. Select the code element of the aforementioned specified weight bit Sel[1] in the enable code value, such as binary 0. If the code element is flipped, the source lines S1 and S2 of the two rows of transistors belonging to the first combination, namely the first row and the second row of transistors, are connected through the coupling capacitor C. C Transient coupling is performed once. If the code element of the weight bit Sel[1] in the enable code value changes from binary 0 to 1, the code element is flipped.

[0144] See also Figure 5, as mentioned above, when any combination (taking the second combination as an example) is selected, the value of the address code at this time switches to the only enable code value that can activate any combination (such as the second combination) to be valid. Assuming that the enable code value is a certain value

[01010] , Sel =

[01010] , select a code element of a specified weight bit in the enable code value

[01010] . For example, the enable code value can be expressed as Sel[4] = 0, Sel[3] = 1, Sel[2] = 0, Sel[1] = 1, Sel[0] = 0, and let the specified weight bit selected in the enable code value be Sel[0], the highest weight bit is Sel[4] and the lowest weight bit is Sel[0]. Then the specified weight bit selected in the enable code value is the lowest weight bit Sel[0]. Of course, the specified weight bit can also be the second lowest bit, the highest bit, the second highest bit, the third highest bit, etc. Here, the lowest weight bit Sel[0] is used as the specified weight bit. Select the code element of the aforementioned specified weight bit Sel[0] in the enable code value, for example, binary 0. If the code element is flipped, the source lines S3 and S4 of the two rows of transistors belonging to the second combination, namely the third and fourth rows of transistors, are connected through the coupling capacitor C. C Transient coupling is performed once. If the code element of the weighted bit Sel[0] in the enable code value changes from binary 0 to 1, the code element is flipped.

[0145] See also Figure 6 When any combination is selected, the address code value switches to a unique enable code value that can activate that combination. A code element with a specified weight bit is selected in the enable code value. If the code element flips, the source lines of the two rows of transistors belonging to that combination are transiently coupled once through the coupling capacitor. This is used to achieve charge balance between the parasitic capacitances of the source lines of the two rows of transistors belonging to that combination, thereby expanding the number of columns in the storage transistor array to adapt to the columns of the table in the weight matrix of the neural network (for example, adapting the number of array columns N to the number of matrix columns n).

[0146] See also Figure 7 When the first combination (the first and second rows of transistors) is selected, the value of the address code is switched to the only enable code value that can activate any combination to a valid value, such as Sel =

[01001] . In the enable code value, a code element of a specified weight bit is selected, such as Sel[1]. If the code element of Sel[1] is flipped, the source lines S1 and S2 of the two rows of transistors belonging to any combination are connected through the coupling capacitor C. C Transient coupling is once used for the parasitic capacitance C of the source lines S1 and S2 of the two rows of transistors belonging to any combination. P1 、C P2 The number of columns in the transistor array is expanded to match the number of columns in the weight matrix of the neural network (e.g. N matches n). P1The parasitic capacitance value at the source line S1 is the parasitic capacitance C P2 The parasitic capacitance value at the source line S2. The source or components of parasitic capacitance are relatively complex, such as the external capacitance of the slender source line itself, the source parasitic capacitance of each transistor mounted on the source line, the capacitance of the source line to the substrate, and the associated capacitance between the source line and other conductors. C As an example of a coupling capacitor, for example, a transistor with its source and drain short-circuited is used as a coupling capacitor.

[0147] See also Figure 6 , the switch TR1 is controlled by the control module CTL. The control module CTL includes, for example, a falling edge capture circuit or a rising edge capture circuit, which can also be called a falling edge detection circuit or a rising edge detection circuit, to realize the capture of the code element of the specified weight bit in the enable code value, such as the code element flip of Sel[1]. The control module CTL, for example, the so-called falling edge capture circuit or the rising edge capture circuit acts as a monostable trigger circuit (one shot), that is, when the falling edge capture circuit or the rising edge capture circuit senses the flip of the code element Sel[1], it generates an extremely narrow pulse signal for controlling the switch TR1. That is, the code element Sel[1] of the specified weight bit is selected in the enable code value. If the code element Sel[1] flips, the source lines S1 and S2 of the two rows of transistors belonging to the first combination are connected through the coupling capacitor C C Transient coupling once. When a very narrow pulse signal appears, such as a high level signal, the control switch TR1 is transiently turned on once, and the source lines S1 and S2 pass through C C and TR1 transient coupling. Considering that the weight is characterized by the difference in threshold voltages of a pair of complementary transistors located in the same column but arranged in two rows in the memory transistor array, and the threshold voltages of complementary transistors are naturally different, it will inevitably lead to the parasitic capacitance C of the source lines S1 and S2 of the two rows of transistors in the first combination. P1 、C P2 There are inherent differences in the amount of charge. The smaller the threshold voltage, the greater the current flowing from the corresponding transistor to the source line and the greater the amount of parasitic capacitance charging of the corresponding source line. The larger the threshold voltage, the smaller the current flowing from the corresponding transistor to the source line and the less the amount of parasitic capacitance charging of the corresponding source line. Parasitic capacitance with a large amount of charge will inevitably flow its own large charge charging current to the current subtractor I_Mi, resulting in a part of the hidden current in the difference between the output currents at the source lines of the two rows of transistors. An output data of the neural network is represented by the ratio of the difference between the output currents at the source lines S1 and S2 of the two rows of transistors in the first combination divided by the preset coefficient. The additional hidden current means that an output data of the neural network at the first combination has deviated. However, according to this article, the parasitic capacitance C of the source lines S1 and S2 of the two rows of transistors in the first combination P1 、C P2To achieve charge balance between the two source lines, the transient coupling of the two source lines will cause the parasitic capacitors with large charge, such as C P1 Transiently releases part of the power to another such as C P2 Before a set of output currents at the two source lines S1 and S2 are delivered to the current subtractor, a balanced adjustment is made to make the charge of the parasitic capacitance of the two source lines converge, so as to avoid the additional current caused by the unbalanced charge of the parasitic capacitance of the two source lines introduced into the current difference IS12 of a set of output currents IS1 and IS2. The additional current means the deviation of the result. The parasitic capacitance C of the source lines S1 and S2 of the two rows of transistors in the first combination is equal to the charge of the parasitic capacitance of the two source lines. P1 、C P2 The charge balance is achieved between the two rows of transistors. The parasitic capacitance C of the source lines S1 and S2 of the two rows of transistors is P1 、C P2 Before the current difference calculation is performed on the set of output currents IS1 and IS2 at the source lines S1 and S2 of the two rows of transistors, a charge equalization adjustment is performed to make the charge equal. This avoids the additional introduction of the parasitic capacitances of the source lines S1 and S2 of the two rows of transistors, i.e., C, into the current difference IS12 of the set of output currents IS1 and IS2 due to the difference in threshold voltages of any pair of complementary transistors in the two rows of transistors belonging to the first combination. P1 、C P2 The additional current is caused by the unbalanced charge.

[0148] See also Figure 6 Optionally, when any combination is selected, the value of the address code is switched to the only enable code value that can activate the any combination to be valid, and a code element of a specified weight bit is selected in the enable code value. If the code element is flipped, the source lines of the two rows of transistors to which the any combination belongs are transiently coupled once through the coupling capacitor. It is used to achieve charge balance between the parasitic capacitances of the source lines of the two rows of transistors to which the any combination belongs. Before the current difference calculation is performed on a set of output currents at the source lines of the two rows of transistors, there is a single charge balance adjustment to make the charge of the parasitic capacitances of the source lines of the two rows of transistors converge, so as to avoid the additional current caused by the unbalanced charge of the parasitic capacitances of the source lines of the two rows of transistors introduced into the current difference of the set of output currents due to the difference in threshold voltages of any pair of complementary transistors in the two rows of transistors to which the any combination belongs. Any combination includes the first combination to the Mth combination.

[0149] See also Figure 7 For the first combination, connect C between source lines S1 and S2. CTR1 and TR1 are controlled by the sub-control module C1 in the control module CTL. The sub-control module C1 includes a falling edge capture circuit or a rising edge capture circuit acting as a monostable trigger circuit SH, and also includes a latch LK. The data comparison circuit of the latch LK compares the current value of the address code with the only enable code value that can activate the first combination to be valid, such as Sel =

[01001] . If the current value of the address code, such as Sel [4:0], is equal to the enable code value, the latch LK issues an enable signal En. The enable signal notifies the monostable trigger circuit SH that it can sense the flip of the code element Sel [1]. If a flip occurs, an extremely narrow pulse signal is generated to control the switch TR1. If the current value of the address code, such as Sel [4:0], is not equal to the enable code value, the latch LK issues a disable signal Dis that is the opposite of the enable signal. The disable signal locks the monostable trigger circuit SH and cannot control TR1. For example, at this time, an extremely narrow pulse signal cannot be generated to control the switch TR1. If the code element Sel[1] is flipped, the source lines S1 and S2 of the two rows of transistors belonging to the first combination are connected through the coupling capacitor C C Transient coupling once. The premise for transiently coupling the source lines of the two rows of transistors belonging to any combination, such as S1 and S2, through the coupling capacitor is that the current value of the address code changes from the active code value to the non-active code value; on the contrary, if the current value of the address code changes from the non-active code value to the active code value, then the source lines S1 and S2 of the two rows of transistors belonging to any combination are not allowed to be transiently coupled through the coupling capacitor under this condition. The transient coupling event of the source lines of the two rows of transistors belonging to any combination is based on the fact that the any combination switches from a selected state to an unselected state at the multiplexer, rather than from an unselected state to a selected state. Otherwise, the charge balance of the two source lines loses its original purpose and the transient coupling becomes meaningless.

[0150] See also Figure 7 For the second combination, connect C between source lines S3 and S4. CTR2 and TR2 are controlled by another sub-control module within control module CTL. This sub-control module also includes a falling edge capture circuit or a rising edge capture circuit acting as a monostable trigger circuit SH, and a latch LK. The data comparison circuit of latch LK compares the current value of the address code with the only enable code value that can activate the first valid combination, such as Sel =

[01010] . If the current value of the address code, such as Sel[4:0], is equal to the enable code value, latch LK issues an enable signal En. The enable signal notifies the monostable trigger circuit SH that it can sense the flip-flop of code element Sel[0]. If a flip-flop occurs, a very narrow pulse signal is generated to control switch TR2. If the current value of the address code, such as Sel[4:0], is not equal to the enable code value, latch LK issues a disable signal Dis, which is the opposite of the enable signal. The disable signal locks the monostable trigger circuit SH, making it unable to control TR1. For example, at this time, it is impossible to generate a very narrow pulse signal to control switch TR2. If the code element Sel[0] is flipped, the source lines S3 and S4 of the two rows of transistors belonging to the second combination are connected through the coupling capacitor C C Transient coupling once. Similarly, the premise for the transient coupling of the source lines of the two rows of transistors belonging to any combination, such as S3 and S4, through the coupling capacitor is that the current value of the address code changes from an active code value to a non-active code value; conversely, if the current value of the address code changes from a non-active code value to an active code value, then the source lines S3 and S4 of the two rows of transistors belonging to any combination are not allowed to be transiently coupled through the coupling capacitor under this condition. The transient coupling event of the source lines of the two rows of transistors belonging to any combination is based on the fact that any combination switches from a selected state to a non-selected state at the multiplexer, rather than from a non-selected state to a selected state.

[0151] See also Figure 7 For the Mth combination, it is also configured to connect the source lines S2M and S(2M-1) of the two rows of transistors belonging to the Mth combination through the coupling capacitor C C The transient coupling is performed once on the switch TRM.

[0152] See also Figure 7 When the first combination is selected, the value of the address code is switched to the only valid enable code value that can activate the first combination, such as Sel =

[01001] . The enable code value selects a specified weight bit code element, such as Sel [1]. If the code element flips, such as from binary 0 to 1, the source lines S1 and S2 of the first row transistors and the second row transistors of the first combination are connected through the coupling capacitor C. CTransient coupling once. If the code element flips, the gate voltages of the two rows of transistors belonging to the first combination (i.e., the word line voltages of G1 and G2) are also synchronously pulled down to a voltage lower than the potential when the neural network is running. When the neural network uses the weight matrix to perform matrix operations, if it is assumed that the word line potentials of G1 and G2 are V_G1 / G2 when the neural network is running, then if the code element flips, the gate voltages of the two rows of transistors belonging to the first combination must be lower than V_G1 / G2. The gate voltage is pulled down by the flip event of the code element Sel[1] and can be performed using any method or circuit in the prior art that can pull down the potential. For example, a pull-down switch is set between the gates of the two rows of transistors and a potential VG lower than V_G1 / G2, and the flip event of the code element Sel[1] is captured by the falling edge capture circuit or the rising edge capture circuit as a monostable trigger circuit SH. The extremely narrow pulse signal output by the monostable trigger circuit controls the pull-down switch to be turned on briefly, during which the voltages of G1 and G2 are pulled down to VG. Therefore, if the code element flips, the current voltage of the gate of the two rows of transistors belonging to the first combination (note that the first combination is temporarily separated from the neural network calculation due to the flip of the code element Sel[1]) is also synchronously pulled down to a potential V_G1 / G2 lower than the gate potential of the first combination when participating in the neural network calculation. The current gate voltage is pulled to VG as follows. Note that one of the important purposes is to prevent the floating gate injection charge of the first and second rows of transistors belonging to the first combination from being programmed by the transient current caused by the transient short circuit between the pair of source lines S1 and S2 of the two rows of transistors belonging to the first combination. If the gate voltage is not pulled down to VG but instead remains at a higher level, such as V_G1 / G2, the parasitic capacitor with the higher charge in source lines S1 or S2 will lose voltage due to the transient short, generating a transient current between source lines S1 and S2. This transient voltage drop and the large charge release in the source line, such as S2, will create a sudden voltage difference between the gates of the transistors in the row corresponding to the discharge source line, such as word line G2. This will cause the floating gates of the transistors in the row corresponding to G2 to absorb tunneling charge, effectively implicitly changing the preset weight value and causing the floating gate charge to be programmed by the transient current. Conversely, if the gate voltage is pulled down to VG, the transient voltage difference between the gates of the transistors in the row corresponding to source line S2, such as word line G2, and the discharge source line S2 is reduced, preventing the floating gate charge of the first and second rows of transistors in the first combination from being programmed by the transient current caused by the transient short between the pair of source lines S1 and S2 in the first combination. Another important purpose is to reduce the current flowing into the source lines S1 and S2 of the first and second rows of transistors belonging to the first combination during the symbol flipping period, such as the flipping period of the symbol Sel[1].If the current gate voltage is not pulled down to VG but instead remains at a higher level, such as V_G1 / G2, the two rows of transistors corresponding to word lines G1 and G2 will each have a larger current flowing through them under the higher gate voltage V_G1 / G2, that is, the drain current has a higher current level. This will cause a larger current to flow into source lines S1 and S2 during the code element flip period. The large current on source lines S1 and S2 will completely defeat the original purpose of transiently coupling the source lines of the two rows of transistors in the first combination through the coupling capacitor during the code element flip period. As mentioned above, the weight is characterized by the difference in threshold voltages of a corresponding pair of complementary transistors located in the same column but arranged in two rows in the memory transistor array. The natural difference in threshold voltages of complementary transistors will inevitably lead to parasitic capacitance C on the source lines S1 and S2 of the two rows of transistors in the first combination. P1 、C P2 The large current in the source line during the symbol flip period will cause the parasitic capacitance C P1 、C P2 The difference in charge between the two rows is further amplified, which is related to the parasitic capacitance C of the source lines of the two rows of transistors in the first combination. P1 、C P2 When the code element is flipped, the current voltage of the gate of the two rows of transistors belonging to the first combination is pulled down to a level lower than the gate potential of the first combination when participating in the neural network calculation, reducing the current flowing from the source lines S1 and S2 of the two rows of transistors belonging to the first combination during the code element flip period from the first and second rows of transistors, avoiding C P1 、C P2 The difference in charge is further amplified.

[0153] See also Figure 7 In the optional example, when any combination is selected, the value of the address code at this time is switched to the only enable code value that can activate the any combination to be valid, and a code element of a specified weight bit is selected in the enable code value. If the code element is flipped, the source lines of the two rows of transistors belonging to the any combination are transiently coupled once through the coupling capacitor. If the code element is flipped, the current voltage of the gate of the two rows of transistors belonging to the any combination is also synchronously pulled down to a level lower than the gate potential of the any combination when participating in the neural network calculation. This is to prevent the floating gate injection charge of the two rows of transistors belonging to the any combination from being programmed by the transient current of the transient short circuit between the pair of source lines of the two rows of transistors belonging to the any combination. And reduce the current flowing from the two rows of transistors belonging to the any combination to the pair of source lines during the code element flip period. For the explanation, please refer to the relevant embodiments of V_G1 / G2 and VG mentioned above.

[0154] See also Figure 4This application also relates to an artificial intelligence integrated memory, comprising a flash memory having a memory transistor array for constructing and implementing a neural network. The memory transistor array serves as a carrier for the neural network's weight matrix. The neural network's input data is transmitted to a series of bit lines in the memory transistor array, and the neural network's output data is captured from a series of source lines in the memory transistor array, enabling the memory to integrate artificial intelligence computing functions based on the neural network. Each weight in the neural network's weight matrix is ​​represented by the difference in threshold voltages between a pair of complementary transistors located in the same column but arranged in two rows in the memory transistor array. The gates of any pair of complementary transistors are coupled together, and the drains of any pair of complementary transistors are coupled to the same bit line. The raw input data of the neural network is converted into voltage-formatted input quantities and then input to the bit lines of the memory transistor array. The ratio of the difference in output currents from the source lines of each pair of transistors in each row of the memory transistor array divided by a preset coefficient K serves as output data for the neural network. The artificial intelligence integrated memory includes an in-memory computing chip.

[0155] The above description and accompanying drawings provide exemplary embodiments of specific structures of the present invention. The present invention provides preferred embodiments thereof, but these descriptions are not intended to be limiting. Various changes and modifications will undoubtedly become apparent to those skilled in the art upon reading the above description. Therefore, the appended claims should be construed to cover all changes and modifications within the true intent and scope of the present invention.

Claims

1. A storage and calculation method based on flash memory, characterized in that: include: A flash memory-based memory is provided, which has a memory transistor array; Using a memory transistor array as a carrier of a neural network's weight matrix, setting the neural network's input data to be transmitted to a series of bit lines of the memory transistor array, and setting the neural network's output data to be retrieved from a series of source lines of the memory transistor array, thereby achieving flash memory-based storage and computing; wherein each weight in the weight matrix of the neural network is represented by a difference in threshold voltages of a corresponding pair of complementary transistors located in the same column but arranged in two rows in the memory transistor array, the gates of any pair of complementary transistors being coupled together, and the drains of any pair of complementary transistors being coupled to the same bit line; The memory transistor array uses a combination of two rows of transistors to define a row of weights in the weight matrix. Multiple rows of transistors in the memory transistor array provide multiple combinations. A multiplexer is used to time-share a set of output currents at the source lines of the different combinations and transmit them to a current subtractor. The current subtractor calculates the current difference between the output currents at the source lines of the two rows of transistors corresponding to each combination. The address code that controls the multiplexer is used to determine whether any combination is selected. When any combination is selected, the value of the address code switches to a unique enable code value that can activate the combination to a valid state. A code element with a specified weight bit is selected in the enable code value. If the code element is flipped, the source lines of the two rows of transistors belonging to the combination are transiently coupled once through a coupling capacitor to achieve charge balancing between the parasitic capacitances of the source lines of the two rows of transistors belonging to the combination.

2. The method according to claim 1, wherein: The raw input data of the neural network is converted into an input quantity in a voltage value format, and is transmitted to a series of bit lines of the memory transistor array based on the input quantity sorted into a vector; Any pair of complementary transistors receives the voltage value on the bit line of the column where they are located, so that the difference between the drain-source voltages of the any pair of complementary transistors is the same.

3. The method according to claim 1, wherein: An output data of the neural network is represented by a ratio of a difference between the output currents at the source lines of two rows of transistors corresponding to a row of weights divided by a preset coefficient, wherein any two transistors in the two rows of transistors located in the same column and sharing a common bit line are considered to be a pair of complementary transistors; The multiple ratios provided by a series of source lines of the memory transistor array are regarded as output quantities arranged into a vector provided by the memory transistor array.

4. The method according to claim 1, wherein: The method of adjusting any weight in the weight matrix includes: changing the floating gate injection charge of each pair of complementary transistors selected by the any weight, adjusting the difference in the threshold voltages of the two selected complementary transistors by the relative change of the floating gate injection charge of the two selected complementary transistors, and then adjusting the size of the weight at the position of the selected pair of complementary transistors.

5. The method according to claim 1, wherein: A digital-to-analog converter is arranged at the bit line of the storage transistor array, and is used to convert the input data of the neural network into a voltage value that meets the input signal format requirement of the bit line.

6. The method according to claim 1, wherein: An analog-to-digital converter is configured at the source line of the storage transistor array, and is used to convert the output signal in the form of output current at the source line into output data that meets the digital output format requirements of the neural network.

7. The method according to claim 1, wherein: The address code that controls the multiplexer is used to determine whether any combination is selected; Only a group of output currents at the two source lines of a selected combination is delivered to the current subtractor, and a group of output currents at the two source lines of the other unselected combinations are not allowed to be delivered to the current subtractor.

8. An artificial intelligence integrated memory, characterized in that: include: Memory in the form of flash memory with an array of memory transistors used to construct a neural network implementation; Using a memory transistor array as a carrier of a weight matrix of a neural network, setting the input data of the neural network to be transmitted to a series of bit lines of the memory transistor array, and setting the output data of the neural network to be retrieved from a series of source lines of the memory transistor array, so that the memory integrates artificial intelligence computing functions based on the neural network; Each weight in the weight matrix of the neural network is represented by the difference in threshold voltages of a corresponding pair of complementary transistors located in the same column but arranged in two rows in the memory transistor array, the gates of any pair of complementary transistors being coupled together, and the drains of any pair of complementary transistors being coupled to the same bit line; The original input data of the neural network is converted into an input quantity in a voltage value format and then transmitted to the bit line of the storage transistor array. The difference between the output currents of the source lines of each of the two rows of transistors in the storage transistor array is divided by a preset coefficient to serve as an output data of the neural network. The memory transistor array uses a combination of two rows of transistors to define a row of weights in the weight matrix. Multiple rows of transistors in the memory transistor array provide multiple combinations. A multiplexer is used to time-share a set of output currents at the source lines of the different combinations and transmit them to a current subtractor. The current subtractor calculates the current difference between the output currents at the source lines of the two rows of transistors corresponding to each combination. The address code that controls the multiplexer is used to determine whether any combination is selected. When any combination is selected, the value of the address code switches to a unique enable code value that can activate the combination to a valid state. A code element with a specified weight bit is selected in the enable code value. If the code element is flipped, the source lines of the two rows of transistors belonging to the combination are transiently coupled once through a coupling capacitor to achieve charge balancing between the parasitic capacitances of the source lines of the two rows of transistors belonging to the combination.

9. The artificial intelligence integrated memory according to claim 8, characterized in that: A digital-to-analog converter is configured at the bit line of the storage transistor array, and is used to convert the input data of the neural network into a voltage value that meets the input signal format requirement of the bit line; An analog-to-digital converter is configured at the source line of the storage transistor array, and is used to convert the output signal in the form of output current at the source line into output data that meets the digital output format requirements of the neural network.

10. A storage and calculation method based on flash memory, characterized in that: include: A flash memory-based memory is provided, which has a memory transistor array; Using a memory transistor array as a carrier of a neural network's weight matrix, setting the neural network's input data to be transmitted to a series of bit lines of the memory transistor array, and setting the neural network's output data to be retrieved from a series of source lines of the memory transistor array, thereby achieving flash memory-based storage and computing; wherein each weight in the weight matrix of the neural network is represented by a difference in threshold voltages of a corresponding pair of complementary transistors located in the same column but arranged in two rows in the memory transistor array, the gates of any pair of complementary transistors being coupled together, and the drains of any pair of complementary transistors being coupled to the same bit line; The memory transistor array uses a combination of two rows of transistors to define a row of weights in the weight matrix. Multiple rows of transistors in the memory transistor array provide multiple combinations. A multiplexer is used to time-share a set of output currents at the source lines of the different combinations and transmit them to a current subtractor. The current subtractor calculates the current difference between the output currents at the source lines of the two rows of transistors corresponding to each combination. The address code that controls the multiplexer is used to determine whether any combination is selected. When any combination is selected, the value of the address code is switched to a unique enable code value that can activate the combination to a valid state. A code element with a specified weight bit is selected in the enable code value. If the code element is flipped, the source lines of the two rows of transistors belonging to the combination are transiently coupled once through a coupling capacitor. If the code element is flipped, the current voltage of the gates of the two rows of transistors belonging to the combination is also synchronously lowered to a level lower than the gate potential of the combination when participating in the neural network calculation, so as to prevent the floating gate injection charge of the two rows of transistors belonging to the combination from being programmed by the transient current caused by the transient short circuit between a pair of source lines of the two rows of transistors belonging to the combination.

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