Quantum adder, operation method and related device

Abstract

The invention discloses a quantum adder, an operation method and a related device, the quantum adder comprises a plurality of chips connected through an EPR module, one chip is used for processing one data segment, the data segment comprises an addend segment and an addend segment, and the chip comprises an addition module used for adding the addend segment and the addend segment based on quantum Fourier transform, obtaining an addition result and carry information of the data segments; the loading module is used for loading the carry information transmitted by the EPR module to the addition result and the carry information obtained by the chip based on the addition module so as to update the addition result and the carry information of the chip; and the inverse quantum Fourier transform module is used for converting the newest addition result into a binary string. According to the embodiment of the invention, the efficiency of additive operation in quantum calculation can be improved.

Description

Technical Field

[0001] The present application belongs to the field of quantum computing technology, and in particular to a quantum adder, a calculation method and related devices. Background Art

[0002] With the rapid development of quantum computing, the number of quantum bits required is increasing. Due to the difficulty of quantum bit integration, it is necessary to connect multiple small-bit chips to form a large-bit chip to achieve large-scale quantum computing, thereby promoting the development of quantum computing.

[0003] A large-bit chip composed of small-bit chips needs to realize entanglement operations between small-bit chips, and a quantum / classical hybrid channel is indispensable. The current popular solution is teleportation to achieve entanglement operations. To execute quantum algorithms on a chip "integrated" using teleportation, the algorithm needs to be distributed to each small-bit chip to achieve distribution. Specifically, Figure 1 As shown in the figure, each small bit chip realizes teleportation through EPR (the abbreviation of the initials of Einstein, Podolsky and Rosen). The complexity of teleportation operation is very high. The time required to perform a teleportation operation is equivalent to the time required to operate thousands of quantum logic gates.

[0004] Currently, distributed adders are created by splitting quantum circuits. Each sub-circuit runs on a small-bit chip. The splitting of quantum circuits also decomposes the multi-bit quantum logic gates acting on the two sub-circuits. After the decomposition, the multi-bit quantum logic gates are located on different small-bit chips. In order to realize the addition function, many teleportation operations are required, and too many teleportation operations will seriously affect the efficiency of addition in quantum computing. Summary of the invention

[0005] The purpose of this application is to provide a quantum adder, a calculation method and related devices, aiming to improve the calculation efficiency of addition in quantum computing.

[0006] An embodiment of the present application provides a quantum adder, the quantum adder comprising a plurality of chips connected via an EPR module, one chip being used to process a data segment, the data segment comprising a addend segment and a summand segment, the chip comprising:

[0007] An addition module, used to obtain the addition result and carry information of the data segments based on quantum Fourier transform;

[0008] A loading module, used for loading the carry information transmitted by the EPR module onto the addition result and carry information obtained by the chip based on the addition module, so as to update the addition result and carry information of the chip;

[0009] The inverse quantum Fourier transform module is used to convert the latest addition result into a binary string.

[0010] Optionally, the addition module acts on a first quantum bit, a second quantum bit and a third quantum bit in the chip, wherein the first quantum bit is a quantum bit allocated to the addend segment in the chip, the second quantum bit is a quantum bit allocated to the addend segment in the chip, and the third quantum bit is a quantum bit allocated to the chip for storing carry information.

[0011] Optionally, the EPR module acts on the third quantum bit and the fourth quantum bit of one chip, and the fourth quantum bit and the fifth quantum bit of another chip, wherein the fourth quantum bit is a quantum bit allocated in the chip to generate an EPR pair, and the fifth quantum bit is a quantum bit allocated in the chip to receive carry information updated by other chips.

[0012] Optionally, the loading module is used to load the received carry information as the lowest bit data of the addition result into the phase of the quantum state corresponding to the second quantum bit and the third quantum bit of the chip, wherein the second quantum bit stores the addition result.

[0013] Optionally, the quantum adder further includes an inverse EPR module for setting the fifth quantum bit in the chip to a |0> state.

[0014] Optionally, the quantum adder further includes a return-to-zero module, which is used to set the third quantum bit and / or the fifth quantum bit in the specific chip to the |0> state without changing the addition result of the data segment of the specific chip.

[0015] Another embodiment of the present application provides a computing method, the method comprising:

[0016] Processing the added data to obtain data segments;

[0017] Using any of the above-mentioned quantum adders, a binary string representing the result of each data segment addition is obtained;

[0018] Based on all binary strings, the operation result of the data to be added is generated.

[0019] Optionally, the method further comprises:

[0020] When all binary strings are obtained, the return-to-zero modules in the specific chip are executed in sequence according to the sequence numbers of the data segments from high to low.

[0021] Another embodiment of the present application provides a computing device, the device comprising:

[0022] A processing module, used for processing the data to be added to obtain data segments;

[0023] An acquisition module, used to obtain a binary string representing the result of each data segment addition using any of the above-mentioned quantum adders;

[0024] A generating module is used to generate the operation result of the data to be added based on all binary strings.

[0025] An embodiment of the present application provides a storage medium, in which a computer program is stored, wherein the computer program is configured to implement any of the above-mentioned quantum adders and / or any of the above-mentioned computing methods when running.

[0026] An embodiment of the present application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to implement any of the above-described quantum adders and / or any of the above-described computing methods.

[0027] Compared with the prior art, the present application provides a quantum adder, the quantum adder includes a plurality of chips connected by an EPR module, one chip is used to process a data segment, the data segment includes an addend segment and an augend segment; the chip includes an addition module, which is used to obtain the addition result and carry information of the data segment based on quantum Fourier transform; a loading module, which is used to load the carry information transmitted by the EPR module onto the addition result and carry information obtained by the chip based on the addition module to update the addition result and carry information of the chip; an inverse quantum Fourier transform module, which is used to convert the latest addition result into a binary string. In the present application, one chip processes one data segment, and no carry is required in one chip. The carry information is transmitted through the EPR module, and there is no need to split the quantum circuit, so the decomposition of the quantum logic gate is greatly reduced, and the number of teleportation operations is greatly reduced, thereby reducing the time required for addition operations and improving the operation efficiency of addition in quantum computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A schematic diagram of a distributed structure for running a quantum algorithm provided in this application;

[0029] Figure 2A network block diagram of a quantum computing system for implementing a quantum adder provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of the structure of a quantum adder provided in an embodiment of the present application;

[0031] Figure 4 A schematic diagram of a quantum circuit of a QFTA provided in an embodiment of the present application;

[0032] Figure 5 A schematic diagram of another quantum circuit of QFTA provided in an embodiment of the present application;

[0033] Figure 6 A schematic diagram of a quantum circuit of a quantum adder provided in an embodiment of the present application;

[0034] Figure 7 A schematic diagram of a quantum circuit of another quantum adder provided in an embodiment of the present application;

[0035] Figure 8 A flowchart of a calculation method provided in an embodiment of the present application;

[0036] Fig. 9 A schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0037] Fig.10 A schematic diagram of the structure of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application. They are only intended to help those skilled in the art to better understand the implementation methods of the present application and are not to be construed as limitations on the present application.

[0039] In various implementations in the present application, the size of the sequence number of each process does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the implementation method of the present application. It should be noted that unless otherwise specifically stated, the relative arrangement of the components and steps, numerical expressions and numerical values ​​described in these embodiments do not limit the scope of the present application. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present application and its application or use.

[0040] The techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0041] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0042] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0043] Figure 2 1 is a network block diagram of a quantum computing system for implementing a quantum adder provided in an embodiment of the present application. The quantum computing system may include a network 110, a server 130, a wireless device 130, a client 140, a storage unit 150, a classical processing system 160, a quantum processing system 170, and may also include additional memories, classical processors, quantum processors, and other devices not shown.

[0044] Network 110 is a medium used to provide communication links between various devices and computers connected together in the quantum computing system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks and combinations thereof. The connection method can be wired, wireless communication links or optical fiber cables, etc.

[0045] The server 130 and the client 140 are conventional data processing systems that may contain data and applications or software tools that perform conventional computing processes. The client 140 may be a personal computer or a network computer, so the data may also be provided by the server 130. The wireless device 130 may be a smart phone, a tablet, a laptop, a smart wearable device, etc. The storage unit 150 may include a database 151, which may be configured to store data such as quantum bit parameters, quantum logic gate parameters, quantum circuits, quantum programs, etc.

[0046] The classical processing system 160 (quantum processing system 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 163 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application 162 (application 173). The application 162 (application 173) may be used to implement a quantum adder provided according to an embodiment of the present application.

[0047] Any data or information stored or generated in the classical processing system 160 (quantum processing system 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application program executed by it can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0048] It should be noted that a true quantum computer is a hybrid structure, which includes at least Figure 1 There are two major parts in it: the classical processing system 160, which is responsible for performing classical calculations and control; and the quantum processing system 170, which is responsible for running quantum programs and thus realizing quantum calculations.

[0049] The classical processing system 160 and the quantum processing system 170 may be integrated into one device or distributed in two different devices. For example, the first device including the classical processing system 160 runs a classical computer operating system, on which quantum application development tools and services are provided, as well as storage and network services required for quantum applications. Users develop quantum applications through the quantum application development tools and services thereon, and send quantum programs to the second device including the quantum processing system 170 through the network services thereon. The second device runs a quantum computer operating system, parses the code of the quantum program through the quantum computer operating system, and compiles it into instructions that can be recognized and executed by the quantum computer measurement and control system. The quantum processor 170 implements the quantum algorithm corresponding to the quantum program according to the instructions.

[0050] In the classic processing system 160 based on silicon chips, the unit of the classic processor 161 is a CMOS tube. This computing unit is not limited by time and coherence, that is, this computing unit is not limited by the length of use and is available at any time. In addition, in silicon chips, the number of such computing units is also sufficient. Currently, the number of computing units in a classic processor is tens of thousands. The number of computing units is sufficient and the computing logic that can be selected by the CMOS tube is fixed, for example: AND logic. When calculating with the help of CMOS tubes, a large number of CMOS tubes are combined with limited logic functions to achieve the calculation effect.

[0051] Unlike this logic unit in the classical processing system 160, the basic computing unit of the quantum processor 171 in the quantum processing system 170 is a quantum bit, and the input of the quantum bit is limited by coherence and coherence time, that is, the quantum bit is limited by the use time and is not available at any time. Making full use of the quantum bit within the available use time of the quantum bit is a key problem in quantum computing. In addition, the number of quantum bits in a quantum computer is one of the representative indicators of the performance of a quantum computer. Each quantum bit realizes the computing function through the logical function configured on demand. In view of the limited number of quantum bits, the logical functions in the field of quantum computing are diverse, such as: Hadamard gate (Hadamard gate, H gate), Pauli-X gate (X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), X gate, RY gate, RZ gate, CNOT gate, CR gate, iSWAP gate, Toffoli gate, etc. In quantum computing, it is necessary to use limited quantum bits combined with a variety of logical functions to achieve the computing effect.

[0052] Based on these differences, the design of the logical function acting on quantum bits (including the design of whether the quantum bits are used or not and the design of the efficiency of the use of each quantum bit) is the key to improving the computing performance of quantum computers and requires special design. The above-mentioned design for quantum bits is a technical problem that ordinary computing devices do not need to consider or face. Based on this, in order to improve the computing efficiency of addition in quantum computing, this application proposes a quantum adder, computing method and related devices, aiming to improve the computing efficiency of addition in quantum computing.

[0053] See also Figure 3 , Figure 3 A schematic diagram of the structure of a quantum adder provided in an embodiment of the present application, wherein the quantum adder 300 includes a plurality of chips 301 connected via an EPR module 302, wherein one chip 301 is used to process one data segment, wherein the data segment includes an addend segment and an augend segment, and the chip 301 includes:

[0054] An addition module 3011 is used to obtain the addition result and carry information of the data segments based on quantum Fourier transform;

[0055] A loading module 3012, used for loading the carry information transmitted by the EPR module 302 onto the addition result and carry information obtained by the chip 301 based on the addition module 3011, so as to update the addition result and carry information of the chip 301;

[0056] The inverse quantum Fourier transform module 3013 is used to convert the latest addition result into a binary string.

[0057] The quantum adder is used to calculate the sum of the data to be added. The data segmentation is obtained after processing the data to be added. The data to be added includes addends and augends, which can be in binary form. By dividing the binary data string, the corresponding segmentation can be obtained. According to the number of quantum bits of the chip, the augend b can be divided into b t b t-1 …b 0 , divide the addend a into a t a t -1 …a 0 , a data segment includes a summand segment b t and an addend segment a t The length of a data segment is determined by the number of quantum bits in the chip. When the number of quantum bits in the chip is different, different data segments can also have different lengths. The summand segments and addend segments can be numbered in order from low to high. For example, the summand b = 011110 is processed into 3 data segments, then b 3 =01, b 2 =11, b 1 =10, b 1 The lowest bit of the addend is segmented, b 2 Compared to b 1 The high-order bits of the summand are segmented, b 3 The highest bit of the augend segment is the sequence number of a data segment, and the sequence number of the augend segment is determined by the sequence number of the augend segment and the augend segment. One chip processes one data segment, that is, it is used to calculate the addition of one data segment. The data segments are stored in the quantum bits on the chip, so that the addition between them will not introduce teleportation operations. In addition, the storage of a t and storage b t The number of bits can be equal, or in certain circumstances, they can be unequal.

[0058] The adding module 3011 may be a quantum Fourier transform (QFT) adder for implementing a t +b t A quantum circuit of QFTA (QFT adder) can be Figure 4 As shown, anc is the quantum bit that stores carry information, b0-b m is the quantum bit that stores the segment of the summand, a0-a m It is the quantum bit that stores the addend segment. Specifically, the addend segment in the form of binary string is transformed into the phase of quantum state through the QFT module, and then through multiple controlled R gates (R1...R m) to realize the addition operation of the addend segment and the augend segment in phase. + (Inverse Quantum Fourier Transform) is used to transform the result of the data segment operation back into the form of a binary string. The addition module 3011 can be composed of a QFT module and an R gate module. In fact, the QFT module in the QFT adder can be removed by swapping the target bit of the controlled R gate, and the quantum circuit can be Figure 5 As shown, QFTs are used to represent the QFT module without swap. Figure 5 The adder shown is still a QFTA.

[0059] The EPR module 302 transmits the carry information from one chip to another chip, specifically, transmits the carry information from one chip to the chip processing the adjacent high-order data segment. After receiving the carry information, the loading module 3012 of the chip processing the high-order data segment loads the carry information on the addition result and the carry information obtained by the addition module 3011 to realize the upward carry. It should be noted that the chip processing the lowest-order data segment will not receive the carry information, and the loading module 3012 in the chip is not executed in the actual process. This is reflected in the quantum circuit of the quantum adder 300, which is manifested as the quantum circuit corresponding to the chip does not have the loading module 3012.

[0060] QFT + Module 3013 is used to convert the latest addition result. For chips that process the lowest bit data segment, the addition result obtained using addition module 3011 is the latest addition result. The addition result obtained by other chips using addition module 3011 is not the latest addition result because it needs to be updated using the received carry information. The addition result updated using loading module 3012 is the latest addition result.

[0061] The quantum adder provided in the present application is a distributed quantum adder, in which one chip performs an addition operation on a data segment, and an EPR module is used between different chips to realize the transmission of carry information, so as to realize distributed processing of data segments. The data to be processed is segmented according to the processing capacity of the chip, and there is no need to split the quantum circuit. Therefore, the decomposition of quantum logic gates is greatly reduced, and the number of teleportation operations is greatly reduced, thereby reducing the time required for addition operations and improving the addition operation efficiency in quantum computing.

[0062] In the present application, the addition module 3011 can be executed in parallel. When the addition modules 3011 of all chips are executed, the chip processing the lowest bit data segment transmits the carry information to the chip processing the higher bit data segment through the EPR module 302, and the chip executes the loading module 3012 and QFT. + Module 3013, then execute EPR module 302, and so on, until the chip processing the highest bit data segment completes QFT + Module 3013.

[0063] In addition, the quantum adder provided by the present application does not require carry in the chip, which improves the utilization rate of quantum bits, thereby increasing the amount of data that can be processed by a single chip, thereby requiring fewer chips to process the same order of magnitude of data. The reduction in the number of chips also reduces teleportation operations, thereby saving computing resources and shortening the time of addition operations, thereby improving the efficiency of addition operations in quantum computing.

[0064] In some embodiments of the present application, the addition module 3011 can act on the first quantum bit, the second quantum bit and the third quantum bit in the chip, wherein the first quantum bit is the quantum bit allocated to the addend segment in the chip, the second quantum bit is the quantum bit allocated to the addend segment in the chip, and the third quantum bit is the quantum bit allocated to the chip for storing carry information.

[0065] In the embodiment of the present application, for each chip, the first qubit is used to store the addend segment, specifically the quantum state of the stored addend segment, and the second qubit is used to store the augend segment. When the addend result is obtained by using the addend module 3021, the second qubit is used to store the addend result, where the addend result is the result of adding the augend segment and the addend segment without a carry. The first qubit and the second qubit may include more than one qubit, and the specific number is determined by the length of the augend segment or the addend segment.

[0066] In some possible implementations of the present application, the EPR module 302 may act on the third qubit and the fourth qubit of one chip, and the fourth qubit and the fifth qubit of another chip, wherein the fourth qubit is a qubit allocated in the chip to generate an EPR pair, and the fifth qubit is a qubit allocated in the chip to receive the updated carry information of other chips. In some implementations, the EPR module 302 may use a CNOT gate to implement the transmission of carry information.

[0067] In order to realize quantum teleportation, at least one qubit needs to be allocated in each chip for generating EPR pairs, and the fourth qubit between the two chips can generate EPR pairs. The EPR module 302 realizes the entanglement of the third qubit on one chip with the fifth qubit on another chip, and transmits the carry information on the third qubit in one chip to the fifth qubit of another chip through teleportation. It should be noted that the fifth qubit is not allocated in the chip that processes the lowest bit data segment.

[0068] In some possible implementations of the present application, the loading module 3012 is used to load the received carry information as the lowest bit data of the addition result into the phase of the quantum state corresponding to the second quantum bit and the third quantum bit of the chip, wherein the second quantum bit stores the addition result.

[0069] Exemplarily, the carry information received by chip 3 is 1, and the addition result obtained by chip 3 using addition module 3011 is 1010. After the carry information is processed by loading module 3012, the addition result stored in the second quantum bit of chip 3 becomes 1011, and the quantum state of the third quantum bit remains unchanged. If the carry information received by chip 3 is 1, and the addition result obtained by chip 3 using addition module 3011 is 1111, after the carry information is processed by loading module 3012, the addition result stored in the second quantum bit of chip 3 becomes 0000, and the carry information of the third quantum bit changes from 0 to 1. In some embodiments, loading module 3012 can be implemented using a controlled R gate.

[0070] In some possible implementations of the present application, the quantum adder further includes an inverse EPR module for setting the fifth quantum bit in the chip to a |0> state.

[0071] The inverse EPR module and the EPR module 302 act on the same quantum bit. The inverse EPR module is the inverse operation of the EPR module 302, and realizes setting the fifth quantum bit in the chip to the |0> state.

[0072] When the quantum adder includes an inverse EPR module, a quantum circuit of a quantum adder can be as follows: Figure 6 As shown, the chip that processes the lowest bit of the data segment does not need to receive the carry information, so it does not need to load the module 3012 for further processing. Therefore, the chip can directly use QFTA to process the data segment. 1 QFTA 2- and QFTA t- Indicates that QFT is not included + QFTA of the module, R indicates loading module 3012, anc i represents the third qubit in the ith chip, anci0 represents the fifth qubit in the i-th chip. When there are fewer chips, the teleportation time can be reduced by returning only the fifth qubit to zero.

[0073] In some possible implementations of the present application, the quantum adder further includes a return-to-zero module for setting the third quantum bit and / or the fifth quantum bit in a specific chip to a |0> state without changing the addition result of the data segment of the specific chip.

[0074] The specific chip is any chip of the quantum adder except the chip that processes the highest bit data segment. Figure 7 From the quantum circuit of another quantum adder shown, it can be concluded that the return-to-zero module can include multiple functions, and the specific structure of the return-to-zero module will be different depending on the chip it acts on. Figure 7 The functions implemented by the modules in the two virtual boxes are reversible. Chip 2 to chip t-1 contain the same return-to-zero module. The return-to-zero module in chip 1 is The module resets the third qubit in chip 1 to zero. The module is a QFTA acting on the first, second and third qubits in chip 1. 1 The inverse operation of the module is then performed by QFTA acting on the first quantum bit and the second quantum bit. 1 The module realizes the segmented addition of data, so that the binary string obtained by measuring the second quantum bit is still the result of the addition. In the return-to-zero module from chip 2 to chip t-1, unit 1 is used to realize the return to zero of the third quantum bit, and unit 2 is used to realize the segmented addition of data to obtain the corresponding binary string. The inverse EPR module acting between the two chips is used to return to zero of the fifth quantum bit.

[0075] The embodiment of the present application provides a quantum adder, which includes multiple chips connected by an EPR module, one chip is used to process a data segment, and the data segment includes an addend segment and an augend segment; the chip includes an addition module, which is used to obtain the addition result and carry information of the data segment based on quantum Fourier transform; a loading module, which is used to load the carry information transmitted by the EPR module onto the addition result and carry information obtained by the chip based on the addition module to update the addition result and carry information of the chip; an inverse quantum Fourier transform module, which is used to convert the latest addition result into a binary string. In the present application, one chip processes one data segment, and the length of the data segment is determined according to the number of quantum bits in the chip. There is no need to carry in one chip, and the carry information is transmitted through the EPR module, and there is no need to split the quantum circuit again, so the decomposition of the quantum logic gate is greatly reduced, and the number of teleportation operations is greatly reduced, thereby reducing the time required for addition operations and improving the operation efficiency of addition in quantum computing.

[0076] See also Figure 8 , Figure 8 A computing method provided in an embodiment of the present application includes:

[0077] S801: Process the data to be added to obtain data segments;

[0078] S802: Using the quantum adder described in any of the above embodiments, obtaining a binary string representing the result of each data segment addition;

[0079] S803: Based on all binary strings, generate the operation result of the data to be added.

[0080] In the implementation mode of the present application, a chip is assigned to a data segment. When the quantum adder provided by any of the above embodiments of the present application is used to process the data segments, for each data segment, the addition module in the corresponding chip is used to perform operations to obtain the addition result and carry information. Chips 1-t respectively process data segments 1-t. When chip 1 executes QFT + After the module is loaded, the carry information is transmitted to chip 2 through the EPR module between chip 1 and chip 2. Chip 2 uses the loading module to process the received carry information and then executes the QFT in chip 2. + Module, get b 2 b 1 +a 2 a 1 The result is that the updated carry information of chip 2 is transmitted to chip 3, and this process is repeated until chip t executes QFT. +The module measures the updated carry information in chip t and the second quantum bits of all chips to obtain the carry information and the binary string. The binary string is sorted according to the sequence number of the data segment, and the highest bit of the sorted binary string is the measured carry information, thereby obtaining the operation result. Exemplarily, the quantum adder includes 3 chips, the carry information measured by chip 3 is 0, the binary string measured by chip 1 is 001, the binary string measured by chip 2 is 101, and the binary string measured by chip 3 is 010, then a binary string of 010101001 can be obtained, and the binary string can be directly used as the operation result of the addend and the augend, or the binary string can be converted into decimal and the decimal value can be used as the operation result. Of course, there can be other ways, which will not be described one by one here.

[0081] In some possible implementations of the present application, when all binary strings are obtained, the return-to-zero modules in the specific chip are executed in sequence according to the data segment sequence numbers from high to low.

[0082] The specific implementation method is shown in the above embodiment and will not be described in detail here.

[0083] See also Fig. 9 , Fig. 9 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. The device comprises:

[0084] A processing module 901 is used to process the data to be added to obtain data segments;

[0085] An obtaining module 902 is used to obtain a binary string representing the result of each data segment addition by using the quantum adder described in any of the above embodiments;

[0086] The generating module 903 is used to generate the operation result of the data to be added based on all binary strings.

[0087] See also Fig.10 The present application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to implement the quantum adder described in any one of the above embodiments and / or the operation method described in any one of the above embodiments. Fig.10 , the computer device may be a classical computer. The computer device may also be a quantum computer.

[0088] An embodiment of the present application further provides a storage medium, wherein the storage medium stores a computer program, wherein the computer program is configured to implement the quantum adder described in any one of the above embodiments and / or the operation method described in any one of the above embodiments when running.

[0089] The embodiments of the present application also provide a computer program product comprising instructions, which, when executed by a computer, enables the computer to implement the quantum adder described in any one of the above embodiments and / or the operation method described in any one of the above embodiments.

[0090] It can be understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited to this.

[0091] Unless otherwise stated, all technical and scientific terms used in the embodiments of the present application have the same meaning as those generally understood by those skilled in the art of the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more related listed items. The singular forms of "a kind of", "above" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0092] It can be understood that the processor of the embodiment of the present application can be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method implementation can be completed by the hardware integrated logic circuit or software instructions in the processor. The above processor can be a general processor, a digital signal processor (DigitalSignal Processor, DSP), an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiment of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present application can be directly embodied as a hardware decoding processor to perform, or the hardware and software modules in the decoding processor are combined and executed. The software module can be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0093] It is understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (programmable ROM, PROM), an erasable programmable read-only memory (erasable PROM, EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory may be a random access memory (RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0094] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0095] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method implementation methods and will not be repeated here.

[0096] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device implementation described above is only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0097] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

Claims

1. A quantum adder, characterized in that: The quantum adder includes a plurality of chips connected by EPR modules, one chip is used to process one data segment, the data segment includes an addend segment and an augend segment, and the chip includes: An addition module, used to obtain the addition result and carry information of the data segments based on quantum Fourier transform; A loading module, used for loading the carry information transmitted by the EPR module onto the addition result and carry information obtained by the chip based on the addition module, so as to update the addition result and carry information of the chip; The inverse quantum Fourier transform module is used to convert the latest addition result into a binary string.

2. The quantum adder according to claim 1, characterized in that: The addition module acts on the first quantum bit, the second quantum bit and the third quantum bit in the chip, wherein the first quantum bit is a quantum bit allocated to the addend segment in the chip, the second quantum bit is a quantum bit allocated to the addend segment in the chip, and the third quantum bit is a quantum bit allocated in the chip to store carry information.

3. The quantum adder according to claim 2, characterized in that: The EPR module acts on the third quantum bit and the fourth quantum bit of one chip, and the fourth quantum bit and the fifth quantum bit of another chip, wherein the fourth quantum bit is a quantum bit allocated in the chip to generate an EPR pair, and the fifth quantum bit is a quantum bit allocated in the chip to receive carry information updated by other chips.

4. The quantum adder according to claim 3, characterized in that: The loading module is used to load the received carry information as the lowest bit data of the addition result to the phase of the quantum state corresponding to the second quantum bit and the third quantum bit of the chip, wherein the second quantum bit stores the addition result.

5. The quantum adder according to claim 4, characterized in that: The quantum adder also includes an inverse EPR module for setting the fifth quantum bit in the chip to a |0> state.

6. The quantum adder according to claim 4, characterized in that: The quantum adder also includes a return-to-zero module, which is used to set the third quantum bit and / or the fifth quantum bit in the specific chip to the |0> state without changing the addition result of the data segment of the specific chip.

7. A calculation method, characterized in that: The method comprises: Processing the added data to obtain data segments; Using the quantum adder described in any one of claims 1 to 6, a binary string representing the result of each data segment addition is obtained; Based on all binary strings, the operation result of the data to be added is generated.

8. The method according to claim 7, characterized in that The method further comprises: When all binary strings are obtained, the return-to-zero modules in the specific chip are executed in sequence according to the sequence numbers of the data segments from high to low.

9. A computing device, characterized in that: The device comprises: A processing module, used for processing the data to be added to obtain data segments; An acquisition module, used to obtain a binary string representing the result of each data segment addition using the quantum adder according to any one of claims 1 to 6; A generating module is used to generate the operation result of the data to be added based on all binary strings.

10. A storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program is configured to implement the quantum adder according to any one of claims 1 to 6 and / or the method according to claim 7 or 8 when run.

11. A computer device comprising a memory and a processor, characterized in that: A computer program is stored in the memory, and the processor is configured to run the computer program to implement the quantum adder according to any one of claims 1 to 6 and / or the method according to claim 7 or 8.

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