Gamma line interconnection circuit and display driving circuit including same

Abstract

The invention discloses a gamma line interconnection circuit and a display driving circuit including the gamma line interconnection circuit. The gamma line interconnect circuit may include a resistor string including a first resistor connected between a first node and a second node and a second resistor connected between the second node and a third node, a first switch connected between the first gamma line and the first node, a second switch connected between the second gamma line and the third node, and a third switch connected between the second node and the third node. The first switch is connected between the first gamma line and the first node and is configured to operate based on an interconnect signal, the second switch is connected between the second gamma line and the second node and is configured to operate based on the interconnect signal, and the third switch is connected between the third gamma line and the third node and is configured to operate based on the interconnect signal.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0082146 filed in the Korean Intellectual Property Office on June 26, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a display device, and more particularly to a gamma line interconnection circuit and a display driving circuit including the gamma line interconnection circuit. Background Art

[0003] The display device may include a display panel and a display driving circuit, wherein the display panel includes a plurality of pixels. The display driving circuit may control the display panel through a plurality of source driving circuits. For example, each source driving circuit may control the grayscale of a pixel of the display panel based on a gamma voltage received through a gamma line.

[0004] When the source driving circuit changes the gray level of the pixel, a voltage level swing (e.g., a glitch) may occur in the voltage level of the gamma line. Specifically, according to the recent trend of high resolution and higher integration of display devices, the time required to restore the gamma line voltage level swing that occurs when the gray level of the pixel is changed is gradually increasing due to the parasitic resistance of the gamma line. Therefore, it is increasingly difficult for the display driving circuit to drive the display panel at a high rate.

[0005] In addition, when the voltage level of the gamma line swings, errors may also occur in the output of the source driver circuit operating based on the gamma line with the voltage level swing. In this case, errors may also occur in the image displayed by the display panel operating based on the output of the source driver circuit. Summary of the invention

[0006] The present disclosure is to solve the above technical objectives. More specifically, the present disclosure will provide a gamma line interconnection circuit that minimizes the influence of gamma line parasitic resistance on grayscale adjustment, and a display driving circuit including the gamma line interconnection circuit.

[0007] According to an embodiment of the present disclosure, a gamma line interconnection circuit may be provided. The gamma line interconnection circuit may include: a resistor string including a first resistor connected between a first node and a second node and a second resistor connected between the second node and a third node; a first switch connected between the first gamma line and the first node and configured to operate based on an interconnection signal; a second switch connected between the second gamma line and the second node and configured to operate based on an interconnection signal; and a third switch connected between the third gamma line and the third node and configured to operate based on the interconnection signal.

[0008] According to an embodiment of the present disclosure, a display driving circuit may be provided. The display driving circuit may include: a source driving circuit that controls a display panel; a gamma voltage generator that provides first to Nth gamma voltages to first to Nth gamma lines connected to the source driving circuit, respectively, where N is an integer greater than 2; and a gamma line interconnection circuit that interconnects the first to Nth gamma lines in a first time period from a first time point when a grayscale value of the source driving circuit is changed.

[0009] According to an embodiment of the present disclosure, a display device may be provided. The display device may include a display panel and a display driving circuit, the display panel including a first plurality of pixels and a second plurality of pixels, and the display driving circuit controls the first plurality of pixels and the second plurality of pixels. Wherein, the display driving circuit includes: a gamma voltage generator, providing different gamma voltages to a plurality of gamma lines; a first source driving circuit array, connected to the plurality of gamma lines, and including a first plurality of source driving circuits configured to control the first plurality of pixels; a second source driving circuit array, connected to the plurality of gamma lines, and including a second plurality of source driving circuits configured to control the second plurality of pixels; and a gamma line interconnection circuit, located between the first source driving circuit array and the second source driving circuit array, and interconnecting the plurality of gamma lines during a predetermined time period after one or more grayscale values ​​of the first plurality of source driving circuits and the second plurality of source driving circuits are changed. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0011] Figure 2 is shown in more detail Figure 1 Block diagram of some configurations of display driver circuits.

[0012] Figure 3A and Figure 3B Shown in more detail Figure 2 Configuration and operation of one of the source driver circuits.

[0013] Figure 4 It is shown Figure 3A and Figure 3B A graph of the voltage level of the victim gamma line.

[0014] Figure 5 Shows Shows Figure 1 A block diagram of the operation of the gamma line interconnect circuit.

[0015] Figure 6 According to the embodiment of the present disclosure Figure 5 Circuit diagram of the gamma ray interconnect circuit.

[0016] Fig. 7A and Figure 7B Equivalent resistance between a source driver and a gamma voltage generator according to an operation mode of a gamma line interconnection circuit is shown.

[0017] Figure 8 The operation of the gamma line interconnection circuit and the voltage level of the victim gamma line according to an embodiment of the present disclosure are shown.

[0018] Fig. 9 A source driving circuit connected to a gamma line according to an embodiment of the present disclosure is shown.

[0019] Fig.10 Show according to Fig. 9 The voltage level of the second output signal of the operation of the gamma line interconnection circuit.

[0020] Fig.11 Show Figure 1 A method of operating a gamma ray interconnect circuit.

[0021] FIG. 12A to FIG. 12C The configurations of the gamma line interconnection circuits implemented according to the embodiments are respectively shown.

[0022] Fig.13 The configuration of a gamma line interconnection circuit implemented according to an embodiment is shown.

[0023] Fig.14 It is shown Fig.13 The current provides the circuit diagram of the circuit.

[0024] Fig.15 By way of example Figure 1 Partial configuration of a gamma voltage generator.

[0025] Fig.16 Another embodiment of the present disclosure is shown in FIG. Figure 5 A circuit diagram of a configuration of a gamma line interconnect circuit.

[0026] Fig.17 FIG. 1 shows a layout of a display driving circuit according to an embodiment.

[0027] Fig.18 FIG. 1 shows a layout of a display driving circuit according to an embodiment.

[0028] Fig.19 The configuration layout of a display driving circuit according to an embodiment of the present disclosure is shown.

[0029] Fig. 20 Show reference Figures 17 to 19 The voltage level swing of the victim gamma line of the described layout.

[0030] Fig.21Show reference Figures 17 to 19 A layout is described in which the gray level of the output signal of the source driver circuit is changed.

[0031] Fig. 22 The configuration layout of a display driving circuit according to an embodiment of the present disclosure is shown.

[0032] Fig.23 The configuration layout of a display driving circuit according to an embodiment of the present disclosure is shown.

[0033] Fig.24 A configuration of a gamma line interconnection circuit according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present disclosure will be described clearly and in detail to the extent that a person of ordinary skill in the technical field to which the present disclosure belongs can easily practice the present disclosure. Details (such as detailed configuration and structure) are provided only to facilitate an overall understanding of the embodiments of the present disclosure. Therefore, without departing from the technical spirit and scope of the present disclosure, those skilled in the art may perform variations of the embodiments described herein. In addition, for clarity and conciseness, descriptions of well-known functions and structures are omitted. Components in the following drawings or specific embodiments may be connected to other elements except the constituent elements shown in the drawings or described in the specific embodiments. The terms used in the present disclosure are terms defined in consideration of the functions of the present disclosure, and are not limited to specific functions. The definition of the terms may be determined based on the details described in the specific embodiments.

[0035] The constituent elements described with reference to the terms used in the specific embodiments (such as, drivers or blocks) can be implemented in the form of software, hardware, or a combination thereof. Exemplarily, the software can be machine code, firmware, embedded code, and application software. For example, the hardware can include circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, inertial sensors, micro-electromechanical systems (MEMS), passive components, or a combination thereof.

[0036] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure. Figure 1 The display device DPD may include a display driving circuit 100 and a display panel DP. The display device DPD may be included in an electronic device configured to display image information, such as a display, TV, laptop computer, tablet PC, smart phone, navigation, etc.

[0037] The display panel DP may include a plurality of pixels connected to a plurality of gate lines GL and a plurality of source lines SL. Each of the plurality of pixels may display one of the primary colors in response to an electrical signal provided from the display driving circuit 100. The primary colors may include red, green, and blue. However, the scope of the present disclosure is not limited thereto.

[0038] In one embodiment, the display panel DP may be one of various types of panels such as a liquid crystal display panel, an organic light emitting display panel, an electrophoretic display panel, an electrowetting display panel, etc. However, the scope of the present disclosure is not limited thereto.

[0039] The display driving circuit 100 may include a control logic circuit 110 , a gate driver 120 , a source driver 130 , a gamma voltage generator 140 , and a gamma line interconnect circuit (GIC).

[0040] The control logic circuit 110 may receive video data (VDT) from an external source. For example, the control logic circuit 110 may receive the video data VDT from various types of electronic devices such as an application processor (AP), a graphics processor (GPU), etc. In this case, the video data VDT may include data for controlling each of a plurality of pixels of the display panel DP.

[0041] The gate driver 120 may be connected to the display panel DP through a plurality of gate lines GL. The gate driver 120 may control the plurality of gate lines GL in response to control of the control logic circuit 110.

[0042] The source driver 130 may be connected to the display panel DP through a plurality of source lines SL. The source driver 130 may be connected to the gamma voltage generator 140 through a plurality of gamma lines (GML).

[0043] The gamma voltage generator 140 may generate a plurality of gamma voltages in response to the control of the control logic circuit 110. The gamma voltage generator 140 may provide a plurality of gamma voltages to a plurality of gamma lines GML, respectively. In this case, the plurality of gamma voltages may correspond to different gray levels (e.g., different shades of gray). For example, when there are 256 different gray levels (ranging from pure black (level 0) to pure white (level 255)), the plurality of gamma voltages may correspond to the 256 different gray levels, respectively. The term "gray level" may also be referred to as "brightness level" because the gray level indicates how bright or dark a pixel should be.

[0044] In one embodiment, the gamma voltages may be referred to as gray voltages. However, the scope of the present disclosure is not limited thereto.

[0045] The source driver 130 may control the plurality of source lines SL in response to the control of the control logic circuit 110. For example, the source driver 130 may include a plurality of source driving circuits that respectively control the plurality of source lines SL.

[0046] A plurality of source driver circuits may be connected to a plurality of gamma lines GML, respectively. Each of the plurality of source driver circuits may determine the grayscale of an output signal to be provided to a pixel based on a grayscale value provided from the control logic circuit 110. For example, each of the plurality of source driver circuits may generate an output signal to be provided to a source line SL connected thereto based on a gamma voltage corresponding to the grayscale value provided from the control logic circuit 110 (i.e., a voltage provided from one of the plurality of gamma lines GML). That is, each of the plurality of source driver circuits may select one of the plurality of gamma voltages provided through the plurality of gamma lines GML in response to the grayscale value provided from the control logic circuit 110, and may operate based on the selected gamma voltage. Reference will be made to FIG. 3A to FIG. 3B A more detailed operation of the source driver circuit is described in more detail.

[0047] In one embodiment, multiple source driver circuits may share multiple gamma lines. For example, a first source driver circuit may be connected to the same gamma line as a second source driver circuit.

[0048] In one embodiment, when the grayscale value provided to the first source driver circuit changes and causes the gamma voltage "for generating an output signal by the first source driver circuit" to change from the voltage of the first gamma line to the voltage of the second gamma line, voltage fluctuations (e.g., swings or glitches) may occur in the voltage of the second gamma line. In this case, voltage fluctuations may also occur in the output signal generated by the second source driver circuit, which operates based on the voltage of the second gamma line. At the same time, since it takes a certain amount of time to stabilize the output signal of the second source driver circuit, the operating speed of the display device DPD may be degraded. Hereinafter, a specific embodiment that minimizes the impact of gamma line voltage fluctuations will be described.

[0049] The gamma line interconnection circuit GIC may interconnect the plurality of gamma lines GML. For example, the gamma line interconnection circuit GIC may establish connections between the plurality of gamma lines GML through resistors. In this case, a resistance-capacitance (RC) time constant between the source driver 130 and the gamma voltage generator 140 may be reduced. Therefore, according to an embodiment of the present disclosure, voltage level fluctuations of the gamma lines may be minimized.

[0050] In one embodiment, the gamma line interconnection circuit GIC may be formed to interconnect the plurality of gamma lines GML only within a predetermined period of time after the grayscale value provided to a portion of the plurality of source driving circuits changes. That is, the gamma line interconnection circuit GIC may be formed to release or loosen the interconnection of the plurality of gamma lines GML after a predetermined time has passed. In this case, the voltage level distortion of the plurality of gamma lines GML caused by the interconnection between the plurality of gamma lines GML may be minimized. Figures 5 to 8 The detailed configuration and operation of the gamma line interconnect circuit GIC are described in more detail.

[0051] Figure 2 is shown in more detail Figure 1 The block diagram of some configurations of the display driver circuit. Figure 1 and Figure 2 The gamma voltage generator 140 may be connected to the plurality of gamma lines GML. For example, the gamma voltage generator 140 may be connected to the first gamma line GML1 to the nth gamma line GMLn.

[0052] The gamma voltage generator 140 may provide different voltages to the first to nth gamma lines GML1 to GMLn. Hereinafter, for a more concise description, the voltages provided to the first to nth gamma lines GML1 to GMLn will be referred to as first to nth gamma voltages, respectively. However, the scope of the present disclosure is not limited thereto.

[0053] The source driver 130 may include first to m-th source driving circuits SDC1 to SDCm. The first to m-th source driving circuits SDC1 to SDCm may be connected to first to m-th source lines SL1 to SLm, respectively.

[0054] Each of the first to m-th source driving circuits SDC1 to SDCm may include a source amplifier SA and a decoder DEC.

[0055] Hereinafter, for a more concise description, the operations of the source amplifier SA and the decoder DEC of the first source driver circuit SDC1 will be representatively described. However, the scope of the present disclosure is not limited thereto, and the second source driver circuit SDC2 to the mth source driver circuit SDCm may also operate in a similar manner.

[0056] The decoder DEC of the first source driving circuit SDC1 may be connected to the first to n-th gamma lines GML1 to GMLn. The decoder DEC of the first source driving circuit SDC1 may select one of the first to n-th gamma lines GML1 to GMLn in response to the control of the control logic circuit 110. For example, the decoder DEC of the first source driving circuit SDC1 may select one of the first to n-th gamma lines GML1 to GMLn according to the grayscale value received from the control logic circuit 110.

[0057] The decoder DEC of the first source driver circuit SDC1 may generate an input signal to be provided to the source amplifier SA based on the gamma voltage provided from the selected gamma line. In this case, the source amplifier SA may provide an output signal to the first source line SL1 based on the received input signal. Hereinafter, for a more concise description, the grayscale value provided to the source driver circuit by the control logic circuit 110 will be referred to as the grayscale of the source driver circuit. However, the scope of the present disclosure is not limited to these terms.

[0058] Meanwhile, when the gray level of the first source driving circuit SDC1 is changed, the decoder DEC of the first source driving circuit SDC1 may select a gamma line corresponding to the changed gray level from among the first to nth gamma lines GML1 to GMLn. In this case, the source amplifier SA of the first source driving circuit SDC1 may provide an output signal generated based on a gamma voltage provided from the selected gamma line (i.e., the gamma line corresponding to the changed gray level) to the first source line SL1.

[0059] In one embodiment, when the gray level of the first source driving circuit SDC1 is changed, the voltage level of the gamma line corresponding to the changed gray level may swing. Figure 3A and Figure 3B as well as Figure 4 The voltage level swing of the gamma lines occurring due to the change of the gray level of the source driving circuit is described in more detail.

[0060] In one embodiment, "n" may correspond to the number of gray levels supported by the display device DPD, and "m" may correspond to a column of pixels arranged in the display panel DP. However, the scope of the present disclosure is not limited thereto.

[0061] Figure 3A and Figure 3B Shown in more detail Figure 2 The configuration and operation of one of the source driver circuits of FIG. Figure 3A , the configuration and operation of the source driver circuit before the gray scale is changed will be described, and reference will be made to Figure 3B, the configuration and operation of the source driver circuit after the grayscale level is changed will be described. In addition, in the following, it is assumed that the source driver circuit SDC is Figure 2 However, the scope of the present disclosure is not limited thereto.

[0062] First, refer to Figures 1 to 3A , the source driving circuit SDC may include a source amplifier SA and a decoder DEC. The source amplifier SA may include an operational amplifier. Specifically, the output terminal of the operational amplifier may be connected to the source line SL, the inverting input terminal may be connected to the output terminal of the operational amplifier, and the non-inverting input terminal may be connected to the decoder DEC.

[0063] Before the gray level is changed, the gray level of the source driving circuit SDC may correspond to the voltage level of the aggressor gamma line GML_aggressor. That is, the source driving circuit SDC may operate based on the voltage of the aggressor gamma line GML_aggressor. For example, the decoder DEC may generate an input signal to be provided to the source amplifier SA based on the gamma voltage "V1" provided from the aggressor gamma line GML_aggressor. In this case, the source amplifier SA may generate an output signal to be provided to the source line SL based on the input signal provided from the decoder DEC.

[0064] The parasitic capacitance PC may exist between the inverting input terminal and the non-inverting input terminal of the operational amplifier. Therefore, when the decoder DEC provides the input signal to the source amplifier SA, a voltage corresponding to the gamma voltage V1 provided from the aggressor gamma line GML_aggressor may be charged into the parasitic capacitance PC.

[0065] Continue to refer to Figure 3B , the gray level of the source driving circuit SDC may be changed to correspond to the voltage level of the victim gamma line GML_victim. That is, after the gray level is changed, the source driving circuit SDC may operate based on the voltage of the victim gamma line GML_victim instead of the aggressor gamma line GML_aggressor. In this case, the decoder DEC may generate an input signal to be provided to the source amplifier SA based on the gamma voltage "V2" provided from the victim gamma line GML_victim. The source amplifier SA may generate an output to be provided to the source line SL based on the input signal provided from the decoder DEC.

[0066] However, when the grayscale of the source driving circuit SDC is changed from the gamma voltage V1 corresponding to the aggressor gamma line GML_aggressor to the gamma voltage V2 corresponding to the victim gamma line GML_victim, because the parasitic capacitance PC is used as a path for charges to flow between the two input terminals of the amplifier, a "charge sharing" phenomenon may occur due to the charges stored in the parasitic capacitance PC. For example, when the decoder DEC changes the grayscale voltage used to generate the input signal to be provided to the source amplifier SA from the voltage of the aggressor gamma line GML_aggressor to the voltage of the victim gamma line GML_victim, the voltage level of the victim gamma line GML_victim may swing or fluctuate due to the charges stored in the parasitic capacitance PC. The voltage change may cause a temporary redistribution of the charges in the parasitic capacitance PC. The redistribution of charges may produce an unexpected voltage drop or voltage rise across the parasitic capacitance PC, resulting in a voltage fluctuation in the voltage level of the victim gamma line GML_victim. The voltage fluctuation may introduce noise or distortion in the output signal of the amplifier. Referring to Figure 4 The voltage level swing of the victim gamma line GML_victim is described in more detail.

[0067] In one embodiment, each of the aggressor gamma line GML_aggressor and the victim gamma line GML_victim may be one of the first to nth gamma lines GML1 to GMLn.

[0068] Figure 4 It is shown Figure 3A and Figure 3B A graph of the voltage level of the victim gamma line. Figure 4 , the horizontal axis of the graph represents time, and the vertical axis of the graph represents the voltage level of the victim gamma line GML_victim. Figures 1 to 4 , the gray level of the source driving circuit SDC may be changed at the switching time point tSW. For example, at the switching time point tSW, the gray level of the source driving circuit SDC may be changed to correspond to the voltage level of the victim gamma line GML_victim.

[0069] In one embodiment, the switching time point tSW may be included in a horizontal blanking period during which the gate driver 120 changes the active row of the display panel DP. However, the scope of the present disclosure is not limited thereto.

[0070] In an ideal case (e.g., when there is no parasitic capacitance PC), the voltage level of the victim gamma line GML_victim before and after the switching time point tSW may be maintained at a constant "V2" (as shown by the dotted line). In this case, the source driving circuits among the first source driving circuit SDC1 to the mth source driving circuit SDCm that operate at a grayscale corresponding to the victim gamma line GML_victim may provide uniform or consistent output signals to the source lines.

[0071] On the other hand, as previously referred to Figure 3A and Figure 3B As described, when charge sharing occurs (i.e., when the parasitic capacitance PC exists), after the switching time point tSW, a swing (shown by a solid line) may occur in the voltage level of the victim gamma line GML_victim. For example, after the switching time point tSW, the voltage level of the victim gamma line GML_victim may be reduced to "V3", "V3" being lower than "V2", and then the voltage level of the victim gamma line GML_victim may be increased again. In this case, from the switching time point tSW until the first time point t1 (at the first time point t1, the voltage level of the victim gamma line GML_victim is restored to "V2"), the source driver circuit operating at a gray level corresponding to the victim gamma line GML_victim may fail to provide a uniform or consistent output signal to the source line.

[0072] Figure 5 Shows Shows Figure 1 A block diagram of the operation of the gamma line interconnect circuit. Figures 1 to 5 The gamma line interconnection circuit GIC may include a resistor string RSTR. The resistor string RSTR may include a plurality of resistors.

[0073] In one embodiment, a plurality of resistors included in the resistor string RSTR may be connected in series. However, the scope of the present disclosure is not limited thereto.

[0074] The gamma line interconnection circuit GIC may interconnect the first gamma line GML1 to the nth gamma line GMLn in response to the interconnection signal ICN. For example, when the interconnection signal ICN is in a logic high state, the gamma line interconnection circuit GIC may operate in a coarse recovery mode. In this case, the gamma line interconnection circuit GIC may interconnect the first gamma line GML1 to the nth gamma line GMLn. More specifically, the gamma line interconnection circuit GIC may connect the first gamma line GML1 to the nth gamma line GMLn to different nodes of the resistor string RSTR, respectively.

[0075] On the other hand, when the interconnection signal ICN is in a logic low state, the gamma line interconnection circuit GIC may operate in a fine recovery mode. In this case, the gamma line interconnection circuit GIC may disconnect the first gamma line GML1 from the nth gamma line GMLn. For example, the gamma line interconnection circuit GIC may release the interconnection between the first gamma line GML1 to the nth gamma line GMLn and the resistor string RSTR.

[0076] Will refer to Figures 6 to 8 , Fig.16 and Fig.24 The detailed configuration and operation of the gamma line interconnect circuit GIC are described in more detail.

[0077] In one embodiment, the interconnect signal ICN may be provided from the control logic circuit 110 .

[0078] Figure 6 According to the embodiment of the present disclosure Figure 5 A circuit diagram of a gamma line interconnection circuit is shown below. Figure 6 , a gamma line interconnection circuit GIC formed to interconnect the first to n-th gamma lines GML1 to GMLn in response to an interconnection signal ICN will be described.

[0079] Reference Figures 1 to 6 , the gamma line interconnection circuit GIC may include first to n-th switches SW1 to SWn. One terminal of each of the first to n-th switches SW1 to SWn may be connected to the first to n-th gamma lines GML1 to GMLn, respectively. The other terminal of each of the first to n-th switches SW1 to SWn may be connected to the first to n-th nodes N1 to Nn, respectively. For example, the first switch SW1 may be connected between the first gamma line GML1 and the first node N1, and the n-th switch SWn may be connected between the n-th gamma line GMLn and the n-th node Nn.

[0080] The gamma line interconnection circuit GIC may include a resistor string RSTR. The resistor string RSTR may include a first resistor R1 to an (n-1)th resistor Rn-1 connected in series between a first node N1 and an nth node Nn. In this case, the first resistor R1 to the (n-1)th resistor Rn-1 may be connected to each other through a second node N2 to the (n-1)th node Nn-1. For example, the first resistor R1 may be connected between the first node N1 and the second node N2, and the second resistor R2 may be connected between the second node N2 and the third node N3. In a similar manner, the (n-1)th resistor Rn-1 may be connected between the (n-1)th node Nn-1 and the nth node Nn.

[0081] The first to n-th switches SW1 to SWn may operate in response to the interconnection signal ICN. For example, the first to n-th switches SW1 to SWn may be turned on when the interconnection signal ICN is in a logic high state, and may be turned off when the interconnection signal ICN is in a logic low state. That is, the first to n-th switches SW1 to SWn may be turned on during the operation of the gamma line interconnection circuit GIC in the coarse recovery mode, and may be turned off during the operation of the gamma line interconnection circuit GIC in the fine recovery mode.

[0082] In one embodiment, when the gamma line interconnect circuit GIC operates in the coarse recovery mode, a resistance-capacitance (RC) time constant between the source driver 130 and the gamma voltage generator 140 may be reduced by connecting the first resistor R1 to the (n-1)th resistor Rn-1 between the first gamma line GML1 to the nth gamma line GMLn.

[0083] In one embodiment, when the gamma line interconnection circuit GIC operates in the fine recovery mode, since the first gamma line GML1 to the nth gamma line GMLn are disconnected, the voltage level of the first gamma line GML1 to the nth gamma line GMLn can be accurately restored to the voltage level of the gamma voltage generated by the gamma voltage generator 140.

[0084] In the following, reference will be made to Fig. 7A and Figure 7B The RC time constant between the source driver 130 and the gamma voltage generator 140 according to the logic level of the interconnection signal ICN is described in more detail.

[0085] exist Figure 6 , for a more concise explanation, the configuration of the gamma line interconnection circuit GIC that interconnects the first gamma line GML1 to the nth gamma line GMLn in response to the interconnection signal ICN has been representatively described. However, the scope of the present disclosure is not limited thereto, and the gamma line interconnection circuit GIC may be implemented to interconnect some of the first gamma line GML1 to the nth gamma line GMLn. An embodiment of the gamma line interconnection circuit GIC implemented to interconnect some of the first gamma line GML1 to the nth gamma line GMLn will be referred to. Fig.16 However, in the following, Figure 6 The function and operation of the gamma line interconnect circuit GIC will be representatively described.

[0086] Fig. 7A and Figure 7B FIG. 1 shows an equivalent resistor between a source driver and a gamma voltage generator according to an operation mode of a gamma line interconnection circuit. Fig. 7A, the equivalent resistance between the source driving circuit SDC and the gamma voltage generator 140 when the gamma line interconnection circuit GIC operates in the fine recovery mode will be described, and with reference to Figure 7B , an equivalent resistance between the source driving circuit SDC and the gamma voltage generator 140 when the gamma line interconnection circuit GIC operates in the coarse recovery mode will be described.

[0087] First, refer to Figures 1 to 6 and Fig. 7A , when the gamma line interconnection circuit GIC operates in the fine recovery mode, the gamma line interconnection circuit GIC may not establish the connection between the first gamma line GML1 to the nth gamma line GMLn. In this case, the equivalent resistance between the source driving circuit SDC and the gamma voltage generator 140 may be determined by the parasitic resistance PR (shown by the dotted line) connected in series.

[0088] At the same time, refer to Figures 1 to 6 and Figure 7B , when the gamma line interconnection circuit GIC operates in the coarse recovery mode, the gamma line interconnection circuit GIC may interconnect the first gamma line GML1 to the nth gamma line GMLn. That is, the gamma line interconnection circuit GIC may be connected between the first gamma line GML1 to the nth gamma line GMLn through the first resistor R1 to the (n-1)th resistor Rn-1. In this case, the equivalent resistance between the source driving circuit SDC and the gamma voltage generator 140 may be determined by the parasitic resistance PR and the first resistor R1 to the (n-1)th resistor Rn-1 (shown by a dotted line).

[0089] That is, according to an embodiment of the present disclosure, when the gamma line interconnection circuit GIC operates in the coarse recovery mode, the equivalent resistance encountered when the current travels from the source driver circuit SDC to the gamma voltage generator 140 can be reduced compared to the case where the gamma line interconnection circuit GIC operates in the fine recovery mode. Therefore, when the gamma line interconnection circuit GIC operates in the coarse recovery mode, the RC time constant between the source driver circuit SDC and the gamma voltage generator 140 can be reduced compared to the case where the gamma line interconnection circuit GIC operates in the fine recovery mode. In this case, the voltage level swing of the victim gamma line GML_victim (occurring when the gray level of the source driver circuit SDC is changed) caused by the parasitic capacitance PC of the source driver circuit SDC can be minimized.

[0090] However, when the gamma line interconnection circuit GIC operates in the coarse recovery mode, errors may occur in the voltage levels of the first gamma line GML1 to the nth gamma line GMLn due to the first resistor R1 to the (n-1)th resistor Rn-1 connected between the first gamma line GML1 to the nth gamma line GMLn. That is, even after a sufficient time has passed after the grayscale of the source driving circuit SDC is changed, the voltage levels of the first gamma line GML1 to the nth gamma line GMLn may not achieve uniformity or consistency. For example, even after a sufficient time has passed after the grayscale of the source driving circuit SDC is changed, the voltage level of the first gamma line GML1 in the area close to the gamma voltage generator 140 will be different from the voltage level of the area far from the gamma voltage generator 140. In this case, since different gamma voltages are provided to different source driving circuits operating at the same grayscale, errors may occur in the image output by the display panel DP.

[0091] On the other hand, when the gamma line interconnection circuit GIC operates in the fine recovery mode, the first resistor R1 to the (n-1)th resistor Rn-1 between the first gamma line GML1 to the nth gamma line GMLn may not be connected. In this case, after the grayscale of the source driving circuit SDC is changed and sufficient time has passed, the voltage levels of the first gamma line GML1 to the nth gamma line GMLn will be able to converge to the expected voltage level. For example, after sufficient time has passed after the grayscale of the source driving circuit SDC is changed, due to the high input impedance of the source amplifier SA, the voltage level of the first gamma line GML1 becomes uniform regardless of the distance from the gamma voltage generator 140. Therefore, when the gamma line interconnection circuit GIC operates in the fine recovery mode, uniform and consistent gamma voltages can be provided to different source driving circuits.

[0092] In one embodiment, Fig. 7A and Figure 7B The sizes of the parasitic resistances PR shown in may be the same as or different from each other.

[0093] That is, the scope of the present disclosure may not be limited to the size of the parasitic resistance PR.

[0094] To explain more concisely, Fig. 7A and Figure 7B Only the parasitic resistance PR and the first resistor R1 to the (n-1)th resistor Rn-1 are shown, but the scope of the present disclosure is not limited thereto. For example, the magnitude of the equivalent resistance observed from the source driving circuit SDC in the direction of the gamma voltage generator 140 (i.e., the equivalent resistance encountered when the current travels from the source driving circuit SDC to the gamma voltage generator 140) may be determined based on the resistance of the voltage divider circuit within the gamma voltage generator 140. FIG. 12A to FIG. 12C Describe the configuration of a voltage divider circuit.

[0095] Figure 8 2 shows the operation of the gamma line interconnection circuit and the voltage level of the victim gamma line according to an embodiment of the present disclosure. Figures 1 to 8 , the interconnection signal ICN may be in a logic low state before the switching time point tSW. In this case, the gamma line interconnection circuit GIC may not interconnect the first to nth gamma lines GML1 to GMLn, and the voltage level of the victim gamma line GML_victim may be constant at “V2” until the switching time point tSW.

[0096] The gray level of the source driving circuit SDC may be changed at the switching time point tSW. For example, the gray level of the source driving circuit SDC may be changed to correspond to the victim gamma line GML_victim.

[0097] The interconnection signal ICN may transition to a logic high state at the switching time point tSW In this case, the gamma line interconnection circuit GIC may enter the coarse recovery mode COARSE in response to the interconnection signal ICN transitioning to a logic high state.

[0098] When the gamma line interconnection circuit GIC operates in the coarse recovery mode COARSE, the RC time constant between the source driving circuit SDC and the gamma voltage generator 140 can be reduced. In this case, the voltage level swing of the victim gamma line GML_victim caused by the change of the gray level of the source driving circuit SDC can be minimized. For example, after the switching time point tSW, the voltage level swing of the victim gamma line GML_victim is reduced compared to the previous reference voltage level swing. Figure 4 Different from the description, the voltage level of the victim gamma line GML_victim may be reduced to V4.

[0099] In one embodiment, the voltage difference between V2 and V4 may be less than the voltage difference between V2 and V3. For example, V4 may have a higher voltage than V3. However, the scope of the present disclosure is not limited in this regard.

[0100] The interconnection signal ICN may transition to a logic low state at a second time point t2 after the switching time point tSW. In this case, the gamma line interconnection circuit GIC may enter the fine recovery mode FINE in response to the interconnection signal ICN transitioning to a logic low state.

[0101] In one embodiment, the time interval between the switching time point tSW and the second time point t2 may be predetermined. However, the scope of the present disclosure is not limited thereto, and the second time point t2 may be determined based on the recovery voltage of the victim gamma line GML_victim. For example, the second time point t2 may be determined as the time when the voltage level of the victim gamma line GML_victim reaches a voltage level (e.g., a reference voltage level) corresponding to a predetermined ratio (e.g., 80%) of V2. However, hereinafter, for a more concise explanation, it will be assumed that the second time point t2 represents a time point at which a predetermined period of time has passed since the switching time point tSW.

[0102] When the gamma line interconnection circuit GIC operates in the fine restoration mode FINE, the gamma line interconnection circuit GIC may not interconnect the first to nth gamma lines GML1 to GMLn. In this case, the voltage level of the victim gamma line GML_victim may be accurately restored to V2.

[0103] After the third time point t3, the voltage level of the victim gamma line GML_victim may maintain V2. In this case, the voltage V2 may be uniformly provided to a plurality of source driving circuits SDC operating at a grayscale corresponding to the victim gamma line GML_victim.

[0104] In one embodiment, the time interval between the switching time point tSW and the third time point t3 may be smaller than the time interval between the switching time point tSW and the third time point t3. Figure 4 That is, according to an embodiment of the present disclosure, since the gamma line interconnection circuit GIC operates in the coarse recovery mode COARSE between the switching time point tSW and the second time point t2, the voltage level swing of the victim gamma line GML_victim can be minimized.

[0105] In one embodiment, when the voltage level swing of the victim gamma line GML_victim is minimized, the time required for the settling of the output signal of the source driving circuit SDC operating based on the voltage level of the victim gamma line GML_victim can be minimized. Therefore, according to an embodiment of the present disclosure, the operating speed of the display device DPD can be improved.

[0106] In one embodiment, the time interval between the switching time point tSW and the second time point t2 may be greater than the time interval between the second time point t2 and the third time point t3. That is, after the grayscale of the source driver circuit SDC is changed, the time period during which the gamma line interconnection circuit GIC operates in the coarse recovery mode COARSE may be longer than the time period during which the gamma line interconnection circuit GIC operates in the fine recovery mode FINE. More specifically, the ratio of the time interval between the switching time point tSW and the second time point t2 to the time interval between the second time point t2 and the third time point t3 may be about "3:1". However, the scope of the present disclosure is not limited thereto.

[0107] In one embodiment, when the voltage level of the victim gamma line GML_victim maintains the voltage V2, the victim gamma line GML_victim may be referred to as being in a stable state. For example, before the switching time point tSW and after the third time point t3, the victim gamma line GML_victim may be referred to as being in a stable state. However, the scope of the present disclosure is not limited thereto.

[0108] Fig. 9 FIG. 2 shows a source driving circuit connected to a gamma line according to an embodiment of the present disclosure. Figures 1 to 9 , the gamma voltage generator 140 may provide different gamma voltages to the first gamma line GML1 to the nth gamma line GMLn. The first gamma line GML1 to the nth gamma line GMLn may be connected to a plurality of source driving circuits. The gamma line interconnection circuit GIC may interconnect the first gamma line GML1 to the nth gamma line GMLn in response to an interconnection signal ICN. The configuration and function of the gamma voltage generator 140 and the gamma line interconnection circuit GIC are similar to those described above, and thus a detailed description is omitted.

[0109] The first and second source driving circuits SDCa and SDCb may be connected to the first to nth gamma lines GML1 to GMLn. Each of the first and second source driving circuits SDCa and SDCb may be one of the first to mth source driving circuits SDC1 to SDCm described above.

[0110] The grayscale level of the first source driving circuit SDCa can be the same as that of the above reference Figure 3A and Figure 3BThe method described above may be changed in a similar manner. For example, the grayscale of the first source driver circuit SDCa may be changed to correspond to the first gamma line GML1. In this case, the first source driver circuit SDCa may provide a first output signal OUTa generated based on the voltage level of the first gamma line GML1 to the source line. Hereinafter, for a more concise description, the first source driver circuit SDCa will also be referred to as the source driver circuit SDC_TGGL, and the first output signal OUTa will also be referred to as the output signal OUT_TGGL.

[0111] The gray level of the second source driver circuit SDCb may not be changed. For example, the gray level of the second source driver circuit SDCb may be maintained to correspond to the first gamma line GML1. In this case, the second source driver circuit SDCb may provide the second output signal OUTb generated based on the voltage level of the first gamma line GML1 to the source line. Hereinafter, for a more concise description, the second source driver circuit SDCb will also be referred to as the source driver circuit SDC_DC, and the second output signal OUTb will also be referred to as the output signal OUT_DC.

[0112] When the gray level of the first source driving circuit SDCa is changed to correspond to the first gamma line GML1, the voltage level of the first gamma line GML1 may swing. That is, when the gray level of the first source driving circuit SDCa is changed, the first gamma line GML1 may become a victim gamma line GML_victim. In this case, an error may occur in the output of the second source driving circuit SDCb having a gray level corresponding to the first gamma line GML1.

[0113] That is, although the video data VDT indicates that the second output signal OUTb maintains a constant voltage level, when the voltage level of the first gamma line GML1 swings, the voltage of the second output signal OUTb may also swing. Therefore, when the voltage level swing of the first gamma line GML1 is minimized, the voltage swing of the second output signal OUTb may also be minimized. For example, when the gamma line interconnection circuit GIC is connected to the first gamma line GML1 as described above, Figures 5 to 8 When operating in a similar manner as described above, since the swing of the voltage level of the first gamma line GML1 can be minimized, the voltage swing of the second output signal OUTb can also be minimized. Fig.10 The operation of the gamma line interconnection circuit GIC according to the change of the gray level of the first source driving circuit SDCa and the swing of the second output signal OUTb is described in more detail.

[0114] Fig.10 Show according to Fig. 9 The voltage level of the second output signal of the operation of the gamma line interconnection circuit. Figures 1 to 10, the gray level of the first source driver circuit SDCa may be changed at the switching time point tSW. For example, before the switching time point tSW, the gray level of the first source driver circuit SDCa may correspond to the second gamma line GML2, and after the switching time point tSW, the gray level of the first source driver circuit SDCa may correspond to the first gamma line GML1. In this case, after the switching time point tSW, the voltage level of the first gamma line GML1 may swing.

[0115] The interconnection signal ICN may transition to a logic high state at the switching time point tSW. In this case, the gamma line interconnection circuit GIC may enter the coarse recovery mode COARSE. The interconnection signal ICN may transition to a logic low state at a second time point t2 after the switching time point tSW. In this case, the gamma line interconnection circuit GIC may enter the fine recovery mode FINE. The method of determining the second time point t2 and the operation of each operation mode of the gamma line interconnection circuit GIC are similar to those described above with reference to Figure 8 The methods and operations described are therefore omitted in detail.

[0116] The curve diagram shown by one dash-one dot line shows the voltage level of the second output signal OUTb in an ideal case (for example, when there is no parasitic capacitance PC in the source drive circuit). In this case, regardless of the change of the gray level of the first source drive circuit SDCa, the voltage level of the second output signal OUTb can be maintained at the voltage Vc. That is, hereinafter, for a more concise description, it is assumed that the video data VDT indicates that the second output signal OUTb will maintain a constant voltage level. However, the scope of the present disclosure is not limited to this.

[0117] The dotted line graph shows the voltage level of the second output signal OUTb when the gamma line interconnection circuit GIC operates only in the fine recovery mode FINE. That is, the dotted line graph shows the voltage level of the second output signal OUTb when the gamma line interconnection circuit GIC does not interconnect the first gamma line GML1 to the nth gamma line GMLn regardless of the grayscale change of the first source driving circuit SDCa. In this case, the voltage level of the second output signal OUTb may be reduced to the voltage Ve, and may be restored to the voltage Vc after the third time point t3.

[0118] The solid line graph shows the voltage level of the second output signal OUTb when the gamma line interconnection circuit GIC operates in the coarse recovery mode COARSE from the switching time point tSW to the second time point t2 according to an embodiment of the present disclosure. In this case, the voltage level of the second output signal OUTb may be reduced to the voltage Vd and may be restored to the voltage Vc at the third time point t3.

[0119] In one embodiment, the voltage difference between Vc and Vd may be less than the voltage difference between Vc and Ve. For example, Vd may be a higher voltage than Ve. However, the scope of the present disclosure is not limited thereto.

[0120] That is, the magnitude and duration of the swing of the second output signal OUTb caused by the voltage swing of the victim gamma line GML_victim (e.g., the first gamma line GML1) caused by the grayscale change of the first source driver circuit SDCa can be minimized. In this case, errors observed by the user of the display device DPD can be minimized.

[0121] Fig.11 Show Figure 1 The method of operating the gamma ray interconnection circuit. Figures 1 to 11 In operation S100, the gamma line interconnection circuit GIC may connect the plurality of gamma lines to the plurality of nodes of the resistor string RSTR, respectively. For example, when the gray level of one of the source driver circuits is changed, the gamma line interconnection circuit GIC may turn on the switch between the resistor string RSTR and the gamma line. In this case, the RC time constant between the source driver 130 and the gamma voltage generator 140 is minimized, so the voltage level of the victim gamma line GML_victim may be quickly restored.

[0122] In operation S200, the gamma line interconnection circuit GIC may release the interconnection between the plurality of nodes of the resistor string RSTR and the plurality of gamma lines. For example, the gamma line interconnection circuit GIC may disconnect the switch between the resistor string RSTR and the gamma line after a predetermined time has elapsed after performing step S100. In this case, since no resistor is connected between the plurality of gamma lines, the voltage level of the victim gamma line GML_victim may be restored to an accurate level.

[0123] FIG. 12A to FIG. 12C The configurations of the gamma line interconnection circuits implemented according to the embodiments are respectively shown.

[0124] First, refer to Figures 1 to 8 and Fig. 12A , the gamma voltage generator 140 may include a plurality of gamma amplifiers (GA) and a voltage divider circuit. In this case, the number of gamma amplifiers GA included in the gamma voltage generator 140 may be less than the number of gamma lines (ie, "n").

[0125] A plurality of gamma amplifiers GA may be connected to different gamma lines through different tap nodes. Hereinafter, for a more concise description, it is assumed that the kth gamma amplifier GAk is connected to the kth gamma line GMLk through the kth tap node NTAPk. For example, the first gamma amplifier GA1 may be connected to the first gamma line GML1 through the first tap node NTAP1, and the nth gamma amplifier GAn may be connected to the nth gamma line GMLn through the nth tap node NTAPn.

[0126] The first gamma amplifier GA1 may receive the first gamma seed voltage GS1 through the first input terminal. The second input terminal and the output terminal of the first gamma amplifier GA1 may be connected to the first tap node NTAP1. In this case, the first gamma amplifier GA1 may provide a gamma voltage corresponding to the first gamma seed voltage GS1 to the first tap node NTAP1. Similarly, the nth gamma amplifier GAn may provide a voltage corresponding to the nth gamma seed voltage GSn to the nth tap node NTAPn.

[0127] For a more concise description, hereinafter, a node directly connected to a gamma amplifier and a gamma line will be referred to as a tap node, and a gamma line connected through the gamma amplifier and the tap node will be referred to as a tap line. However, the scope of the present disclosure is not limited thereto.

[0128] The voltage divider circuit may include a first voltage dividing resistor RDIV1 to an (n-1)th voltage dividing resistor RDIVn-1. The first voltage dividing resistor RDIV1 to the (n-1)th voltage dividing resistor RDIVn-1 may be connected in series between the first tap node NTAP1 and the nth tap node NTAPn. In this case, the second gamma line GML2 to the (n-1)th gamma line GMLn-1 may be connected to nodes between the first voltage dividing resistor RDIV1 to the (n-1)th voltage dividing resistor RDIVn-1, respectively. For example, the second gamma line GML2 may be connected to a node between the first voltage dividing resistor RDIV1 and the second voltage dividing resistor RDIV2.

[0129] The gamma line interconnection circuit GIC may be connected to the first tap node NTAP1 through the first holding line HL1. For example, the first node N1 may be connected to the first tap node NTAP1 through the first holding line HL1. In this case, the first node N1 and the first tap node NTAP1 may be connected in parallel through the first gamma line GML1 and the first holding line HL1.

[0130] The gamma line interconnection circuit GIC may be connected to the nth tap node NTAPn through the second holding line HL2. For example, the nth node Nn may be connected to the nth tap node NTAPn through the second holding line HL2. In this case, the nth node Nn and the nth tap node NTAPn may be connected in parallel through the nth gamma line GMLn and the second holding line HL2.

[0131] That is, according to Fig. 12A In an embodiment of the present invention, the resistor string RSTR may be connected to the first tap node NTAP1 and the n-th tap node NTAPn. In this way, the resistor string RSTR may receive a first hold voltage through the first hold line HL1 and a second hold voltage through the second hold line HL2. In this case, even if the first switch SW1 of the gamma line interconnection circuit GIC is turned off, the resistor string RSTR does not float. Therefore, the voltage level swing of the first gamma line GML1 to the n-th gamma line GMLn that may occur when the first switch SW1 to the n-th switch SWn are turned on again can be minimized.

[0132] Next, refer to Figures 1 to 8 and Fig. 12B , the gamma voltage generator 140 may further include a first dummy gamma amplifier DGA1 and a second dummy gamma amplifier DGA2.

[0133] The first dummy gamma amplifier DGA1 may generate a voltage corresponding to the first gamma amplifier GA1. For example, a first input terminal of the first dummy gamma amplifier DGA1 may receive a first gamma seed voltage GS1. A second input terminal of the first dummy gamma amplifier DGA1 may be connected to an output terminal of the first dummy gamma amplifier DGA1. The output terminal of the first dummy gamma amplifier DGA1 may be connected to a first node N1 through a first holding line HL1.

[0134] Similarly, the second dummy gamma amplifier DGA2 may generate a voltage corresponding to the nth gamma amplifier GAn. For example, the first input terminal of the second dummy gamma amplifier DGA2 may receive the nth gamma seed voltage GSn. The second input terminal of the second dummy gamma amplifier DGA2 may be the output terminal of the second dummy gamma amplifier DGA2. The output terminal of the second dummy gamma amplifier DGA2 may be connected to the nth node Nn via the second holding line HL2.

[0135] That is, according to Fig. 12B In the embodiment, although the first to nth switches SW1 to SWn of the gamma line interconnection circuit GIC are turned off, the resistor string RSTR is not floated. Therefore, the voltage level swing of the first to nth gamma lines GML1 to GMLn that may occur when the first to nth switches SW1 to SWn are turned on again can be minimized.

[0136] Next, refer to Figures 1 to 8 and Fig. 12C , a resistor string RSTR can be connected to the tap node.

[0137] For example, a node connected to a tap line through a switch in the resistor string RSTR may be connected to a corresponding tap node. For example, a first node N1 connected to a first gamma line GML1 through a first switch SW1 may be connected to the first gamma line GML1 through a first tap node NTAP1. Similarly, a third node N3 connected to a third gamma line GML3 through a third switch SW3 may be connected to a third tap node NTAP3 “connected to the third gamma line GML3”, and an nth node Nn connected to an nth gamma line GMLn through an nth switch SWn may be connected to an nth tap node NTAPn “connected to the nth gamma line GMLn”.

[0138] That is, according to Fig. 12C In the embodiment of the present invention, the corresponding nodes of the resistor string RSTR may be connected to different tap nodes. Although the first to nth switches SW1 to SWn are turned off, the voltage level of the resistor string RSTR may be determined based on the gamma voltage, so the voltage level swing of the first to nth gamma lines GML1 to GMLn that may occur when the first to nth switches SW1 to SWn are turned on again may be minimized.

[0139] For a more concise description, Fig. 12C Although an embodiment in which the third gamma line GML3 is a tap line has been described, the scope of the present disclosure is not limited thereto. That is, any gamma line among the first to nth gamma lines GML1 to GMLn may be implemented as a tap line.

[0140] Fig.13 FIG. 2 shows a configuration of a gamma line interconnection circuit implemented according to an embodiment. Figures 1 to 8 and Fig.13 , nodes included in the resistor string RSTR of the gamma line interconnection circuit GIC may be connected to the current supply circuit CPC, respectively. For example, the first node N1 to the nth node Nn may be connected to the first current supply circuit CPC1 to the nth current supply circuit CPCn, respectively.

[0141] When the gamma line interconnection circuit GIC operates in the coarse recovery mode COARSE, each of the first to nth current supply circuits CPC1 to CPCn may supply current to the connected node. In this case, current may be supplied to the first to nth gamma lines GML1 to GMLn through the resistor string RSTR, so that the voltage level of the victim gamma line GML_victim may be recovered more quickly.

[0142] In one embodiment, due to the change of the grayscale of the source driving circuit, the size of the voltage level swing that may occur in the first gamma line GML1 to the nth gamma line GMLn may vary. For example, among the first gamma line GML1 to the nth gamma line GMLn, the size of the voltage level swing that occurs in the tap line may be smaller than the size of the voltage level swing that occurs in the gamma lines other than the tap line. Therefore, each of the first current supply circuit CPC1 to the nth current supply circuit CPCn may be implemented to provide a current of optimized intensity to the connected node according to the size of the voltage level swing of the corresponding gamma line. In this case, the distribution of the voltage level swing that occurs in different gamma lines can be minimized. Referring to Fig.14 and Fig.15 A more detailed configuration of the current supply circuit is described.

[0143] Fig.14 It is shown Fig.13 The circuit diagram of the current supply circuit. Figures 1 to 8 , Fig.13 and Fig.14 , the first current supply circuit CPC1 to the nth current supply circuit CPCn may be implemented as a push-and-pull current source, respectively. Hereinafter, for a more concise description, the configuration of the kth current supply circuit CPCk among the first current supply circuit CPC1 to the nth current supply circuit CPCn will be described as a representative example. However, the scope of the present disclosure is not limited thereto, and each of the first current supply circuit CPC1 to the nth current supply circuit CPCn may be implemented in a similar manner.

[0144] The kth current supply circuit CPCk may include a first transistor TR1, a second transistor TR2, a first current source CS1, and a second current source CS2. The first current source CS1 may be connected between a drain terminal of the first transistor TR1 and a power supply voltage VDD. The second current source CS2 may be connected between a drain terminal of the second transistor TR2 and a ground voltage.

[0145] Source terminals of the first transistor TR1 and the second transistor TR2 may be connected to the kth node Nk. In this case, the current supply circuit CPC may supply a current to the kth node Nk based on a voltage supplied to a gate terminal N_G1 (hereinafter, referred to as a first gate terminal) of the first transistor TR1 and a voltage supplied to a gate terminal N_G2 (hereinafter, referred to as a second gate terminal) of the second transistor TR2.

[0146] In one embodiment, the current supply circuit CPC may be configured to operate only during a period when the interconnection signal ICN is in a logic high state. That is, the current supply circuit CPC may be configured to supply current to the kth node Nk only when the gamma line interconnection circuit GIC operates in the coarse recovery mode COARSE. For example, the switch may be further connected between the source terminals of the first transistor TR1 and the second transistor TR2 and the kth node Nk. However, the scope of the present disclosure is not limited to this, and it may be configured so that the first current source CS1 and the second current source CS2 operate only during a period when the interconnection signal ICN is in a logic high state. That is, the scope of the present disclosure is not limited to the specific implementation method of the current supply circuit CPC.

[0147] In one embodiment, the first gate terminal N_G1 and the second gate terminal N_G2 may receive the same voltage. For example, the first gate terminal N_G1 and the second gate terminal N_G2 may be implemented to receive one of a plurality of gamma seed voltages (e.g., the kth gamma seed voltage GSk). However, the scope of the present disclosure is not limited thereto, and the first gate terminal N_G1 and the second gate terminal N_G2 may be implemented to receive any tap voltage.

[0148] In one embodiment, the voltage received by the first gate terminal N_G1 and the voltage received by the second gate terminal N_G2 may be different for each of the first current providing circuit CPC1 to the nth current providing circuit CPCn. For example, the voltage provided to the first gate terminal N_G1 and the second gate terminal N_G2 of the first current providing circuit CPC1 may be the first gamma seed voltage GS1, and the voltage provided to the first gate terminal N_G1 and the second gate terminal N_G2 of the nth current providing circuit CPCn may be the nth gamma seed voltage GSn. However, the scope of the present disclosure is not limited thereto.

[0149] In one embodiment, the first gate terminal N_G1 and the second gate terminal N_G2 may be implemented to receive different voltages. For example, the first gate terminal N_G1 and the second gate terminal N_G2 may be implemented to receive different gamma seed voltages. Fig.15 An embodiment in which the first gate terminal N_G1 and the second gate terminal N_G2 receive different voltages is described in more detail.

[0150] Fig.15 By way of example Figure 1 The gamma voltage generator is configured as follows. Figures 1 to 8 , FIG. 12A to FIG. 12C and Figures 13 to 15 , the gamma voltage generator 140 may include a gamma seed voltage generator GSG and a plurality of gamma amplifiers GA. The configuration and operation of the plurality of gamma amplifiers GA are similar to those previously described with reference to FIG. 12A to FIG. 12CThe configuration and operation are described, and thus a detailed description is omitted.

[0151] The gamma seed voltage generator GSG may include a plurality of gamma seed resistors RGS. The plurality of gamma seed resistors RGS may be connected in series between a gamma seed top voltage VGST and a gamma seed bottom voltage VGSB.

[0152] In one embodiment, the gamma seed top voltage VGST may be a power supply voltage, and the gamma seed bottom voltage VGSB may be a ground voltage. However, the scope of the present disclosure is not limited thereto.

[0153] In one embodiment, the plurality of gamma seed resistors RGS may have the same size as each other. However, the scope of the present disclosure is not limited thereto, and the plurality of gamma seed resistors RGS may have different sizes.

[0154] A plurality of gamma amplifiers GA may be connected to different nodes between a plurality of gamma seed resistors RGS. For example, a first gamma amplifier GA1 may be connected to a first gamma seed node NGS1. In this case, a first gamma seed voltage GS1 may be provided from the first gamma seed node NGS1 to the first gamma amplifier GA1. Similarly, an nth gamma seed voltage GSn may be provided from an nth gamma seed node NGSn to the nth gamma amplifier GAn.

[0155] The first gate terminal N_G1 and the second gate terminal N_G2 of the kth current supply circuit CPCk may be connected to different nodes of the gamma seed voltage generator GSG. That is, the first gate terminal N_G1 and the second gate terminal N_G2 may be implemented to receive different gamma seed voltages. In this case, the voltage supplied to the first gate terminal N_G1 may be a voltage high enough to turn on the first transistor TR1. Similarly, the voltage supplied to the second gate terminal N_G2 may be a voltage high enough to turn on the second transistor TR2.

[0156] In one embodiment, the gamma seed node connected to the first gate terminal N_G1 and the second gate terminal N_G2 of the kth current supply circuit CPCk may be determined based on the magnitude of the voltage level swing occurring in the kth gamma line GMLk. In this case, when the gamma line interconnection circuit GIC operates in the coarse recovery mode, a current of optimized intensity may be provided to each gamma line, so that the distribution of the voltage level swing occurring in different gamma lines may be minimized.

[0157] For a more concise description, Fig.15, an embodiment in which the gamma seed voltage generator GSG generates a plurality of gamma seed voltages GS1 to GSn through a plurality of resistors is representatively described, but the scope of the present disclosure is not limited thereto. For example, the plurality of gamma seed voltages GS1 to GSn may be provided from outside the gamma voltage generator 140. In this case, the first gate terminal N_G1 and the second gate terminal N_G2 of the k-th current providing circuit CPCk may be implemented to receive different gamma seed voltages from the outside.

[0158] Fig.16 Another embodiment of the present disclosure is shown in FIG. Figure 5 A circuit diagram of the configuration of the gamma line interconnection circuit. Figures 1 to 5 7 , the gamma line interconnection circuit GIC_1 may be implemented to interconnect some of the first to n-th gamma lines GML1 to GMLn in response to an interconnection signal ICN.

[0159] The gamma voltage generator 140 may include a plurality of gamma amplifiers GA1, GA2, ..., GAn and a voltage divider circuit including resistors RDIV1, RDIV2, RDIV3, ..., RDIVn-1. The detailed configuration of the gamma voltage generator 140 is similar to that of the reference Fig. 12A or Fig. 12C The configuration described herein is omitted and a detailed description is therefore omitted.

[0160] The gamma line interconnection circuit GIC_1 may include a plurality of switches respectively connected to the plurality of tap lines. For example, the gamma line interconnection circuit GIC_1 may include a first switch connected to the first gamma line GML1, a third switch connected to the third gamma line GML3, and an nth switch SWn connected to the nth gamma line GMLn.

[0161] One terminal of the plurality of switches not connected to the gamma line may be connected to the resistor string RSTR. For example, one terminal of the switch SWk not connected to the gamma line may be connected to the kth node Nk. That is, the first switch SW1 is connected between the first gamma line GML1 and the first node N1, and the third switch SW3 may be connected between the third gamma line GML3 and the third node N3.

[0162] The resistor string RSTR may include a plurality of resistors R1, R3, ... Rn. Each of the plurality of resistors may be connected between a plurality of switches connected to the tap line. For example, the first resistor R1 may be connected between the first node N1 and the third node N3.

[0163] The switches of the gamma line interconnection circuit GIC_1 may operate in response to the interconnection signal ICN. For example, when the interconnection signal ICN is in a logic high state, the first switch SW1, the third switch SW3, and the nth switch SWn may be turned on, and when the interconnection signal ICN is in a logic low state, the first switch SW1, the third switch SW3, and the nth switch SWn may be turned off. That is, the first switch SW1, the third switch SW3, and the nth switch SWn may be turned on when the gamma line interconnection circuit GIC_1 operates in a coarse recovery mode, and may be turned off when the gamma line interconnection circuit GIC_1 operates in a fine recovery mode.

[0164] That is, according to an embodiment of the present disclosure, the gamma line interconnection circuit GIC_1 may be implemented to interconnect a plurality of tap lines in response to an interconnection signal ICN. However, the scope of the present disclosure is not limited to the number and type of gamma lines interconnected by the gamma line interconnection circuit. For example, the gamma line interconnection circuit may be implemented to interconnect odd gamma lines among a plurality of gamma lines, or to interconnect even gamma lines among a plurality of gamma lines. That is, it may be implemented to interconnect any gamma lines.

[0165] Fig.17 FIG. 2 shows a layout of a display driving circuit according to an embodiment. Figure 1 and Fig.17 , the arrangement layout of the display driving circuit 10a implemented in a 1 gamma block structure will be described.

[0166] The gamma voltage generator 140 may be disposed at the center of the display driving circuit 10a. On both sides of the gamma voltage generator 140, a source driving circuit array SDCA_L and a source driving circuit array SDCA_R may be disposed.

[0167] Each of the source driving circuit arrays SDCA_L and SDCA_R may include a plurality of source driving circuits. The plurality of source driving circuits may be connected to the gamma voltage generator 140 through a plurality of gamma lines, respectively. In this case, when the gray level of the source driving circuit away from the gamma voltage generator 140 is changed, similar to Figure 4 As described above, a relatively large voltage level swing may occur in the victim gamma line GML_victim.

[0168] Fig.18 FIG. 1 shows a layout of a display driving circuit according to an embodiment. Figure 1 , Fig.17 and Fig.18 The arrangement layout of the display driving circuit 10 b implemented in a 2-gamma block structure is described.

[0169] The central block CB may be disposed at the center of the display driving circuit 10b. The central block CB may include the control logic circuit 110. However, the scope of the present disclosure is not limited to the types of constituent elements of the display driving circuit 10b.

[0170] The first gamma voltage generator 140a (GVG#1) may be disposed on the left side of the central block CB. The second gamma voltage generator 140b (GVG#2) may be disposed on the right side of the central block CB.

[0171] The source driving circuit array SDCA_L2 may be disposed on the left side of the first gamma voltage generator 140a, and the source driving circuit array SDCA_L1 may be disposed on the right side of the first gamma voltage generator 140a. Each of the source driving circuit arrays SDCA_L1 and SDCA_L2 may include a plurality of source driving circuits. Each source driving circuit included in the source driving circuit arrays SDCA_L1 and SDCA_L2 may be connected to the first gamma voltage generator 140a through a plurality of gamma lines.

[0172] The source driving circuit array SDCA_R1 may be disposed on the left side of the second gamma voltage generator 140b, and the source driving circuit array SDCA_R2 may be disposed on the right side of the second gamma voltage generator 140b. Each of the source driving circuit arrays SDCA_R1 and SDCA_R2 may include a plurality of source driving circuits. Each source driving circuit included in the source driving circuit arrays SDCA_R1 and SDCA_R2 may be connected to the second gamma voltage generator 140b through a plurality of gamma lines.

[0173] Therefore, when the number of source driving circuits included in the display driving circuit 10a is the same as the number of source driving circuits included in the display driving circuit 10b, the average distance between the source driving circuit and the voltage driving circuit of the display driving circuit 10b is shorter than the average distance between the source driving circuit and the voltage driving circuit of the driving circuit 10a. For example, the distance between the first gamma voltage generator 140a of the display driving circuit 10b and the farthest source driving circuit may be about half of the distance between the farthest source driving circuit and the gamma voltage generator 140 of the display driving circuit 10a. In this case, since the magnitude of the parasitic resistance between the source driving circuit and the voltage driving circuit of the display driving circuit 10b is reduced, the voltage level swing occurring in the victim gamma line may be reduced.

[0174] However, according to Fig.18In the embodiment of the present invention, the display driving circuit 10b may include a first gamma voltage generator 140a and a second gamma voltage generator 140b. That is, the display driving circuit 10b may include more gamma voltage generators than the display driving circuit 10a. Therefore, the area and power consumption of the display driving circuit 10b will be greater than the area and power consumption of the display driving circuit 10a.

[0175] Fig.19 The following is a diagram showing a layout of a display driving circuit according to an embodiment of the present disclosure. Fig.19 The arrangement layout of the display driving circuit 100 implemented with a 1-gamma block having a 2-GIC structure is described. Figures 1 to 8 as well as Fig.17 , the gamma voltage generator 140 may be disposed at the center of the display driving circuit 100 .

[0176] The source driving circuit array SDCA_L1 and the source driving circuit array SDCA_L2 may be disposed on the left side of the gamma voltage generator 140. The source driving circuit array SDCA_R1 and the source driving circuit array SDCA_R2 may be disposed on the right side of the gamma voltage generator 140.

[0177] The source driving circuit array SDCA_L1 and the source driving circuit array SDCA_R1 may be disposed adjacent to the gamma voltage generator 140. The source driving circuit array SDCA_L2 and the source driving circuit array SDCA_R2 may be disposed at a distance from the gamma voltage generator 140.

[0178] Each of the source driving circuit arrays SDCA_L1 , SDCA_L2 , SDCA_R1 , and SDCA_R2 may include one or more of first to m-th source driving circuits SDC1 to SDCm.

[0179] The gamma voltage generator 140 may be connected to the source driving circuit arrays SDCA_L1, SDCA_L2, SDCA_R1, and SDCA_R2 through the first to nth gamma lines GML1 to GMLn. In this case, the first to nth gamma lines GML1 to GMLn may be implemented in a form extending to the left and right from the gamma voltage generator 140. However, the scope of the present disclosure is not limited thereto.

[0180] The gamma line interconnection circuit GIC_L may be disposed between the source driving circuit array SDCA_L1 and the source driving circuit array SDCA_L2. For example, the gamma line interconnection circuit GIC_L may be disposed between a region of the first gamma line GML1 to the nth gamma line GMLn connected to the source driving circuit array SDCA_L1 and a region of the first gamma line GML1 to the nth gamma line GMLn connected to the source driving circuit array SDCA_L2.

[0181] The gamma line interconnection circuit GIC_R may be disposed between the source driving circuit array SDCA_R1 and the source driving circuit array SDCA_R2. For example, the gamma line interconnection circuit GIC_R may be disposed between a region of the first gamma line GML1 to the nth gamma line GMLn connected to the source driving circuit array SDCA_R1 and a region of the first gamma line GML1 to the nth gamma line GMLn connected to the source driving circuit array SDCA_R2.

[0182] When one or more gray levels of the first source driving circuit SDC1 to the mth source driving circuit are changed, the gamma line interconnection circuit GIC_L and the gamma line interconnection circuit GIC_R may interconnect the first gamma line GML1 with the nth gamma line GMLn. In this case, the voltage level swing of the victim gamma line GML_victim determined by the magnitude of the parasitic resistance between the source driving circuit and the voltage driving circuit may be minimized. Therefore, when the display driving circuit 100 is implemented with a 1-gamma block 2-GIC structure, the voltage level swing of the victim gamma line GML_victim may be smaller than when the display driving circuit 10a is implemented with a 1-gamma block structure. Figures 1 to 15 The detailed configuration and operation of the gamma line interconnection circuit GIC_L and the gamma line interconnection circuit GIC_R are described, and thus, the detailed description will be omitted.

[0183] At the same time, the gamma line interconnection circuit GIC_L and the gamma line interconnection circuit GIC_R can be implemented with a smaller number of circuits than the gamma voltage generator. That is, the gamma line interconnection circuit GIC_L and the gamma line interconnection circuit GIC_R can be implemented with a smaller area than the gamma voltage generator, and can be implemented to consume less power. Therefore, compared with the display driving circuit 10b implemented with a 2-gamma block structure, the display driving circuit 100 with a 1-gamma block 2-GIC structure can have a smaller area and power consumption.

[0184] Fig. 20 Shown according to reference Figures 17 to 19 The voltage level swing of the victim gamma line of the described layout. Figures 1 to 10 as well as Figures 17 to 20 ,exist Fig. 20, the horizontal axis represents time, and the vertical axis represents the voltage level of the victim gamma line GML_victim when the gray level of any source driving circuit is changed. In the following, it is assumed that the source driving circuit with a changed gray level is the source driving circuit farthest from the gamma voltage generator 140, but the scope of the present disclosure is not limited thereto.

[0185] The single-point dashed line graph shows the voltage level of the victim gamma line GML_victim of the display driving circuit 10a implemented in the 1-gamma block structure. That is, when the display driving circuit 10a is implemented in the 1-gamma block structure, as previously described with reference to Figure 4 As described, the voltage level of the victim gamma line GML_victim may be reduced to V3 after the switching time point tSW.

[0186] The dashed line graph shows the voltage level of the victim gamma line GML_victim of the display driving circuit 10b implemented in the 2-gamma block structure. That is, when the display driving circuit 10b is implemented in the 2-gamma block structure, the voltage level of the victim gamma line GML_victim may decrease to V5 after the switching time point tSW.

[0187] As reference Figures 1 to 15 and Fig.19 As described above, the solid line graph shows the voltage level of the victim gamma line GML_victim when the display driving circuit 100 is implemented with a 1-gamma block 2-GIC structure. That is, when the display driving circuit 100 is implemented with a 1-gamma block 2-GIC structure, the voltage level of the victim gamma line GML_victim may be reduced to V4 after the switching time point tSW, which has been previously referred to. Figure 8 Described this.

[0188] In one embodiment, the voltage difference between V2 and V4 may be less than the voltage difference between V2 and V5. The voltage difference between V2 and V5 may be less than the voltage difference between V2 and V3. For example, V4 may be a higher voltage than V5, and V5 may be a higher voltage than V3. However, the scope of the present disclosure is not limited thereto.

[0189] That is, according to the embodiment of the present disclosure, the voltage level swing of the victim gamma line GML_victim can be minimized while minimizing the area of ​​the display driving circuit 100. For example, when the display driving circuit is implemented with a 1-gamma block 2-GIC structure according to the embodiment of the present disclosure, similar to the case where the display driving circuit is implemented with a 2-gamma block structure, the voltage level swing of the victim gamma line GML_victim can be minimized (i.e., compared with the case where the display driving circuit is implemented with a 1-gamma structure, the voltage level swing of the victim gamma line GML_victim is reduced), while minimizing the area and power consumption of the display driving circuit (i.e., compared with the case where the display driving circuit is implemented with a 2-gamma block structure).

[0190] To describe it more concisely, Fig. 20 , the voltage level of the victim gamma line GML_victim when the gray level of the source driving circuit display farthest from the gamma voltage generator 140 is changed is representatively described, but the scope of the present disclosure is not limited thereto. For example, the second voltage V2 to the fifth voltage V5 may vary depending on whether the gray level of the source driving circuit is changed, the size of the resistor included in the gamma line interconnection circuit GIC, etc.

[0191] Fig.21 Shown according to reference Figures 17 to 19 The gray scale of the layout described above is changed by a graph showing the output signal of the source driver circuit. Figures 1 to 10 as well as Figures 17 to 21 , assuming that the gray level of the source driver circuit SDC_TGGL is changed at the switching time point tSW. Fig.21 , the horizontal axis of the graph represents time, and the vertical axis of the graph represents the voltage of the output signal OUT_TGGL. In the following, for a more concise description, it is assumed that the output signal OUT_TGGL has a voltage Vpre before the gray level of the source driver circuit SDC_TGGL is changed, and after a sufficient time has passed after the gray level of the source driver circuit SDC_TGGL is changed, the voltage of the output signal OUT_TGGL becomes Vpost. In addition, in the following, it is assumed that the source driver circuit SDC_TGGL is the source driver circuit that is set farthest from the gamma voltage generator 140, but the scope of the present disclosure is not limited to this.

[0192] The single-dot chain line graph shows the voltage level of the output signal OUT_TGGL when the display driving circuit 10a is implemented in a 1-gamma block structure. In this case, the output signal OUT_TGGL may reach Vpost at a sixth time point t6.

[0193] The dashed line graph shows the voltage level of the output signal OUT_TGGL when the display driving circuit 10b is implemented in a 2-gamma block structure. In this case, the output signal OUT_TGGL may reach Vpost at the fifth time point t5.

[0194] As previously referred Figures 1 to 5 and Fig.19 As described, the solid line graph shows the voltage level of the output signal OUT_TGGL when the display driving circuit 100 is implemented with a 1-gamma block having a 2-GIC structure. In this case, the output signal OUT_TGGL may reach Vpost at a fourth time point t4.

[0195] The fourth time point t4 may be before the fifth time point t5, and the fifth time point t5 may be before the sixth time point t6. That is, when the display driving circuit 100 is implemented with a 1-gamma block having a 2-GIC structure, the voltage level swing of the victim gamma line GML_victim may be minimized, and thus, the time (e.g., the swing length) required for the source driving circuit SDC_TGGL to generate a desired voltage through a grayscale change may be minimized.

[0196] Fig. 22 FIG. 1 shows a layout of a display driving circuit according to an embodiment of the present disclosure. Fig. 22 , the display driving circuit 200 can be implemented with a 1-gamma block 4-GIC structure.

[0197] The source driving circuit arrays SDCA_L1 to SDCA_L3 may be disposed on the left side of the gamma voltage generator 140. The source driving circuit arrays SDCA_R1 to SDCA_R3 may be disposed on the right side of the gamma voltage generator 140. Each of the source driving circuit arrays SDCA_L1 to SDCA_L3 and SDCA_R1 to SDCA_R3 may include one or more of the first to m-th source driving circuits SDC1 to SDCm.

[0198] The gamma line interconnection circuit GIC_L1 may be disposed between the source driving circuit array SDCA_L1 and the source driving circuit array SDCA_L2. The gamma line interconnection circuit GIC_L2 may be disposed between the source driving circuit array SDCA_L2 and the source driving circuit array SDCA_L3.

[0199] The gamma line interconnection circuit GIC_R1 may be disposed between the source driving circuit array SDCA_R1 and the source driving circuit array SDCA_R2. The gamma line interconnection circuit GIC_R2 may be disposed between the source driving circuit array SDCA_R2 and the source driving circuit array SDCA_R3.

[0200] To describe it more concisely, Fig.21 , the output signal OUT_TGGL is representatively described in the case where the source driving circuit SDC_TGGL is disposed farthest from the gamma voltage generator 140, but the scope of the present disclosure is not limited thereto. For example, the fourth voltage t4 to the sixth voltage t6 may vary according to the distance between a specific source driving circuit SDC_TGGL and the gamma voltage generator 140, the size of the resistor included in the gamma line interconnection circuit GIC, and the like.

[0201] exist Fig. 22 In the embodiment, for a more concise description, four gamma line interconnection circuits are provided for one gamma voltage generator 140, but the scope of the present disclosure is not limited to the number of gamma line interconnection circuits. For example, the display driving circuit can be implemented in various formats (such as a 1-gamma block structure with 6-GIC).

[0202] Fig.23 FIG. 2 shows a layout of a display driving circuit according to an embodiment of the present disclosure. Fig.23 , the display driving circuit 300 can be implemented in a 2-gamma block 4-GIC structure.

[0203] The center block CB may be disposed at the center of the display driving circuit 300. For example, the center block CB may include the control logic circuit 110. However, the scope of the present disclosure is not limited thereto.

[0204] The first gamma voltage generator 140a may be disposed on the left side of the central block CB. The second gamma voltage generator 140b may be disposed on the right side of the central block CB.

[0205] The source driving circuit array SDCA_L3 and the source driving circuit array SDCA_L4 may be disposed on the left side of the first gamma voltage generator 140a. The source driving circuit array SDCA_L1 and the source driving circuit array SDCA_L2 may be disposed between the first gamma voltage generator 140a and the center block CB. The source driving circuit array SDCA_L3 and the source driving circuit array SDCA_L2 may be disposed adjacent to the first gamma voltage generator 140a.

[0206] The gamma line interconnection circuit GIC_L2 may be disposed between the source driving circuit array SDCA_L3 and the source driving circuit array SDCA_L4. The gamma line interconnection circuit GIC_L1 may be disposed between the source driving circuit array SDCA_L2 and the source driving circuit array SDCA_L1.

[0207] The source driving circuit array SDCA_R3 and the source driving circuit array SDCA_R4 may be disposed on the right side of the second gamma voltage generator 140b. The source driving circuit array SDCA_R1 and the source driving circuit array SDCA_R2 may be disposed between the second gamma voltage generator 140b and the center block CB. The source driving circuit array SDCA_R3 and the source driving circuit array SDCA_R2 may be disposed adjacent to the second gamma voltage generator 140b.

[0208] The gamma line interconnection circuit GIC_R2 may be disposed between the source driving circuit array SDCA_R3 and the source driving circuit array SDCA_R4. The gamma line interconnection circuit GIC_R1 may be disposed between the source driving circuit array SDCA_R2 and the source driving circuit array SDCA_R1.

[0209] exist Fig.23 In the embodiment, for a more concise description, an embodiment in which four gamma line interconnection circuits are provided for two gamma voltage generators is representatively described, but the scope of the present disclosure is not limited to the number of gamma voltage generators and gamma line interconnection circuits.

[0210] Fig.24 FIG. 2 shows a configuration of a gamma line interconnection circuit according to another embodiment of the present disclosure. Figure 5 and Fig.24 , Figure 1 The gamma line interconnect circuit GIC in the Fig.24 . The gamma line interconnection circuit GIC_2 shown in FIG. The gamma line interconnection circuit GIC_2 may include a first switch SW1 to an (n-1)th switch SWn-1 and a first resistor R1 to an (n-1)th resistor Rn-1. The first switch SW1 to the (n-1)th switch SWn-1 and the first resistor R1 to the (n-1)th resistor Rn-1 may be connected between the first gamma line GML1 to the nth gamma line GMLn, respectively. For example, the first switch SW1 and the first resistor R1 may be connected in series between the first gamma line GML1 and the second gamma line GML2, and the second switch SW2 and the second resistor R2 may be connected in series between the second gamma line GML2 and the third gamma line GML3. In this way, the n-1th switch SWn-1 and the n-1th resistor Rn-1 may be connected in series between the n-1th gamma line GMLn-1 and the nth gamma line GMLn.

[0211] The first switch SW1 to the (n-1)th switch SWn-1 may operate in response to the interconnection signal ICN. For example, the first switch SW1 to the (n-1)th switch SWn-1 may be turned on when the interconnection signal ICN is in a logic high state, and may be turned off when the interconnection signal ICN is in a logic low state. That is, the gamma line interconnection circuit GIC may operate in a coarse recovery mode or a fine recovery mode in response to the logic level of the interconnection signal ICN. In this case, the voltage level swing of the victim gamma line GML_victim may be minimized. The timing of the logic level transition of the interconnection signal ICN is similar to that of the reference signal ICN. Figures 1 to 8 The time for description, and thus the detailed description will be omitted.

[0212] The above description is a specific embodiment for carrying out the present disclosure. The present disclosure will include not only the above-mentioned embodiments, but also embodiments that can be simply changed or easily changed in design. In addition, the present disclosure will also include technologies that can be easily modified and implemented using the disclosed embodiments. Therefore, the scope of the present disclosure should not be limited to the above-mentioned embodiments, and should be limited by the scope of the claims and the scope equivalent to the scope of the claims of the present disclosure.

Claims

1. A gamma ray interconnection circuit, comprising: a resistor string including a first resistor connected between a first node and a second node and a second resistor connected between the second node and a third node; a first switch connected between the first gamma line and the first node and configured to operate based on an interconnection signal; a second switch connected between the second gamma line and the second node and configured to operate based on the interconnection signal; as well as The third switch is connected between the third gamma line and the third node and is configured to operate based on the interconnection signal.

2. The gamma line interconnection circuit according to claim 1, wherein: When the interconnect signal is in a logic high state, each of the first switch, the second switch, and the third switch is turned on, and When the interconnect signal is in a logic low state, each of the first switch, the second switch, and the third switch is turned off.

3. The gamma line interconnection circuit according to claim 2, wherein: The interconnection signal is transformed into a logic high state at a first time point when a grayscale value provided to a first source driving circuit connected to the first gamma line, the second gamma line, and the third gamma line is changed.

4. The gamma ray interconnection circuit according to claim 3, wherein: The interconnection signal transitions to a logic low state at a second time point after a first time period has elapsed from the first time point.

5. The gamma line interconnection circuit according to claim 4, wherein: After the first time point, the first source driving circuit operates based on the voltage level of the first gamma line.

6. The gamma ray interconnection circuit according to claim 5, wherein: At a third time point after a second period of time has passed from the second time point, a voltage level of the first gamma line reaches a voltage level equal to that of the first gamma line before the first time point.

7. The gamma line interconnection circuit according to claim 6, wherein: The first time period is greater than the second time period.

8. The gamma line interconnection circuit according to claim 4, further comprising: a first current providing circuit connected to the first node and configured to operate between a first time point and a second time point; a second current providing circuit connected to the second node and configured to operate between the first time point and the second time point; as well as The third current supply circuit is connected to the third node and is configured to operate between the first time point and the second time point.

9. The gamma ray interconnection circuit according to any one of claims 1 to 8, wherein: The first node is configured to receive a first holding voltage through a first holding line, and The third node is configured to receive a second holding voltage through a second holding line.

10. The gamma line interconnection circuit according to claim 9, wherein: The voltage level of the first hold voltage corresponds to the voltage level of the first gamma line, and The voltage level of the second hold voltage corresponds to the voltage level of the third gamma line.

11. The gamma line interconnection circuit according to claim 1, wherein: The first gamma line, the second gamma line, and the third gamma line are connected to output nodes of different gamma amplifiers.

12. A display driving circuit, comprising: A source driving circuit controls the display panel; a gamma voltage generator for providing first to Nth gamma voltages to first to Nth gamma lines connected to the source driving circuit, respectively, wherein N is an integer greater than 2; as well as The gamma line interconnection circuit interconnects the first gamma line to the Nth gamma line within a first time period from a first time point when the grayscale value of the source driving circuit is changed.

13. The display driving circuit according to claim 12, wherein: The gamma line interconnect circuit includes: The first switch to the Nth switch are connected between the first gamma line to the Nth gamma line and the first node to the Nth node, respectively; and The resistor string includes first to N-1th resistors respectively connected between adjacent node pairs among the first to Nth nodes.

14. The display driving circuit according to claim 13, wherein: Each of the first to Nth switches is configured as: is turned on during a first time period from a first time point to a second time point, and Disconnected before the first time point and after the second time point.

15. The display driving circuit according to claim 14, wherein: During a first time period between a first time point and a second time point, a first resistance-capacitance time constant between the source driving circuit and the gamma voltage generator is smaller than a second resistance-capacitance time constant between the source driving circuit and the gamma voltage generator after the second time point.

16. The display driving circuit according to claim 13, wherein: The gamma voltage generator includes: a first gamma amplifier configured to output a first gamma voltage to a first tap node connected to a first gamma line; a second gamma amplifier configured to output an Nth gamma voltage to a second tap node connected to an Nth gamma line; and The voltage divider circuit is connected between the first tap node and the second tap node and is configured to output the second gamma voltage to the N-1th gamma voltage.

17. The display driving circuit according to claim 16, wherein: The first node is connected to the first tap node via a first holding line, and The second node is connected to the second tap node through a second holding line.

18. The display driving circuit according to claim 16, wherein: The gamma voltage generator also includes: a first dummy gamma amplifier configured to provide a first dummy voltage corresponding to a first gamma voltage to the first node; and The second dummy gamma amplifier is configured to provide a second dummy voltage corresponding to an Nth gamma voltage to the Nth node.

19. A display device comprising: A display panel comprising a first plurality of pixels and a second plurality of pixels; as well as A display driving circuit is configured to control the first plurality of pixels and the second plurality of pixels, Wherein, the display driving circuit comprises: a gamma voltage generator, providing different gamma voltages to a plurality of gamma lines; a first source driver circuit array connected to the plurality of gamma lines and comprising a first plurality of source driver circuits configured to control the first plurality of pixels; a second source driver circuit array connected to the plurality of gamma lines and comprising a second plurality of source driver circuits configured to control the second plurality of pixels; and A gamma line interconnection circuit is located between the first source driver circuit array and the second source driver circuit array, and interconnects the plurality of gamma lines during a predetermined time period after one or more grayscale values ​​of the first plurality of source driver circuits and the second plurality of source driver circuits are changed.

20. The display device according to claim 19, wherein: The gamma line interconnect circuit includes: a resistor string; and a plurality of switches respectively connected between one of the plurality of nodes included in the resistor string and one of the plurality of gamma lines; and Each of the plurality of switches is turned on during a time period from a first time point to a second time point, and is turned off before the first time point and after the second time point.

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