Display device

Abstract

A display device includes: a first pixel and a second pixel; a first data line connected to the first pixel and configured to have a data voltage applied to the first data line; and a second data line connected to the second pixel, the second data line being adjacent to the first data line and configured to have a data voltage applied to the second data line, in which the first data line includes a 1A-th data line in a first data layer, and the second data line includes a 2B-th data line in a second data layer different from the first data layer.

Description

[0001] This application is a divisional application of the invention with a filing date of February 27, 2020, application number 202010124243.1 and name “Display Device”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0023263, filed on February 27, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] Aspects of some example embodiments of the present disclosure relate to a display device. Background Art

[0005] With the development of the information society, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation devices, smart televisions (TVs), etc. Examples of display devices include flat panel display devices such as liquid crystal display (LCD) devices, field emission display (FED) devices, organic light emitting diode (OLED) display devices, etc.

[0006] OLED display devices include self-luminous elements that can allow pixels of a display panel to emit light, and thus can display images without a backlight unit that provides light to the display panel. Therefore, compared with other display devices, OLED display devices can be designed in various forms and shapes.

[0007] The above information disclosed in this Background section is only for enhancement of understanding of the background technology and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0008] Aspects of some example embodiments of the present disclosure include a display device having a through-hole in a display area thereof.

[0009] However, the embodiments of the present disclosure are not limited to those set forth herein. The above and other embodiments of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0010] According to some example embodiments of the present disclosure, a display device includes: a first pixel and a second pixel; a first data line connected to the first pixel and having a data voltage applied to the first data line; and a second data line connected to the second pixel, the second data line being adjacent to the first data line and having a data voltage applied to the second data line, wherein the first data line includes a 1A data line in a first data layer, and the second data line includes a 2B data line in a second data layer disposed in a different layer from the first data layer.

[0011] According to some example embodiments of the present disclosure, a display device includes: a first pixel and a second pixel; a first data line connected to the first pixel and having a data voltage applied to the first data line; and a second data line connected to the second pixel, the second data line being adjacent to the first data line and having a data voltage applied to the second data line, wherein the first data line includes a 2A data line in a second data layer, and the second data line includes a 2B data line disposed in the second data layer, the 2B data line is connected to the second pixel through a first data bridge electrode, and the 2A data line is connected to the first pixel through a second data bridge electrode.

[0012] According to some example embodiments of the present disclosure, a display device includes: a first substrate having a first through hole area defined on the first substrate and having a first through hole formed therein, a first wiring area surrounding the first through hole area, and a pixel area in which a pixel is arranged to surround the first wiring area; and a first data line and a second data line on the first substrate are adjacent to each other, wherein the first data line includes a plurality of metal layers in the pixel area and includes a second metal layer among the plurality of metal layers in the first wiring area.

[0013] According to some example embodiments of the present disclosure, a display device is provided, which includes: a first substrate having a through-hole area defined on the first substrate in which a through-hole is formed, a wiring area surrounding the through-hole area, and a pixel area in which pixels surround the wiring area; and a first data line and a second data line on the first substrate are adjacent to each other, wherein the first data line includes a first metal layer in both the pixel area and the wiring area, and the second data line includes a second metal layer in both the pixel area and the wiring area.

[0014] According to some example embodiments of the present disclosure, a display device is provided, the display device comprising: a first substrate having a through hole area defined on the first substrate in which a through hole is formed, a wiring area surrounding the through hole area, and a pixel area in which pixels are positioned to surround the wiring area; and a first data line and a second data line on the first substrate are adjacent to each other, wherein the first data line comprises a first metal layer in the wiring area and a second metal layer in the pixel area, and the second data line comprises the second metal layer in both the pixel area and the wiring area.

[0015] According to the aforementioned and other embodiments of the present disclosure, the camera device overlaps with the through hole formed in the display area of ​​the display panel, and thus an image of the background in front of the display panel can be captured through the through hole and the camera hole. That is, the camera device can be placed to overlap with the display area instead of overlapping with the non-display area of ​​the display panel, and as a result, the display area of ​​the display panel can be widened.

[0016] In addition, since the first data line and the second data line adjacent to each other do not need any bridge electrode in the wiring area, the load of the first data line and the second data line can be prevented from increasing due to the presence of the bridge electrode. Moreover, any difference between the load of the first data line and the second data line passing through the wiring area and the load of the data line not passing through the wiring area can be minimized.

[0017] Other features and embodiments may be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other embodiments and aspects of the present disclosure will become more apparent by describing embodiments of the present disclosure in more detail with reference to the accompanying drawings, in which:

[0019] Figure 1 is a perspective view of a display device according to some example embodiments of the present disclosure;

[0020] Figure 2 yes Figure 1 An exploded perspective view of a display device;

[0021] Figure 3 It is a graphic Figure 1 A plan view of a display panel;

[0022] Figure 4 is along Figure 3 A cross-sectional view taken along line II';

[0023] Figure 5 It is a graphic Figure 4 A plan view of an example of a display unit;

[0024] Figure 6 It is a graphic Figure 5 A plan view of area A;

[0025] Figure 7 It is a graphic Figure 6 A plan view of area B;

[0026] Fig. 8A It is a graphic Figure 7 An example plan view of a region C1;

[0027] Figure 8B It is a graphic Figure 7 A plan view of another example of the area C1;

[0028] Fig. 9 It is a graphic Fig. 8A A plan view of a first data metal layer and a second data metal layer;

[0029] Fig.10 is along Fig. 8A A cross-sectional view taken along line II-II';

[0030] Fig.11 is along Fig. 8A A cross-sectional view taken along line III-III';

[0031] Fig.12 is along Figure 7 A cross-sectional view taken along line IV-IV';

[0032] Fig.13 is along Figure 7 A cross-sectional view taken along line V-V';

[0033] Fig.14 It is a graphic Figure 7 A plan view of another example of the area C1;

[0034] Fig.15 It is a graphic Fig.14 A plan view of a first data metal layer and a second data metal layer;

[0035] Fig.16 It is a graphic Figure 7 A plan view of another example of the area C1;

[0036] Fig.17 It is a graphic Fig.16 A plan view of a first data metal layer and a second data metal layer;

[0037] Fig.18 It is a graphic Figure 7 A plan view of another example of the area C1;

[0038] Fig.19 It is a graphic Fig.18 A plan view of a first data metal layer and a second data metal layer; and

[0039] Fig. 20 It is a graphic Figure 4 A plan view of another example of a display unit. DETAILED DESCRIPTION

[0040] Aspects of some example embodiments of the present invention will now be described more fully below with reference to the accompanying drawings in which example embodiments of the present invention are shown. However, the present invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be exhaustive and comprehensive, and fully convey the scope of the present invention to those skilled in the art. Throughout the specification, the same reference numerals indicate the same components. In the accompanying drawings, the thickness of layers and regions is magnified for clarity.

[0041] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0042] Hereinafter, aspects of some example embodiments of the present invention will be described with reference to the accompanying drawings.

[0043] Figure 1 is a perspective view of a display device according to some example embodiments of the present disclosure. Figure 2 yes Figure 1 An exploded perspective view of a display device.

[0044] refer to Figure 1 and Figure 2 , the display device 10 may be a mobile terminal. Examples of mobile terminals include smart phones, tablet personal computers (PCs), personal digital assistants (PDAs), portable multimedia players (PMPs), game consoles, wristwatch-type electronic devices, etc. However, the display device 10 is not limited to being a mobile terminal, but may be used in large electronic devices such as televisions (TVs) or outdoor billboards, or in medium-sized electronic devices or small electronic devices such as monitors, notebook computers, car navigation devices, or cameras.

[0045] The display device 10 includes a cover window 100 , a display panel 110 , a first driving circuit unit 200 , a display circuit board 300 , a second driving circuit unit 400 , a main circuit board 800 , a main processor 810 , a camera device 820 , and a lower cover 900 .

[0046] As used herein, the terms "above", "top" and "top surface" refer to the direction in which the cover window 100 is arranged relative to the display panel 110, that is, the Z-axis direction, and as used herein, the terms "below", "bottom" and "bottom surface" refer to the direction in which the lower cover 900 is arranged relative to the display panel 110, that is, the direction opposite to the Z-axis direction. Moreover, as used herein, the terms "left", "right", "upper" and "lower" refer to their respective directions when viewed from above the display panel 110. For example, the term "left" refers to the X-axis direction, the term "right" refers to the direction opposite to the X-axis direction, the term "upper" refers to the Y-axis direction, and the term "lower" refers to the direction opposite to the Y-axis direction.

[0047] The display device 10 may have a rectangular shape in a plan view. For example, in a plan view, the display device 10 may have a rectangular shape having a pair of short sides extending in a first direction (or an X-axis direction) and a pair of long sides extending in a second direction (or a Z-axis direction). The corners where the short sides and long sides of the display device 10 meet may be rounded or right angled. The planar shape of the display device 10 is not specifically limited, and the display device 10 may be formed in another polygonal shape, a circular shape, or an elliptical shape in a plan view.

[0048] The cover window 100 may be located above the display panel 110 to cover the top surface of the display panel 110. Therefore, the cover window 100 may protect the top surface of the display panel 110. The cover window 100 may be attached to the touch sensing device via an adhesive member. The adhesive member may be an optically clear adhesive (OCA) or an optically clear resin (OCR).

[0049] The cover window 100 may be formed of glass, sapphire, and / or plastic. The cover window 100 may be rigid or flexible.

[0050] The cover window 100 may include a light-transmitting portion DA100 corresponding to the display area DA of the display panel 110 and a light-shielding portion NDA100 corresponding to the non-display area NDA of the display panel 110. A camera hole CMH penetrating the cover window 100 may be formed in the light-transmitting portion DA100 of the cover window 100. The camera hole CMH may overlap with the through hole TH of the display panel 110. The light-shielding portion NDA100 of the cover window 100 may be opaque. Alternatively, the light-shielding portion NDA100 of the cover window 100 may be formed as a decorative layer, and a pattern formed on the decorative layer may be viewed by a user when no image is displayed. For example, a company's logo or a string of various characters may be patterned on the light-shielding portion NDA100 of the cover window 100.

[0051] The display panel 110 may be located under the cover window 100. The display panel 110 may include a display area DA and a non-display area NDA. The display area DA may be an area in which an image is displayed, and the non-display area NDA may be an area in which an image is not displayed and may be located at the periphery of the display area DA. Figure 2 As illustrated in , the non-display area NDA may be positioned to surround the display area DA, but the present disclosure is not limited thereto. The display area DA may overlap with the light-transmitting portion DA100 of the cover window 100, and the non-display area NDA may overlap with the light-shielding portion NDA100 of the cover window 100. In the display area DA of the display panel 110, a through hole TH penetrating the display panel 110 may be formed. The through hole TH may overlap with the camera hole CMH of the cover window 100 and with the camera device 820 of the main circuit board 800.

[0052] The display panel 110 may be an LED display panel including a light emitting diode (LED). For example, the display panel 110 may be an OLED display panel using an organic LED (OLED), an mLED display panel using a micro LED (mLED), or a QLED display panel using a quantum dot LED (QLED). Assuming that the display panel 110 is an OLED display panel, reference will be made later to Figure 3 and Figure 4 The display panel 110 is described.

[0053] A polarizing film may be attached to the top surface of the display panel 110 to prevent visibility reduction that may be caused by reflection of external light. The polarizing film may be a λ / 2 (or half-wave) plate or a λ / 4 (or quarter-wave) plate.

[0054] The first driving circuit unit 200 may be located at a first side of the display panel 110. The first driving circuit unit 200 may output signals and voltages for driving pixels of a display unit of the display panel 110. The first driving circuit unit 200 may be formed as an integrated circuit (IC) and may be attached to the first substrate in a chip on glass (COG) or chip on plastic (COP) manner.

[0055] The display circuit board 300 may be attached to the first side of the display panel 110. For example, the display circuit board 300 may be attached to a pad provided on the first side of the display panel 110 via an anisotropic conductive film. The pad of the display panel 110 may be located outside the first driving circuit unit 200.

[0056] The second driving circuit unit 400 may be located on the display circuit board 300. The second driving circuit unit 400 may output a touch driving signal for driving the touch electrode of the touch sensing layer, and may detect the capacitance of the touch electrode. The second driving circuit unit 400 may be formed as an IC. The second driving circuit unit 400 may not only detect the presence of a touch input, but also calculate the touch coordinates of the touch input based on the capacitance of the touch electrode.

[0057] The panel bottom member may be located on the bottom surface of the display panel 110. The panel bottom member may include at least one of a heat dissipation layer for effectively releasing heat from the display panel 110, an electromagnetic wave shielding layer for shielding electromagnetic waves, a light shielding layer for shielding incident light from the outside, a light absorption layer for absorbing incident light from the outside, and a buffer layer for absorbing external impact.

[0058] The main circuit board 800 may be located below the display panel 110. The main circuit board 800 may be connected to the display circuit board 300 via a cable. Therefore, the first driving circuit unit 200 located on the display panel 110, the second driving circuit unit 400 of the display circuit board 300, and the main processor 810 of the main circuit board 800 may be electrically connected to each other. The main circuit board 800 may be a printed circuit board (PCB) or a flexible PCB (FPCB).

[0059] The main processor 810 and the camera device 820 may be located on the main circuit board 800. A mobile communication module capable of transmitting or receiving wireless signals to or from a base station, an external terminal, and a server via a mobile communication network, and a sound module for outputting sound may be further located on the main circuit board 800. Examples of wireless signals include voice signals, video call signals, and various data that may be transmitted together with text / multimedia messages.

[0060] The main processor 810 may control all functions of the display device 10. For example, the main processor 810 may output digital video data and a timing signal to the first driving circuit unit 200 via the display circuit board 300 so that the display panel 110 displays an image. Also, the main processor 810 may receive touch coordinate data including touch row data or touch coordinates from the second driving circuit unit 400, and may execute an application displayed at the touch position. Also, the main processor 810 may control driving of the camera device 820. The main processor 810 may be an application processor implemented as an IC.

[0061] The camera device 820 may overlap the through hole TH of the display panel 110. Therefore, the camera device 820 may capture an image of a background in front of the display panel 110 through the through hole TH and the camera hole CMH. The camera device 820 may be a complementary metal oxide semiconductor (CMOS) image sensor or a charge coupled device (CCD) image sensor. The camera device 820 may process an image frame such as a still image or a moving image obtained by the image sensor.

[0062] The lower frame may be located between the display panel 110 and the main circuit board 800. The lower frame may be formed to surround a bottom surface and / or a side surface of the display panel 110. The lower frame may include a synthetic resin and / or a metal.

[0063] The lower cover 900 may be located below the main circuit board 800. The lower cover 900 may form a bottom exterior of the display device 10. The lower cover 900 may include plastic and / or metal.

[0064] exist Figure 1 and Figure 2 In an embodiment of the present invention, the camera device 820 may overlap with the through hole TH formed in the display area DA of the display panel 110, and may capture an image of a background in front of the display panel 110 through the through hole TH and the camera hole CMH. That is, the camera device 820 may be arranged to overlap with the display area DA instead of the non-display area NDA, and as a result, the display area DA of the display panel 110 may be widened.

[0065] Figure 3 It is a graphic Figure 1 A plan view of the display panel.

[0066] refer to Figure 3 , the display panel 110 may include a main area MA and a protrusion area PA protruding from one side of the main area MA.

[0067] The main area MA may be formed in a rectangular shape in a plan view, the rectangular shape having a pair of short sides extending in a first direction (or X-axis direction) and a pair of long sides extending in a second direction (or Y-axis direction). The angles where the short sides and long sides of the main area MA meet may be rounded with a predetermined curvature or may be right angles. The planar shape of the main area MA is not specifically limited, and the main area MA may be formed in another polygonal shape, a circular shape, or an elliptical shape in a plan view. The main area MA may be flat, but the present disclosure is not limited thereto. The main area MA may include arc portions on both sides of the main area MA, in which case the arc portions may have a consistent or varying curvature.

[0068] The main area MA may include a display area DA in which pixels are formed to display an image and a non-display area NDA at the periphery of the display area DA.

[0069] Not only pixels but also scan lines and data lines connected to the pixels may be located in the display area DA. In the display area DA, a through hole TH penetrating the display panel 110 may be formed. Pixels, scan lines, and data lines are not formed in the through hole TH. In the case where the main area MA includes an arc portion, the display area DA may also be located on the arc portion. In this case, an image displayed by the display panel 110 may be viewed even from the arc portion.

[0070] The non-display area NDA may be defined as a region ranging from an edge of the display area DA to an edge of the display panel 110. A scan driver for applying a scan signal to a scan line and a link line connecting a data line and the first driving circuit unit 200 may be located in the non-display area NDA.

[0071] The protruding area PA may protrude from one side of the main area MA. For example, the protruding area PA may protrude from the lower side of the main area MA. Figure 3 The length of the protrusion area PA in the first direction (or the X-axis direction) may be smaller than the length of the main area MA in the first direction (or the X-axis direction).

[0072] The protruding area PA may include a bending area BA and a pad area PDA. In this case, the pad area PDA may be located on one side of the bending area BA, and the main area MA may be located on the other side of the bending area BA. For example, the pad area PDA may be located on the lower side of the bending area BA, and the main area MA may be located on the upper side of the bending area BA.

[0073] The display panel 110 may be formed to be flexible and thus may be foldable, bendable or rollable. Therefore, the display panel 110 may be bent in the thickness direction (or Z-axis direction) in the bending area BA. In this case, when the display panel 110 has not been bent, the pad area PDA of the display panel 110 may face upward, and once the display panel 110 is bent, the pad area PDA of the display panel 110 may face downward. Since the pad area PDA is located below the main area MA when the display panel 110 is bent, the pad area PDA may overlap with the main area MA.

[0074] The first driving circuit unit 200 and pads electrically connected to the display circuit board 300 may be located in the pad area PDA of the display panel 110 .

[0075] The first drive circuit unit 200 outputs a signal and a voltage for driving the display panel 110. For example, the first drive circuit unit 200 may supply a data voltage to a data line. The first drive circuit unit 200 may also supply a scan control signal to a scan driver. The first drive circuit unit 200 may be formed as an IC and may be mounted on the display panel 110 (specifically, in the pad area PDA) in a COG, COP or ultrasonic bonding manner, but the present disclosure is not limited thereto. Alternatively, the first drive circuit unit 200 may be mounted on a display circuit board 300.

[0076] The pads located in the pad area PDA may include display pads electrically connected to the first driving circuit unit 200 and touch pads electrically connected to the touch lines.

[0077] The display circuit board 300 may be attached to the pad via an anisotropic conductive film. As a result, the leads of the display circuit board 300 may be electrically connected to the pad. The display circuit board 300 may be a flexible film such as an FPCB, a PCB, or a chip on film (COF).

[0078] The second driving circuit unit 400 may be connected to the touch electrodes of the touch sensor layer of the display panel 110. The second driving circuit unit 400 applies a driving signal to the touch electrodes of the touch sensor layer and measures the capacitance of the touch electrodes of the touch sensor layer. The driving signal may be a signal having a plurality of driving pulses. The second driving circuit unit 400 may not only determine the presence of a touch input, but also calculate the touch coordinates of the touch input based on the capacitance of the touch electrodes of the touch sensor layer.

[0079] The second driving circuit unit 400 may be located on the display circuit board 300. The second driving circuit unit 400 may be formed as an IC and may be mounted on the display circuit board 300.

[0080] Figure 4 is along Figure 3 A cross-sectional view taken along line II'.

[0081] refer to Figure 4 The display panel 110 may include a display unit DU and a touch sensing unit (or a touch sensor layer TSL). The display unit DU includes a first substrate SUB1 and a thin film transistor (TFT) layer TFTL, a light emitting element layer EML, and a thin film encapsulation layer TFEL located on the first substrate SUB1, and the touch sensing unit includes the touch sensor layer TSL.

[0082] The first substrate SUB1 may be formed of an insulating material such as glass, quartz, or a polymer resin. Examples of polymer resins include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), and combinations thereof. Alternatively, the first substrate SUB1 may include a metal material.

[0083] The first substrate SUB1 may be a rigid substrate or a bendable, foldable, or rollable flexible substrate. In the case where the first substrate SUB1 is a flexible substrate, the first substrate SUB1 may be formed of PI, but the present disclosure is not limited thereto.

[0084] The TFT layer TFTL may be located on the first substrate SUB1. In the TFT layer TFTL, a TFT of each pixel, a scan line, a data line, a power line, a scan control line, and a routing line connecting a pad and a data line may be formed. Each TFT may include a gate electrode, a semiconductor layer, a source electrode, and a drain electrode. Figure 5 As illustrated in FIG. 1 , in the case where the scan driver 111 is formed in the non-display area NDA of the display panel 110 , the scan driver 111 may include a TFT.

[0085] The TFT layer TFTL may be located in the display area DA and in the non-display area NDA. For example, the TFT of each pixel and the scan line, data line, and power line of the TFT layer TFTL may be located in the display area DA. The scan control line and routing line of the TFT layer TFTL may be located in the non-display area NDA.

[0086] The light emitting element layer EML may be located on the TFT layer TFTL. The light emitting element layer EML may include pixels (each pixel having a first electrode, a light emitting layer, and a second electrode) and a pixel defining film defining the pixel. The light emitting layer may be an organic light emitting layer including an organic material. In this case, the light emitting layer may include a hole transport layer, an organic light emitting layer, and an electron transport layer. In response to a predetermined voltage applied to the first electrode of the pixel via the TFT of the TFT layer TFTL and a cathode voltage applied to the second electrode of the pixel, holes and electrons may move to the organic light emitting layer via the hole transport layer and the electron transport layer, respectively, and may be combined in the organic light emitting layer to emit light. The pixels of the light emitting element layer EML may be located in the display area DA.

[0087] The thin film encapsulation layer TFEL may be located on the light emitting element layer EML. The thin film encapsulation layer TFEL prevents oxygen or moisture from penetrating into the light emitting element layer EML. To this end, the thin film encapsulation layer TFEL may include at least one inorganic film. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, or a titanium oxide layer, but the present disclosure is not limited thereto. Moreover, the thin film encapsulation layer TFEL protects the light emitting element layer EML from foreign matter such as dust. To this end, the thin film encapsulation layer TFEL may include at least one organic film. The organic film may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a PI resin, but the present disclosure is not limited thereto.

[0088] The thin film encapsulation layer TFEL may be located in both the display area DA and the non-display area NDA. For example, the thin film encapsulation layer TFEL may be arranged to cover the light emitting element layer EML in the display area DA and the non-display area NDA and to cover the TFT layer TFTL in the non-display area NDA.

[0089] The touch sensor layer TSL may be located on the thin film encapsulation layer TFEL. When the touch sensor layer TSL is directly located on the thin film encapsulation layer TFEL, the thickness of the display device 10 may be reduced compared to when a separate touch panel including the touch sensor layer TSL is attached to the thin film encapsulation layer TFEL.

[0090] The touch sensor layer TSL may include a touch electrode for detecting a touch input from a user in a capacitive manner and a touch line for connecting a pad and the touch electrode. For example, the touch sensor layer TSL may detect a touch input from a user in a self-capacitive manner or a mutual-capacitive manner.

[0091] The touch electrodes of the touch sensor layer TSL may be arranged to overlap the display area DA, and the touch lines of the touch sensor layer TSL may be arranged to overlap the non-display area NDA.

[0092] The cover window 100 may be located on the touch sensor layer TSL, in which case the touch sensor layer TSL and the cover window 100 may be attached to each other via an adhesive member such as OCA or OCR. Alternatively, a polarizing film may be located on the touch sensor layer TSL, in which case the polarizing film and the cover window 100 may be attached to each other via an adhesive member.

[0093] Figure 5 It is a graphic Figure 4 A plan view of an example of a display unit.

[0094] For convenience, Figure 5Only the pixels PX, the scan lines SL, the data lines DL, the scan control lines SCL, the routing lines RL, the scan driver 111, the first driving circuit unit 200, and the display pads DP of the display unit DU are illustrated.

[0095] refer to Figure 5 , scan lines SL, data lines DL and pixels PX are located in the display area DA. The scan lines SL may be formed in parallel in a first direction (or X-axis direction), and the data lines DL may be formed in parallel in a second direction (or Y-axis direction).

[0096] A through hole TH penetrating the display panel 110 is formed in the display area DA. Figure 5 Only one through hole TH is illustrated as being formed in the display area DA, but the present disclosure is not limited thereto. Fig. 20 As illustrated in FIG. 2 , two through holes TH may be formed in the display area DA, or three or more through holes TH may be formed in the display area DA. Also, Figure 5 The through hole TH is illustrated as having a circular shape in a plan view, but the present disclosure is not limited thereto. Alternatively, the through hole TH may be formed in an elliptical shape, a polygonal shape, or an amorphous shape in a plan view.

[0097] The pixel PX, the scan line SL, and the data line DL cannot be located in the through hole TH. Therefore, since the scan line SL is formed in the first direction (or the X-axis direction), the scan line SL may be arranged to bypass the through hole TH to pass through the upper side or the lower side of the through hole TH and be connected to the pixel PX on the left side or the right side of the through hole TH. Since the data line DL is formed in the second direction (or the Y-axis direction), the data line DL may be arranged to bypass the through hole TH to pass through the left side or the right side of the through hole TH and be connected to the pixel PX on the upper side or the lower side of the through hole TH. This will be referred to later. Figure 6 The relative arrangements of the through holes TH, the pixels PX, the scan lines SL, and the data lines DL are described in detail.

[0098] The pixels PX may be located at intersections between the scan lines SL and the data lines DL. Each of the pixels PX may be connected to at least one of the scan lines SL and one of the data lines DL. Fig. 8A Each of the pixels PX is illustrated as being connected to three scan lines SL and one data line DL, but the present disclosure is not limited thereto.

[0099] Each of the pixels PX may include a TFT (including a driving transistor and one or more switching transistors), an OLED, and a capacitor. In response to a scan signal applied by the switching transistor via the scan line SL, the pixel PX may receive a data voltage via the data line DL, and may emit light by supplying a driving current to the OLED of the pixel PX according to the data voltage applied to the gate electrode of the driving transistor of the pixel PX. Fig. 8A Each of the pixels PX is illustrated as including one driving transistor, six switching transistors, an OLED, and a capacitor, but the present disclosure is not limited thereto.

[0100] The scan driver 111 may be connected to the first driving circuit unit 200 via at least one scan control line SCL. The scan driver 111 may generate a scan signal according to a scan control signal, and may provide the scan signal to the scan line SL. Figure 5 The scan driver 111 is illustrated as being formed in a portion of the non-display area NDA on the left side of the display area DA, but the present disclosure is not limited thereto. In another example, the scan driver 111 may be formed in portions of the non-display area NDA on both the left and right sides of the display area DA.

[0101] The first drive circuit unit 200 is connected to the display pad DP and thus receives digital video data and timing signals. The first drive circuit unit 200 converts the digital video data into positive / negative analog data voltages and provides the positive / negative analog data voltages to the data lines DL via the routing lines RL. Moreover, the first drive circuit unit 200 generates a scan control signal for controlling the scan driver 111 and provides the scan control signal via the scan control line SCL. The pixel PX to be provided with the data voltage can be selected by the scan signal generated by the scan driver 111, and the data voltage can be provided to the selected pixel PX. The first drive circuit unit 200 can be formed as an IC and can be attached to the first substrate SUB1 in a COG, COP or ultrasonic bonding manner.

[0102] Figure 6 It is a graphic Figure 5 A plan view of area A. Figure 7 It is a graphic Figure 6 A plan view of area B.

[0103] For the sake of convenience, the pixel PX is not shown in the figure. Figure 6 , and only the pth to p+7th scan lines SLp to SLp+7th and the s+5th to tth data lines DLs+5 to DLtth are illustrated. Figure 7 middle.

[0104] refer to Figure 6 and Figure 7 , the display area DA may include the through hole TH, the dead space area DSA, the wiring area LA, and the pixel area PXA.

[0105] The dead area DSA may be arranged to surround the through hole TH. The pixel PX, the scan line SL, and the data line DL may not be located in the dead area DSA. The dead area DSA is an area for preventing the through hole TH from encroaching the wiring area LA due to an error in forming the through hole TH.

[0106] The wiring area LA may be arranged to surround the dead zone area DSA. Since the pixel PX is not located in the wiring area LA, the wiring area LA is classified as a non-display area NDA in which an image is not displayed.

[0107] The p+1th scan line SLp+1 to the qth scan line SLq (where p and q are positive integers satisfying the following inequality: q≥p+3) and the q+1th scan line SLq+1 to the r+1th scan line SLr+1 (where r≥q+2) may be located in the wiring area LA. The p+1th scan line SLp+1 to the qth scan line SLq may be bent in the second direction (or the Y-axis direction), and thus may bypass the through hole TH to pass through the upper side of the through hole TH, and the q+1th scan line SLq+1 to the r+1th scan line SLr+1 may be bent in the opposite direction of the second direction (or the opposite direction of the Y-axis direction), and thus may bypass the through hole TH to pass through the lower side of the through hole TH.

[0108] The s+1th data line DLs+1 to the tth data line DLt (where s and t are positive integers satisfying the following inequality: t≥s+6) and the t+1th data line DLt+1 to the uth data line DLu (where u is a positive integer satisfying the following inequality: u≥t+6) may be located in the wiring area LA. The s+1th data line DLs+1 to the tth data line DLt may be bent in the opposite direction of the first direction (or the opposite direction of the X-axis direction), and thus may bypass the through hole TH to pass through the left side of the through hole TH, and the t+1th data line DLt+1 to the uth data line DLu may be bent in the first direction (or the X-axis direction), and thus may bypass the through hole TH to pass through the right side of the through hole TH.

[0109] In the wiring area LA, the p+1th to qth scan lines SLp+1 and the q+1th to slr+1th scan lines SLq+1 and the r+1th to slr+1th scan lines may intersect with the s+1th to tth data lines DLs+1 and the t+1th to tth data lines DLt+1 and the uth data lines DLt+1. The distance between the p+1th to qth scan lines SLp+1 and the distance between the q+1th to slr+1th scan lines SLq+1 and the r+1th to slr+1th scan lines SLr+1 in the wiring area LA may be smaller than in the pixel area PXA.

[0110] The pixel area PXA refers to an area where the pixel PX is located. In the pixel area PXA, the scan lines SL may be arranged to extend in parallel in a first direction (or X-axis direction), and the data lines DL may be arranged to extend in parallel in a second direction (or Y-axis direction).

[0111] Each of the pixels PX may overlap at least one of the scan lines SL and one of the data lines DL. Fig. 8A Each of the pixels PX is illustrated as being connected to three scan lines SL and one data line DL, but the present disclosure is not limited thereto.

[0112] In order to minimize the size of the wiring area LA, the distance between the s+1th data line DLs+1 to the tth data line DLt and the distance between the t+1th data line DLt+1 to the uth data line DLu in the wiring area LA may be set to be smaller than in the pixel area PXA. Furthermore, in order to minimize the size of the wiring area LA, each pair of adjacent scan lines SL may be located in different metal layers in the wiring area LA, while in the pixel area PXA, each pair of adjacent scan lines SL is located in the same gate layer.

[0113] For example, the p+1th scan line SLp+1 may include the 1A scan line SLA1 and the 1B scan line SLB1 and the first scan bridge electrode SBE1 located in the same gate layer. The first scan bridge electrode SBE1 may be connected to the 1A scan line SLA1 through a first scan contact hole SCT1 exposing the 1A scan line SLA1, and may be connected to the 1B scan line SLB1 through a second scan contact hole SCT2 exposing the 1B scan line SLB1. The 1A scan line SLA1 may be a scan line connected to the pixel PX, and the 1B scan line SLB1 may be a scan line bypassing the through hole TH in the wiring area LA.

[0114] The p+2 scan line SLp+2 adjacent to the p+1 scan line SLp+1 may include the 2A scan line SLA2 and the 2B scan line SLB2 located in different gate layers and the second scan bridge electrode SBE2. The second scan bridge electrode SBE2 may be connected to the 2A scan line SLA2 through the third scan contact hole SCT3 exposing the 2A scan line SLA2, and may be connected to the 2B scan line SLB2 through the fourth scan contact hole SCT4 exposing the 2B scan line SLB2. The 2A scan line SLA2 may be a scan line connected to the pixel PX, and the 2B scan line SLB2 may be a scan line bypassing the through hole TH in the wiring area LA.

[0115] exist Figure 6 and Figure 7 In the embodiment of the present invention, the p+1 scan line SLp+1 including the 1A scan line SLA1 and the 1B scan line SLB1 located in the same gate layer and the p+2 scan line SLp+2 including the 2A scan line SLA2 and the 2B scan line SLB2 located in different metal layers both include scan bridge electrodes. Therefore, any difference in wiring resistance between the p+1 scan line SLp+1 and the p+2 scan line SLp+2 can be minimized. That is, any difference in RC time constant between the p+1 scan line SLp+1 and the p+2 scan line SLp+2 can be minimized.

[0116] Fig. 8A It is a graphic Figure 7 FIG. 1 is a plan view of an example of region C1. Fig. 9 It is a graphic Fig. 8A A plan view of a first data metal layer and a second data metal layer.

[0117] Fig. 8A and Fig. 9 Each of the pixels PX is illustrated as including seven transistors and one capacitor, but the present disclosure is not limited thereto.

[0118] Reference 8A and Fig. 9 , each of the pixels PX may include a driving transistor DT, first to sixth switching transistors ST1 to ST6 , and a capacitor.

[0119] The driving transistor DT may include a driving active layer DT_ACT, a driving gate electrode DT_G, a driving source electrode DT_S, and a driving drain electrode DT_D. The driving active layer DT_ACT may overlap with the driving gate electrode DT_G. The driving source electrode DT_S may be connected to the sixth drain electrode D6 of the sixth switching transistor ST6. The driving drain electrode DT_D may be connected to the source electrode S1 of the first switching transistor ST1 and the source electrode S4 of the fourth switching transistor ST4.

[0120] The first switching transistor ST1 may include a first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1. The first gate electrode G1 may be a portion of the p+1 scan line SLp+1 that overlaps the first active layer ACT1. The first source electrode S1 may be connected to the drain electrode DT_D of the driving transistor DT. The first drain electrode D1 may be connected to the gate electrode DT_G of the driving transistor DT. The first switching transistor ST1 may be formed as a dual transistor. In this case, the first switching transistor ST1 may include two first active layers ACT1 and two first gate electrodes G1, such as Fig. 8A As shown in the figure.

[0121] The second switching transistor ST2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2. The second gate electrode G2 may be a portion of the p-th scan line SLp that overlaps the second active layer ACT2. The second source electrode S2 may be connected to the gate electrode DT_G of the driving transistor DT and the first drain electrode D1 of the first switching transistor ST1. The second drain electrode D2 may be connected to the initialization voltage line VIL through the fourth contact hole CNT4. The second switching transistor ST2 may be formed as a double transistor. In this case, the second switching transistor ST2 may include two second active layers ACT2 and two second gate electrodes G2, such as Fig. 8A As shown in the figure.

[0122] The third switching transistor ST3 may include a third active layer ACT3, a third gate electrode G3, a third source electrode S3, and a third drain electrode D3. The third gate electrode G3 may be a portion of the p-th scan line SLp that overlaps the third active layer ACT3. The third source electrode S3 may be connected to the anode electrode 171 of the OLED. The third drain electrode D3 may be connected to the initialization voltage line VIL through a fourth contact hole CNT4.

[0123] The fourth switching transistor ST4 may include a fourth active layer ACT4, a fourth gate electrode G4, a fourth source electrode S4, and a fourth drain electrode D4. The fourth gate electrode G4 may be a portion of the p+1 emission control line ELp+1 that overlaps the fourth active layer ACT4. The fourth source electrode S4 may be connected to the drain electrode DT_D of the driving transistor DT and the first source electrode S1 of the first switching transistor ST1. The fourth drain electrode D4 may be connected to the anode electrode 171 of the OLED.

[0124] The fifth switching transistor ST5 may include a fifth active layer ACT5, a fifth gate electrode G5, a fifth source electrode S5, and a fifth drain electrode D5. The fifth gate electrode G5 may be a portion of the p+1 emission control line ELp+1 that overlaps the fifth active layer ACT5. The fifth drain electrode D5 may be connected to the source electrode DT_S of the driving transistor DT and the sixth drain electrode D6 of the sixth switching transistor ST6. The fifth source electrode S5 may be connected to the first power supply voltage line VDL through the seventh contact hole CNT7.

[0125] The sixth switching transistor ST6 may include a sixth active layer ACT6, a sixth gate electrode G6, a sixth source electrode S6, and a sixth drain electrode D6. The sixth gate electrode G6 may be a portion of the p+1 scan line SLp+1 that overlaps the sixth active layer ACT6. The sixth source electrode S6 may be connected to the data line through the third contact hole CNT3. The sixth drain electrode D6 may be connected to the driving source electrode DT_S of the driving transistor DT.

[0126] The first electrode CE1 of the capacitor may be substantially identical to the gate electrode DT_G of the driving transistor DT, and the second electrode CE2 of the capacitor may overlap the gate electrode DT_G of the driving transistor DT and may be connected to the first power supply voltage line VDL through the eighth contact hole CNT8 .

[0127] The first bridge electrode BE1 may be connected to the driving gate electrode DT_G through the first contact hole CNT1. The first bridge electrode BE1 may be connected to the first drain electrode D1 of the first switching transistor ST1 through the second contact hole CNT2.

[0128] The second bridge electrode BE2 may be connected to the second drain electrode D2 of the second switch transistor ST2 through the fourth contact hole CNT4. The second bridge electrode BE2 may be connected to the initialization voltage line VIL through the fifth contact hole CNT5. The second bridge electrode BE2 may be arranged to intersect the p-th scan line SLp.

[0129] The third bridge electrode BE3 may be connected to the fourth drain electrode D4 of the fourth switch transistor ST4 through the sixth contact hole CNT6. The third bridge electrode BE3 may be connected to the fourth bridge electrode BE4 through the ninth contact hole CNT9. The fourth bridge electrode BE4 may be connected to the anode electrode 171 through the anode contact hole AND_CNT.

[0130] The s+5th data line DLs+5 may include the 1Ath data line DLA1, and the s+6th data line DLs+6 adjacent to the s+5th data line DLs+5 may include the 1Bth data line DLB1 and the 2Bth data line DLB2. The 2Bth data line DLB2 may be connected to the 1Bth data line DLB1 through the first data contact hole DCT1.

[0131] The 1A data line DLA1, the 1B data line DLB1, the first power supply voltage line VDL, the first bridge electrode BE1, the second bridge electrode BE2, and the third bridge electrode BE3 may be formed as a first data layer. On the other hand, the 2B data line DLB2 and the fourth bridge electrode BE4 may be formed as a second data layer located in a different layer from the first data layer.

[0132] The s+5th data line DLs+5 may include only the 1Ath data line DLA1 in both the pixel area PXA and the wiring area LA. The s+6th data line DLs+6 may include the 1Bth data line DLB1 and the 2Bth data line DLB2 in the pixel area PXA, but may include only the 2Bth data line DLB2 in the wiring area LA. In order to minimize the size of the wiring area LA, in the wiring area LA, the distance between the s+5th data line DLs+5 and the s+6th data line DLs+6 may be set to be smaller than in the pixel area PXA. Moreover, in the wiring area LA, the s+5th data line DLs+5 and the s+6th data line DLs+6 may be arranged to overlap each other.

[0133] The pixel PX may include a first pixel that outputs a first light, a second pixel that outputs a second light, and a third pixel that outputs a third light. For example, the first pixel may be a red pixel that outputs red light, the second pixel may be a green pixel that outputs green light, and the third pixel may be a blue pixel that outputs blue light. In this example, the s+5th data line DLs+5 may be connected to at least one of the first pixel, the second pixel, and the third pixel, and the s+6th data line DLs+6 may be connected to at least one of the first pixel, the second pixel, and the third pixel, but not to the same pixel as the s+5th data line DLs+5. For example, the s+5th data line DLs+5 may be connected to the first pixel and the third pixel, and the s+6th data line DLs+6 may be connected to the second pixel.

[0134] Since the s+5th data line DLs+5 includes only the 1Ath data line DLA1, and the s+6th data line DLs+6 includes the 1Bth data line DLB1 and the 2Bth data line DLB2, the wiring resistance of the s+5th data line DLs+5 may be different from the wiring resistance of the s+6th data line DLs+6. That is, the RC time constant of the s+5th data line DLs+5 may be different from the RC time constant of the s+6th data line DLs+6. However, the first pixel and the third pixel are connected to the s+5th data line DLs+5, and the second pixel is connected to the s+6th data line DLs+6. Therefore, the brightness of the pixel PX can be prevented from changing according to any difference in wiring resistance between the data lines DL.

[0135] Fig. 8A and Fig. 9The s+5th data line DLs+5 shown in the figure includes only the 1Ath data line DLA1, and the s+6th data line DLs+6 shown in the figure includes the 1Bth data line DLB1 and the 2Bth data line DLB2, but the present disclosure is not limited thereto. Alternatively, each odd-numbered data line may include the 1Ath data line DLA1, and each even-numbered data line may include the 1Bth data line DLB1 and the 2Bth data line DLB2.

[0136] In 8A and Fig. 9 In an embodiment, between a pair of adjacent data lines, the first data line includes only the 1A data line DLA1 located in the first data layer, and the second data line includes the 1B data line DLB1 and the 2B data line DLB2 located in the first data layer and the second data layer, respectively. In particular, in the wiring area LA, the second data line includes only the 2B data line DLB2. Therefore, in the wiring area LA, the first data line and the second data line do not require any bridge electrode. Therefore, the load of the first data line and the second data line can be prevented from increasing due to the presence of the bridge electrode. Moreover, any difference between the load of the first data line and the second data line passing through the wiring area LA and the load of the data line not passing through the wiring area LA can be minimized. Here, the first data line and the second data line can be the s+5th data line DLs+5 and the s+6th data line DLs+6, respectively.

[0137] Fig. 8A The 2B data line DLB2 is connected to the 1B data line DLB1 through a single first data contact hole DCT1, but the present disclosure is not limited thereto. Figure 8B , the 2B data line DLB2 may be connected to the 1B data line DLB1 through a plurality of first data contact holes (DCT1_1 and DCT1_2). In this case, at least one of the plurality of first data contact holes (DCT1_1 and DCT1_2) may be arranged to overlap at least one of the first gate electrode G1 of the first switching transistor ST1, the first active layer ACT1, the first source electrode S1, and the first drain electrode D1. Figure 8B It is shown that the “ 1_2 ”th data contact hole DCT1_2 among the first data contact holes ( DCT1_1 and DCT1_2 ) overlaps the first gate electrode G1 of the first switching transistor ST1 and the first active layer ACT1 .

[0138] Fig.10 is along Fig. 8A A cross-sectional view taken along line II-II'. Fig.11 is along Fig. 8A A cross-sectional view taken along line III-III'. Fig.12 is along Figure 7 A cross-sectional view taken along line IV-IV'. Fig.13 is along Figure 7 A cross-sectional view taken along line V-V'.

[0139] Reference 10 to Fig.13 The TFT layer TFTL and the light emitting element layer EML are formed on the first substrate SUB1. The TFT layer TFTL includes an active layer ACT, a first gate layer GTL1, a second gate layer GTL2, a first data metal layer DTL1, a second data metal layer DTL2, a gate insulating film 130, a first interlayer insulating film 141, a second interlayer insulating film 142, a third interlayer insulating film 143 and a planarizing film 160.

[0140] The buffer film BF may be formed on the first substrate SUB1. The buffer film BF may be formed on the first substrate SUB1 to protect the organic light emitting layer 172 of the TFT and the light emitting element layer EML from moisture that may penetrate into the TFT and the organic light emitting layer 172 through the first substrate SUB1. The buffer film BF may include a plurality of inorganic films alternately stacked. For example, the buffer film BF may be formed as a multilayer film in which at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer is alternately stacked. The buffer film BF may not be provided.

[0141] The active layer ACT may be formed on the first substrate SUB1 or the buffer film BF. The active layer ACT may include polycrystalline silicon, single crystal silicon, low temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor. A light shielding layer that blocks external light from being incident on the active layer ACT may be formed under the active layer ACT.

[0142] In the case where the active layer ACT is formed of polysilicon, the active layer ACT may have conductivity. The active layer ACT may include not only active layers (DT_ACT and ACT1 to ACT6) of the driving transistor DT and the first to sixth switching transistors ST1 to ST6, but also source electrodes (DT_S and S1 to S6) and drain electrodes (DT_G and D1 to D6) of the driving transistor DT and the first to sixth switching transistors ST1 to ST6.

[0143] The gate insulating film 130 may be formed on the active layer ACT. The gate insulating film 130 may be formed as an inorganic film such as, for example, a silicon nitride layer, a silicon nitride oxide layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0144] The first gate layer GTL1 may be formed on the gate insulating film 130. The first gate layer GTL1 may include gate electrodes (DT_G and G1 to G6) of the driving transistor DT and the first to sixth switching transistors ST1 to ST6, the scan line SL, the emission control line EL, the 1A scan line SLA1 and the 1B scan line SLB1 of the p+1 scan line SLp+1, and the 2A scan line SLA2 of the p+2 scan line SLp+2. The first gate layer GTL1 may be formed as a single layer or multilayer film including molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or alloys thereof.

[0145] The first interlayer insulating film 141 may be formed on the first gate layer GTL1. The first interlayer insulating film 141 may be formed as an inorganic film such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer insulating film 141 may include a plurality of inorganic films.

[0146] The second gate layer GTL2 may be formed on the first interlayer insulating film 141. The second gate layer GTL2 may include an initialization voltage line VIL, a second electrode CE2 of a capacitor, and a 2B scan line SLB2 of a p+2 scan line SLp+2. The second gate layer GTL2 may be formed as a single layer or multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

[0147] The second interlayer insulating film 142 may be formed on the second gate layer GTL2. The second interlayer insulating film 142 may be formed as an inorganic film such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer insulating film 142 may include a plurality of inorganic films.

[0148] The first data metal layer DTL1 may be formed on the second interlayer insulating film 142. The first data metal layer DTL1 may include a 1A data line DLA1 of an s+5th data line DLs+5, a 1B data line DLB1 of an s+6th data line DLs+6, a first power supply voltage line VDL, a first bridge electrode BE1, a second bridge electrode BE2, a third bridge electrode BE3, a first scan bridge electrode SBE1, and a second scan bridge electrode SBE2. The first data metal layer DTL1 may be formed as a single layer or a multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or alloys thereof.

[0149] The first bridge electrode BE1 may be connected to the driving gate electrode DT_G of the driving transistor DT through the first contact hole CNT1 penetrating the first interlayer insulating film 141 and the second interlayer insulating film 142. The 1A data line DLA1 of the s+5th data line DLs+5 may be connected to the sixth source electrode S6 of the sixth switch transistor ST6 through the third contact hole CNT3 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142. The third bridge electrode BE3 may be connected to the fourth drain electrode D4 of the fourth switch transistor ST4 through the sixth contact hole CNT6 penetrating the gate insulating film 130, the first interlayer insulating film 141, and the second interlayer insulating film 142.

[0150] The first scan bridge electrode SBE1 may be connected to the 1A scan line SLA1 through a first scan contact hole SCT1 penetrating the first and second interlayer insulating films 141 and 142. Also, the first scan bridge electrode SBE1 may be connected to the 1B scan line SLB1 through a second scan contact hole SCT2 penetrating the first and second interlayer insulating films 141 and 142.

[0151] The second scan bridge electrode SBE2 may be connected to the 2A scan line SLA2 through a third scan contact hole SCT3 penetrating the first and second interlayer insulating films 141 and 142 . Also, the second scan bridge electrode SBE2 may be connected to the 2B scan line SLB2 through a fourth scan contact hole SCT4 penetrating the second interlayer insulating film 142 .

[0152] The third interlayer insulating film 143 may be formed on the first data metal layer DTL1. The third interlayer insulating film 143 may be formed as an inorganic film, such as, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The third interlayer insulating film 143 may include a plurality of inorganic films. The third interlayer insulating film 143 may be thicker than the first interlayer insulating film 141 and the second interlayer insulating film 142.

[0153] The second data metal layer DTL2 may be formed on the third interlayer insulating film 143. The second data metal layer DTL2 may include the s+6th data line DLs+6, the 2B data line DLB2, and the fourth bridge electrode BE4. The second data metal layer DTL2 may be formed as a single layer or multilayer film including Mo, Al, Cr, Au, Ti, Ni, Nd, Cu, or an alloy thereof.

[0154] The 2B data line DLB2 of the s+6th data line DLs+6 may be connected to the 1B data line DLB1 through the first data contact hole DCT1 penetrating the third interlayer insulating film 143. The first data contact hole DCT1 may be arranged to overlap at least one of the first gate electrode G1, the first active layer ACT1, the first source electrode S1, and the first drain electrode D1 of the first switching transistor ST1. That is, the first data contact hole DCT1 of the 1B data line DLB1 and the second 2B data line DLB2 connected to the s+6th data line DLs+6 may be arranged to overlap at least one of the first gate electrode G1, the first active layer ACT1, the first source electrode S1, and the first drain electrode D1 of the first switching transistor ST1 of each pixel PX connected to the s+5th data line DLs+5 adjacent to the s+6th data line DLs+6.

[0155] The fourth bridge electrode BE4 may be connected to the third bridge electrode BE3 through a ninth contact hole CNT9 penetrating the third interlayer insulating film 143 .

[0156] The planarization film 160 may be formed to planarize a height difference formed by the active layer ACT, the first gate layer GTL1, the second gate layer GTL2, the first data metal layer DTL1, and the second data metal layer DTL2. The planarization film 160 may be formed as an organic film including acrylic resin, epoxy resin, phenolic resin, polyamide resin, or PI resin.

[0157] Fig.10 and Fig.11The driving transistor DT and the first, fourth, and sixth switching transistors ST1, ST4, and ST6 are illustrated as having a top gate structure in which the driving gate electrode DT_G and the first, fourth, and sixth gate electrodes G1, G4, and G6 are respectively located above the driving active layer DT_ACT and the first, fourth, and sixth active layers ACT1, ACT4, and ACT6, but the present disclosure is not limited thereto. Alternatively, the driving transistor DT and the first switching transistor ST1, the fourth switching transistor ST4 and the sixth switching transistor ST6 can be configured to have a bottom gate structure or a double gate structure, in which the driving gate electrode DT_G and the first gate electrode G1, the fourth gate electrode G4 and the sixth gate electrode G6 are respectively located below the driving active layer DT_ACT and the first active layer ACT1, the fourth active layer ACT4 and the sixth active layer ACT6, and in the double gate structure, the driving gate electrode DT_G and the first gate electrode G1, the fourth gate electrode G4 and the sixth gate electrode G6 are not only respectively located above the driving active layer DT_ACT and the first active layer ACT1, the fourth active layer ACT4 and the sixth active layer ACT6, but also located below the driving active layer DT_ACT and the first active layer ACT1, the fourth active layer ACT4 and the sixth active layer ACT6.

[0158] The second switching transistor ST2, the third switching transistor ST3 and the fifth switching transistor ST5 are connected to Fig.10 and Fig.11 The first switching transistor ST1 , the fourth switching transistor ST4 , and the sixth switching transistor ST6 are substantially the same, and thus, a detailed description thereof will be omitted.

[0159] A light emitting element layer EML may be formed on the TFT layer TFTL. The light emitting element layer EML includes a light emitting element 170 and a pixel defining film 180.

[0160] The light emitting element 170 and the pixel defining film 180 are formed on the planarization film 160. The light emitting element 170 may include a first electrode 171, an organic light emitting layer 172, and a second electrode 173.

[0161] The first electrode 171 may be formed on the planarization film 160. The first electrode 171 may be connected to the fourth bridge electrode BE4 via a contact hole AND_CNT penetrating the planarization film 160.

[0162] In the case where the light-emitting element 170 has a top emission structure and emits light in a direction from the organic light-emitting layer 172 to the second electrode 173, the first electrode 171 can be formed of a metal material with high reflectivity, such as a stack of Al and Ti (e.g., Ti / Al / Ti), a stack of Al and ITO (e.g., ITO / Al / ITO), a silver (Ag)-palladium (Pd)-copper (Cu) (APC) alloy, or a stack of an APC alloy and ITO (e.g., ITO / APC / ITO).

[0163] The pixel defining film 180 may be formed to define the first electrode 171 on the planarization film 160 and thus define the light emitting region of each of the pixels PX. The pixel defining film 180 may be formed to cover the edge of each of the first electrodes 171. The pixel defining film 180 may be formed as an organic film including acrylic resin, epoxy resin, phenolic resin, polyamide resin, or PI resin.

[0164] The light emitting region of each of the pixels PX may be defined as a region in which the first electrode 171, the organic light emitting layer 172, and the second electrode 173 are sequentially stacked so that holes from the first electrode 171 and electrons from the second electrode 173 may be combined together in the organic light emitting layer 172 to emit light. Each of the pixels PX may include a red sub-pixel that emits red light, a green sub-pixel that emits green light, and a blue sub-pixel that emits blue light.

[0165] The organic light emitting layer 172 is formed on the first electrode 171 and on the pixel defining film 180. The organic light emitting layer 172 may include an organic material and may therefore emit light of a predetermined color. For example, the organic light emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer. In this example, the organic light emitting layer 172 of the red sub-pixel of each pixel PX in the pixel PX may emit red light, the organic light emitting layer 172 of the green sub-pixel of each pixel PX in the pixel PX may emit green light, and the organic light emitting layer 172 of the blue sub-pixel of each pixel PX in the pixel PX may emit blue light. In another example, the organic light emitting layer 172 of each pixel PX in the pixel PX may emit white light, in which case the red sub-pixel, the green sub-pixel, and the blue sub-pixel of each pixel PX in the pixel PX may overlap with the red color filter layer, the green color filter layer, and the blue color filter layer, respectively.

[0166] The second electrode 173 is formed on the organic light emitting layer 172 and the pixel defining film. The second electrode 173 may be formed to cover the organic light emitting layer 172. The second electrode 173 may be a common layer formed in common for all pixels PX. A capping layer may be formed on the second electrode 173.

[0167] In the case where the light emitting element 170 has a top emission structure, the second electrode 173 may be formed of a transparent metal material through which light can be transmitted, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a translucent metal material, such as an alloy of magnesium (Mg) and Ag. When the second electrode 173 is formed of a translucent metal material, the emission efficiency of the light emitting element 170 may be improved due to the microcavity.

[0168] The second substrate SUB2 is located on the light emitting element layer EML. The space between the light emitting element layer EML and the second substrate SUB2 may be vacuum filled. Alternatively, a filling film may be located between the light emitting element layer EML and the second substrate SUB2, in which case the filling film may be an epoxy filling film or a silicon filling film. Also alternatively, an encapsulation film may be formed between the light emitting element layer EML and the second substrate SUB2. The encapsulation film may include at least one inorganic film to prevent oxygen or moisture from penetrating into the light emitting element layer EML, or may include at least one organic film to protect the light emitting element layer EML from foreign matter such as dust.

[0169] Fig.14 It is a graphic Figure 7 FIG. 1 is a plan view of another example of region C1. Fig.15 It is a graphic Fig.14 A plan view of a first data metal layer and a second data metal layer.

[0170] Fig.14 and Fig.15 Examples and Fig. 8A and Fig. 9 The difference of the embodiment is that the s+5th data line DLs+5 includes not only the 1A data line DLA1 but also the 2A data line DLA2. Fig. 8A and Fig. 9 The different embodiments are described Fig.14 and Fig.15 Embodiment of the invention.

[0171] refer to Fig.14 and Fig.15 , the s+5th data line DLs+5 includes the 1A data line DLA1 and the 2A data line DLA2, and the s+6th data line DLs+6 adjacent to the s+5th data line DLs+5 includes the 1B data line DLB1 and the 2B data line DLB2. The 2A data line DLA2 may be connected to the 1A data line DLA1 through the second data contact hole DCT2. The 2B data line DLB2 may be connected to the 1B data line DLB1 through the first data contact hole DCT1.

[0172] 1A data line DLA1, 1B data line DLB1, first power supply voltage line VDL, first bridge electrode BE1, second bridge electrode BE2 and third bridge electrode BE3 may be formed as a first data layer. On the other hand, 2A data line DLA2, 2B data line DLB2 and fourth bridge electrode BE4 may be formed as a second data layer.

[0173] The s+5th data line DLs+5 includes both the 1A data line DLA1 and the 2A data line DLA2 in the pixel area PXA, but only includes the 1A data line DLA1 in the wiring area LA. The s+6th data line DLs+6 includes the 1B data line DLB1 and the 2B data line DLB2 in the pixel area PXA, but only includes the 2B data line DLB2 in the wiring area LA. In order to minimize the size of the wiring area LA, in the wiring area LA, the distance between the s+5th data line DLs+5 and the s+6th data line DLs+6 may be set to be smaller than in the pixel area PXA. Moreover, in the wiring area LA, the s+5th data line DLs+5 and the s+6th data line DLs+6 may be arranged to overlap each other.

[0174] Since the s+5th data line DLs+5 includes the 1A data line DLA1 and the 2A data line DLA2, and the s+6th data line DLs+6 includes the 1B data line DLB1 and the 2B data line DLB2, any difference in wiring resistance between the s+5th data line DLs+5 and the s+6th data line DLs+6 can be minimized. That is, any difference in RC time constant between the s+5th data line DLs+5 and the s+6th data line DLs+6 can be minimized.

[0175] Fig.14 and Fig.15 The s+5th data line DLs+5 is shown to include both the 1A data line DLA1 and the 2A data line DLA2, and the s+6th data line DLs+6 is shown to include both the 1B data line DLB1 and the 2B data line DLB2, but the present disclosure is not limited thereto. Alternatively, each odd-numbered data line may include the 1A data line DLA1 and the 2A data line DLA2, and each even-numbered data line may include both the 1B data line DLB1 and the 2B data line DLB2.

[0176] at 14 and Fig.15In an embodiment of the present invention, between a pair of adjacent data lines, the first data line includes both the 1A data line DLA1 and the 2A data line DLA2 located in the first data layer and the second data layer, respectively, and the second data line includes both the 1B data line DLB1 and the 2B data line DLB2 located in the second data layer. Specifically, in the wiring area LA, the first data line includes only the 1A data line DLA1, and the second data line includes only the 2B data line DLB2. Therefore, in the wiring area LA, the first data line and the second data line do not require any bridge electrode. Therefore, the load of the first data line and the second data line can be prevented from increasing due to the presence of the bridge electrode. Moreover, any difference between the load of the first data line and the second data line passing through the wiring area LA and the load of the data line not passing through the wiring area LA can be minimized. Here, the first data line and the second data line can be the s+5th data line DLs+5 and the s+6th data line DLs+6, respectively.

[0177] Fig.14 The 2B data line DLB2 is shown connected to the 1B data line DLB1 through a single first data contact hole DCT1, and the 2A data line DLA2 is shown connected to the 1A data line DLA1 through a single second data contact hole DCT2, but the present disclosure is not limited thereto. Alternatively, as Figure 8B , the 2B data line DLB2 may be connected to the 1B data line DLB1 through a plurality of first data contact holes (DCT1_1 and DCT1_2). Similarly, the 2A data line DLA2 may be connected to the 1A data line DLA1 through a plurality of second data contact holes DCT2. In this case, at least one of the plurality of first data contact holes (DCT1_1 and DCT1_2) may be arranged to overlap at least one of the first gate electrode G1, the first active layer ACT1, the first source electrode S1, and the first drain electrode D1 of the first switching transistor ST1, and at least one of the plurality of second data contact holes DCT2 may also be arranged to overlap at least one of the first gate electrode G1, the first active layer ACT1, the first source electrode S1, and the first drain electrode D1 of the first switching transistor ST1.

[0178] Fig.16 It is a graphic Figure 7 FIG. 1 is a plan view of another example of region C1. Fig.17 It is a graphic Fig.16 A plan view of a first data metal layer and a second data metal layer.

[0179] Fig.16 and Fig.17 Examples and Fig. 8A and Fig. 9The difference of the embodiment is that the s+6th data line DLs+6 only includes the 2B data line DLB2. Fig. 8A and Fig. 9 The different embodiments are described Fig.16 and Fig.17 Embodiment of the invention.

[0180] refer to Fig.16 and Fig.17 , the s+5th data line DLs+5 includes only the 1A data line DLA1, and the s+6th data line DLs+6 adjacent to the s+5th data line DLs+5 includes only the 2B data line DLB2. In this case, the 2B data line DLB2 may be connected to the first data bridge electrode BE5 through the third data contact hole DCT3, and the first data bridge electrode BE5 may be connected to the sixth source electrode S6 of the sixth switching transistor ST6 through the third contact hole CNT3'.

[0181] The 1A data line DLA1, the first power supply voltage line VDL, the first bridge electrode BE1, the second bridge electrode BE2, the third bridge electrode BE3 and the first data bridge electrode BE5 may be formed as a first data layer. On the other hand, the 2B data line DLB2 and the fourth bridge electrode BE4 may be formed as a second data layer located in a layer different from the first data layer.

[0182] The s+5th data line DLs+5 includes only the 1Ath data line DLA1 in both the pixel area PXA and the wiring area LA. The s+6th data line DLs+6 includes only the 2Bth data line DLB2 in both the pixel area PXA and the wiring area LA. In order to minimize the size of the wiring area LA, in the wiring area LA, the distance between the s+5th data line DLs+5 and the s+6th data line DLs+6 may be set to be smaller than in the pixel area PXA. Moreover, in the wiring area LA, the s+5th data line DLs+5 and the s+6th data line DLs+6 may be arranged to overlap each other.

[0183] Since the s+5th data line DLs+5 includes the 1A data line DLA1 and the s+6th data line DLs+6 includes the 2B data line DLB2, any difference in wiring resistance between the s+5th data line DLs+5 and the s+6th data line DLs+6 can be minimized. That is, any difference in RC time constant between the s+5th data line DLs+5 and the s+6th data line DLs+6 can be minimized.

[0184] Fig.16 and Fig.17The s+5th data line DLs+5 includes the 1Ath data line DLA1, and the s+6th data line DLs+6 includes the 2Bth data line DLB2, but the present disclosure is not limited thereto. Alternatively, each odd-numbered data line may include the 1Ath data line DLA1, and each even-numbered data line may include the 2Bth data line DLB2.

[0185] exist Fig.16 and Fig.17 In an embodiment, between a pair of adjacent data lines, the first data line includes a 1A data line DLA1 located in the first data layer, and the second data line includes a 2B data line DLB2 located in the second data layer. Therefore, in the wiring area LA, the first data line and the second data line do not require any bridge electrode. Therefore, the load of the first data line and the second data line can be prevented from increasing due to the presence of the bridge electrode. Moreover, any difference between the load of the first data line and the second data line passing through the wiring area LA and the load of the data line not passing through the wiring area LA can be minimized. Here, the first data line and the second data line can be the s+5th data line DLs+5 and the s+6th data line DLs+6, respectively.

[0186] Fig.16 The first data bridge electrode BE5 is shown to be connected to the 2B data line DLB2 through a single third data contact hole DCT3, but the present disclosure is not limited thereto. Alternatively, the first data bridge electrode BE5 may be connected to the 2B data line DLB2 through a plurality of third data contact holes DCT3. In this case, at least one third data contact hole DCT3 of the plurality of third data contact holes DCT3 may be arranged to overlap at least one of the first gate electrode G1 of the first switching transistor ST1, the first active layer ACT1, the first source electrode S1, and the first drain electrode D1.

[0187] Fig.18 It is a graphic Figure 7 FIG. 1 is a plan view of another example of region C1. Fig.19 It is a graphic Fig.18 A plan view of a first data metal layer and a second data metal layer.

[0188] Fig.18 and Fig.19 Examples and Fig. 8A and Fig. 9 The difference of the embodiment is that the s+5th data line DLs+5 includes only the 2A data line DLA2 in the pixel area PXA and only the 1A data line DLA1 in the wiring area LA, and the s+6th data line DLs+6 includes only the 2B data line DLB2. Fig. 8A and Fig. 9 The different embodiments are described Fig.18 and Fig.19 Embodiment of the invention.

[0189] refer to Fig.18 and Fig.19 , the s+5th data line DLs+5 may include the 2A data line DLA2 in the pixel area PXA. In this case, in each pixel PX adjacent to the wiring area LA, the 2A data line DLA2 may be connected to the 1A data line DLA1 via the second data contact hole DCT2. On the other hand, in each pixel PX not adjacent to the wiring area LA, the 2A data line DLA2 may be connected to the second data bridge electrode via the second data contact hole DCT2. The second data bridge electrode may be formed to be substantially the same as the first data bridge electrode BE5. The second data bridge electrode or the 1A data line DLA1 may be connected to the sixth source electrode S6 of the sixth switching transistor ST6 through the third contact hole CNT3".

[0190] The s+6th data line DLs+6 adjacent to the s+5th data line DLs+5 includes only the 2B data line DLB2. In this case, the 2B data line DLB2 may be connected to the first data bridge electrode BE5 through the third data contact hole DCT3, and the first data bridge electrode BE5 may be connected to the sixth source electrode S6 of the sixth switching transistor ST6 through the third contact hole CNT3'.

[0191] The 1A data line DLA1, the first power supply voltage line VDL, the first bridge electrode BE1, the second bridge electrode BE2, the third bridge electrode BE3, the first data bridge electrode BE5, and the second data bridge electrode may be formed as a first data layer. On the other hand, the 2A data line DLA2, the 2B data line DLB2, and the fourth bridge electrode BE4 may be formed as a second data layer located in a layer different from the first data layer.

[0192] The s+5th data line DLs+5 includes only the 2Ath data line DLA2 in the pixel area PXA and only the 1Ath data line DLA1 in the wiring area LA. The s+6th data line DLs+6 includes only the 2Bth data line DLB2 in both the pixel area PXA and the wiring area LA. In order to minimize the size of the wiring area LA, in the wiring area LA, the distance between the s+5th data line DLs+5 and the s+6th data line DLs+6 may be set to be smaller than in the pixel area PXA. Moreover, in the wiring area LA, the s+5th data line DLs+5 and the s+6th data line DLs+6 may be arranged to overlap each other.

[0193] Since the s+5th data line DLs+5 includes the 2Ath data line DLA2 in the pixel area PXA and the 1Ath data line DLA1 in the wiring area LA, and the s+6th data line DLs+6 includes the 2Bth data line DLB2 in both the pixel area PXA and the wiring area LA, any difference in wiring resistance between the s+5th data line DLs+5 and the s+6th data line DLs+6 can be minimized. That is, any difference in RC time constant between the s+5th data line DLs+5 and the s+6th data line DLs+6 can be minimized.

[0194] Fig.18 and Fig.19 The s+5th data line DLs+5 shown in the figure includes the 2A data line DLA2 in the pixel area PXA and the 1A data line DLA1 in the wiring area LA, and the s+6th data line DLs+6 shown in the figure includes the 2B data line DLB2 in both the pixel area PXA and the wiring area LA, but the present disclosure is not limited thereto. Alternatively, each odd-numbered data line may include the 2A data line DLA2 in the pixel area PXA and the 1A data line DLA1 in the wiring area LA, and each even-numbered data line may include the 2B data line DLB2 in both the pixel area PXA and the wiring area LA.

[0195] exist Fig.18 and Fig.19 In an embodiment of the present invention, between a pair of adjacent data lines, the first data line includes a 2A data line DLA2 located in the second data layer in the pixel area PXA, and includes a 1A data line DLA1 located in the first data layer in the wiring area LA, and the second data line includes a 2B data line DLB2 located in the second data layer. Specifically, in the wiring area LA, the first data line includes only the 1A data line DLA1, and the second data line includes only the 2B data line DLB2. Therefore, in the wiring area LA, the first data line and the second data line do not require any bridge electrode. Therefore, the load of the first data line and the second data line can be prevented from increasing due to the presence of the bridge electrode. Moreover, any difference between the load of the first data line and the second data line passing through the wiring area LA and the load of the data line not passing through the wiring area LA can be minimized. Here, the first data line and the second data line can be the s+5th data line DLs+5 and the s+6th data line DLs+6, respectively.

[0196] Fig.18The first data bridge electrode BE5 is shown to be connected to the 2B data line DLB2 through a single third data contact hole DCT3, and the 2A data line DLA2 or the second data bridge electrode is shown to be connected to the 1A data line DLA1 through a single second data contact hole DCT2, but the present disclosure is not limited thereto. Alternatively, the first data bridge electrode BE5 may be connected to the 2B data line DLB2 through a plurality of third data contact holes DCT3. Similarly, the 2A data line DLA2 or the second data bridge electrode may be connected to the 1A data line DLA1 through a plurality of second data contact holes DCT2. In this case, at least one third data contact hole DCT3 among the plurality of third data contact holes DCT3 may be arranged to overlap at least one of the first gate electrode G1, the first active layer ACT1, the first source electrode S1, and the first drain electrode D1 of the first switching transistor ST1, and at least one second data contact hole DCT2 among the plurality of second data contact holes DCT2 may also be arranged to overlap at least one of the first gate electrode G1, the first active layer ACT1, the first source electrode S1, and the first drain electrode D1 of the first switching transistor ST1.

[0197] Although embodiments are described above, it is not intended that these embodiments describe all possible forms of the inventive concept of the present disclosure. On the contrary, the words used in the specification are descriptive rather than restrictive words, and it is understood that various changes can be made without departing from the spirit and scope of the inventive concept of the present disclosure. In addition, the features of various implementation embodiments can be combined to form further embodiments of the present disclosure. Therefore, embodiments according to the present invention are limited by the attached claims and their equivalents.

Claims

1. A display device, comprising: a first substrate having a first through hole region defined on the first substrate in which a first through hole is formed, a first wiring region surrounding the first through hole region, and a pixel region in which pixels are arranged around the first wiring region; as well as A first data line and a second data line are adjacent to each other on the first substrate, The first data line includes a first sub-data line (DLA1) in the first wiring area and the pixel area and a second sub-data line (DLA2) in the pixel area, and The first sub-data line is disposed on the second sub-data line, and an interlayer insulating film is interposed between the first sub-data line and the second sub-data line. 2 . The display device according to claim 1 , wherein in the pixel region and the first wiring region, the second data line and the second sub-data line are disposed on the same layer.

3. The display device according to claim 1, wherein the first sub-data line (DLA1) is connected to the first transistor of the first pixel among the pixels through a first contact hole (CNT3”), and the second sub-data line (DLA2) is connected to the first sub-data line (DLA1) through a second contact hole (DCT2).

4. The display device according to claim 3, wherein the second contact hole (DCT2) is larger than the first contact hole (CNT3").

5. The display device according to claim 1, further comprising: a first bridge electrode (BE5) connected to a first transistor of a second pixel adjacent to the first pixel in a first direction among the pixels through a third contact hole (CNT3'), The second data line is connected to the first bridge electrode through a fourth contact hole (DCT3).

6. The display device according to claim 5, wherein: The first data line and the second data line extend in the pixel area in a second direction perpendicular to the first direction.

7. The display device according to claim 5, wherein the fourth contact hole (DCT3) is larger than the third contact hole (CNT3').

8. The display device according to claim 5, wherein each of the first pixel and the second pixel further comprises: An organic light emitting diode, comprising a first electrode, a second electrode and an organic light emitting layer between the first electrode and the second electrode; a driving transistor configured to provide a driving current to the organic light emitting diode, and The second switch transistor is between the gate electrode and the drain electrode of the driving transistor.

9. The display device according to claim 8, wherein each of the first pixel and the second pixel further comprises: a second bridge electrode connected to a second switching transistor, and The first data line and the second bridge electrode are arranged on the same layer. 10 . The display device of claim 8 , wherein the first data line overlaps at least one of a gate electrode, an active layer, a source electrode, and a drain electrode of the second switching transistor.

11. The display device according to claim 8, wherein the pixel further comprises: a third switch transistor, between the drain electrode of the driving transistor and the first electrode of the organic light emitting diode; a third bridge electrode connected to the drain electrode of the fourth switch transistor through a third contact hole; and The fourth bridge electrode is connected to the third bridge electrode through a fourth contact hole. 12 . The display device according to claim 11 , wherein the first data line and the third bridge electrode are disposed on a same layer, and the second data line and the fourth bridge electrode are disposed on another same layer.

13. The display device according to claim 1, wherein: A second through hole region having a second through hole formed therein and a second wiring region surrounding the second through hole region are further defined on the first substrate, The pixel region surrounds the second wiring region, The display device further includes a third data line and a fourth data line adjacent to each other on the first substrate, and The third data line includes a third sub-data line (DLA1) in the first wiring area and the pixel area and a fourth sub-data line (DLA2) in the pixel area, and The fourth sub-data line is disposed on the third sub-data line, and the interlayer insulating film is disposed between the fourth sub-data line and the third sub-data line. 14 . The display device according to claim 8 , wherein in the pixel region and the first wiring region, the fourth data line and the fourth sub-data line are disposed on the same layer.

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