Data writing method and device of memory

Abstract

The invention discloses a data writing method and device of a memory, and belongs to the technical field of memories. The method comprises the following steps: the memory receives a write instruction of a controller indicating to write data with a specified length into the memory; the memory writes data of a specified length to a storage medium of the memory based on a write instruction. As the writing instruction can specify the length of the data to be written, when the data with the specified length needs to be written, the number of the writing instructions needing to be sent can be reduced, and the overhead of the writing instructions is reduced.

Description

[0001] This application is a divisional application. The application number of the original application is 202210191660.7, and the original application date is February 28, 2022. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a method and device for writing data into a storage device. Background Art

[0003] In the field of storage technology, when a controller writes data to a storage medium of a memory, the controller needs to send a write instruction and the data to be written to the memory to instruct the writing of the data to be written to the storage medium of the memory.

[0004] Generally, the write instructions sent by the controller to the same memory can indicate that the length of the data to be written is the same and is a fixed value.

[0005] However, when the same data (such as 0 or 1) needs to be written continuously, if the total length of the data is greater than the length of the data to be written that can be written by one write instruction, the controller needs to send multiple write instructions and data, resulting in a large overhead for writing data. Summary of the invention

[0006] The present application provides a method and device for writing data into a memory. The present application reduces the overhead of write instructions. The technical solution provided by the present application is as follows:

[0007] In a first aspect, the present application provides a method for writing data to a memory, the method comprising: the memory receives a write instruction from a controller instructing to write data of a specified length to the memory; the memory writes the data of the specified length to a storage medium of the memory based on the write instruction.

[0008] In the data writing method of the memory provided in the present application, the memory receives a write instruction from a controller to write data of a specified length to the memory, and the memory writes data of the specified length to the storage medium of the memory based on the write instruction. Since the write instruction can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write instructions that need to be sent can be reduced, thereby reducing the overhead of the write instruction. In addition, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened, and the saved time can be used to write other data, thereby reducing the write latency of the memory and effectively improving the write bandwidth of the memory.

[0009] In one possible implementation, since the memory includes multiple storage arrays, the data access processes between the multiple storage arrays do not affect each other, and writing data to the storage array is achieved by controlling the bit lines and word lines of the storage array. In addition, each bit line corresponds to an address range, different bit lines correspond to different address ranges, and the addresses corresponding to multiple bit lines connected to the same storage array constitute a segment of addresses within the address range of the storage array. Each word line corresponds to an address range, different word lines correspond to different address ranges, and the addresses corresponding to multiple word lines connected to the same storage array constitute a segment of addresses within the address range of the storage array. In addition, each storage array corresponds to an address range, different storage arrays correspond to different address ranges, and the addresses corresponding to multiple storage arrays in the same storage constitute a segment of addresses within the address range of the memory. Therefore, the specified length is reflected by any one or more of the following: the total number of bit lines with consecutive addresses that need to be controlled to write data based on a write instruction, the total number of word lines with consecutive addresses that need to be controlled to write data based on a write instruction, and the total number of storage arrays with consecutive addresses to which data is written based on a write instruction.

[0010] In one possible implementation, the bit lines with consecutive addresses may be a plurality of bit lines to which electrical signals are sequentially applied when the memory is subjected to a bit line scan. Typically, the plurality of bit lines with consecutive addresses are sequentially deployed on the memory array. Similarly, the word lines with consecutive addresses may be a plurality of word lines to which electrical signals are sequentially applied when the memory is subjected to a word line scan. And the plurality of word lines with consecutive addresses are typically sequentially deployed on the memory array. The memory arrays with consecutive addresses may be a plurality of memory arrays to which data is sequentially written when data needs to be sequentially written to the plurality of memory arrays in the memory. And the plurality of memory arrays with consecutive addresses are typically sequentially deployed on the memory.

[0011] In a possible implementation scenario, the write instruction further indicates that the current value of the current signal used to execute the write operation indicated by the write instruction is less than a reference value, and the reference value is the current value of the current signal used to execute the write operation indicated by the write instruction that does not indicate a current value.

[0012] By indicating through a write instruction that the current value of the current signal used to perform the write operation is less than the reference value, the power consumption of the write operation can be reduced. In addition, since the power consumption of the write operation is low, for a memory including multiple storage arrays, the controller can concurrently access instructions to multiple storage arrays of the memory according to the power consumption of the memory, so as to flexibly allocate bandwidth and power consumption among the multiple storage arrays, thereby meeting more application requirements.

[0013] In another possible implementation scenario, the write instruction further indicates that data of a specified length is allowed to be written in one or more time periods according to the power consumption of the memory.

[0014] When the write instruction indicates that data of a specified length can be written in multiple time periods according to the power consumption of the memory, the memory can choose to write part of the data of the specified length in each of the multiple time periods according to the overall power consumption of the memory, so as to achieve the purpose of reducing the overall power consumption of the memory.

[0015] In another possible implementation scenario, the write instruction further indicates: for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored in the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

[0016] When the data stored in the storage address is the same as the data indicated by the write instruction to be written to the storage address, by not performing a write operation on the storage address, the operation time of the write operation indicated by the write instruction can be effectively reduced, thereby achieving fast writing to the memory, and shortening the instruction interval corresponding to the write instruction, so that other data can be written using the saved time, thereby reducing the write latency of the memory and improving the write bandwidth of the memory.

[0017] Furthermore, the data of the specified length may include multiple identical data. For example, when the data is represented by binary values, the data of the specified length is data consisting of multiple binary values ​​1, or the data of the specified length is data consisting of multiple binary values ​​0.

[0018] At this time, by specifying the length in the write instruction, it is possible to send one write instruction to indicate the writing of data of the specified length. Compared with the write instructions in the related art that indicate the same and fixed length of the data to be written, there is no need to send multiple write instructions to indicate writing, thereby reducing the number of write instructions that need to be sent.

[0019] In a second aspect, the present application provides a data writing device for a memory, the data writing device comprising: a receiving module for receiving a write instruction from a controller instructing to write data of a specified length to the memory; and an access module for writing data of a specified length to a storage medium of the memory based on the write instruction.

[0020] Optionally, the memory includes multiple storage arrays, and data access processes between the multiple storage arrays do not affect each other. Writing data to the storage array is achieved by controlling the bit lines and word lines connected to the storage array, and the specified length is reflected by any one or more of the following: the total number of address-contiguous bit lines that need to be controlled to write data based on a write instruction, the total number of address-contiguous word lines that need to be controlled to write data based on a write instruction, and the total number of address-contiguous storage arrays to which data is written based on a write instruction.

[0021] Optionally, the write instruction further indicates that the current value of the current signal used to perform the write operation indicated by the write instruction is smaller than a reference value, and the reference value is the current value of the current signal used to perform the write operation indicated by the write instruction without indicating the current value.

[0022] Optionally, the write instruction further indicates that data of a specified length is allowed to be written in one or more time periods according to power consumption of the memory.

[0023] Optionally, the write instruction also indicates: for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data the write instruction indicates to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored in the storage address is the same as the data the write instruction indicates to be written to the storage address, no write operation is performed on the storage address.

[0024] Optionally, the data of the specified length is data consisting of multiple binary values ​​1, or the data of the specified length is data consisting of multiple binary values ​​0.

[0025] In a third aspect, the present application provides a computer device including a memory and a processor, wherein the memory stores program instructions, and the processor runs the program instructions to execute the method provided in the first aspect of the present application and any possible implementation thereof.

[0026] In a fourth aspect, the present application provides a computer-readable storage medium, which is a non-volatile computer-readable storage medium, and the computer-readable storage medium includes program instructions. When the program instructions are executed on a computer device, the computer device executes the method provided in the first aspect of the present application and any possible implementation thereof.

[0027] In a fifth aspect, the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method provided in the first aspect of the present application and any possible implementation thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a schematic diagram of an application scenario involved in a method for writing data into a memory provided in an embodiment of the present application;

[0029] Figure 2 It is a schematic diagram of transmitting a write instruction and data to be written provided by an embodiment of the present application;

[0030] Figure 3 It is a schematic diagram of another method of transmitting a write instruction and data to be written provided in an embodiment of the present application;

[0031] Figure 4 is a schematic diagram of the structure of a memory provided by an embodiment of the present application;

[0032] Figure 5 is a structural diagram of a storage component provided in an embodiment of the present application;

[0033] Figure 6 is a schematic diagram of a storage array provided in an embodiment of the present application;

[0034] Figure 7 is a flow chart of a method for writing data into a memory provided by an embodiment of the present application;

[0035] Figure 8 It is a structural schematic diagram of a data writing device for a memory provided in an embodiment of the present application;

[0036] Fig. 9 It is a structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0038] At present, in the field of storage technology, when a controller writes data to a storage medium of a memory, the controller needs to send a write instruction and data to be written to the memory to indicate that the data to be written is written to the storage medium of the memory. In addition, the length of the data to be written that can be indicated by the write instruction sent by the controller to the same memory is the same and is a fixed value. Therefore, when the same data (for example, 0 or 1) needs to be written continuously, if the total length of the data is greater than the length of the data to be written that can be written by a write instruction, the controller needs to send multiple write instructions and data, resulting in a large overhead for writing data. In addition, since the improvement of the memory write bandwidth (especially the write bandwidth of the same storage array that is continuously written) is restricted by the instruction interval (time write to write, tW2W), when a large number of instructions need to be sent, the execution interval that needs to be waited is long, resulting in the write bandwidth of the memory being affected. Among them, the memory includes one or more storage arrays (banks), and the data access processes between the multiple storage arrays do not affect each other.

[0039] An embodiment of the present application provides a method for writing data to a memory. The method includes: the memory receives a write instruction from a controller indicating that data of a specified length is written to the memory, and the memory writes data of the specified length to a storage medium of the memory based on the write instruction. Since the write instruction can specify the length of the data to be written, when data of a specified length needs to be written, the number of write instructions that need to be sent can be reduced, thereby reducing the overhead of the write instruction. In addition, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened, and the saved time can be used to write other data, thereby reducing the write latency of the memory and effectively improving the write bandwidth of the memory.

[0040] Figure 1 Schematic diagram of the structure of the implementation environment involved in the method for writing data into the memory provided in the embodiment of the present application. Figure 1 As shown, the implementation environment includes: a processor 01 and a storage system 02. Optionally, the storage system 02 can be a storage chip. In addition, the storage system 02 includes a controller 021 and a memory 022. A communication connection is established between the processor 01 and the controller 021, and a communication connection is established between the controller 021 and the memory 022. The processor 01 is used to indicate a write requirement to the controller 021, that is, to notify the controller 021 of the logical address of the data to be written that needs to be written. The controller 021 is used to determine the physical address for writing the data to be written according to the instruction of the processor 01, and send a write instruction to the memory 022 according to the physical address and the data to be written. The memory 022 is used to write the data to be written to the corresponding physical address according to the write instruction.

[0041] Optionally, the processor 01 may be a hardware chip, which may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. Alternatively, the processor 01 may be a general-purpose processor, such as a central processing unit (CPU), a network processor (NP), or a combination of a CPU and a NP.

[0042] The memory 022 may be a non-volatile memory (NVM) such as a phase change memory (PCM), a spin transfer torque memory (shared transistor technology random access memory, STT-RAM), or a resistive random-access memory (RRAM). The embodiment of the present application is described by taking the memory 022 as a phase change memory as an example. Phase change memory is a new type of non-volatile semiconductor memory based on sulfur compounds. The memory 022 includes a plurality of memory cells. The storage medium of each memory cell is implemented by a phase change material, which utilizes the difference in electrical properties between the crystalline and amorphous states of the phase change material to store 0 / 1 bit information. Among them, the high-resistance amorphous state is defined as a write 0 state (i.e., RESET (0) state), and the low-resistance crystalline state is defined as a write 1 state (i.e., SET (1) state, also called erase 1 state). The write 0 state is obtained by performing a write operation on the memory cell. The write operation is achieved by applying a high-amplitude and narrow-width electrical pulse to the memory cell. Under the action of this electric pulse, the temperature of the phase change material is rapidly raised to above the melting temperature and then suddenly cooled. Since the microscopic atoms of the phase change material do not have sufficient time to crystallize in this process, the phase change material remains in a high-resistance amorphous state. The erase state is obtained by performing an erase operation on the storage unit. The erase operation is achieved by applying an electric pulse with a lower amplitude than the electric pulse of the write operation but a relatively long duration to the storage unit. Under the action of this electric pulse, the temperature of the phase change material is raised to above the crystallization temperature and below the melting temperature, and the phase change material can be transformed into a low-resistance state through a thermal crystallization process in this process. The read operation of the phase change memory 022 is achieved by applying an electric pulse with a lower amplitude than the electric pulse of the write operation and the electric pulse of the erase operation to the storage unit. Under the action of this electric pulse, the resistance information of the phase change material is sensed by the read circuit in the form of current or voltage, thereby realizing the read operation of the storage unit. Among them, since both the write operation and the erase operation write data to the storage unit, the write operation in the embodiment of the present application does not distinguish between a write operation and an erase operation.

[0043] In an embodiment of the present application, the memory 022 can be used as a memory for temporarily storing data required for the operation of the processor 01. Correspondingly, the controller 021 can be a memory controller. And an application scenario of the data writing method of the memory 022 provided in the embodiment of the present application can be: the processor 01 generates operation data during operation, and the operation data needs to be stored in the memory. In this application scenario, the collaborative process between the processor 01, the controller 021 and the memory includes: the processor 01 indicates to the controller 021 that the operation data needs to be stored, the controller 021 obtains the operation data, and determines the storage address for storing the operation data in the storage space of the memory, and then sends a write instruction and operation data to the memory according to the operation data and the storage address, and the memory stores the operation data at the corresponding storage address according to the write instruction.

[0044] Among them, the write instruction and the data to be written can be sent through different ports. For example, when it is necessary to send a write instruction and operation data to the memory, such as Figure 2 and Figure 3 As shown, port 1 can be used to send a write instruction to the memory, and port 2 can be used to send operation data to the memory. In addition, the write instruction can include the write instruction itself for indicating the write operation and the storage address for storing the data to be written. In an implementable manner, the write instruction itself and the storage address can be sent to the memory through the same port. For example, Figure 2 As shown, the write instruction itself and the storage address can be sent to the memory using port 1. Alternatively, the write instruction itself and the storage address can be sent to the memory via different ports. For example, Figure 3 As shown, port 1 can be used to send the write instruction itself to the memory, and port 3 can be used to send the storage address to the memory.

[0045] In one possible implementation, Figure 4 As shown, the memory 022 includes: a storage component 0221, a driving circuit 0222, a control component 0223 and an input / output (I / O) port 0224. The implementation process of the data writing method of the memory 022 provided in the embodiment of the present application can be implemented by the control component 0223, the driving circuit 0222, the storage component 0221 and the I / O port 0224. Among them, the control component 0223 is used to determine the control parameters required for the access operation indicated by the write instruction, and instruct the driving circuit 0222 to provide a driving signal to the storage component 0221 according to the control parameters. The storage component 0221 is used to write data under the drive of the driving signal.

[0046] like Figure 5As shown, the storage component 0221 includes one or more storage arrays (banks) 0221a, and the data access processes between the multiple storage arrays 0221a do not affect each other, that is, each storage array 0221a can accept read and write instructions independently or in parallel and complete the corresponding operations. Each storage array 0221a includes multiple storage cells a1. Each storage cell a1 is connected to a word line (word line, WL) and a bit line (bit line, BL), and at least one of the word lines and bit lines connected to different storage cells a1 is different. The read and write operations on different storage cells a1 can be achieved by applying electrical signals to the word lines and bit lines connected to the corresponding storage cells a1. And when at least one of the word lines and bit lines to which the electrical signals are applied during the read and write operations is different, the storage cells a1 acted upon by the read and write operations are different. For example, as Figure 6 As shown, a plurality of bit lines BL and a plurality of word lines WL are arranged in a crisscross pattern on the memory array 0221a. The plurality of word lines WL are arranged in sequence along the column direction, and each word line WL extends in the row direction. The plurality of bit lines BL are arranged in sequence along the row direction, and each bit line BL extends in the column direction. Each memory cell a1 is connected to a bit line BL and a word line WL, respectively, and at least one of the word lines WL and the bit lines BL connected to different memory cells a1 is different.

[0047] In one possible implementation, Figure 6 As shown, the memory cell a1 includes a variable resistor R and a gating device T connected in series. The variable resistor R is used as a storage medium of the memory cell a1 for storing information. In addition, the material used to make the variable resistor R includes a phase change material. One end of the variable resistor R is connected to the bit line BL, the other end of the variable resistor R is connected to the first port of the gating device T, and the word line WL is connected to the second port of the gating device T. The voltage difference between the word line WL and the bit line BL determines the opening and closing of the loop between the bit line and the word line, such as when the voltage difference between the word line WL and the bit line BL is greater than a specific threshold voltage, the loop between the two is opened. When the loop between the bit line and the word line is opened, the electrical signal applied to the bit line BL can be transmitted to the variable resistor R, and the data writing and reading of the variable resistor R can be realized under the control of the electrical signal.

[0048] It should be understood that the above content is an illustrative description of the application scenario of the data writing method of the memory provided in the embodiment of the present application, and does not constitute a limitation on the application scenario of the event analysis method. A person of ordinary skill in the art can know that as business needs change, its application scenario can be adjusted according to application needs, and the embodiment of the present application does not list them one by one.

[0049] Below Figure 1 Taking the application scenario shown in the figure as an example, the implementation process of the data writing method of the memory provided by the embodiment of the present application is described. Figure 7As shown, the implementation process of the data writing method of the memory may include the following steps:

[0050] Step 701: A memory receives a write instruction from a controller instructing the memory to write data of a specified length into the memory.

[0051] According to the above content, the storage system includes a controller and a memory, and the controller is used to send a write instruction to the memory. For example, when the memory is used as a memory, the processor is used to indicate to the controller that the operation data needs to be stored. After the controller obtains the operation data, it can determine the storage address for storing the operation data in the storage space of the memory, and then send the write instruction and the operation data to the memory according to the operation data and the storage address, so that the memory stores the operation data at the corresponding storage address according to the write instruction.

[0052] Since the memory includes multiple storage arrays, the data access processes between the multiple storage arrays do not affect each other, and writing data to the storage array is achieved by controlling the bit lines and word lines of the storage array. In addition, each bit line corresponds to an address range, different bit lines correspond to different address ranges, and the addresses corresponding to multiple bit lines connected to the same storage array constitute a segment of addresses within the address range of the storage array. Each word line corresponds to an address range, different word lines correspond to different address ranges, and the addresses corresponding to multiple word lines connected to the same storage array constitute a segment of addresses within the address range of the storage array. In addition, each storage array corresponds to an address range, different storage arrays correspond to different address ranges, and the addresses corresponding to multiple storage arrays in the same storage constitute a segment of addresses within the address range of the memory. Therefore, the specified length can be reflected by any one or more of the following: the total number of bit lines with continuous addresses that need to be controlled to write data based on a write instruction, the total number of word lines with continuous addresses that need to be controlled to write data based on a write instruction, and the total number of storage arrays with continuous addresses to which data is written based on a write instruction.

[0053] In one implementation, the bit lines with consecutive addresses may be a plurality of bit lines to which electrical signals are sequentially applied when the memory is subjected to bit line scanning. Generally, the plurality of bit lines with consecutive addresses are sequentially deployed on the memory array. Moreover, for every two adjacent bit lines, the first address of the latter bit line may be equal to the maximum address of the previous bit line + 1. For example, Figure 6 As shown, the bit lines BL(1), BL(2) and BL(3) on the storage array are continuously arranged bit lines, and when the memory is subjected to bit line scanning, electrical signals are applied to the bit lines BL(1), BL(2) and BL(3) in sequence, so that the bit lines BL(1), BL(2) and BL(3) are bit lines with continuous addresses.

[0054] In one implementation, the word lines with consecutive addresses may be a plurality of word lines to which electrical signals are sequentially applied when the memory is scanned for word lines. Typically, the plurality of word lines with consecutive addresses are sequentially deployed on the memory array. Furthermore, for every two adjacent word lines, the first address of the latter word line may be equal to the maximum address of the previous word line + 1. For example, Figure 6 As shown, word line WL(1), word line WL(2) and word line WL(3) on the storage array are word lines arranged continuously, and when the memory is word line scanned, electrical signals are applied to word line WL(1), word line WL(2) and word line WL(3) in sequence, so word line WL(1), word line WL(2) and word line WL(3) are word lines with continuous addresses.

[0055] In one implementation, the storage arrays with consecutive addresses may be multiple storage arrays into which data is written in sequence when data needs to be written in sequence to multiple storage arrays in the memory. Usually, multiple storage arrays with consecutive addresses are deployed in sequence on the memory. Moreover, for every two storage arrays with adjacent logical addresses, the first address of the latter storage array may be equal to the maximum address of the previous storage array + 1. For example, Figure 5 As shown, the memory 0221 includes a plurality of memory arrays 0221a arranged in sequence, and when data is continuously written to the plurality of memory arrays 0221a in the memory 0221, data is written to the memory array 0221a(1) and the memory array 0221a(2) in sequence, so the memory array 0221a(1) and the memory array 0221a(2) are memory arrays with consecutive addresses.

[0056] In an embodiment of the present application, data of a specified length may include multiple identical data. For example, when data is represented by binary values, the data of the specified length may be data composed of multiple binary values ​​1, or the data of the specified length may be data composed of multiple binary values ​​0. At this time, by specifying the length in the write instruction, it is possible to send a write instruction to indicate writing of the data of the specified length. Compared with the write instruction in the related art that indicates the length of the data to be written is the same and is a fixed value, there is no need to send multiple write instructions to indicate writing, thereby reducing the number of write instructions that need to be sent.

[0057] In one possible implementation, the write instruction may also indicate that the current value of the current signal used to perform the write operation indicated by the write instruction is less than the reference value. Wherein, the reference value is the current value of the current signal used to perform the write operation indicated by the write instruction that does not indicate the current value. Since when a write operation is performed on a certain storage unit, it is necessary to apply a current pulse signal to the bit line connected to the storage unit, and apply a gate enable voltage signal to the word line connected to the storage unit, so that the electrical characteristics of the storage medium of the storage unit change under the action of the signal, so as to store information through the changed electrical characteristics. Therefore, when the write instruction does not indicate the current value, the current values ​​of the current pulse signals applied to the bit lines connected to all storage units in the same storage array can be the same, and the current value is the reference value. When the write instruction indicates that the current value of the current signal used to perform the write operation indicated by the write instruction is less than the reference value, it is equivalent to the write instruction indicating that a smaller current or transient operation current is used to perform the write operation. In one possible implementation, using a smaller current or transient operation current to perform the write operation can be achieved by reducing the number of bits operated at the same time by the write operation.

[0058] By indicating through a write instruction that the current value of the current signal used to perform the write operation is less than the reference value, the power consumption of the write operation can be reduced. In addition, since the power consumption of the write operation is low, for a memory including multiple storage arrays, the controller can concurrently access instructions to multiple storage arrays of the memory according to the power consumption of the memory, so as to flexibly allocate bandwidth and power consumption among the multiple storage arrays, thereby meeting more application requirements. Since the write instruction indicates that the write operation is performed using a smaller current or a transient operation current, the power consumption of the write operation can be reduced, and the write instruction can also be called a low power write instruction.

[0059] In another possible implementation, the write instruction may also indicate that data of a specified length is allowed to be written in one or more time periods according to the power consumption of the memory. The power consumption of the memory includes the sum of the power consumption of multiple storage arrays in the memory. When the write instruction indicates that data of a specified length is allowed to be written in multiple time periods according to the power consumption of the memory, the memory may select to write part of the data of the specified length in each of the multiple time periods according to the overall power consumption of the memory, so as to achieve the purpose of reducing the overall power consumption of the memory. Since writing data according to the instructions of the write instruction can also reduce the power consumption of the memory, the write instruction may also be called a low-power write instruction.

[0060] In another possible implementation, the write instruction may also indicate: for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data written to the storage address indicated by the write instruction, a write operation is performed on the storage address based on the write instruction, and when the data stored in the storage address is the same as the data written to the storage address indicated by the write instruction, the write operation is not performed on the storage address. For example, assuming that the data stored in a certain storage address is all 1, and the write instruction indicates that when the data stored in the storage address is different from the data written to the storage address indicated by the write instruction, a write operation is performed on the storage address based on the write instruction, and when the data stored in the storage address is the same as the data written to the storage address indicated by the write instruction, the write operation is not performed on the storage address. Then, when the write operation indicated by the write instruction is performed, when the data of the bit to be written to the storage address is 0, the data stored in the bit needs to be refreshed to 0, and when the data of the bit to be written to the storage address is 1, no operation is performed on the bit. Since there is no need to perform an operation on the bit at this time, fast writing to the memory can be achieved.

[0061] When the data stored in the storage address is the same as the data written to the storage address by the write instruction, by not performing the write operation on the storage address, the operation time of the write operation indicated by the write instruction can be effectively reduced, and fast writing to the memory can be achieved, and the instruction interval corresponding to the write instruction can be shortened, so that other data can be written using the saved time, reducing the write latency of the memory and improving the write bandwidth of the memory. Since the write instruction can reduce the operation time of executing the write operation, the write instruction can be called a fast write instruction.

[0062] Corresponding to the fast write instruction, a possible application scenario may be: before performing a write operation on the continuous address of the memory, the controller instructs the memory to pre-write all the continuous addresses to a uniform value, so that when the memory performs a write operation according to the subsequently received write instruction, it only needs to operate on the bits of the data stored in the continuous address that are different from the data indicated by the write instruction. For example, during the idle period of a certain storage array of the memory, the controller can control the memory to write all the bits of the continuous address of the specified length of the storage array to a uniform value by indicating a write instruction or a low-power write instruction to write data of a specified length, so that when the controller receives an urgent data write request, it can use a fast write instruction to perform a write operation in the continuous address. Among them, the uniform value can be set according to the performance of the memory. For example, when the memory writes 0 quickly and writes 1 slowly, the uniform value can be 1.

[0063] In addition, the write instruction can also directly specify the data to be written, such as specifying to write a binary value 1 or 0. By indicating the write instruction to write a binary value 1 of a specified length or a binary value 0 of a specified length, it is not necessary to transmit the data to be written through the data bus, which can reduce the power consumption of data transmission. At this time, the write instruction can also be called a write 1 instruction or a write 0 instruction, or it can also be called an instruction to write a specified length of 0 or an instruction to write a specified length of 1. Similarly, the above-mentioned low-power write instruction can also be called a low-power write 1 instruction or a low-power write 0 instruction, or it can also be called a low-power write instruction of a specified length of 0 or a low-power write instruction of a specified length of 1. The above-mentioned fast write instruction can also be called a fast write 1 instruction or a fast write 0 instruction, or it can also be called a fast write instruction of a specified length of 0 or a fast write instruction of a specified length of 1.

[0064] Step 702: The memory writes data of a specified length to a storage medium of the memory based on a write instruction.

[0065] After receiving the write instruction sent by the controller, the memory can perform the write operation according to the write instruction to write the data to be written to the storage medium of the memory. In addition, when the content of the write operation instruction is different, the implementation method of executing the write operation is slightly different. The following describes the implementation methods of executing the corresponding write operation in accordance with various situations for various implementation methods of the write instruction in step 701.

[0066] In the first case, when the specified length of the write instruction is reflected based on the total number of consecutive bit lines of the address that need to be controlled by the write instruction to write data, the memory can find the first storage address indicated by the write instruction according to the hierarchy of the storage array, word line and bit line according to the write instruction, and then perform the write operation on the first storage address, and then increase the address of the bit line by one to find the second storage address indicated by the write instruction, and then perform the write operation on the second storage address, and so on, traverse and perform the write operation according to the hierarchy of the bit line, word line and storage array until the write operation indicated by the write instruction is completed.

[0067] In the second case, when the specified length of the write instruction is reflected based on the total number of consecutive word lines of addresses that need to be controlled by the write instruction to write data, the memory can find the first storage address indicated by the write instruction according to the levels of the storage array, word line and bit line according to the write instruction in the process of executing the write operation indicated by the write instruction, and then perform the write operation on the first storage address, and then increase the address of the word line by one to find the second storage address indicated by the write instruction, and then perform the write operation on the second storage address, and so on, traverse and perform the write operation according to the levels of the word line, bit line and storage array until the write operation indicated by the write instruction is completed.

[0068] In the third case, when the specified length of the write instruction is reflected based on the total number of consecutive storage arrays whose addresses need to be controlled by the write instruction to write data, the memory can find the first storage address indicated by the write instruction according to the levels of the storage array, bit line and word line according to the write instruction, and then perform the write operation on the first storage address, and then increase the address of the storage array by one to find the second storage address indicated by the write instruction, and then perform the write operation on the second storage address, and so on, traverse and perform the write operation according to the levels of the storage array, bit line and word line, until the write operation indicated by the write instruction is completed. For example, Figure 5 The arrow b1 in FIG. 1 is the direction in which the storage address of the storage array 0021a increases. Figure 6 The arrow b2 in FIG. 1 is the direction in which the bit line BL on the memory array 0221a is scanned, that is, the direction in which the storage address of the bit line BL increases. Figure 6 The arrow b3 in FIG. 1 is a scanning direction for the word line WL on the memory array 0221a, that is, a direction in which the storage address of the word line WL increases. The memory array, the bit line and the word line can be traversed in this order.

[0069] In the fourth case, when the data of the specified length in the write instruction includes multiple identical data, the memory can directly refresh the bits of the storage address of the specified length indicated by the write instruction to the identical data according to the write instruction during the process of executing the write operation indicated by the write instruction.

[0070] In the fifth case, when the write instruction also indicates that the current value of the current signal used to perform the write operation indicated by the write instruction is less than the reference value, the memory can apply a current pulse signal to the bit line connected to the storage cell indicated by the write instruction during the process of executing the write operation indicated by the write instruction, and the current value of the current pulse signal is less than the reference value, and apply a selection enable voltage signal to the word line connected to the storage cell to complete the write operation indicated by the write instruction.

[0071] In the sixth case, when the write instruction also indicates that data of a specified length is allowed to be written in one or more time periods according to the power consumption of the memory, the memory can predict the overall power consumption of the memory during the process of executing the write operation indicated by the write instruction, and write the data indicated by the write instruction in one or more time periods when the overall power consumption of the memory is lower, thereby achieving the purpose of reducing the overall power consumption of the memory.

[0072] In the seventh case, when the write instruction is the above-mentioned fast write instruction, during the process of executing the write operation indicated by the write instruction, for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data indicated by the write instruction to be written to the storage address, the memory may perform the write operation on the storage address based on the write instruction; when the data stored in the storage address is the same as the data indicated by the write instruction to be written to the storage address, the memory may not perform the write operation on the storage address.

[0073] It should be noted that in the actual application of the memory, the write instruction can be a combination of part or all of the above-mentioned multiple implementation methods. When the write instruction is a combination of the above-mentioned multiple implementation methods, when the memory executes the write operation, it can perform the write operation based on the combination of the write instruction implementation methods and comprehensively use the above-mentioned situations corresponding to the write instruction implementation methods. The implementation process will not be repeated here.

[0074] Step 703: The memory feeds back a write response to the write instruction to the controller.

[0075] After the memory responds to the write instruction, it can feed back a write response to the write instruction to the controller to feedback whether the write operation indicated by the write instruction is completed. It should be noted that the memory may not feed back a write response to the controller, and the controller may determine the execution result of the write instruction in other ways. For example, an instruction delay may be defined, and when the controller does not receive feedback from the memory within a specified time period after sending the write instruction, it is determined that the write operation is not completed.

[0076] In summary, in the data writing method of the memory provided in the embodiment of the present application, the memory receives a write instruction instructing the controller to write data of a specified length to the memory, and the memory writes data of a specified length to the storage medium of the memory based on the write instruction. Since the write instruction can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write instructions that need to be sent can be reduced, thereby reducing the overhead of the write instruction. In addition, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened, and the saved time can be used to write other data, thereby reducing the write latency of the memory and effectively improving the write bandwidth of the memory.

[0077] It should be noted that the order of steps in the method for writing data to the memory provided in the embodiment of the present application can be adjusted appropriately, and the steps can be increased or decreased accordingly according to the situation. Any technician familiar with the technical field can easily think of a change within the technical scope disclosed in the present application, and all of them should be included in the protection scope of the present application, so they will not be repeated here.

[0078] The present application also provides a device for writing data into a memory. Figure 8 As shown, the data writing device 80 of the memory includes:

[0079] The receiving module 801 is used to receive a write instruction from a controller instructing to write data of a specified length into a memory.

[0080] The access module 802 is used to write data of a specified length to the storage medium of the memory based on the write instruction.

[0081] Optionally, the memory includes multiple storage arrays, and data access processes between the multiple storage arrays do not affect each other. Writing data to the storage array is achieved by controlling the bit lines and word lines connected to the storage array, and the specified length is reflected by any one or more of the following: the total number of address-contiguous bit lines that need to be controlled to write data based on a write instruction, the total number of address-contiguous word lines that need to be controlled to write data based on a write instruction, and the total number of address-contiguous storage arrays to which data is written based on a write instruction.

[0082] Optionally, the write instruction further indicates that the current value of the current signal used to perform the write operation indicated by the write instruction is smaller than a reference value, and the reference value is the current value of the current signal used to perform the write operation indicated by the write instruction without indicating the current value.

[0083] Optionally, the write instruction further indicates that data of a specified length is allowed to be written in one or more time periods according to power consumption of the memory.

[0084] Optionally, the write instruction also indicates: for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data the write instruction indicates to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored in the storage address is the same as the data the write instruction indicates to be written to the storage address, no write operation is performed on the storage address.

[0085] Optionally, the data of the specified length is data consisting of multiple binary values ​​1, or the data of the specified length is data consisting of multiple binary values ​​0.

[0086] In summary, in the data writing device of the memory provided in the embodiment of the present application, the receiving module receives the write instruction of the controller indicating to write data of a specified length to the memory, and the writing module writes the data of the specified length to the storage medium of the memory based on the write instruction. Since the write instruction can specify the length of the data to be written, when the data of the specified length needs to be written, the number of write instructions that need to be sent can be reduced, thereby reducing the overhead of the write instruction. In addition, since the number of write instructions that need to be sent is reduced, the instruction interval that the memory needs to wait for is shortened, and the saved time can be used to write other data, thereby reducing the write latency of the memory and effectively improving the write bandwidth of the memory.

[0087] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding contents in the aforementioned method embodiments and will not be repeated here.

[0088] An embodiment of the present application provides a computer device. Figure 1 The storage system shown can be deployed in the computing device. The computing device includes a memory and a processor, the memory stores program instructions, and the processor runs the program instructions to execute the data writing method of the memory provided by the present application or execute any step of the data writing method of the memory provided by the present application.

[0089] Fig. 9 Schematic diagram of the structure of a computer device 90 provided in an embodiment of the present application. Fig. 9 As shown, the computer device 90 includes a memory 901, a processor 902, a communication interface 903 and a bus 904. The memory 901, the processor 902 and the communication interface 903 are connected to each other through the bus 904. In addition, the computer device 90 may include multiple processors 902, so that the functions of the above-mentioned different functional modules can be realized by different processors.

[0090] The memory 901 may be a read-only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory 901 may store executable code sequences. When the executable code stored in the memory 901 is executed by the processor 902, the processor 902 and the communication interface 903 are used to execute the data writing method of the memory provided in the embodiment of the present application. The memory 901 may also include software modules and data required for other running processes such as an operating system.

[0091] The processor 902 may be a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU), or one or more integrated circuits.

[0092] The processor 902 may also be an integrated circuit chip with signal processing capabilities. In the implementation process, some or all of the functions of the data writing method of the memory of the present application may be completed by the hardware integrated logic circuit or software instructions in the processor 902. The above-mentioned processor 902 may also be a general-purpose processor, a digital signal processor (digital signal processing, DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware decoding processor, or may be executed by a combination of hardware and software modules in a decoding processor. The software module may be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 901, and the processor 902 reads the information in the memory 901 and combines its hardware to complete the data writing method of the memory of the embodiment of the present application.

[0093] The communication interface 903 uses a transceiver module such as, but not limited to, a transceiver to implement communication between the computer device 90 and other devices or a communication network. For example, the communication interface 903 can be any one or any combination of the following devices: a network interface (such as an Ethernet interface), a wireless network card, and other devices with network access functions.

[0094] The bus 904 may include a path for transmitting information between various components of the computer device 90 (eg, the memory 901 , the processor 902 , and the communication interface 903 ).

[0095] It should be noted that, when the computer device is a client, the computer device also includes a display screen, which is used to display a graphical user interface of the program development platform.

[0096] The descriptions of the processes corresponding to the above-mentioned figures have different emphases. For parts that are not described in detail in a certain process, please refer to the relevant descriptions of other processes.

[0097] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product providing a program development platform includes one or more computer instructions, and when these computer program instructions are loaded and executed on a computer device, the process or function of the data writing method of the memory provided in the embodiment of the present application is implemented in whole or in part.

[0098] The computer device may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium stores computer program instructions that provide a program development platform.

[0099] An embodiment of the present application also provides a computer-readable storage medium, which is a non-volatile computer-readable storage medium. The computer-readable storage medium includes program instructions. When the program instructions are executed on a computer device, the computer device executes a method for writing data to a memory as provided in an embodiment of the present application.

[0100] The embodiment of the present application also provides a computer program product including instructions. When the computer program product is run on a computer, the computer executes the method for writing data into a memory provided by the embodiment of the present application.

[0101] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0102] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions. For example, the resistance value information involved in this application is obtained with full authorization.

[0103] In the embodiments of the present application, the terms "first", "second" and "third" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance. The term "at least one" means one or more, and the term "plurality" means two or more, unless otherwise expressly defined.

[0104] The term "and / or" in this application is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0105] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the concept and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for writing data into a memory, characterized in that: The method comprises: The memory receives a write instruction from the controller instructing the memory to write data of a specified length, wherein the specified length is any specified length; The memory writes the data of the specified length to the storage medium of the memory based on the write instruction.

2. The method according to claim 1, characterized in that The memory includes multiple storage arrays, and the data access processes between the multiple storage arrays do not affect each other. Writing data to the storage arrays is achieved by controlling the bit lines and word lines connected to the storage arrays. The specified length is reflected by any one or more of the following: the total number of address-contiguous bit lines that need to be controlled to write data based on the write instruction, the total number of address-contiguous word lines that need to be controlled to write data based on the write instruction, and the total number of address-contiguous storage arrays to which data is written based on the write instruction.

3. The method according to claim 1 or 2, characterized in that: The write instruction further indicates that a current value of a current signal used to perform a write operation indicated by the write instruction is smaller than a reference value, wherein the reference value is a current value of a current signal used to perform a write operation indicated by a write instruction that does not indicate a current value.

4. The method according to any one of claims 1 to 3, characterized in that: The write instruction also indicates that the data of the specified length is allowed to be written in one or more time periods according to the power consumption of the memory.

5. The method according to any one of claims 1 to 4, characterized in that: The write instruction also indicates: for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored in the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

6. The method according to any one of claims 1 to 5, characterized in that: The data of the specified length is data consisting of multiple binary values ​​1, or the data of the specified length is data consisting of multiple binary values ​​0.

7. A data writing device for a memory, characterized in that: The device comprises: A receiving module, used for receiving a write instruction from a controller instructing to write data of a specified length into a memory; An access module is used to write the data of the specified length to the storage medium of the memory based on the write instruction.

8. The device according to claim 7, characterized in that The memory includes multiple storage arrays, and the data access processes between the multiple storage arrays do not affect each other. Writing data to the storage arrays is achieved by controlling the bit lines and word lines connected to the storage arrays. The specified length is reflected by any one or more of the following: the total number of address-contiguous bit lines that need to be controlled to write data based on the write instruction, the total number of address-contiguous word lines that need to be controlled to write data based on the write instruction, and the total number of address-contiguous storage arrays to which data is written based on the write instruction.

9. The device according to claim 7 or 8, characterized in that The write instruction further indicates that a current value of a current signal used to perform a write operation indicated by the write instruction is smaller than a reference value, wherein the reference value is a current value of a current signal used to perform a write operation indicated by a write instruction that does not indicate a current value.

10. The device according to any one of claims 7 to 9, characterized in that: The write instruction also indicates that the data of the specified length is allowed to be written in one or more time periods according to the power consumption of the memory.

11. The device according to any one of claims 7 to 10, characterized in that: The write instruction also indicates: for any storage address indicated by the write instruction, when the data stored in the storage address is different from the data indicated by the write instruction to be written to the storage address, a write operation is performed on the storage address based on the write instruction; when the data stored in the storage address is the same as the data indicated by the write instruction to be written to the storage address, no write operation is performed on the storage address.

12. The device according to any one of claims 7 to 11, characterized in that The data of the specified length is data consisting of multiple binary values ​​1, or the data of the specified length is data consisting of multiple binary values ​​0.

13. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores program instructions, and the processor runs the program instructions to execute the method according to any one of claims 1 to 6.

14. A computer-readable storage medium, characterized in that: The method comprises program instructions, and when the program instructions are executed on a computer device, the computer device is caused to execute the method according to any one of claims 1 to 6.

15. A computer program product, characterized in that When the computer program product is executed on a computer, the computer is enabled to execute the method according to any one of claims 1 to 6.

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