On-chip check circuit, memory and storage device

Abstract

The invention provides an on-chip check circuit, a memory and a storage device.The on-chip check circuit comprises an encoder and a first error correction circuit, and the encoder generates a first check code in a write-in stage according to write-in data and a bit group represented by an error correction matrix and writes the first check code into a storage array; in a reading stage, generating a second check code according to the read data and the bit group represented by the error correction matrix, and generating an error correction code based on the read first check code and the generated second check code; the first error correction circuit receives the read data, performs single-bit error correction on the read data according to an error correction code output by the encoder and then outputs first error correction data; wherein the error correction matrix comprises an error correction code corresponding to each bit under each beat, and the error correction matrix meets the condition that the XOR result of the error correction codes corresponding to any multiple bits is not the same as the error correction code corresponding to any bit located in the same beat as one of the multiple bits. According to the scheme, data verification can be realized.

Description

Technical Field

[0001] The present application relates to memory technology, and more particularly to an on-chip verification circuit, a memory, and a storage device. Background Art

[0002] With the development of memory technology, memories are widely used in various fields. For example, dynamic random access memory (DRAM) is widely used.

[0003] In practical applications, in order to ensure data reliability, on-die error checking and correction (On-Die ECC) is introduced. Specifically, on-die error checking and correction can support the correction of single-bit errors, but for multi-bit errors, on-die error checking and correction may cause miscorrection. The miscorrected data is transmitted to the outside for further verification, such as memory bar-level error checking and correction (Rank-level ECC), which further aggravates the bit error situation. Summary of the invention

[0004] Embodiments of the present application provide an on-chip verification circuit, a memory, and a storage device.

[0005] According to some embodiments, the first aspect of the present application provides an on-chip check circuit, which is applied to a memory, and the on-chip check circuit includes: an encoder, connected to a storage array of the memory, and used to generate a first check code and write it into the storage array according to the write data and the bit grouping represented by the error correction matrix in the write phase; and, in the read phase, generate a second check code according to the read data and the bit grouping represented by the error correction matrix, and generate an error correction code based on the read first check code and the second check code; a first error correction circuit, connected to the encoder, is used to receive the read data, and according to the error correction code output by the encoder, performs single-bit error correction on the read data and outputs first error correction data; wherein the error correction matrix includes an error correction code corresponding to each bit in each beat, and the error correction matrix satisfies: the XOR result of the error correction codes corresponding to any multiple bits is not the same as the error correction code corresponding to any bit in the same beat as one of the multiple bits.

[0006] In some embodiments, in the error correction matrix, the XOR result of the error correction code corresponding to any multiple bits belonging to the same beat is not the same as the error correction code corresponding to any bit in the error correction matrix; the XOR result of the error correction code corresponding to any multiple bits belonging to different beats is not the same as the error correction code corresponding to any bit in the same beat as one of the multiple bits.

[0007] In some embodiments, the on-chip verification circuit also includes: a data selector; a first input end of the data selector receives write data, a second input end of the data selector receives read data, and an output end of the data selector is connected to an input end of the encoder and a storage array; the data selector is used to output write data in a write phase and output read data in a read phase.

[0008] In some embodiments, the first error correction circuit includes: a first decoder and a first correction circuit; the input end of the first decoder is connected to the encoder, the first decoder is used to receive the error correction code output by the encoder, determine the first target position to be flipped based on the error correction code and the error correction matrix, and output a first error correction instruction pointing to the first target position; the first correction circuit is connected to the output end of the first decoder, the first correction circuit is used to receive the read data, and according to the first error correction instruction, flip the bits under the first target position to obtain first error correction data.

[0009] In some embodiments, the on-chip verification circuit further includes: a plurality of buffer circuits, including: a first buffer circuit, wherein an input end of the first buffer circuit receives write data, and an output end of the first buffer circuit is connected to a first input end of a data selector, for buffering and outputting the received write data; a second buffer circuit, wherein an input end of the second buffer circuit is connected to an output end of the data selector, and an output end of the second buffer circuit is connected to a storage array, for buffering and outputting the write data output by the data selector during a write phase; and a third buffer circuit, wherein an input end of the third buffer circuit is connected to an encoder, and an output end of the third buffer circuit is connected to the storage array, for buffering and outputting the write data output by the encoder during a write phase. A check code buffer output; a fourth buffer circuit, the input end of the fourth buffer circuit is connected to the storage array, the output end of the fourth buffer circuit is connected to the encoder, and is used to buffer and output the first check code read from the storage array in the reading phase; a fifth buffer circuit, the input end of the fifth buffer circuit is connected to the storage array, the output end of the fifth buffer circuit is connected to the second input end of the data selector and the first error correction circuit, and is used to buffer and output the read data read from the storage array in the reading phase; a sixth buffer circuit, the input end of the sixth buffer circuit is connected to the output end of the first error correction circuit, and the output end of the sixth buffer circuit is used to buffer and output the first error correction data output by the first error correction circuit.

[0010] In some embodiments, a buffer circuit includes: an even number of inverters connected in series.

[0011] In some embodiments, the XOR result of the error correction codes corresponding to any multiple bits is not the same as the error correction code corresponding to any bit located in the same beat as one of the multiple bits, including: the XOR result of the error correction codes corresponding to any two bits in the same beat is not the same as the error correction code corresponding to any bit located in the same beat as one of the two bits.

[0012] In some embodiments, in the error correction matrix, the XOR results of the error correction codes corresponding to different multiple bits belonging to the same beat are different.

[0013] In some embodiments, the on-chip check circuit further includes: a second error correction circuit; the second error correction circuit is connected to the encoder, receives a multi-bit error correction instruction, and read data or a first error correction data, and is used to respond to the multi-bit error correction instruction pointing to the target beat number, and output the second error correction data after performing multi-bit error correction on the received data according to the error correction code output by the encoder; wherein the multi-bit error correction instruction pointing to the target beat number indicates that the read data has a multi-bit error located in the same beat, and the multi-bit error occurs in the target beat number.

[0014] In some embodiments, the second error correction circuit includes: a second decoder and a second correction circuit; the input end of the second decoder is connected to the encoder, the second decoder receives an error correction code and a multi-bit error correction instruction, and is used to respond to the multi-bit error correction instruction pointing to the target beat number, determine the second target position to be flipped based on the target beat number pointed to by the multi-bit error correction instruction, the error correction code and the error correction matrix, and output the second error correction instruction pointing to the second target position; the second correction circuit is connected to the output end of the second decoder, the second correction circuit is used to receive the read data or the first error correction data, and according to the second error correction instruction, perform data error correction on the bits under the second target position to obtain second error correction data.

[0015] In some embodiments, the second correction circuit is connected to a data input terminal of the first error correction circuit for receiving read data, or the second correction circuit is connected to an output terminal of the first error correction circuit.

[0016] According to some embodiments, a second aspect of the present application provides a memory, comprising: a storage array, and an on-chip verification circuit as described in any of the preceding items.

[0017] According to some embodiments, the third aspect of the present application provides a storage device, comprising: an off-chip check circuit and at least one memory as in any of the preceding items; the off-chip check circuit is connected to the at least one memory, and is used to check each beat of data in the first error correction data output by the at least one memory during the reading phase, and the check includes single-bit error correction and multi-bit detection.

[0018] In some embodiments, the off-chip check circuit includes: an indication circuit; an indication circuit, which is used to send a multi-bit error correction instruction pointing to a target beat number to all memories if there are multi-bit errors in the same beat data.

[0019] In some embodiments, the off-chip verification circuit also includes: a processing circuit for performing a first data integration on the first error correction data output by different memories, and performing data verification on the integrated data; if there is no data error or it can be corrected, the off-chip verified data is output; if the memory needs to perform a second correction, after receiving the second error correction data, the erroneous data is replaced on the integrated data based on the second error correction data and the data is verified again; if there is no data error or it can be corrected, the off-chip verified data is output.

[0020] The on-chip check circuit, memory and storage device provided by the embodiment of the present application include an encoder and a first error correction circuit, wherein the encoder is responsible for generating check codes for the writing and reading stages, and obtaining the error correction code according to the check codes of the two stages; the first error correction circuit performs single-bit error correction on the data read out in the reading stage according to the error correction code. The check code in this scheme is generated by the encoder based on the bit grouping represented by the error correction matrix, and the error correction matrix includes the error correction code corresponding to each bit in each beat, and satisfies that the bit corresponding to the XOR result of any multiple error correction codes is not in the same beat with any bit of the multiple bits, so even if there are multiple bit errors that lead to the generation of a miscorrected error correction code, since the miscorrected error correction code is not in the same beat with the bit where the multiple bit errors occur, it will not cause new same-beat multi-bit errors, thereby avoiding further expansion of data errors, enabling data verification, and effectively improving the reliability of verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the description, are used to explain the principles of the embodiments of the present application.

[0022] Figure 1 An example diagram of a memory architecture according to an embodiment;

[0023] Figure 2 A structural diagram of a storage unit according to an embodiment of the present invention;

[0024] Figure 3 A schematic diagram of an example on-chip verification process;

[0025] Figure 4 is a schematic diagram of an example architecture;

[0026] Figure 5 A data structure diagram of an example;

[0027] Figure 6 is a schematic diagram of the structure of an example on-chip verification circuit;

[0028] Figure 7 is an example of a single-bit error situation;

[0029] Figure 8 is an example of a double bit error situation;

[0030] Fig. 9 A data structure diagram of an example;

[0031] Fig.10 is a schematic diagram of the structure of an example on-chip verification circuit;

[0032] Fig.11 is a schematic diagram of the structure of an example on-chip verification circuit;

[0033] Fig.12 is a schematic diagram of the structure of an example on-chip verification circuit;

[0034] Fig.13 is a schematic structural diagram of an exemplary buffer circuit;

[0035] Fig.14 is a schematic diagram of the structure of an example on-chip verification circuit;

[0036] Fig.15 is a schematic diagram of the structure of an example on-chip verification circuit;

[0037] Fig.16 A structural diagram of a memory device of an example;

[0038] Fig.17 A diagram showing an example structure of a storage device.

[0039] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0040] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application.

[0041] The terms "including" and "having" in this application are used to express an open-ended inclusive meaning, and mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms "first" and "second" are used only as marks or distinctions, and are not intended to limit the order or quantity of their objects. In addition, the different elements and regions in the drawings are only schematically shown, and are therefore not limited to the sizes or distances shown in the drawings.

[0042] The technical solution is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0043] The technical solution is described in detail with specific embodiments below. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present disclosure will be described below in conjunction with the accompanying drawings.

[0044] Figure 1 FIG. 1 is an example diagram of a memory architecture shown in an embodiment, such as Figure 1 As shown, taking DRAM as an example, it includes data input / output buffer, row decoder, column decoder, sense amplifier and storage array. Among them, the data input / output buffer belongs to the peripheral area circuit, and the sense amplifier, row decoder, column decoder and storage array belong to the array area circuit. The storage array is mainly composed of word lines, bit lines and storage cells. The word lines in the storage array extend in the row direction, and the bit lines in the storage array extend in the column direction. The intersection of the word lines and the bit lines is the storage cell of the storage array.

[0045] Each storage unit is used to store one bit of data. Figure 2 As shown, Figure 2 This is a structural example diagram of a memory cell according to an embodiment, and the memory cell is mainly composed of a transistor switch M and a capacitor C. The capacitor is used to store data, and the transistor switch is used to turn off or on according to the selected state.

[0046] A certain storage cell can be activated by controlling the word line and the bit line to access the storage cell. Take the read scenario as an example: when the data in the storage cell needs to be read, the word line of the row where the storage cell is located can be selected through the row decoder, and accordingly, the transistor M in the diagram is turned on, and the state of the capacitor C at this time can be sensed by sensing and amplifying the bit line signal. For example, if the bit data stored in the storage cell is 1, then after the transistor M is turned on, 1 will be read from the bit line of the storage cell, and vice versa. In addition, take the write scenario as an example: when bit data needs to be written to a certain storage cell, such as writing 1. The word line of the row where the storage cell is located can be selected through the row decoder, and the corresponding transistor M in the diagram is turned on, and by setting the logic level of the bit line to 1, the capacitor C is charged, that is, 1 is written to the storage cell. Conversely, if 0 is to be written, the logic level of the bit line is set to 0, so that the capacitor C is discharged, that is, 0 is written to the storage cell.

[0047] In actual applications, considering the influence of various factors, such as process deviation, ionizing radiation, temperature, data loss, etc., the actual read data may be inconsistent with the written data, resulting in data errors. Therefore, in order to ensure the accuracy of the data, on-chip error checking and correction (On-Die ECC) is introduced. Based on on-chip error checking and correction, the memory can verify its own data and correct single-bit errors. Taking DDR5 of double-rate synchronous dynamic random access memory (DDR for short) as an example, it generates 8 bits of check bits for every 128 bits of data. As an example, Figure 3 FIG. 1 is a flow chart of an example on-chip verification process. Figure 3 As shown, the process of on-chip verification generally includes: when data is written, the bit checker writes 128 bits of data (write data) into the memory as needed, generates 8 bits of first verification data, and stores the write data and the verification data in the memory together; when data is read, 128 bits of data (read data) and 8 bits of first verification data are read from the memory, and the error correction code generator generates 8 bits of second verification data based on the read 128 bits of data, and compares the generated second verification data with the first verification data read from the memory to generate an error correction code. Among them, the error correction code can be used to determine whether the read data has a data error. For example, if the error correction code is all 0, it means that there is no error. If it is not 0, it means that there is a data error. Correspondingly, the error correction code decoder can decode the error correction code to locate the data error position, and the error corrector performs flip correction on the bits at the data error position, for example, flipping 0 to 1 or flipping 1 to 0. After data error correction is implemented, the 128 bits of data after error correction are output.

[0048] In the example technology, there are on-chip and off-chip verification settings for data verification, for example, library-level error checking and correction (rank-level ECC for short). Combined with practical applications, the entire DRAM system can be divided into the following layers from top to bottom, namely, channel, dual in-line memory modules (DIMMs for short), library (RANK), chip, storage block (Bank), sub-array, local sub-array (MAT), row, and cell. Among them, a library refers to a chip that receives the same chip select (CS) signal and can be accessed through the same memory channel. All chips in a library share the address line, control line, and data line provided by the same memory channel. The memory controller can perform read and write operations on all chips in the same library. Specifically, the object of on-chip verification is the data in the storage array of each chip, and the data is output beat by beat when outputting the data; the object of off-chip verification is each beat of data output by all chips in a library. As an example, Figure 4 A schematic diagram of an example architecture is shown below. Figure 5 This is a data structure diagram of an example, such as Figure 4 As shown in FIG. 1 , a dual in-line memory module is provided with a library and a chip for storing verification data (the chip not filled with shade in the figure). The library includes eight storage chips ( Figure 4 Assuming that each memory chip outputs 8 bits per beat and a total of 16 beats, then Figure 5 As shown, the above library includes DRAM0~DRAM7, and the data stored in each memory chip is d0~d127, a total of 128 bits, and each memory chip has 8 data ports, DQ0~DQ7. The 128 bits of data are output in 16 beats, and each beat outputs 8 bits of data through the data ports DQ0~DQ7. For example, for any memory chip, the memory chip outputs 8 bits, d0~d7, through the data ports DQ0~DQ7 in the first beat, and outputs 8 bits, d8~d15, through the data ports DQ0~DQ7 in the second beat, and so on, until the 16th beat outputs d120~d127. Combined with the above example explanation, the on-chip check is that each memory chip checks the 128 bits stored in itself, and the off-chip check is to check the data output by the eight memory chips in each beat at the RANK level. For example, each memory chip outputs 8 bits per beat, and the eight memory chips output 64 bits per beat. The off-chip check is to check the 64 bits in each beat. The current on-chip check technology can realize the correction of single-bit errors, and the off-chip check technology can realize the correction of single-bit errors and the detection of multi-bit (such as double-bit) errors.

[0049] In practical applications, multi-bit errors may occur in a certain memory chip, and the on-chip verification of the multi-bit errors may be miscorrected. The data after the miscorrection is transmitted to the outside of the memory chip for off-chip verification. When the newly generated miscorrected bits are verified off-chip, more miscorrections may be further generated, resulting in aggravated errors. In order to avoid the consequences of the above data errors being amplified, some aspects of the embodiments of the present application involve the above considerations. The following is an example introduction to the scheme in combination with some embodiments.

[0050] Embodiment 1

[0051] Figure 6 FIG. 1 is a schematic diagram of a structure of an exemplary on-chip verification circuit. Figure 6 As shown, the on-chip verification circuit 31 includes: an encoder 11 and a first error correction circuit 12;

[0052] The encoder 11 is connected to the storage array 13 of the memory, and is used to generate a first check code according to the write data Data1 and the bit grouping represented by the error correction matrix in the write phase and write the first check code into the storage array 13; and to generate a second check code according to the read data Data2 and the bit grouping represented by the error correction matrix in the read phase, and generate an error correction code Syn based on the read first check code and the second check code;

[0053] The first error correction circuit 12 is connected to the encoder 11 and is used for receiving the read data Data2 and performing single-bit error correction on the read data Data2 according to the error correction code output by the encoder 11 and then outputting the first error correction data Correct Data1.

[0054] The error correction matrix includes an error correction code corresponding to each bit in each beat, and the error correction matrix satisfies: the XOR result of the error correction codes corresponding to any multiple bits is not the same as the error correction code corresponding to any bit in the same beat as one of the multiple bits. In practical applications, the circuit provided in this embodiment can be applied to various memories, as an example, it can be applied to including but not limited to double data rate synchronous dynamic random access memory (DDR for short).

[0055] It should be noted that the writing of the first check bit into the storage array mentioned in this application needs to be understood according to the actual design of the chip. In some embodiments, there is no difference between the target storage area for writing data and the check code, that is, each area of ​​a single DRAM can be used to store the written data and the check code; in other embodiments, the target storage area for writing data and the check code is differentiated and stored in different locations of the DRAM. This article does not impose any restrictions on the writing area of ​​the check code, and the final storage location of the written data and the check code is collectively referred to as the storage array.

[0056] Specifically, a single-bit error means that there is an error in one bit of the data to be verified. If a data error occurs, the originally written data and the read data are inconsistent. For example, a bit in the data originally written into the storage array is 1 or 0, but in the storage array of the memory, due to some factors, the stored bit is flipped to 0 or 1, and the subsequent read of the bit will be erroneous. Figure 7 For an example single-bit error scenario, Figure 7 As shown, the data to be verified is the verification object of on-chip verification. For example, a memory stores 128 bits. Assume that the bits filled with shaded spaces are erroneous bits. As shown in the figure, there is an error in one bit d0 among the 128 bits stored in the memory, that is, a single-bit error occurs. In practical applications, both on-chip verification and off-chip verification can achieve single-bit error correction. That is, in the case of a single-bit error, the bit where the error occurs can be accurately located and the data of that bit can be flipped, thereby achieving accurate error correction. Figure 7 As shown, the error of bit d0 can be corrected by on-chip checking, thereby obtaining accurate 128 bits.

[0057] In practical applications, in addition to the above single-bit error situation, multi-bit errors may also occur. Specifically, a multi-bit error means that at least two bits of data are wrong. Figure 8 An example of a double bit error situation is Figure 8 As shown, still taking the on-chip check as an example, among the 128 bits shown in the figure, two bits, namely bit d0 and bit d17, are erroneous, i.e., a double-bit error occurs. For multi-bit errors, the current on-chip check and off-chip check can detect multi-bit errors, but cannot correct multi-bit errors. This is because, although the check can detect whether there are multiple bits in the data to be checked that have errors, the current check cannot determine which specific bits have errors, so it is impossible to perform effective error correction. On the contrary, taking the on-chip check as an example, still combined with the on-chip check, the on-chip check can detect multiple bits in the data to be checked. Figure 8 For example, assuming that data error correction is performed based on on-chip verification, if the error correction code generated based on multi-bit errors is the same as the error correction code corresponding to a certain bit, it may cause errors in new bits, such as Figure 8 As shown in the figure, the error correction code generated by the multi-bit error is the same as the error correction code corresponding to d6. After the on-chip check is performed, a new bit error is generated, that is, d6 is miscorrected. It can be found that the new error bit d6 caused by the miscorrection is in the same beat as the original error bit d0. Combined with the above-mentioned verification process of on-chip verification and off-chip verification, it can be known that each beat of data in all memories under a library will be subjected to off-chip verification. Combined with this example, Figure 8The first beat data output by the memory shown in the figure will contain multiple bit errors (d6 and d0), and together with the first beat data output by other memories in the same bank (not shown in the figure), they are transmitted to the off-chip verification circuit for off-chip verification. It can be seen that the verification object of this off-chip verification, that is, the first beat data output by each memory, contains at least Figure 8 The two bits shown in the figure are wrong, that is, there are multi-bit errors. Combined with the above, it can be seen that the current off-chip verification technology cannot effectively correct multi-bit errors. On the contrary, due to the existence of multi-bit errors, new bit errors may be further generated in the data obtained after performing off-chip verification, causing data errors to be amplified layer by layer in various levels of verification inside and outside the chip.

[0058] In order to avoid the above situation, this embodiment designs a grouping method of bit grouping, which is defined by an error correction matrix. Further, by adding constraints to the error correction matrix, the positions of miscorrection that may be caused during data verification are constrained and adjusted to avoid the situation that may cause further amplification of errors in the future. Combined with the principle of data verification, the principle of data verification is to group the data to be verified, and each data to be verified is divided into one or more groups, each group contains and only contains one check bit, and the grouping rules of different data to be verified are different, so as to obtain error correction codes that are different from each other corresponding to the grouping rules, that is, each bit of the error correction code represents whether it is divided into the corresponding group. In essence, each error correction bit of the error correction code and each check bit of the check code are corresponding, that is, each error correction bit is obtained by XORing the corresponding check bit in the check code written and read. Therefore, for the check code, it is equivalent to completing the bit grouping. Specifically, after a certain bit of data is divided into a group corresponding to a certain check bit, whether an error occurs in the bit will affect the value of the check bit, and then affect the value of the error correction code generated based on the check code. For example, if an error occurs in the generated bit, the value of the check bit will change compared to the value of the check bit when writing, and the corresponding bit of the error correction code obtained based on the check code and the check code generated when writing is also 1. This is because the error correction code is usually obtained by performing XOR processing on the check code generated when writing and the check code generated when reading. Based on the defined grouping method, check codes are generated for the data when writing and reading respectively, and the check code when writing and the check code when reading are obtained. Subsequently, the XOR result of the two check codes, that is, the error correction code, is used to determine which bit has an error, thereby achieving single-bit error correction.

[0059] The error correction matrix of this embodiment defines the error correction code corresponding to each bit in each beat, that is, the design of bit grouping is essentially completed. By way of example, Table 1 is an example error correction matrix. As shown in Table 1, DQ0~DQ7 respectively represent eight data ports of a certain memory, 0~15 in the second row represent 16 beats, and pc0~pc7 respectively represent 8 bits of error correction code. It should be noted that here, the example is that the memory has eight data ports, that is, 8 bits of data are output per beat, a total of 16 beats are output, and the data length of the error correction code is 8 bits. It can be understood that the actual application is not limited to the situation shown in the table.

[0060] Table 1

[0061]

[0062] Combined with the data structure shown in the previous figure, for example, the 0th column under DQ0 represents the bit output by a certain memory through the data port DQ0 in the 1st beat, that is, d0 in the entire 128 bits. Correspondingly, the error correction code corresponding to d0 is pc0~pc7 under this column, that is, 00000101; and so on, referring to the 1st column under DQ0, the error correction code corresponding to d8 is 11110101; referring to the 0th column under DQ3, the error correction code corresponding to d3 is 01100101. Specifically, the error correction matrix of this embodiment includes the error correction code corresponding to each bit in each beat, reflecting the check code affected when a single-bit error occurs in a certain bit. For example, referring to Table 1, it can be seen that the error correction code corresponding to d0 is 00000101, that is, the grouping situation is that d0 is divided into the group corresponding to the check code p5 and the check code p7. In other words, the error correction matrix actually defines the bit grouping situation in data verification. It should be noted that PB in the above table (the cell to the right of DQ7) is the error correction code of the check code. In practical applications, in order to ensure accurate data verification based on the check code, in addition to verifying the check data, the check code is also verified, that is, the error correction code of the check code is obtained, so as to avoid inaccurate data verification based on the check code due to errors in the check code itself. That is to say, Table 1 at least shows the error correction code corresponding to 128-bit data + 8-bit check code, a total of 136 bits.

[0063] Taking the case of a single-bit error as an example, assuming that the encoder 11 generates a first check code based on the write data and the bit grouping represented by the above error correction matrix, and obtains a second check code based on the read data and the above error correction matrix, then when a single-bit error occurs, for example, when d0 is an error bit, the error correction code Syn generated by the encoder 11 based on the first check code and the second check code will be 00000101. Correspondingly, the first error correction circuit 12 can determine the position d0 based on the error correction code output by the encoder 11 and the above error correction matrix, thereby performing data flipping on the data under d0.

[0064] The above example uses a single-bit error as an example to illustrate the principle of the error correction matrix. In combination with the above, in order to avoid the problem of error amplification that may occur when there are multiple bit errors, the error correction matrix in this solution satisfies the following conditions: the XOR result of the error correction code corresponding to any multiple bits is not the same as the error correction code corresponding to any bit in the same beat as one of the multiple bits. In practical applications, the reason for the miscorrection is that the error correction bit of the error correction code is affected multiple times by multiple erroneous bits, resulting in an erroneous error correction code corresponding to a certain bit. For example, in combination with the example of Table 1 above, when the bit corresponding to the second column under DQ0 (the data output by the memory through DQ0 in the third beat, i.e., d16) and the bit corresponding to the third column (the data output by the memory through DQ0 in the fourth beat, i.e., d24) are both erroneous, the error correction bits pc3 and pc7 will be affected twice, resulting in an erroneous error correction code. Specifically, the check code mentioned in this embodiment refers to data generated based on the data to be checked, and the type corresponding to the data to be checked is the check code, and there are many situations as to whether the check code itself is accurate. For example, when multiple bit errors occur, the generated check code may be wrong, so the subsequently generated error correction code may also be wrong, that is, the error correction code does not point to the bit where the error actually occurred, which will lead to false correction.

[0065] In this embodiment, the error correction matrix satisfies that the XOR result of the error correction code corresponding to any multiple bits is not the same as the error correction code corresponding to any bit in the same beat as one of the multiple bits. Through this design, when a multi-bit error occurs, the generated error correction code does not point to the bit in the same beat as the multiple bits in which the error occurs, so as to avoid the error being amplified. For ease of understanding, Fig. 9 This is a data structure diagram of an example, such as Fig. 9 As shown, still combining the aforementioned single memory outputting 128 bits in 16 beats as an example, assuming that a multi-bit error occurs, as shown in the figure, still taking the error of bit d0 and bit d17 as an example, based on the error correction matrix that meets the conditions set in this embodiment, the bit corresponding to the obtained error correction code will not be the same-beat data of d0 and d17. Based on this, it is only necessary to meet the requirement that the generated error correction code does not point to any bit in the 128 bits, that is, no miscorrected bit is generated, or, as Fig. 9As shown, based on the bit grouping represented by the error correction matrix, the XOR result of the error correction code corresponding to d0 and d17 is designed to be the error correction code corresponding to d15 which is not in the same beat as d0 or d17, that is, even if the generated error correction code points to one of the 128 bits, as long as the erroneous bit pointed to and the multiple bits that originally had errors are not in the same beat, then when the off-chip check is performed later, since the error in the one-beat data where the erroneous bit is located is a single-bit error, the error correction of the erroneous bit can be achieved through the off-chip check. Among them, the number of "multiple bits" can be multiple, for example, double-bit error, triple-bit error, quad-bit error, or even eight-bit full error. Accordingly, in one example, the XOR result of the error correction code corresponding to any multiple bits is not the same as the error correction code corresponding to any bit in the same beat as one of the multiple bits, including: the XOR result of the error correction code corresponding to any two bits in the same beat is not the same as the error correction code corresponding to any bit in the same beat as one of the two bits.

[0066] In practical applications, there are many specific ways for the error correction matrix to meet the above conditions. In one example, in the error correction matrix, the XOR result of the error correction code corresponding to any multiple bits belonging to the same beat is not the same as the error correction code corresponding to any bit in the error correction matrix; the XOR result of the error correction code corresponding to any multiple bits belonging to different beats is not the same as the error correction code corresponding to any bit in the same beat as one of the multiple bits. For example, it can be understood that the value of each error correction bit of an 8-bit error correction code can be 0 or 1, so the value of an 8-bit error correction code exists in 2 to the 8th power, that is, 256 cases. Combined with the above example, assuming that the amount of data to be checked in the memory is 128 bits, only 128 of the 256 cases need to be selected to design the error correction code corresponding to each bit in each beat in the error correction matrix. In practical applications, the error correction code of the check code can also be considered, so another 8 cases need to be selected to design the error correction code of the check code, that is, a total of 136 cases out of 256 need to be occupied to design the error correction matrix. Based on this example, it can be seen that there are 120 cases left unused, so as an example, the XOR result of the error correction code corresponding to any multiple bits in the error correction matrix can be designed to be the value of these 120 cases. Correspondingly, when a multi-bit error occurs, the error correction code generated by the encoder 11 will not be the error correction code corresponding to any single bit in the error correction matrix, and the first error correction circuit 12 will not perform data flipping on the data in 128 bits based on the error correction code, thereby avoiding the generation of miscorrected bits. Through the above scheme, there is no need to add new check bits, and the data error can be avoided from being amplified when a multi-bit error occurs.

[0067] Specifically, the encoder 11 receives the written data during writing and receives the read data during reading, and obtains the check code in the writing stage and the check code in the reading stage in combination with the grouping method represented by the error correction matrix, and obtains the error correction code based on the two. Therefore, for the encoder 11, the data received at different stages are different. Therefore, in order to ensure the reliable operation of the encoder, in one example, Fig.10 FIG. 1 is a schematic diagram of a structure of an exemplary on-chip verification circuit. Fig.10 As shown, the on-chip verification circuit 31 further includes: a data selector 14;

[0068] The first input end of the data selector 14 receives the write data Data1, the second input end of the data selector 14 receives the read data Data2, and the output end of the data selector 14 is connected to the input end of the encoder 11 and the storage array 13;

[0069] The data selector 14 is used to output write data Data1 in the write phase and output read data Data2 in the read phase.

[0070] Specifically, the data selector 14 provides corresponding data to the encoder according to the current stage. For example, in the writing stage, the data selector 14 can respond to the selection signal and select to output the data received by the first input terminal. In the reading stage, the data selector 14 responds to the selection signal and selects to output the data received by the second input terminal. The selection signal mentioned here can be generated by the relevant circuit or component in the memory, and the selection signal can be designed to be in different level states to indicate the data selector to output the data of the first input terminal or the second input terminal. In practical applications, the specific implementation method of the data selector 14 is not limited. For example, it can include a multiplexer (MUX), or it can be implemented by circuit design based on some transmission circuits (such as transmission gates, controllable switches, etc.). The specific implementation method of the data selector is not limited here.

[0071] Through the data selector of this example, the write data required to generate the first check code can be provided to the encoder in the write phase, and the read data required to generate the second check code can be provided to the encoder in the read phase, thereby ensuring the normal operation of the encoder, avoiding data verification errors caused by data reception errors, and improving the accuracy and reliability of data verification. In addition, data selection and output are performed through the data selector, and there is no need to design a special data transmission circuit for the encoder, thereby effectively simplifying the circuit structure and reducing costs.

[0072] Based on the error correction code Syn output by the encoder 11, the first error correction circuit 12 performs single-bit error correction on the read data Data2 according to the error correction code Syn to obtain the first error correction data Correct Data1. The specific structure of the first error correction circuit 12 is not limited. In an example diagram, Fig.11 FIG. 1 is a schematic diagram of a structure of an exemplary on-chip verification circuit. Fig.11 As shown, the first error correction circuit 12 includes: a first decoder 121 and a first correction circuit 122;

[0073] An input end of the first decoder 121 is connected to the encoder 11. The first decoder 121 is used to receive the error correction code Syn output by the encoder 11, determine the first target position to be flipped based on the error correction code Syn and the error correction matrix, and output a first error correction instruction SBC pointing to the first target position;

[0074] The first correction circuit 122 is connected to the output end of the first decoder 121 . The first correction circuit 122 is used for receiving the read data Data2 , and performing data flipping on the bits at the first target position according to the first error correction instruction SBC to obtain the first error correction data Correct Data1 .

[0075] Specifically, the encoder 11 generates the error correction code Syn according to the first check code generated during writing and the second check code generated during reading. In combination with the above, it can be seen that the first check code and the second check code are generated by the encoder 11 according to the write data and the read data, respectively, based on the grouping method represented by the error correction matrix. Therefore, the error correction code generated by the encoder 11 according to the first check code and the second check code matches the conditions satisfied by the above error correction matrix. It can be seen that the error correction matrix satisfies that the bits corresponding to the XOR results of any multiple error correction codes are not in the same beat with any bit of the multiple bits. By limiting the above conditions, single-bit errors can be accurately determined based on the error correction matrix, thereby performing single-bit error correction, and avoiding error amplification when multiple bit errors occur. Specifically, for a single-bit error, the error correction code Syn generated by the encoder 11 accurately points to the error bit position. Accordingly, the first decoder 121 can accurately determine the error bit position corresponding to the error correction code Syn based on the error correction matrix according to the error correction code Syn output by the encoder 11, that is, at this time, the first target position obtained by the first decoder 121 is accurate and points to the actual error bit. Accordingly, the first decoder 121 outputs the first error correction instruction SBC pointing to the first target position. The first correction circuit 122 receives the read data Data2 and the first error correction instruction SBC output by the first decoder 121 pointing to the first target position, and according to the first error correction instruction SBC, performs data flipping on the bit at the first target position in the read data Data2, for example, if the bit at the first target position in the read data is 1, it is modified to 0, and if it is 0, it is modified to 1. It can be understood that since the error correction code Syn provided by the encoder 11 is accurate in the case of a single-bit error, the first error correction instruction SBC output by the first decoder according to the error correction code Syn is also accurate, so the data flipping performed by the first correction circuit 122 can achieve accurate error correction.

[0076] In the case of multiple bit errors, based on the conditions satisfied by the error correction matrix, the error correction code Syn generated by the encoder 11 is inaccurate, that is, it does not accurately point to the actual error bit. Specifically, the error correction code Syn at this time may not be the error correction code corresponding to any single bit in the error correction matrix, or it may be the error correction code corresponding to a single bit in the error correction matrix, but the single bit is not in the same beat as the actual error bit. Accordingly, the first decoder 121 may not be able to identify the first target position based on the error correction matrix according to the error correction code Syn output by the encoder 11 at this time, and cannot output a recognizable first error correction instruction SBC. For example, the first decoder 121 may not output the first error correction instruction, or output a pre-default invalid instruction, for example, an all-zero instruction, indicating that no data flipping is performed on any bit of the read data. Accordingly, the first correction circuit 122 does not flip the data on any bit of the read data, thereby ensuring that the data error is limited to the original error bit range, and no new bit error is generated. Alternatively, the first decoder 121 can obtain the first target position according to the error correction code Syn output by the encoder 11 at this time, but the first target position at this time does not accurately point to the actual error bit, but points to a bit in other beats. Correspondingly, the first error correction instruction SBC output by the first decoder 121 is also inaccurate. The first correction circuit 122 performs data flipping on the bit under the first target position pointed to by the first error correction instruction SBC at this time, but the data flipping at this time does not achieve effective data error correction, but generates a false correction. Since the false correction bit is not in the same beat as any bit where the actual error occurs, it can be corrected by off-chip verification later, so as to also achieve that the final data error is limited to the original error bit range, and will not cause new uncorrectable bit errors, thereby avoiding data errors from being amplified.

[0077] In practical applications, the error correction matrix can be pre-stored in the encoder 11 and the first decoder 121, so that the first decoder 121 determines the first target position based on the error correction matrix and outputs the first error correction instruction SBC. In this example, the first error correction circuit includes a first decoder and a first correction circuit. The first decoder can determine the position to be flipped based on the error correction matrix according to the error correction code output by the encoder, and output the first error correction instruction pointing to the position to be flipped. The corresponding first correction circuit performs data flipping on the bits at the position to be flipped to obtain the first error correction data. In this example, since the signals generated by the above circuits are all obtained based on the error correction matrix that meets specific conditions, it is possible to avoid miscorrection or the generated miscorrection can be corrected by off-chip verification, thereby achieving accurate and effective single-bit error correction, while effectively avoiding data errors from being amplified for multi-bit error situations.

[0078] In practical applications, in order to ensure accurate and reliable data transmission, a circuit for improving the accuracy of data transmission is also provided. In one example, Fig.12 FIG. 1 is a schematic diagram of a structure of an exemplary on-chip verification circuit. Fig.12 As shown, the on-chip verification circuit 31 further includes: a plurality of buffer circuits, including:

[0079] A first buffer circuit 21, wherein an input end of the first buffer circuit 21 receives the write data Data1, and an output end of the first buffer circuit 21 is connected to a first input end of the data selector 14, for buffering and outputting the received write data Data1;

[0080] A second buffer circuit 22, wherein the input end of the second buffer circuit 22 is connected to the output end of the data selector 14, and the output end of the second buffer circuit 22 is connected to the storage array 13, and is used for buffering and outputting the write data Data1 output by the data selector 14 in the write phase;

[0081] A third buffer circuit 23, where an input end of the third buffer circuit 23 is connected to the encoder 11, and an output end of the third buffer circuit 23 is connected to the storage array 13, and is used to buffer and output the first check code output by the encoder 11 during the writing phase;

[0082] A fourth buffer circuit 24, wherein an input end of the fourth buffer circuit 24 is connected to the storage array 13, and an output end of the fourth buffer circuit 24 is connected to the encoder 11, and is used for buffering and outputting the first check code read from the storage array 13 in a reading phase;

[0083] a fifth buffer circuit 25, wherein an input end of the fifth buffer circuit 25 is connected to the memory array 13, and an output end of the fifth buffer circuit 25 is connected to the second input end of the data selector 14 and the first error correction circuit 12, and is used for buffering and outputting the read data Data2 read from the memory array 13 in the read phase;

[0084] The sixth buffer circuit 26 has an input end connected to the output end of the first error correction circuit 12 , and an output end of the sixth buffer circuit 26 is used to buffer and output the first error correction data Correct Data1 output by the first error correction circuit 12 .

[0085] The specific structure of the buffer circuit is not limited. As an example, the buffer circuit may include an even number of inverters connected in series. For example, taking the first buffer circuit 21 as an example, Fig.13 Schematic diagram of a buffer circuit as an example. Fig.13As shown, the first buffer circuit 21 may include an even number of inverters 211 connected in series. It should be noted that other buffer circuits may also adopt the illustrated structure. In practical applications, when designing the number of inverters in the buffer circuit, the delay on each path may also be considered to optimize signal synchronization and match signal timing.

[0086] The signal transmission conditions in each stage are introduced by way of example with reference to the diagram: In the writing stage, the externally input write data Data1 is transmitted to the first input terminal of the data selector 14. At this time, since it is in the writing stage, the data selector 14 selects to output the write data received by the first input terminal. Accordingly, the write data output by the data selector 14 is transmitted to the storage array 13 on the one hand to realize the storage of the write data, and is also transmitted to the encoder 11 on the other hand. In this stage, the encoder 11 generates a first check code ECC code according to the received write data and the grouping method represented by the error correction matrix, and outputs it to the storage array 13 to store the check code during writing. The above is the relevant signal transmission conditions in the writing stage.

[0087] Next, when it is necessary to read the data stored in the storage array 13, the read data Data2 read from the storage array 13 is transmitted to the second input end of the data selector 14 and the data input end of the first error correction circuit 12, and the first check code ECC code read from the storage array 13 is transmitted to the encoder 11. At this time, since it is in the reading stage, the data selector 14 selects to output the read data received at the second input end to the encoder 11. Correspondingly, the encoder 11 generates a second check code according to the read data provided by the data selector 14 at this time and the grouping method represented by the error correction matrix, and obtains the error correction code Syn according to the second check code and the first check code read from the storage array and outputs it to the first error correction circuit 12. The second error correction circuit 12 performs single-bit error correction on the read data according to the error correction code provided by the encoder 11, obtains the first error correction data Correct Data1, and outputs it to the outside of the chip.

[0088] This example can achieve buffered transmission of signals by setting a buffer circuit, thereby ensuring the accuracy and reliability of signal transmission, and can further optimize signal synchronization and match signal timing by adjusting the delay characteristics of the buffer circuit.

[0089] Furthermore, while avoiding data error amplification, it is also hoped to achieve effective error correction of multi-bit errors. In one example, in combination with the above-mentioned error correction matrix, it is also considered to set error correction codes corresponding to multi-bit errors to achieve effective error correction of multi-bit errors. To achieve the above-mentioned multi-bit error correction, as an example, in the error correction matrix, the XOR results of the error correction codes corresponding to different multiple bits belonging to the same beat are different. It can be understood that, based on the verification principle, the XOR results of the error correction codes corresponding to multiple bits can reflect the error correction codes generated when errors occur in these multiple bits. At the same time, considering that the single-bit error in each beat can also be corrected by off-chip verification, therefore, in order to improve the verification efficiency and achieve multi-bit error correction, this example specifically targets the data in the same beat, and further limits the XOR results of the error correction codes corresponding to different multiple bits belonging to the same beat in the error correction matrix to be different. The "different multiple bits" mentioned here refer to different combination contents. Combined with the data structure of the above example, taking each memory having eight data ports DQ0~DQ7 as an example, it can be known that the memory outputs 8 bits per beat, for example, the first beat outputs d0~d7 from DQ0~DQ7, and the second beat also outputs d8~d15 from DQ0~DQ7. Correspondingly, there are multiple combinations of 8 bits per beat to form a multi-bit combination. For example, taking a double bit under a certain beat as an example, the bits output by DQ0 and DQ1 are one combination, the data output by DQ2 and DQ3 are one combination, and the data output by DQ0 and DQ2 are also another combination. In short, as long as the bits in the combination are not exactly the same, they are regarded as different multi-bits. In addition, here only a double bit is used as an example. It can be understood that the multi-bit here is not limited to the case of two bits, for example, it can also be three bits, four bits, etc. Based on the error correction matrix meeting the above characteristics, an error correction matrix for the multi-bit situation can be established, that is, the error correction matrix includes error correction codes corresponding to each group of multi-bits under the same beat. The error correction code can be obtained by the XOR result of the error correction code corresponding to each bit in the group of multiple bits. Subsequently, based on the error correction matrix for the multi-bit situation, when it is determined that a multi-bit error has occurred in the same beat, the multiple bits where the error has occurred can be determined based on the current error correction code combined with the error correction matrix containing the error correction code corresponding to each group of multiple bits in the same beat, so as to achieve multi-bit error correction.

[0090] Combining the above, as an example, Fig.14 FIG. 1 is a schematic diagram of a structure of an exemplary on-chip verification circuit. Fig.14 As shown, the on-chip verification circuit 31 further includes: a second error correction circuit 15;

[0091] The second error correction circuit 15 is connected to the encoder 11, receives a multi-bit error correction instruction DUE, and read data Data2 or the first error correction data Correct Data1, and is used to respond to the multi-bit error correction instruction DUE pointing to the target beat number, and according to the error correction code Syn output by the encoder 11, performs multi-bit error correction on the received data and then outputs the second error correction data CorrectData2.

[0092] Among them, the multi-bit error correction instruction DUE pointing to the target beat number indicates that the read data Data2 has a multi-bit error located in the same beat, and the multi-bit error occurs in the target beat number. As an example, the multi-bit error correction instruction can be generated by off-chip verification. Specifically, in combination with the foregoing content, the off-chip verification is used to perform data verification on each beat of data output by all memories under the same library, and the off-chip verification can realize single-bit error correction and multi-bit detection. Therefore, for the single-bit error in each beat, it can be effectively corrected by off-chip verification. For the multi-bit error in each beat, when the off-chip verification detects that there is a multi-bit error in the current verified beat, a multi-bit error correction instruction DUE can be issued to the on-chip verification circuit, and the multi-bit error correction instruction points to the current verified beat, that is, the target beat number. In one example, if the second error correction circuit 15 of the on-chip verification circuit receives a multi-bit error correction instruction returned by the off-chip verification circuit, subsequent operations can be performed based on the error correction code. It should be noted that the second error correction circuit 15 receiving the multi-bit error correction instruction DUE mentioned here is only used to indicate the signal connection relationship of the second error correction circuit. In combination with the actual situation, the reception here also includes receiving but not receiving. For example, only when it is determined based on the current error correction code that the memory itself needs to respond to the multi-bit error correction instruction, the multi-bit error correction instruction is received to reduce power consumption. This is because, although the off-chip check can realize multi-bit detection, the off-chip check cannot locate which multi-bit errors occur, and it is also impossible to determine which memory outputs the multi-bit errors in this beat. Therefore, after the off-chip check detects that there are multi-bit errors in this beat, it will send a multi-bit error correction instruction to all memories under the library. Correspondingly, the second error correction circuit of the on-chip check circuit of each memory will only perform subsequent multi-bit error correction processing after determining that the currently received multi-bit error correction instruction is valid.

[0093] As an example, whether a multi-bit error correction instruction needs to be responded to for the memory where the on-chip check circuit is located can be determined based on the error correction code currently output by the encoder 11. For example, if the encoder 11 in the on-chip check circuit of a certain memory does not output an error correction code or the output error correction code is a default invalid code, that is, the result of the on-chip check is characterized as no data error. Therefore, the multi-bit error detected by the on-chip check circuit may occur in the data output by other memories. Therefore, even if the second error correction circuit of the on-chip check circuit receives a multi-bit error correction instruction sent by the off-chip check circuit, there is no need to perform data error correction, so the multi-bit error correction instruction sent to this memory is regarded as not requiring a response. For another example, if the error correction code currently output by the encoder 11 in the on-chip check circuit of a certain memory is not empty or a default invalid code, but the error correction code is not the error correction code corresponding to any multi-bit combination in the error correction matrix, that is, the error correction code cannot be identified, then the multi-bit error correction instruction is regarded as not requiring a response, and data error correction is also not performed. If a multi-bit error correction instruction needs to be responded to, for example, the error correction code output by the current encoder 11 falls into any of the error correction codes corresponding to different multi-bits defined in the error correction instruction, it means that a multi-bit error occurs in the present memory, and accordingly, the second error correction circuit 15 can determine the multi-bits where the error occurs according to the multi-bit combination corresponding to the error correction code, and then perform data error correction. The specific object of error correction can be the read data, and the corresponding second error correction data after error correction can be transmitted to the off-chip verification circuit for off-chip verification again. Or the object of error correction can also be the first error correction data, and the second error correction data obtained after error correction can be transmitted to the off-chip verification circuit, which integrates the first error correction data and the second error correction data, and then performs off-chip verification again. That is to say, in some embodiments, the second error correction circuit 15 will determine whether to respond to the multi-bit error correction instruction DUE based on the error correction code Syn.

[0094] In practical applications, the specific structure of the second error correction circuit is not limited. In one example, Fig.15 FIG. 1 is a schematic diagram of a structure of an exemplary on-chip verification circuit. Fig.15 As shown, the second error correction circuit 15 comprises: a second decoder 151 and a second correction circuit 152;

[0095] The input end of the second decoder 151 is connected to the encoder 11, and the second decoder 151 receives the error correction code Syn and the multi-bit error correction instruction DUE, and is used to respond to the multi-bit error correction instruction DUE pointing to the target beat number, determine the second target position to be flipped based on the target beat number pointed to by the multi-bit error correction instruction DUE, the error correction code Syn and the error correction matrix, and output the second error correction instruction DBC pointing to the second target position;

[0096] The second correction circuit 152 is connected to the output end of the second decoder 151 and is used for receiving the read data Data2 or the first error correction data Correct Data1 and performing data error correction on the bits at the second target position according to the second error correction instruction to obtain the second error correction data Correct Data2.

[0097] Specifically, the encoder 11 generates the error correction code Syn according to the first check code generated during writing and the second check code generated during reading. In combination with the above, it can be seen that the first check code and the second check code are generated by the encoder 11 according to the write data and the read data, respectively, based on the grouping method represented by the error correction matrix. Therefore, the error correction code generated by the encoder 11 according to the first check code and the second check code matches the conditions satisfied by the above error correction matrix. It can be seen that the error correction matrix also satisfies that the XOR results of the error correction codes corresponding to different multiple bits belonging to the same beat are different. As an example, another error correction matrix can be established, which is also referred to as a multi-bit error correction matrix below, including error correction codes corresponding to different multiple bit combinations of the same beat, and the error correction code corresponding to each combination is obtained based on the XOR result of the error correction code corresponding to each bit in the combination.

[0098] In the case of multi-bit errors, the off-chip check circuit will send a multi-bit error correction instruction DUE to the on-chip check circuits of all memories under the library. Taking the on-chip check circuit of a certain memory as an example, the second decoder 151 of the on-chip check circuit detects whether the error correction code Syn output by the current encoder 11 is any error correction code defined in the multi-bit error correction matrix. If not, error correction is not performed. On the contrary, if the error correction code is a certain error correction code defined in the multi-bit error correction matrix, then the various bits under the combination are determined according to the multi-bit combination corresponding to the error correction code in the multi-bit error correction matrix, for example, it is determined that the bit combination corresponding to the error correction code includes the bits output by the data ports DQ0 and DQ1. Further, combined with the target beat number pointed to by the multi-bit error correction instruction DUE, for example, pointing to the second beat, it can be determined that the multi-bits in error are the data output by DQ0 and DQ1 of the memory in the second beat, combined with the data structure of the aforementioned example, that is, d8 and d9. After determining the second target position where a multi-bit error occurs, the second decoder 151 outputs a second error correction instruction pointing to the second target position to the second correction circuit 152. Accordingly, the second correction circuit 152 performs data flipping on the bits at the second target position in the read data, such as d8 and d9 in combination with the above example; or, the second correction circuit 152 may also perform data flipping on the bits at the second target position in the first error correction data Correct Data1 output by the first error correction circuit 12, to achieve multi-bit error correction. The second correction circuit may have multiple correction objects. For multi-bit error correction of the read data, there is no need for an off-chip verification circuit to perform additional processing, thereby improving the efficiency of the off-chip verification. For multi-bit error correction of the first error correction data, there is no need to set a cache structure for caching the read data for the second error correction circuit, thereby simplifying the structure of the on-chip verification circuit. Accordingly, in one example, the second correction circuit 152 is connected to the data input end of the first error correction circuit 12 for receiving the read data Data2, or the second correction circuit 152 is connected to the output end of the first error correction circuit 12. Specifically, Fig.15 In the example, multi-bit error correction is performed on the first error correction data.

[0099] In this example, the second error correction circuit includes a second decoder and a second correction circuit. The second decoder determines the multi-bit error position based on the error correction code and the target number of beats pointed to by the multi-bit instruction and the error correction code corresponding to the multi-bit combination in the error correction matrix. The second correction circuit corrects the corresponding bits according to the second error correction instruction pointing to the multi-bit error position, thereby avoiding data error amplification and realizing multi-bit error correction, thereby improving the accuracy and reliability of data verification.

[0100] In practical applications, in order to ensure accurate and reliable data transmission, a circuit for improving the accuracy of data transmission is also provided. Fig.15As shown, the on-chip verification circuit 31 also includes:

[0101] A seventh buffer circuit 27, wherein an input end of the seventh buffer circuit 27 receives a multi-bit error correction instruction DUE, and an output end of the seventh buffer circuit 27 is connected to the second decoder 151, and is used for buffering and outputting the multi-bit error correction instruction DUE;

[0102] The eighth buffer circuit 28 has an input end connected to the output end of the second error correction circuit 15 , and an output end of the eighth buffer circuit 28 is used to buffer and output the second error correction data Correct Data2 output by the second error correction circuit 15 .

[0103] The specific structure of the buffer circuit is not limited. As an example, the buffer circuit may include an even number of inverters connected in series. The signal transmission conditions in each stage are introduced by way of example in combination with the diagram: when the off-chip check circuit detects that there are multiple-bit errors in the current beat, a multiple-bit error correction instruction DUE pointing to the current beat is sent to the seventh buffer circuit 27 of the on-chip check circuit of all memories; taking a certain memory as an example, the seventh buffer circuit 27 of the on-chip check circuit of the memory buffers and outputs the received multiple-bit error correction instruction DUE to the second decoder 151, and the second decoder 151 outputs a second error correction instruction DBC pointing to the position where the multiple-bit error occurs according to the target beat number pointed to by the multiple-bit error correction instruction provided by the seventh buffer circuit 27 and the error correction code Syn currently output by the encoder 11, in combination with the error correction matrix; the second correction circuit 152 performs data error correction on the corresponding bits in the read data or the first error correction instruction according to the second error correction instruction DBC to obtain the second error correction data Correct Data2, uses the output end of the second correction circuit 152 as the output end of the second error correction circuit 15, and outputs the second error correction data Correct Data2 to the eighth buffer circuit 28, and the eighth buffer circuit 28 buffers and outputs the second error correction data Correct Data2 to the outside of the chip.

[0104] This example can achieve buffered transmission of signals by setting a buffer circuit, thereby ensuring the accuracy and reliability of signal transmission, and can further optimize signal synchronization and match signal timing by adjusting the delay characteristics of the buffer circuit.

[0105] The on-chip check circuit provided in the embodiment of the present application includes an encoder and a first error correction circuit, wherein the encoder is responsible for generating check codes for the writing and reading stages, and obtaining an error correction code based on the check codes of the two stages; further, the first error correction circuit performs single-bit error correction on the data read out in the reading stage according to the error correction code. The check code in this scheme is generated by the encoder based on the bit grouping represented by the error correction matrix, and the error correction matrix includes the error correction code corresponding to each bit in each beat, and satisfies that the bit corresponding to the XOR result of any multiple error correction codes is not in the same beat with any bit of the multiple bits, so even if there are multiple bit errors that lead to the generation of a miscorrected error correction code, since the miscorrected error correction code is not in the same beat with the bit where the multiple bit errors occur, it will not cause new multi-bit errors in the same beat, thereby avoiding further expansion of data errors and improving the reliability of verification.

[0106] Embodiment 2

[0107] Fig.16 A structural example diagram of a memory is shown as follows: Fig.16 As shown, the memory includes: a storage array 13, and an on-chip verification circuit 31 as any of the above examples.

[0108] In combination with the scheme of the above-mentioned embodiment, DRAM is taken as an example: in the writing stage, the on-chip check circuit 31 transmits the write data Data1 to the storage array 13, and generates a first check code ECC code based on the write data Data1 and the bit group represented by the error correction matrix and stores it in the storage array 13; in the reading stage, the on-chip check circuit 31 reads the first check code ECC code and the read data Data2 from the storage array, generates a second check code based on the read data Data2 and the bit group represented by the error correction matrix, obtains an error correction code based on the first check code and the second check code, and performs single-bit error correction on the read data Data2 based on the error correction code, and outputs the first error correction data Correct Data1. Among them, the error correction matrix includes the error correction code corresponding to each bit in each beat, and the error correction matrix satisfies: the bit corresponding to the XOR result of any multiple error correction codes is not in the same beat with any bit of the multiple bits, so as to avoid the data error being amplified when a multi-bit error occurs.

[0109] In the memory provided by this embodiment, the on-chip check circuit includes an encoder and a first error correction circuit, wherein the encoder is responsible for generating check codes for the writing and reading stages, and obtaining an error correction code based on the check codes of the two stages; further, the first error correction circuit performs single-bit error correction on the data read out in the reading stage according to the error correction code. The check code in this scheme is generated by the encoder based on the bit grouping represented by the error correction matrix, and the error correction matrix includes the error correction code corresponding to each bit in each beat, and satisfies that the bit corresponding to the XOR result of any multiple error correction codes is not in the same beat with any bit of the multiple bits, so even if there are multiple bit errors that lead to the generation of a miscorrected error correction code, since the miscorrected error correction code is not in the same beat with the bit where the multiple bit errors occur, it will not cause new multi-bit errors in the same beat, thereby avoiding further expansion of data errors and improving the reliability of verification.

[0110] Embodiment 3

[0111] Fig.17 FIG. 1 is a structural diagram of an exemplary storage device, such as Fig.17 As shown, the storage device includes: an off-chip verification circuit 41 and at least one memory 42 as shown in the example of the second embodiment;

[0112] The off-chip verification circuit 41 is connected to at least one memory 42 and is used to verify each beat of data in the first error correction data Correct Data1 output by at least one memory 42 during the reading phase, and the verification includes single-bit error correction and multi-bit detection.

[0113] Combined with the scheme example of the above-mentioned embodiment: in the reading stage, each memory 42 obtains the first error correction data Correct Data1 based on the above-mentioned verification process, and outputs each beat of the first error correction data Correct Data1 beat by beat. The off-chip verification circuit 41 receives the first error correction data Correct Data1 output by all memories 42 in the current beat, and performs off-chip data verification. Combined with the above content, since the error correction matrix used in the on-chip verification meets specific conditions, the on-chip verification will not produce false corrections for multi-bit errors, or even if a false correction occurs, the location of the false correction bit will not cause the off-chip verification to produce new multi-bit errors in the same beat, thereby avoiding the data error from being amplified.

[0114] Furthermore, if there is a single-bit error in the data of the current shot, the off-chip check circuit 41 performs single-bit error correction on the data of the current shot, and if there are multi-bit errors in the data of the current shot, the off-chip check circuit 41 sends a multi-bit error correction instruction to all memories 42. In one example, the off-chip check circuit 41 includes: an indication circuit 411; an indication circuit 411, which is used to send a multi-bit error correction instruction DUE pointing to the target number of shots to all memories 42 if there are multi-bit errors in the same shot of data. Specifically, each memory 42 confirms whether the multi-bit error correction instruction is valid for itself, and if valid, performs multi-bit error correction and outputs the second error correction data Correct Data2. Among them, the memory can perform multi-bit error correction based on the read data, and can also perform multi-bit error correction based on the first error correction data.

[0115] Correspondingly, in order to obtain the final accurate data, the off-chip verification circuit 41 also includes: a processing circuit 412, which is used to perform the first data integration of the first error correction data output by different memories, and perform data verification on the integrated data; if there is no data error or it can be corrected, the off-chip verified data is output; if the memory needs to be corrected twice, after receiving the second error correction data, the erroneous data is replaced based on the second error correction data and the data is verified again, if there is no data error or it can be corrected, the off-chip verified data is output. Specifically, the processing circuit 412 performs the first integration to obtain the verification object of the off-chip verification according to the first error correction result obtained by each memory according to the single-bit error correction, that is, the data belonging to the current shot in the first error correction result of each memory is integrated. The data is verified, and if there is no data error or only a single-bit error (that is, it can be corrected) in the current shot data, the data after off-chip verification is output. Another situation is that if it is found that the integrated data, that is, the data currently captured by each memory, contains multi-bit errors, it is necessary to return to the memory for secondary correction. Accordingly, the indication circuit 411 sends a multi-bit error correction instruction to all memories. Combined with the aforementioned scheme, the memory that needs to respond to the instruction will perform multi-bit error correction on its own data and then output a second error correction result. After the processing circuit 412 receives the second error correction result after the secondary correction, it replaces the erroneous bits in the data obtained by the first integration, and performs data verification again. If the verification passes, the final accurate data is output.

[0116] In the storage device provided in this embodiment, the on-chip check circuit of the memory includes an encoder and a first error correction circuit, wherein the encoder is responsible for generating check codes in the writing and reading stages, and obtaining an error correction code based on the check codes of the two stages; further, the first error correction circuit performs single-bit error correction on the data read out in the reading stage according to the error correction code. The check code in this scheme is generated by the encoder based on the bit grouping represented by the error correction matrix, and the error correction matrix includes the error correction code corresponding to each bit in each beat, and satisfies that the bit corresponding to the XOR result of any multiple error correction codes is not in the same beat with any bit of the multiple bits, so even if there are multiple bit errors that lead to the generation of a miscorrected error correction code, since the miscorrected error correction code is not in the same beat with the bit where the multiple bit errors occur, it will not cause new multi-bit errors in the same beat, thereby avoiding further expansion of data errors and improving the reliability of verification.

[0117] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only.

[0118] It should be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. An on-chip verification circuit, characterized in that: Applied to a memory, the on-chip verification circuit comprises: An encoder connected to the storage array of the memory, and configured to generate a first check code according to the write data and the bit grouping represented by the error correction matrix in a write phase, and write the first check code into the storage array; and to generate a second check code according to the read data and the bit grouping represented by the error correction matrix in a read phase, and generate an error correction code based on the read first check code and the second check code; a first error correction circuit connected to the encoder, configured to receive the read data, and perform single-bit error correction on the read data according to the error correction code output by the encoder, and then output first error-corrected data; The error correction matrix includes an error correction code corresponding to each bit in each beat, and the error correction matrix satisfies: an XOR result of the error correction codes corresponding to any multiple bits is not the same as an error correction code corresponding to any bit in the same beat as one of the multiple bits.

2. The on-chip verification circuit according to claim 1, characterized in that: In the error correction matrix, an XOR result of the error correction codes corresponding to any multiple bits belonging to the same beat is not the same as the error correction code corresponding to any bit in the error correction matrix; The XOR result of the error correction codes corresponding to any multiple bits belonging to different beats is not the same as the error correction code corresponding to any bit located in the same beat as one of the multiple bits.

3. The on-chip verification circuit according to claim 1, characterized in that: The on-chip verification circuit further includes: a data selector; The first input end of the data selector receives the write data, the second input end of the data selector receives the read data, and the output end of the data selector is connected to the input end of the encoder and the storage array; The data selector is used to output the write data in the write phase and output the read data in the read phase.

4. The on-chip verification circuit according to claim 3, characterized in that: The first error correction circuit includes: a first decoder and a first correction circuit; The input end of the first decoder is connected to the encoder, and the first decoder is used to receive the error correction code output by the encoder, determine a first target position to be flipped based on the error correction code and the error correction matrix, and output a first error correction instruction pointing to the first target position; The first correction circuit is connected to the output end of the first decoder, and is used for receiving the read data and performing data flipping on the bits at the first target position according to the first error correction instruction to obtain the first error correction data.

5. The on-chip verification circuit according to claim 4, characterized in that: The on-chip verification circuit further includes: a plurality of buffer circuits, including: a first buffer circuit, wherein an input end of the first buffer circuit receives the write data, and an output end of the first buffer circuit is connected to a first input end of the data selector, and is used for buffering and outputting the received write data; a second buffer circuit, wherein an input end of the second buffer circuit is connected to an output end of the data selector, and an output end of the second buffer circuit is connected to the storage array, and is used for buffering and outputting the write data output by the data selector during the write phase; a third buffer circuit, wherein an input end of the third buffer circuit is connected to the encoder, and an output end of the third buffer circuit is connected to the storage array, and is used for buffering and outputting the first check code output by the encoder during the writing phase; a fourth buffer circuit, wherein an input end of the fourth buffer circuit is connected to the storage array, an output end of the fourth buffer circuit is connected to the encoder, and is used for buffering and outputting the first check code read from the storage array during the reading phase; a fifth buffer circuit, wherein an input end of the fifth buffer circuit is connected to the memory array, an output end of the fifth buffer circuit is connected to the second input end of the data selector and the first error correction circuit, and is used for buffering and outputting the read data read from the memory array in the read phase; A sixth buffer circuit, wherein an input end of the sixth buffer circuit is connected to an output end of the first error correction circuit, and an output end of the sixth buffer circuit is used for buffering and outputting the first error correction data output by the first error correction circuit.

6. The on-chip verification circuit according to claim 5, characterized in that: The buffer circuit includes an even number of inverters connected in series.

7. The on-chip verification circuit according to claim 1, characterized in that: The XOR result of the error correction codes corresponding to the arbitrary multiple bits is not the same as the error correction code corresponding to any bit located in the same beat as one of the multiple bits, including: The XOR result of the error correction codes corresponding to any two bits in the same beat is not the same as the error correction code corresponding to any bit in the same beat as one of the two bits.

8. The on-chip verification circuit according to any one of claims 1 to 7, characterized in that: In the error correction matrix, the XOR results of error correction codes corresponding to different multiple bits belonging to the same beat are different.

9. The on-chip verification circuit according to claim 8, characterized in that: The on-chip verification circuit further includes: a second error correction circuit; The second error correction circuit is connected to the encoder, receives a multi-bit error correction instruction, and the read data or the first error correction data, and is used to respond to the multi-bit error correction instruction pointing to the target beat number, perform multi-bit error correction on the received data according to the error correction code output by the encoder, and then output second error correction data; The multi-bit error correction instruction pointing to the target beat number indicates that a multi-bit error occurs in the read data in the same beat, and the multi-bit error occurs in the target beat number.

10. The on-chip verification circuit according to claim 9, characterized in that: The second error correction circuit includes: a second decoder and a second correction circuit; The input end of the second decoder is connected to the encoder, and the second decoder receives the error correction code and the multi-bit error correction instruction, and is used to respond to the multi-bit error correction instruction pointing to the target beat number, determine the second target position to be flipped based on the target beat number pointed to by the multi-bit error correction instruction, the error correction code and the error correction matrix, and output a second error correction instruction pointing to the second target position; The second correction circuit is connected to the output end of the second decoder, and is used to receive the read data or the first error correction data, and perform data error correction on the bits under the second target position according to the second error correction instruction to obtain the second error correction data.

11. The on-chip verification circuit according to claim 10, characterized in that: The second correction circuit is connected to a data input terminal of the first error correction circuit for receiving the read data, or the second correction circuit is connected to an output terminal of the first error correction circuit.

12. A memory, characterized in that: The invention comprises: a storage array and an on-chip verification circuit as claimed in any one of claims 1 to 11.

13. A storage device, characterized in that: include: An off-chip verification circuit and at least one memory as claimed in claim 12; The off-chip verification circuit is connected to the at least one memory and is used to verify each beat of the first error correction data output by the at least one memory during a reading phase, wherein the verification includes single-bit error correction and multi-bit detection.

14. The storage device according to claim 13, characterized in that: The off-chip verification circuit comprises: an indication circuit; The indication circuit is used to send a multi-bit error correction instruction pointing to the target beat number to all the memories if there are multi-bit errors in the same beat data.

15. The storage device according to claim 14, characterized in that: The off-chip verification circuit also includes: A processing circuit is used to perform a first data integration on the first error-corrected data output by different memories, and to perform data verification on the integrated data; if no data error exists or can be corrected, then the off-chip verified data is output; if the memory needs to perform a second correction, then after receiving the second error-corrected data, the erroneous data is replaced on the integrated data based on the second error-corrected data and the data is verified again; if no data error exists or can be corrected, then the off-chip verified data is output.

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