Filter, preparation method thereof and electronic equipment

Abstract

The invention provides a filter, a preparation method thereof and electronic equipment, and belongs to the technical field of passive devices, and the filter comprises a dielectric substrate, and at least one capacitor and at least one inductor which are arranged on the dielectric substrate; the capacitor comprises a first polar plate and a second polar plate which are oppositely arranged; the first polar plate is positioned on one side, close to the dielectric substrate, of the second polar plate; at least one of the first pole plate and the second pole plate is electrically connected with the inductor; the inductor comprises multiple layers of coil structures which are sequentially arranged on a dielectric substrate, and at least one first interlayer insulating layer is arranged between every two adjacent coil structures. The coil structures of the adjacent layers are electrically connected through first connecting via holes penetrating through the first interlayer insulating layers between the coil structures; the orthographic projections of any two of the multiple layers of coil structures on the dielectric substrate are partially overlapped.

Description

Technical Field

[0001] The present invention belongs to the technical field of passive devices, and in particular relates to a filter and a preparation method thereof, and an electronic device. Background Art

[0002] The advancement of communication technology has put forward higher requirements on the performance and size of electronic components. Among them, passive components such as capacitors, inductors, and resistors account for about 70% of the area of ​​​​the printed circuit board (PCB). With the continuous emergence of new technologies, such as Integrated Product Development (IPD) and other technologies, the area of ​​​​passive components can be reduced by more than 80%. IPD technology integrates the most common passive components in electronic components, effectively reducing the size of discrete components and the combination and routing of components.

[0003] Inductors are a vital component of electronic components. They can be used as discrete devices or as part of a circuit, such as a common LC filter or a connection trace in a package substrate. Traditional inductors have a large area in passive devices due to their spiral structure, so miniaturization and performance optimization of inductors are crucial to the development of inductors. Summary of the invention

[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides a filter and a preparation method thereof, and an electronic device.

[0005] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a filter, comprising a dielectric substrate, at least one capacitor and at least one inductor arranged on the dielectric substrate;

[0006] The capacitor comprises a first plate and a second plate which are arranged opposite to each other, wherein the first plate is located on a side of the second plate close to the dielectric substrate; at least one of the first plate and the second plate is electrically connected to the inductor;

[0007] The inductor comprises a multi-layer coil structure sequentially arranged on the dielectric substrate, and at least one first interlayer insulating layer is arranged between adjacent coil structures; the coil structures of adjacent layers are electrically connected through a first connecting via penetrating the first interlayer insulating layer therebetween;

[0008] The orthographic projections of any two of the multiple layers of the coil structures on the dielectric substrate partially overlap.

[0009] In some embodiments, the capacitor is disposed on a side of the inductor close to the dielectric substrate, and at least one second interlayer insulating layer is disposed between the capacitor and the inductor.

[0010] In some embodiments, the coil structure closest to the dielectric substrate in the multi-layer coil structure is a first coil structure; and the second pole plate is electrically connected to the first coil structure.

[0011] In some embodiments, the capacitor further includes a first lead terminal;

[0012] The first lead end and the second electrode plate are arranged in the same layer, and the two are an integrally formed structure; the first lead end and the first coil structure are electrically connected through a second connecting via, and the second connecting via passes through the second interlayer insulating layer between the second electrode plate and the first coil structure.

[0013] In some embodiments, the coil structure closest to the dielectric substrate in the multi-layer coil structure is a first coil structure;

[0014] The first pole plate and the first coil structure are arranged in the same layer and are electrically connected.

[0015] In some embodiments, the first pole plate and the first coil structure are an integrally formed structure.

[0016] In some embodiments, the coil structure adjacent to the first coil structure in the multi-layer coil structure is a second coil structure;

[0017] A third interlayer insulating layer is provided between the second coil structure and the dielectric substrate, and the third interlayer insulating layer covers the second pole plate, and the first pole plate and the first coil structure formed in one piece.

[0018] In some embodiments, the coil structure adjacent to the first coil structure in the multi-layer coil structure is a second coil structure;

[0019] A fourth interlayer insulating layer and a fifth interlayer insulating layer are provided between the second coil structure and the dielectric substrate, the fourth interlayer insulating layer is provided with a first accommodating portion penetrating along the thickness direction thereof, the first pole plate and the first coil structure formed integrally are confined in the first accommodating portion, and the surfaces of the first pole plate and the first coil structure formed integrally away from the dielectric substrate are flush with the surface of the fourth interlayer insulating layer away from the dielectric substrate;

[0020] The fifth interlayer insulating layer is arranged on a side of the fourth interlayer insulating layer away from the dielectric substrate, and the fifth interlayer insulating layer covers the second electrode plate.

[0021] In some embodiments, the coil structure closest to the dielectric substrate in the multi-layer coil structure is a first coil structure;

[0022] The first coil structure includes a first sub-coil and a second sub-coil which are stacked, and the first sub-coil is located on a side of the second sub-coil close to the dielectric substrate;

[0023] The first pole plate and the first sub-coil are arranged in the same layer and are electrically connected.

[0024] In some embodiments, the first pole plate and the first sub-coil are an integrally formed structure.

[0025] In some embodiments, a connection structure is further included, wherein the connection structure is arranged on a side of the inductor away from the dielectric substrate and is electrically connected to a third coil structure in the inductor that is farthest from the dielectric substrate through a third connection via; the third connection via penetrates a sixth interlayer insulating layer between the connection structure and the third coil structure.

[0026] In some embodiments, the first interlayer insulating layer between any adjacent coil structures includes a first surface and a second surface disposed opposite to each other along a thickness direction thereof, and the first surface and the second surface are parallel to a reference plane of the dielectric substrate extending along a first direction.

[0027] In some embodiments, any seventh interlayer insulating layer in the same layer as the coil structure includes a first surface and a second surface arranged opposite to each other along its thickness direction, and the first surface and the second surface are parallel to a reference plane of the dielectric substrate extending along the first direction.

[0028] In a second aspect, an embodiment of the present disclosure further provides a method for preparing a filter, comprising: providing a dielectric substrate, and forming at least one capacitor and at least one inductor on the dielectric substrate; wherein the step of forming at least one capacitor and at least one inductor comprises:

[0029] A first conductive pattern is formed on the dielectric substrate; the first conductive pattern at least includes a first plate of the capacitor;

[0030] A second conductive pattern is formed on a side of the first conductive pattern away from the dielectric substrate; the second conductive pattern includes a second electrode plate of the capacitor; at least one of the second electrode plate and the first electrode plate is electrically connected to the inductor;

[0031] A multi-layer third conductive pattern is formed on a side of the second conductive pattern away from the dielectric substrate, and at least one first interlayer insulating layer is formed between adjacent third conductive patterns; the third conductive pattern includes a coil structure of the inductor, and the coil structures of adjacent layers are electrically connected through a first connecting via penetrating the first interlayer insulating layer therebetween; and the orthographic projections of any two of the multi-layer coil structures on the dielectric substrate partially overlap.

[0032] In some embodiments, the forming of the first conductive pattern on the dielectric substrate includes: forming a first conductive pattern including the first electrode plate on the dielectric substrate;

[0033] The forming of a multi-layer third conductive pattern on a side of the second conductive pattern away from the dielectric substrate comprises: forming a multi-layer coil structure on a side of the second conductive pattern away from the dielectric substrate, wherein the coil structure closest to the dielectric substrate among the multi-layer coil structure is a first coil structure; and the first coil structure is electrically connected to the second pole plate through a second connecting via hole penetrating a second interlayer insulating layer between the first pole plate and the second pole plate.

[0034] In some embodiments, the coil structure closest to the dielectric substrate in the multi-layer coil structure of the inductor is a first coil structure;

[0035] Forming a first conductive pattern on the dielectric substrate includes:

[0036] A first conductive pattern including the first pole plate and the first coil structure is formed on the dielectric substrate.

[0037] In some embodiments, the first electrode plate and the first coil structure are an integrally formed structure; wherein, after forming the second conductive pattern, the method further includes:

[0038] A third interlayer insulating layer is formed on a side of the second conductive pattern away from the first conductive pattern; the third interlayer insulating layer covers the second electrode plate, and the first electrode plate and the first coil structure formed in one piece.

[0039] In some embodiments, the first electrode plate and the first coil structure are an integrally formed structure;

[0040] The first conductive pattern including the first electrode plate and the first coil structure is formed on the dielectric substrate, comprising:

[0041] forming a fourth interlayer insulating layer on the dielectric substrate; the fourth interlayer insulating layer comprises a first accommodating portion penetrating along a thickness direction thereof;

[0042] The first accommodating portion is filled with the first pole plate and the first coil structure formed integrally to form the first conductive pattern; the first pole plate and the first coil structure formed integrally are away from the surface of the dielectric substrate and are flush with the surface of the fourth interlayer insulating layer away from the dielectric substrate.

[0043] In some embodiments, after forming the second conductive pattern, the method further includes:

[0044] A fifth interlayer insulating layer is formed on a side of the second conductive pattern away from the first conductive pattern, and a surface of the fifth interlayer insulating layer away from the dielectric substrate is parallel to a reference plane of the dielectric substrate extending along the first direction.

[0045] In some embodiments, the step of forming any layer of the third conductive pattern includes:

[0046] forming a seventh interlayer insulating layer on the dielectric substrate formed with the second conductive pattern; the seventh interlayer insulating layer includes a second accommodating portion penetrating along a thickness direction thereof;

[0047] The coil structure material of the inductor is filled in the second accommodation portion to form the third conductive pattern; the third conductive pattern faces away from the surface of the dielectric substrate and is flush with the surface of the seventh interlayer insulating layer faces away from the dielectric substrate.

[0048] In some embodiments, the step of forming any layer of the third conductive pattern includes:

[0049] A third conductive pattern including the coil structure is formed by electroplating on a side of the first interlayer insulating layer facing away from the dielectric substrate.

[0050] In some embodiments, the dielectric substrate includes a glass substrate.

[0051] In a third aspect, an embodiment of the present disclosure further provides an electronic device, comprising a filter as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a front view of a planar (2D) spiral inductor in the prior art;

[0053] Figure 2 A schematic diagram of a filter provided in an embodiment of the present disclosure;

[0054] Figure 3 A front view of a filter provided by an embodiment of the present disclosure;

[0055] Figure 4 A schematic diagram of a specific structure of an exemplary filter provided in an embodiment of the present disclosure;

[0056] Figure 5 A schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure;

[0057] Figure 6 A schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure;

[0058] Figure 7 A schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure;

[0059] Figure 8 A schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure;

[0060] Figure 9a to Figure 9j Preparation provided for the embodiments of the present disclosure Figure 4 Schematic diagram of the filter shown;

[0061] Figure 10a to Figure 10h Preparation provided for the embodiments of the present disclosure Figure 5 Schematic diagram of the filter shown;

[0062] Figure 11a to Figure 11i Preparation provided for the embodiments of the present disclosure Figure 6 Schematic diagram of the filter shown;

[0063] Figure 12a to Figure 12h Preparation provided for the embodiments of the present disclosure Figure 7 Schematic diagram of the filter shown;

[0064] Figure 13a to Figure 13k Preparation provided for the embodiments of the present disclosure Figure 8 Schematic diagram of the filter shown.

[0065] The reference numerals are: 1, dielectric substrate; X, first direction;

[0066] 2. capacitor; 21. first electrode plate; 22. second electrode plate; 23. first lead terminal;

[0067] 3. Inductor; 31. First coil structure; 32. Second coil structure; 33. Third coil structure; O1. First connection end; O2. Second connection end; 311. First sub-coil; 312. Second sub-coil;

[0068] 41, first interlayer insulating layer; 42, second interlayer insulating layer; 43, third interlayer insulating layer; 44, fourth interlayer insulating layer; 45, fifth interlayer insulating layer; 46, sixth interlayer insulating layer; 47, seventh interlayer insulating layer; 40, insulating layer; Via1, first connecting via hole; Via2, second connecting via hole; Via3, third connecting via hole; 441, first accommodating portion; 471, second accommodating portion;

[0069] M1, a first conductive pattern; M2, a second conductive pattern; M3, a third conductive pattern;

[0070] 5. Connection structure; 51. First sub-connection layer; 52. Second sub-connection layer; 53. Barrier layer. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.

[0072] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0073] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.

[0074] In the related art, Figure 1 FIG. 1 is a front view of a planar (2D) spiral inductor in the prior art, as shown in FIG. Figure 1 As shown, 2D IPD currently uses a metal film layer to form a spiral inductor on the glass surface. Since the inductor is made of the same layer of metal, the area of ​​the inductor is large, resulting in a large area of ​​the final device, which is not conducive to the realization of miniaturized devices.

[0075] In view of this, the embodiments of the present disclosure provide a filter, which substantially eliminates one or more of the problems caused by the limitations and defects of the related art. Specifically, in the embodiments of the present disclosure, the filter includes a dielectric substrate, at least one capacitor and at least one inductor arranged on the dielectric substrate; the capacitor includes a first plate and a second plate arranged opposite to each other, and the first plate is located on a side of the second plate close to the dielectric substrate; at least one of the first plate and the second plate is electrically connected to the inductor; the inductor includes a multi-layer coil structure arranged on the dielectric substrate in sequence, and at least one first interlayer insulating layer is arranged between adjacent coil structures; the coil structures of adjacent layers are electrically connected through a first connecting via that penetrates the first interlayer insulating layer between the two; and the orthographic projections of any two of the multi-layer coil structures on the dielectric substrate partially overlap.

[0076] The embodiment of the present disclosure forms a three-dimensional spiral inductor (multi-layer coil structure) and interconnects it with a capacitor to form an LC filter. Since the orthographic projections of any two layers of coil structures in the three-dimensional spiral inductor on the dielectric substrate overlap, compared with the prior art, when forming a coil structure with the same number of turns, the present disclosure can reduce the coil area of ​​the inductor as a whole when viewed from above, thereby saving device space.

[0077] The specific structure of a filter provided by an embodiment of the present disclosure is described in detail below.

[0078] Figure 2 A schematic diagram of a filter provided in an embodiment of the present disclosure; Figure 3 A front view of a filter provided by an embodiment of the present disclosure; Figure 2 and Figure 3As shown, the filter includes a dielectric substrate 1, at least one capacitor 2 and at least one inductor 3 arranged on the dielectric substrate 1; the capacitor 2 includes a first pole plate 21 and a second pole plate 22 arranged opposite to each other, and the first pole plate 21 is located on a side of the second pole plate 22 close to the dielectric substrate 1; at least one of the first pole plate 21 and the second pole plate 22 is electrically connected to the inductor 3; the inductor 3 includes a multi-layer coil structure arranged on the dielectric substrate 1 in sequence, and at least one first interlayer insulating layer 41 is arranged between adjacent coil structures; the coil structures of adjacent layers are electrically connected through a first connecting via 1 penetrating the first interlayer insulating layer 41 between the two; and the orthographic projections of any two of the multi-layer coil structures on the dielectric substrate 1 partially overlap.

[0079] For example, Figure 3 As shown, the multi-layer coil structure includes N layers; the N-layer coil structure is also an N-turn three-dimensional spiral structure, and different coil structures are located in different layers. N≥2, and N is an integer. The end of the i-th coil structure is electrically connected to the head end of the i+1-th coil structure through the first connecting via 1 penetrating the first interlayer insulating layer 41; wherein i is an integer less than or equal to N. The inductor 3 includes two first connection terminals O1 and second connection terminals O2 electrically connected to other components, wherein the first connection terminal O1 is the head end of the first coil structure (that is, the first coil structure 31 described below), and the second connection terminal O2 is the end of the N-th coil structure (that is, the third coil structure 33 described below). The first coil structure is the coil structure located closest to the dielectric substrate 1 in the multi-layer coil structure; the N-th coil structure is the coil structure located farthest from the dielectric substrate 1 in the multi-layer coil structure.

[0080] For example, Figure 3 As shown, the orthographic projections of the coil structures in the multi-layer coil structure on the dielectric substrate 1 partially overlap.

[0081] In combination with the above examples, by arranging coils in a sequential manner and with most of their projections overlapping, the coil area of ​​the inductor 3 as a whole when viewed from above can be reduced, thereby saving device wiring space and facilitating the design of device miniaturization.

[0082] Figure 4 A schematic diagram of a specific structure of an exemplary filter provided in an embodiment of the present disclosure; Figure 5 A schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure; Figure 6 A schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure; Figure 7 A schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure; Figure 8 A schematic diagram of the specific structure of another exemplary filter provided in an embodiment of the present disclosure.

[0083] In some embodiments, Figure 4 As shown, the capacitor 2 is arranged on a side of the inductor 3 close to the dielectric substrate 1 , and at least one second interlayer insulating layer 42 is arranged between the capacitor 2 and the inductor 3 .

[0084] For example, Figure 4 As shown, a second interlayer insulating layer 42 is arranged between the capacitor 2 and the inductor 3, and the second interlayer insulating layer 42 covers the capacitor 2, that is, covers the first electrode plate 21, the second electrode plate 22 in the capacitor 2, and the insulating layer 40 between the first electrode plate 21 and the second electrode plate 22.

[0085] The capacitor 2 is arranged on the side of the inductor 3 close to the dielectric substrate 1 for only one example. Of course, the capacitor 2 can also be arranged on the side of the inductor 3 away from the dielectric substrate 1 , which is not specifically limited in the embodiments of the present disclosure.

[0086] In order to make the structure of the filter of the embodiment of the present disclosure clearer, taking the case where the capacitor 2 is arranged on the side of the inductor 3 close to the dielectric substrate 1 as an example, the filter of the embodiment of the present disclosure is described below with reference to a specific example.

[0087] The first example: Figure 4 As shown, the coil structure closest to the dielectric substrate 1 in the multi-layer coil structure is the first coil structure 31 ; the second pole plate 22 is electrically connected to the first coil structure 31 .

[0088] Exemplarily, the second electrode plate 22 may be electrically connected to the first coil structure 31 through a second connection via 2 penetrating through the second interlayer insulating layer 42 between the second electrode plate 22 and the first coil structure 31 .

[0089] In a possible implementation, Figure 2 As shown, the capacitor 2 further includes a first lead terminal 23 .

[0090] like Figure 4 As shown, the first lead end 23 and the second electrode plate 22 are arranged in the same layer, and the two are an integrally formed structure; the first lead end 23 and the first coil structure 31 are electrically connected through the second connecting via 2, and the second connecting via 2 penetrates the second interlayer insulating layer 42 between the second electrode plate 22 and the first coil structure 31. Here, the first electrode plate 21 and the second electrode plate 22 of the capacitor 2 are arranged opposite to each other, and the orthographic projections on the dielectric substrate 1 completely overlap. The capacitor 2 is provided with a first lead end 23, and the inductor 3 is connected through the first lead end 23 to avoid the coupling capacitor 2 generated between the capacitor 2 and the inductor 3 to affect the device.

[0091] for Figure 4The filter shown can reduce the coil area of ​​the inductor 3 in the top view plane by sequentially connecting and arranging coils with most of the projections overlapping, thereby saving device wiring space and facilitating the design of device miniaturization.

[0092] The second example: Figure 5 As shown, the coil structure closest to the dielectric substrate 1 in the multi-layer coil structure is the first coil structure 31; the first pole plate 21 and the first coil structure 31 are arranged in the same layer and are electrically connected.

[0093] In a possible implementation, Figure 5 As shown, the first pole plate 21 and the first coil structure 31 are an integrally formed structure. In this case, by providing the integrally formed first pole plate 21 and the first coil structure 31, the process steps can be reduced, thereby reducing the production cost. In addition, the integrally formed first pole plate 21 and the first coil structure 31 can effectively reduce the thickness of the overall structure of the inductor 3, thereby achieving a thin and light device.

[0094] In a possible implementation, Figure 5 As shown, the coil structure adjacent to the first coil structure 31 in the multi-layer coil structure is the second coil structure 32; a third interlayer insulating layer 43 is arranged between the second coil structure 32 and the dielectric substrate 1, and the third interlayer insulating layer 43 covers the second pole plate 22, and the integrally formed first pole plate 21 and the first coil structure 31.

[0095] In this case, a third interlayer insulating layer 43 is formed through a single patterning process to cover the second electrode 22, as well as the integrally formed first electrode 21 and the first coil structure 31, thereby achieving insulation between the capacitor 2 and the first coil structure 31 and the upper second coil structure 32, reducing the number of process steps and thus reducing production costs.

[0096] The third example: Figure 6 As shown, the coil structure closest to the dielectric substrate 1 in the multi-layer coil structure is the first coil structure 31; the first pole plate 21 and the first coil structure 31 are arranged in the same layer and are electrically connected.

[0097] In a possible implementation, Figure 6 As shown, the first pole plate 21 and the first coil structure 31 are an integrally formed structure. In this case, by generating the integrally formed first pole plate 21 and the first coil structure 31, the process steps can be reduced, thereby reducing the production cost. In addition, generating the integrally formed first pole plate 21 and the first coil structure 31 can effectively reduce the thickness of the overall structure of the inductor 3, thereby achieving a thin and light device.

[0098] Exemplarily, the integrally formed first electrode plate 21 and the first coil structure 31 can be formed by a seed layer through an electroplating process; the material of the seed layer can be selected from titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc.; the electroplating material can be selected from metal materials such as copper (Cu), gold (Au), aluminum (Al), and silver (Ag).

[0099] The present disclosure forms the integrally formed first pole plate 21 and the first coil structure 31 by electroplating growth of a seed layer, which can improve the adhesion between the integrally formed metal first pole plate 21 and the first coil structure 31 and the dielectric substrate 1 .

[0100] In a possible implementation, Figure 6 As shown, the coil structure adjacent to the first coil structure 31 in the multi-layer coil structure is the second coil structure 32; a fourth interlayer insulating layer 44 and a fifth interlayer insulating layer 45 are arranged between the second coil structure 32 and the dielectric substrate 1, the fourth interlayer insulating layer 44 is provided with a first accommodating portion 441 penetrating along the thickness direction thereof, the integrally formed first pole plate 21 and the first coil structure 31 are confined in the first accommodating portion 441, and the surfaces of the integrally formed first pole plate 21 and the first coil structure 31 facing away from the dielectric substrate 1 are flush with the surface of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1; the fifth interlayer insulating layer 45 is arranged on the side of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1, and the fifth interlayer insulating layer 45 covers the second pole plate 22.

[0101] In this case, the surface of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1 is flush with the surfaces of the integrally formed first electrode plate 21 and the first coil structure 31 facing away from the dielectric substrate 1, so that the surface of the fifth interlayer insulating layer 45 located on the fourth interlayer insulating layer 44, which is relatively arranged in the thickness direction, is parallel to the reference surface of the dielectric substrate 1 extending along the first direction X, thereby reducing the degree of undulation of some film layers, and even more, being able to form an interlayer insulating layer surface without high and low undulations, which is conducive to improving the thickness uniformity of some film layers at different positions, thereby improving the uniformity of device performance.

[0102] The fourth example: Figure 7 As shown, the coil structure closest to the dielectric substrate 1 in the multi-layer coil structure is the first coil structure 31; the first coil structure 31 includes a first sub-coil 311 and a second sub-coil 321 which are stacked, and the first sub-coil 311 is located on a side of the second sub-coil 321 close to the dielectric substrate 1; the first pole plate 21 is arranged in the same layer as the first sub-coil 311 and is electrically connected.

[0103] Exemplarily, there is no other structure between the stacked first sub-coil 311 and the second sub-coil 321 , that is, the second sub-coil 321 is arranged on the surface of the first sub-coil 311 away from the dielectric substrate 1 , and the two are seamlessly connected.

[0104] Exemplarily, the first sub-coil 311 and the second sub-coil 321 may be an integrally formed structure.

[0105] Exemplarily, the first sub-coil 311 may be a seed layer of the second sub-coil 321. The second sub-coil 321 is formed on the seed layer by an electroplating process, and the material of the second sub-coil 321 may be selected from metal materials such as copper (Cu), gold (Au), aluminum (Al), and silver (Ag). In this case, the adhesion between the second sub-coil 321 and the dielectric substrate 1 can be improved.

[0106] In a possible implementation, Figure 7 As shown, the first pole plate 21 and the first sub-coil 311 are an integrally formed structure. In this case, by providing the integrally formed first pole plate 21 and the first sub-coil 311, the process steps can be reduced, thereby reducing the production cost. In addition, the integrally formed first pole plate 21 and the first sub-coil 311 can effectively reduce the thickness of the overall structure of the inductor 3, thereby achieving a thin and light device.

[0107] Exemplarily, the material of the integrally formed first pole plate 21 and first sub-coil 311 may be titanium (Ti) having good adhesion, thereby improving the adhesion between the metal first pole plate 21 and the first sub-coil 311 and the dielectric substrate 1 .

[0108] The fifth example: Figure 8 As shown, the coil structure closest to the dielectric substrate 1 in the multi-layer coil structure is the first coil structure 31; the first pole plate 21 and the first coil structure 31 are arranged in the same layer and are electrically connected.

[0109] In a possible implementation, Figure 8 As shown, the first pole plate 21 and the first coil structure 31 are an integrally formed structure. In this case, by generating the integrally formed first pole plate 21 and the first coil structure 31, the process steps can be reduced, thereby reducing the production cost. In addition, generating the integrally formed first pole plate 21 and the first coil structure 31 can effectively reduce the thickness of the overall structure of the inductor 3, thereby achieving a thin and light device.

[0110] Exemplarily, the integrally formed first electrode plate 21 and the first coil structure 31 can be formed by a seed layer through an electroplating process; the material of the seed layer can be selected from titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc.; the electroplating material can be selected from metal materials such as copper (Cu), gold (Au), aluminum (Al), and silver (Ag).

[0111] The material of the integrally formed first pole plate 21 and first coil structure 31 in the disclosed embodiment may be titanium (Ti) with good adhesion, thereby improving the adhesion between the metal first pole plate 21 and first coil structure 31 and the dielectric substrate 1 .

[0112] In a possible implementation, Figure 8 As shown, the coil structure adjacent to the first coil structure 31 in the multi-layer coil structure is the second coil structure 32; a fourth interlayer insulating layer 44 and a fifth interlayer insulating layer 45 are arranged between the second coil structure 32 and the dielectric substrate 1, the fourth interlayer insulating layer 44 is provided with a first accommodating portion 441 penetrating along the thickness direction thereof, the integrally formed first pole plate 21 and the first coil structure 31 are confined in the first accommodating portion 441, and the surfaces of the integrally formed first pole plate 21 and the first coil structure 31 facing away from the dielectric substrate 1 are flush with the surface of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1; the fifth interlayer insulating layer 45 is arranged on the side of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1, and the fifth interlayer insulating layer 45 covers the second pole plate 22.

[0113] Continue as Figure 8 As shown, the first interlayer insulating layer 41 between any adjacent coil structures includes a first surface and a second surface that are oppositely arranged along the thickness direction thereof, and the first surface and the second surface are parallel to a reference plane extending along the first direction X of the dielectric substrate 1 .

[0114] Continue as Figure 8 As shown, any seventh interlayer insulating layer 47 in the same layer as the coil structure includes a first surface and a second surface arranged opposite to each other along its thickness direction, and the first surface and the second surface are parallel to a reference plane extending along the first direction X of the dielectric substrate 1 .

[0115] In combination with the above embodiments, Figure 8 The filter shown reduces the undulation of each film layer, forming an interlayer insulating layer surface with no ups and downs, which is beneficial to improving the thickness uniformity of each film layer at different positions, thereby improving the uniformity of device performance.

[0116] The above examples are structural descriptions of corresponding types of filters.

[0117] In some embodiments, a flattened film structure may be provided for various types of filters. Specifically, the first interlayer insulating layer 41 between any adjacent coil structures includes a first surface and a second surface that are arranged opposite to each other along the thickness direction thereof, and the first surface and the second surface are parallel to a reference plane of the dielectric substrate 1 extending along the first direction X, thereby improving the thickness uniformity of the first interlayer insulating layer 41 at different positions, thereby improving the uniformity of device performance.

[0118] In some embodiments, a flattened film layer structure may be provided for various types of filters. Specifically, any seventh interlayer insulating layer 47 in the same layer as the coil structure includes a first surface and a second surface arranged opposite to each other along its thickness direction, and the first surface and the second surface are parallel to a reference surface of the dielectric substrate 1 extending along the first direction X, thereby improving the thickness uniformity of the seventh interlayer insulating layer 47 in the same layer as the coil structure and the coil structure at different positions, thereby improving the uniformity of device performance.

[0119] In some embodiments, Figures 4 to 8 As shown, the filter also includes a connection structure 5, which is arranged on the side of the inductor 3 away from the dielectric substrate 1, and is electrically connected to the third coil structure 33 in the inductor 3 farthest from the dielectric substrate 1 through a third connection via 3; the third connection via 3 passes through the sixth interlayer insulating layer 46 between the connection structure 5 and the third coil structure 33.

[0120] Exemplarily, the connection structure 5 may be a copper pillar or a solder ball. The connection structure 5 may serve as a lead-out terminal of the inductor 3 .

[0121] Exemplarily, the connection structure 5 may include a first sub-connection layer 51 and a second sub-connection layer 52 located on a side of the first sub-connection layer 51 away from the dielectric substrate 1. The material of the first sub-connection layer 51 may be a metal material such as copper (Cu), gold (Au), aluminum (Al), silver (Ag), etc., and the material of the second sub-connection layer 52 may be a silver-tin alloy (Sn-Ag) or tin (Sn) and other materials. The embodiment of the present disclosure is described by taking the material of the first sub-connection layer 51 as copper (Cu) and the material of the second sub-connection layer 52 as silver-tin alloy (Sn-Ag) as an example.

[0122] Exemplarily, the connection structure 5 may further include a barrier layer 53 disposed between the first sub-connection layer 51 and the second sub-connection layer 52 ; the material of the barrier layer 53 may be nickel (Ni) to prevent Sn of the second sub-connection layer 52 from penetrating into the first sub-connection layer 51 .

[0123] Exemplarily, the sixth insulating layer includes a first surface and a second surface that are arranged opposite to each other along the thickness direction thereof, and the first surface and the second surface are parallel to a reference plane of the dielectric substrate 1 extending along the first direction X, thereby improving the thickness uniformity of the sixth interlayer insulating layer 46, and further improving the uniformity of the overall performance of the device.

[0124] In some embodiments, the dielectric substrate 1 may be made of glass, high-resistance silicon, ceramics and other materials with high insulation and low dielectric loss. Preferably, the dielectric substrate 1 is made of glass, which has a high dielectric constant and lower dielectric loss.

[0125] In addition, the embodiment of the present disclosure also provides a method for preparing a filter, which can be used to prepare any of the above filters. The method comprises: providing a dielectric substrate 1, forming at least one capacitor 2 and at least one inductor 3 on the dielectric substrate 1; wherein the steps of forming at least one capacitor 2 and at least one inductor 3 include:

[0126] S11 , forming a first conductive pattern M1 on a dielectric substrate 1 .

[0127] The first conductive pattern M1 at least includes the first electrode 21 of the capacitor 2 .

[0128] Exemplarily, for the filter of the first example, the first conductive pattern M1 only includes the first pole plate 21 ; for the filters of the second example to the fifth example, the first conductive pattern M1 includes the first pole plate 21 and the first coil structure 31 of the inductor 3 .

[0129] S12 , forming a second conductive pattern M2 on a side of the first conductive pattern M1 away from the dielectric substrate 1 .

[0130] The second conductive pattern M2 includes the second electrode plate 22 of the capacitor 2 ; at least one of the second electrode plate 22 and the first electrode plate 21 is electrically connected to the inductor 3 .

[0131] After forming the first conductive pattern M1, an insulating layer 40 is formed on the side of the first electrode 21 away from the dielectric substrate 1 to isolate the second electrode 22. Therefore, the step of forming the second electrode 22 includes: forming a second conductive pattern M2 including the second electrode 22 on the side of the insulating layer 40 away from the dielectric substrate 1.

[0132] S13 , forming a plurality of third conductive patterns M3 on a side of the second conductive pattern M2 away from the dielectric substrate 1 , and forming at least one first interlayer insulating layer 41 between adjacent third conductive patterns M3 .

[0133] The third conductive pattern M3 includes a coil structure of an inductor 3 , and the coil structures of adjacent layers are electrically connected through a first connecting via 1 penetrating a first interlayer insulating layer 41 therebetween; the orthographic projections of any two of the multilayer coil structures on the dielectric substrate 1 partially overlap.

[0134] The embodiment of the present disclosure forms a three-dimensional spiral inductor 3 (multi-layer coil structure) and interconnects it with the capacitor 2 to form an LC filter. Since the orthographic projections of any two layers of the coil structure in the three-dimensional spiral inductor 3 on the dielectric substrate 1 overlap, compared with the prior art, when forming a coil structure with the same number of turns, the present disclosure can reduce the overall coil area of ​​the inductor 3 in the top view plane, thereby saving device space.

[0135] In order to make the preparation method of the filter of the embodiment of the present disclosure more clear, the preparation methods of the filters of different examples are described below respectively.

[0136] In some embodiments, Figure 9a to Figure 9j Preparation provided for the embodiments of the present disclosure Figure 4 The schematic diagram of the filter is shown in Figure 9a to Figure 9j As shown, steps S21 to S27 are included, wherein:

[0137] S21, providing a dielectric substrate 1.

[0138] Exemplarily, a dielectric substrate 1 with a thickness of 0.15 to 2 mm and a mass production size is prepared according to the requirements of the process equipment. The material of the dielectric substrate 1 can be selected from glass, high-resistance silicon, ceramics and other materials with high insulation and low dielectric loss. In step S21, a cleaning process before preparation of the dielectric substrate 1 can be included, and ultrasonic cleaning is performed in sequence with organic solvents such as deionized water, ethanol, isopropanol, etc., and the ultrasonic time is at least 15 minutes. After ultrasonic cleaning, it is dried in an oven, and can be dried at 75°C for a certain time according to the last cleaning solvent.

[0139] S22, such as Figure 9a As shown, a first conductive pattern M1 including a first electrode plate 21 is formed on a dielectric substrate 1 .

[0140] For example, Figure 9aAs shown, the first bonding layer is prepared on the dielectric substrate 1 by methods including electroplating, chemical plating, etc., and can also be formed by sputtering. The material of the first bonding layer can generally be selected from metals or metal nitrides with high adhesion to glass, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc. The thickness of the bonding layer can be adjusted according to demand, and the thickness is generally between 30 and 100nm. Through the PVD process, the first conductive pattern material is deposited on the first bonding layer; the first conductive pattern material can generally be selected from metal materials with good conductive properties such as Au, Al, Ag, Cu, etc. The thickness of the first conductive pattern material can be made according to demand, and the thickness is generally between 0.2 and 2um. A layer of PR glue is coated on the surface of the first conductive pattern material away from the dielectric substrate 1. The PR glue uses ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected. The thickness can ensure that the surface of the first conductive pattern material is completely covered to a certain thickness, and the thickness of the PR glue can be set between 1um and 4um. Afterwards, the PR glue is exposed and developed using a mask, and the PR glue above the pattern of the first electrode 21 that needs to be retained is retained, and all other areas are removed. Afterwards, the first conductive pattern material outside the pattern is removed. When the first conductive pattern material is Cu, wet etching can be used. When the first conductive pattern material is Al, wet etching or dry etching can be used. Different metals can choose different etching methods. Afterwards, the PR glue above the metal pattern is removed to form a first conductive pattern M1 including the first electrode 21.

[0141] S23, such as Figure 9b As shown, a second conductive pattern M2 is formed on a side of the first conductive pattern M1 away from the dielectric substrate 1 .

[0142] The second conductive pattern M2 includes a second electrode plate 22 of the capacitor 2 , and the second electrode plate 22 is electrically connected to the inductor 3 .

[0143] For example, Figure 9bAs shown, an insulating layer material can be deposited on the side of the first conductive pattern M1 away from the dielectric substrate 1 by a CVD process. Silicon nitride (SiNx) can be selected as the insulating layer material to serve as the dielectric layer of the upper and lower plates of the capacitor 2. The thickness of the insulating layer material can be designed and determined according to the requirements of the capacitor 2 value, and the thickness can usually be set between 80 and 200 nm. Afterwards, a second conductive pattern material can be deposited on the side of the insulating layer material away from the dielectric substrate 1 by a PVD process. The second conductive pattern material can be selected from materials with good conductive properties such as Cu and Al. The metal thickness is made according to requirements, and the thickness can be selected between 0.2 and 2um. A second bonding layer can be formed between the insulating layer material and the second conductive pattern material. The second bonding layer can be selected from metals or metal nitrides with high adhesion such as Ti, Ta, TiN, TaN, etc. The thickness is adjusted according to the process capability and can be selected between 30 and 100 nm. Afterwards, a layer of PR glue is applied on the side of the second conductive pattern material facing away from the dielectric substrate 1. The PR glue uses ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected. The thickness can ensure that the surface of the second conductive pattern material is completely covered to a certain thickness. The thickness of the PR glue can be considered to be between 1um and 4um. Afterwards, use Mask to expose the PR glue and develop it. The PR glue above the pattern of the second electrode 22 that needs to be retained is retained, and all other areas are removed. Afterwards, the second conductive pattern material outside the pattern is removed. When the second conductive pattern material is Cu, wet etching can be used. When the second conductive pattern material is Al, wet etching or dry etching can be used. Different metals can choose different etching methods. Afterwards, remove the PR glue above the metal pattern to form a second conductive pattern M2 containing the second electrode 22. Afterwards, a layer of PR glue is formed on the side of the second conductive pattern M2 away from the dielectric substrate 1. The PR glue uses ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected. The thickness can ensure that the surface of the insulating layer material is completely covered to a certain thickness. The thickness of the PR glue can be considered to be between 1um and 4um. Afterwards, use Mask to expose the PR glue and develop it. The PR glue above the pattern of the insulating layer 40 that needs to be retained is retained, and all other areas are removed. Afterwards, the insulating layer material outside the pattern is removed, usually by dry etching. Afterwards, remove the PR glue above the insulating layer 40 pattern to form an insulating layer 40.

[0144] S24, such as Fig.9c As shown, a second interlayer insulating layer 42 is formed on the side of the second conductive pattern M2 facing away from the dielectric substrate 1 .

[0145] The second interlayer insulating layer 42 is provided with a second connection via hole via2 penetrating the second interlayer insulating layer 42 in a thickness direction thereof. The second electrode plate 22 is electrically connected to the first coil structure 31 through the second connection via hole via2 .

[0146] For example, Fig.9c As shown, the material of the second interlayer insulating layer 42 can be selected as a photosensitive PI material, and the thickness is determined according to the design requirements, usually between 3 and 8 um; through exposure and development, the PI material at the overlapping position of the first coil structure 31 and the second electrode plate 22 is removed, and solidified to form a second connecting via via2; the PI material is changed from a soft film to a hard film to increase the strength of the film layer. Since the PI material is usually a negative resin, the bottom size of the PI via is smaller than the top size of the via, and the slope angle can be adjusted between 20° and 90° by changing the process conditions to form the second interlayer insulating layer 42.

[0147] S25 , forming a plurality of third conductive patterns M3 on a side of the second interlayer insulating layer 42 away from the dielectric substrate 1 , and forming at least one first interlayer insulating layer 41 between adjacent third conductive patterns M3 .

[0148] At least a third conductive pattern M3 including a coil structure is formed by electroplating on a side of the first interlayer insulating layer 41 away from the dielectric substrate 1 .

[0149] Taking the inductor 3 including a three-layer coil structure as an example, the specific steps include steps S251 to S255, wherein:

[0150] S251, such as Figure 9d As shown, a first coil structure 31 is formed on a side of the second interlayer insulating layer 42 facing away from the dielectric substrate 1 .

[0151] Step S251 may include forming a first conductive film as a first seed layer on the side of the second interlayer insulating layer 42 away from the dielectric substrate 1 by methods including electroplating, chemical plating, etc., or by sputtering, and then spin coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the first seed layer away from the dielectric substrate 1 to form a first coil structure 31.

[0152] The material of the first conductive film is generally a metal or metal nitride with high adhesion such as Ti, Ta, TiN, TaN, etc. The material of the first coil structure is generally a metal material such as Au, Al, Ag, Cu, etc. The thickness of the first coil structure 31 is generally 3 to 7 um. In order to ensure the flatness of the first coil structure 31, the upper surface of the first coil structure 31 (i.e., the surface away from the dielectric substrate 1) can be processed by chemical mechanical polishing (CMP).

[0153] Exemplarily, the first conductive film can be formed by electroplating using an additive method or a subtractive method. For example, taking the additive method as an example, a first conductive film material is deposited on the side of the second interlayer insulating layer 42 away from the dielectric substrate 1 through a PVD process. The first conductive film material is generally Ti, and the thickness of the first conductive film material can be adjusted according to demand to ensure that the surface of the second interlayer insulating layer 42 is completely covered, especially to ensure that the first conductive film material in the PI via and on the side wall of the via is completely covered without breaking. Afterwards, a layer of PR glue is coated on the side of the first conductive film material away from the dielectric substrate 1. The PR glue uses ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be used. The thickness can be determined according to the thickness of the electroplated first coil structure 31. Usually, the thickness of the PR glue is greater than the thickness of the electroplated first coil structure 31; then, use Mask to expose the PR glue and develop it to form the pattern of the first coil structure 31, and remove the PR glue outside the pattern of the first coil structure 31; if positive photoresist is selected, the slope angle of the pattern is generally an acute angle. Combined with the slope angle of the edge of the subsequent electroplated metal pattern and the subsequent process, the closer the slope angle of the PR glue pattern is to a right angle, the better. If negative photoresist is selected, the slope angle of the pattern is generally an obtuse angle. Afterwards, Cu is electroplated on the first seed layer to form the first coil structure material. The thickness of the first coil structure material is determined according to demand, and can usually be selected between 3 and 7um. After that, the remaining PR glue is removed, the remaining first seed layer is completely exposed, and the first seed layer outside the first coil structure 31 pattern is completely etched away to prevent the first seed layer below the first coil structure 31 from being etched to form a chamfer and affect the bonding force between the film layers. The final shape is as follows: Figure 9d shown.

[0154] For example, Figure 9d As shown, the coil structure closest to the dielectric substrate 1 in the multilayer coil structure is the first coil structure 31 ; the first coil structure 31 is electrically connected to the second pole plate 22 through a second connecting via 2 penetrating through the second interlayer insulating layer 42 between the first coil structure and the second pole plate 22 .

[0155] S252, such as Fig.9e As shown, a first interlayer insulating layer 41 is formed on a side of the first coil structure 31 facing away from the dielectric substrate 1 .

[0156] Here, the process of forming the first interlayer insulating layer 41 is the same as the specific process of forming the second interlayer insulating layer 42 , and the repeated parts are not repeated here.

[0157] A first connection via hole via1 penetrating through the thickness direction of the first interlayer insulating layer 41 is formed on the first interlayer insulating layer 41 , and the first coil structure 31 is electrically connected to the second coil structure 32 adjacent thereto through the first connection via hole via1 .

[0158] For example, the material of the first interlayer insulating layer 41 can be a photosensitive PI material. The thickness of the first interlayer insulating layer 41 can be determined according to design requirements, and is usually between 3 and 8 um.

[0159] S253, such as Figure 9f As shown, a second coil structure 32 is formed on the side of the first interlayer insulating layer 41 facing away from the dielectric substrate 1 .

[0160] Step S253 may include forming a second conductive film as a second seed layer on the side of the first interlayer insulating layer 41 away from the dielectric substrate 1 by methods including electroplating, chemical plating, etc., or by sputtering, and then spin coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the second seed layer away from the dielectric substrate 1 to form a second coil structure 32.

[0161] The material of the second conductive film is generally a metal or metal nitride with high adhesion such as Ti, Ta, TiN, TaN, etc. The material of the second coil structure is generally a metal material such as Au, Al, Ag, Cu, etc. The thickness of the second coil structure 32 is generally 3 to 7 um. In order to ensure the flatness of the second coil structure 32, the upper surface of the second coil structure 32 (i.e., the surface away from the dielectric substrate 1) can be processed by chemical mechanical polishing (CMP).

[0162] The specific process of forming the second coil structure 32 may refer to the specific process of forming the first coil structure 31 , and the repeated parts will not be repeated.

[0163] S254, such as Figure 9g As shown, a second first interlayer insulating layer 41 is formed on the side of the second coil structure 32 facing away from the dielectric substrate 1 .

[0164] Here, the process of forming the first interlayer insulating layer 41 is the same as the specific process of forming the second interlayer insulating layer 42 , and the repeated parts are not repeated here.

[0165] A first connection via hole via1 penetrating through the thickness direction of the second first interlayer insulating layer 41 is formed on the second first interlayer insulating layer 41 , and the first coil structure 31 is electrically connected to the third coil structure 33 adjacent thereto through the first connection via hole via1 .

[0166] For example, the material of the second interlayer insulating layer 42 may be a photosensitive PI material. The thickness of the second interlayer insulating layer 41 may be determined according to design requirements, and is usually between 3 and 8 um.

[0167] S255, such as Figure 9h As shown, a third coil structure 33 is formed on the side of the second first interlayer insulating layer 41 facing away from the dielectric substrate 1 .

[0168] Step S255 may include forming a third conductive film as a third seed layer on the side of the second first interlayer insulating layer 41 away from the dielectric substrate 1 by preparing by methods including electroplating, chemical plating, etc., or by sputtering, and then spin coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the third seed layer away from the dielectric substrate 1 to form a third coil structure 33.

[0169] The material of the third conductive film is generally a metal or metal nitride with high adhesion such as Ti, Ta, TiN, TaN, etc. The material of the first coil structure is generally a metal material such as Au, Al, Ag, Cu, etc. The thickness of the second coil structure 32 is generally 3 to 7 um. In order to ensure the flatness of the second coil structure 32, the upper surface of the second coil structure 32 (i.e., the surface away from the dielectric substrate 1) can be processed by chemical mechanical polishing (CMP).

[0170] The specific process of forming the third coil structure 33 may refer to the specific process of forming the first coil structure 31 , and the repeated parts will not be repeated here.

[0171] S26, such as Figure 9i As shown, a sixth interlayer insulating layer 46 is formed on the side of the third coil structure 33 facing away from the dielectric substrate 1 .

[0172] Here, the process of forming the sixth interlayer insulating layer 46 is the same as the specific process of forming the second interlayer insulating layer 42 described above, and the repeated parts are not repeated here.

[0173] A third connection via hole via3 penetrating the sixth interlayer insulating layer 46 in a thickness direction is formed on the sixth interlayer insulating layer 46 , and the third coil structure 33 is electrically connected to the connection structure 5 through the third connection via hole via3 .

[0174] For example, the material of the sixth interlayer insulating layer 46 may be a photosensitive PI material. The thickness of the first interlayer insulating layer 41 may be determined according to design requirements, and is usually between 3 and 8 um.

[0175] S27, such as Figure 9j As shown, a connection structure 5 is formed on the side of the sixth interlayer insulating layer 46 facing away from the dielectric substrate 1 .

[0176] The connection structure 5 can be prepared by selecting a packaging method corresponding to a solder ball or a copper pillar. The solder ball 1 can be made by printing, ball planting, etc., and the copper pillar is made by electroplating.

[0177] Exemplarily, taking the additive method as an example, a fourth conductive film material may be deposited on the side of the sixth interlayer insulating layer 46 facing away from the dielectric substrate 1 by a PVD process, and the fourth conductive film serves as a fourth seed layer of the connection structure 5 . Ti is generally selected as the fourth conductive film material. The thickness of the fourth conductive film material can be adjusted according to demand, and can usually be selected between 100 and 500 nm to ensure that the surface of the sixth interlayer insulating layer 46 is completely covered, and in particular, it is necessary to ensure that the fourth conductive film material in the PI via and on the side wall of the via are completely covered without breaking; then, a layer of PR glue is coated on the side of the fourth conductive film material away from the dielectric substrate 1. The PR glue uses ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected. The thickness can be determined according to the thickness of the electroplated connection structure 5. Usually, the thickness of the PR glue is greater than the thickness of the electroplated connection structure 5; then, the PR glue is exposed and developed using Mask to form a pattern of the connection structure 5, and the PR glue outside the pattern of the connection structure 5 is removed; if a positive photoresist is selected, the slope angle of the pattern is generally an acute angle. Combined with the slope angle of the edge of the subsequent electroplated metal pattern and the subsequent process, the closer the slope angle of the PR glue pattern is to a right angle, the better. Afterwards, Cu is electroplated on the fourth seed layer to form a first sub-connection layer 51; the thickness of the first sub-connection layer 51 can be selected to be between 20 and 60 um; a barrier layer 53 is formed on the side of the first sub-connection layer 51 away from the dielectric substrate 1, and the material of the barrier layer 53 can be Ni, and the thickness of the barrier layer 53 can be selected to be between 3 and 10 um; silver-tin alloy (Sn-Ag) or tin (Sn) is electroplated on the side of the barrier layer 53 away from the dielectric substrate 1 to form a second sub-connection layer 52; the thickness of the second sub-connection layer 52 can be selected to be between 20 and 50 um. Afterwards, the remaining PR glue is removed, the remaining fourth seed layer is completely exposed, and the fourth seed layer outside the connection structure 5 pattern is completely etched away to prevent the fourth seed layer under the connection structure 5 from being etched to form a chamfer and affect the bonding force between the film layers. Afterwards, the second sub-connection layer 52 is reflowed to change the top of the SnAg or Sn film layer from a plane to an arc shape to ensure the welding effect of subsequent devices. The final shape is as follows. Figure 9j shown.

[0178] The above steps S21 to S27 can reduce the overall coil area of ​​the inductor 3 in a top view plane by sequentially connecting and arranging the coils with most of the projections overlapping, thereby saving device wiring space and facilitating the design of device miniaturization.

[0179] In some embodiments, Figure 10a to Figure 10h Preparation provided for the embodiments of the present disclosure Figure 5 The schematic diagram of the filter is shown in Figure 10a to Figure 10h As shown, it includes steps S31 to S37, wherein:

[0180] S31, providing a dielectric substrate 1.

[0181] Exemplarily, a dielectric substrate 1 with a thickness of 0.15 to 2 mm and a mass production size is prepared according to the requirements of the process equipment. The material of the dielectric substrate 1 can be selected from glass, high-resistance silicon, ceramics and other materials with high insulation and low dielectric loss. In step S21, a cleaning process before preparation of the dielectric substrate 1 can be included, and ultrasonic cleaning is performed in sequence with organic solvents such as deionized water, ethanol, isopropanol, etc., and the ultrasonic time is at least 15 minutes. After ultrasonic cleaning, it is dried in an oven, and can be dried at 75°C for a certain time according to the last cleaning solvent.

[0182] S32 , forming a first conductive pattern M1 including a first electrode plate 21 and a first coil structure 31 on the dielectric substrate 1 .

[0183] like Fig.10a As shown, step S32 may include preparing a first conductive film on the dielectric substrate 1 by electroplating, chemical plating, etc., or by sputtering, as a first seed layer; then, spin coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the first seed layer away from the dielectric substrate 1 to form a first conductive pattern M1 including a first electrode 21 and a first coil structure 31.

[0184] Among them, the material of the first seed layer is generally a metal or metal nitride with high adhesion such as Ti, Ta, TiN, TaN, etc. The thickness of the first seed layer can be adjusted according to demand, and the thickness is generally between 30 and 200nm; or, the material of the first seed layer can also be selected from copper (Cu), and the thickness of Cu is generally between 0.1 and 1um. The material of the first conductive pattern M1 is generally a metal material such as Au, Al, Ag, Cu, etc. The first electrode plate 21 and the first coil structure 31 can be an integrally formed structure, and the thickness of the integrally formed first electrode plate 21 and the first coil structure 31 is generally 3 to 7um. In order to ensure the flatness of the integrally formed first electrode plate 21 and the first coil structure 31, the upper surface of the first coil structure 31 (that is, the surface away from the dielectric substrate 1) can be processed by chemical mechanical polishing (CMP).

[0185] For example, Fig.10aAs shown, PR glue is coated on the side of the first conductive film away from the dielectric substrate 1. The PR glue uses ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected. The thickness can be selected according to the different thicknesses of the electroplated first conductive pattern M1. Usually, the thickness of the PR glue is higher than the thickness of the electroplated first conductive pattern M1. Afterwards, the PR glue is exposed and developed using a mask to form a pattern of the first conductive pattern M1, and the PR glue corresponding to the pattern of the first conductive pattern M1 is removed; if a positive photoresist is selected, the slope angle of the pattern is generally an acute angle. Combined with the slope angle of the edge of the subsequent electroplated metal pattern and the subsequent process, the closer the slope angle of the PR glue pattern is to a right angle, the better. If a negative photoresist is selected, the slope angle of the pattern is generally an obtuse angle. Fig.10a The product morphology displayed is the exposure morphology of negative PR glue. Afterwards, Cu is electroplated on the area of ​​the first seed layer that is not covered by the PR glue to form an integrally formed first electrode 21 and a first coil structure 31. Because the electroplated metal will completely fill the internal space of the PR glue, the slope angle of the electroplated M1 metal is determined by the properties of the PR glue. If a positive PR glue is selected, the slope angle of the M1 metal sidewall grown by the additive electroplating is an obtuse angle, that is, the length of the upper surface of the metal is longer than the lower surface. If a negative PR glue is selected, the slope angle of the metal grown by the additive electroplating is an acute angle. The metal morphology of the M1 layer shown in the figure is formed by the negative PR glue using the additive electroplating method. The surface of the electroplated metal will have slight undulations when observed microscopically, and the roughness is generally above 10nm. Afterwards, the remaining PR glue is removed to expose the first seed layer. Afterwards, the first seed layer outside the metal Cu coverage is completely etched away to form the first conductive pattern M1.

[0186] S33 , forming a second conductive pattern M2 on a side of the first conductive pattern M1 away from the dielectric substrate 1 .

[0187] The second conductive pattern M2 includes the second electrode plate 22 of the capacitor 2 . The first electrode plate 21 is electrically connected to the inductor 3 .

[0188] For example, Fig.10bAs shown, an insulating layer material can be deposited on the side of the first conductive pattern M1 away from the dielectric substrate 1 by a CVD process. Silicon nitride (SiNx) can be selected as the insulating layer 40 of the upper and lower plates of the capacitor 2. The thickness of the insulating layer material can be designed and determined according to the requirements of the capacitor 2 value, and the thickness can usually be set between 80 and 200 nm. Afterwards, a second conductive pattern material can be deposited on the side of the insulating layer material away from the dielectric substrate 1 by a PVD process. The second conductive pattern material can be selected from materials with good conductive properties such as Cu and Al. The metal thickness is made according to the requirements, and the thickness can be selected between 0.2 and 2um. An adhesive layer can be formed between the insulating layer material and the second conductive pattern material. The adhesive layer can be selected from metals or metal nitrides with high adhesion such as Ti, Ta, TiN, TaN, etc. The thickness is adjusted according to the process capability and can be selected between 30 and 100 nm. Afterwards, a layer of PR glue is applied on the side of the second conductive pattern material facing away from the dielectric substrate 1. The PR glue uses ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected. The thickness can ensure that the surface of the second conductive pattern material is completely covered to a certain thickness. The thickness of the PR glue can be considered to be between 1um and 4um. Afterwards, use Mask to expose the PR glue and develop it. The PR glue above the pattern of the second electrode 22 that needs to be retained is retained, and all other areas are removed. Afterwards, the second conductive pattern material outside the pattern is removed. When the second conductive pattern material is Cu, wet etching can be used. When the second conductive pattern material is Al, wet etching or dry etching can be used. Different metals can choose different etching methods. Afterwards, remove the PR glue above the metal pattern to form a second conductive pattern M2 containing the second electrode 22. Afterwards, a layer of PR glue is formed on the side of the second conductive pattern M2 away from the dielectric substrate 1. The PR glue uses ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected. The thickness can ensure that the surface of the insulating layer material is completely covered to a certain thickness. The thickness of the PR glue can be considered to be between 1um and 4um. Afterwards, use Mask to expose the PR glue and develop it. The PR glue above the pattern of the insulating layer 40 that needs to be retained is retained, and all other areas are removed. Afterwards, the insulating layer material outside the pattern is removed, usually by dry etching. Afterwards, remove the PR glue above the insulating layer 40 pattern to form an insulating layer 40.

[0189] S34 , forming a third interlayer insulating layer 43 on a side of the second conductive pattern M2 away from the first conductive pattern M1 .

[0190] The third interlayer insulating layer 43 covers the second electrode plate 22 , and the integrally formed first electrode plate 21 and the first coil structure 31 .

[0191] A first connection via hole via1 penetrating the third interlayer insulating layer 43 in a thickness direction is formed on the third interlayer insulating layer 43 , and the first coil structure 31 is electrically connected to the second coil structure 32 adjacent thereto through the first connection via hole via1 .

[0192] For example, Fig.10c As shown, the material of the third interlayer insulating layer 43 can be selected as a photosensitive PI material, and the thickness is determined according to the design requirements, usually between 3 and 8 um; through exposure and development, the PI material at the overlapping position of the first coil structure 31 and the second electrode plate 22 is removed, and solidified to form a first connecting via via1; the PI material is changed from a soft film to a hard film to increase the strength of the film layer. Since the PI material is usually a negative resin, the bottom size of the PI via is smaller than the top size of the via, and the slope angle can be adjusted between 20° and 90° by changing the process conditions to form the third interlayer insulating layer 43.

[0193] It should be noted that the gentler the slope angle, the more evenly the via sidewalls will be covered with the subsequent electroplated metal seed layer, and the less likely it is that the film will peel off. However, a gentler slope angle will cause the top size of the via to increase, and the via slope angle needs to be adjusted based on the size of the previous metal pattern.

[0194] In this step S34, a third interlayer insulating layer 43 is formed through a single patterning process to cover the second electrode 22, and the integrally formed first electrode 21 and the first coil structure 31, thereby achieving insulation between the capacitor 2 and the first coil structure 31 and the upper second coil structure 32, reducing the process steps and thus reducing production costs.

[0195] S35 , forming a plurality of third conductive patterns M3 on a side of the third interlayer insulating layer 43 away from the dielectric substrate 1 , and forming at least one first interlayer insulating layer 41 between adjacent third conductive patterns M3 .

[0196] Taking the inductor 3 including a three-layer coil structure as an example, the process specifically includes steps S351 to S353, wherein:

[0197] S351, such as Fig.10d As shown, a second coil structure 32 is formed on a side of the third interlayer insulating layer 43 facing away from the dielectric substrate 1 .

[0198] Step S351 may include forming a second conductive film as a second seed layer on the side of the third interlayer insulating layer 43 facing away from the dielectric substrate 1 by methods including electroplating, chemical plating, etc., or by sputtering, and then spin coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the second seed layer facing away from the dielectric substrate 1 to form a second coil structure 32.

[0199] The material of the second conductive film is generally a metal or metal nitride with high adhesion such as Ti, Ta, TiN, TaN, etc. The material of the second coil structure is generally a metal material such as Au, Al, Ag, Cu, etc. The thickness of the second coil structure 32 is generally 3 to 7 um. In order to ensure the flatness of the second coil structure 32, the upper surface of the second coil structure 32 (i.e., the surface away from the dielectric substrate 1) can be processed by chemical mechanical polishing (CMP).

[0200] Exemplarily, a second conductive film material can be deposited on the side of the third interlayer insulating layer 43 away from the dielectric substrate 1 through a PVD process. The second conductive film material is generally Ti, and the thickness of the second conductive film material can be adjusted as needed to ensure that the surface of the second interlayer insulating layer 42 is completely covered, especially to ensure that the first conductive film material in the PI via and on the side wall of the via is completely covered without breakage; usually, the thickness of the second conductive film material can be selected to be above 0.2 nm; then, a layer of PR glue is coated on the side of the second conductive film material away from the dielectric substrate 1, and the PR glue is selected from ordinary photosensitive PR glue, and positive PR glue or negative PR glue can be selected, and the thickness can be determined according to the thickness of the electroplated second coil structure 32. Usually, the thickness of the PR glue is greater than the thickness of the electroplated second coil structure 32. Afterwards, use Mask to expose the PR glue and develop it to form the pattern of the second coil structure 32, and remove the PR glue outside the pattern of the second coil structure 32; if a positive photoresist is selected, the slope angle of the pattern is generally an acute angle. Combined with the slope angle of the edge of the subsequent electroplated metal pattern and the subsequent process, the closer the slope angle of the PR glue pattern is to a right angle, the better. If a negative photoresist is selected, the slope angle of the pattern is generally an obtuse angle. Afterwards, Cu is electroplated on the second seed layer to form the second coil structure material. Afterwards, remove the remaining PR glue, expose all the remaining second seed layers, and etch away all the second seed layers outside the second coil structure 32 pattern to prevent the second seed layer under the second coil structure 32 from being etched, forming a chamfer, and affecting the bonding force between the film layers. The final shape is as follows. Fig.10d shown.

[0201] S352, such as Fig.10e As shown, a first interlayer insulating layer 41 is formed on a side of the second coil structure 32 facing away from the dielectric substrate 1 .

[0202] Here, the process of forming the first interlayer insulating layer 41 is the same as the specific process of forming the third interlayer insulating layer 43 , and the repeated parts are not repeated here.

[0203] A first connection via hole via1 penetrating the first interlayer insulating layer 41 in a thickness direction is formed on the first interlayer insulating layer 41 , and the second coil structure 32 is electrically connected to the third coil structure 33 adjacent thereto through the first connection via hole via1 .

[0204] For example, the material of the first interlayer insulating layer 41 may be a photosensitive PI material. The thickness of the first interlayer insulating layer 41 may be determined according to design requirements, and is usually between 3 and 8 um.

[0205] S353, such as Fig.10f As shown, a third coil structure 33 is formed on a side of the first interlayer insulating layer 41 facing away from the dielectric substrate 1 .

[0206] Step S353 may include forming a third conductive film as a third seed layer on the side of the first interlayer insulating layer 41 away from the dielectric substrate 1 by methods including electroplating, chemical plating, etc., or by sputtering, and then spin coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the third seed layer away from the dielectric substrate 1 to form a third coil structure 33.

[0207] The material of the third conductive film is generally a metal or metal nitride with high adhesion such as Ti, Ta, TiN, TaN, etc. The material of the third coil structure 33 is generally a metal material such as Au, Al, Ag, Cu, etc. The thickness of the third coil structure 33 is generally 3 to 7 um. In order to ensure the flatness of the third coil structure 33, the upper surface of the second coil structure 32 (i.e., the surface away from the dielectric substrate 1) can be processed by chemical mechanical polishing (CMP).

[0208] The specific process of forming the third coil structure 33 may refer to the specific process of forming the second coil structure 32 , and the repeated parts will not be repeated.

[0209] S36, such as Figure 10g As shown, a sixth interlayer insulating layer 46 is formed on the side of the third coil structure 33 facing away from the dielectric substrate 1 .

[0210] Here, the process of forming the sixth interlayer insulating layer 46 is the same as the specific process of forming the third interlayer insulating layer 43 described above, and the repeated parts are not repeated here.

[0211] A third connection via hole via3 penetrating the sixth interlayer insulating layer 46 in a thickness direction is formed on the sixth interlayer insulating layer 46 , and the third coil structure 33 is electrically connected to the connection structure 5 through the third connection via hole via3 .

[0212] For example, the material of the sixth interlayer insulating layer 46 may be a photosensitive PI material. The thickness of the first interlayer insulating layer 41 may be determined according to design requirements, and is usually between 3 and 8 um.

[0213] S37, such as Fig.10h As shown, a connection structure 5 is formed on the side of the sixth interlayer insulating layer 46 facing away from the dielectric substrate 1 .

[0214] The specific process of step S37 can refer to the specific implementation process of forming the connection structure 5 in step S27, and the repeated parts will not be repeated.

[0215] In the above steps S31 to S37, compared with the embodiment of steps S21 to S27, the first electrode plate 21 of the capacitor 2 and the first coil structure 31 of the inductor 3 are on the same layer and connected as an integrated structure, which can reduce the process steps and thus reduce the production cost. In addition, the generation of the integrated first electrode plate 21 and the first coil structure 31 can effectively reduce the thickness of the overall structure of the inductor 3 and achieve a thinner device. Specifically, compared with the embodiment of Figure 4 The filter preparation process can reduce a layer of thin film metal, a layer of back-through and an insulating layer, so that the process flow of this embodiment is shorter, the risk is lower, and the cost is also lower.

[0216] In some embodiments, Figure 11a to Figure 11i Preparation provided for the embodiments of the present disclosure Figure 6 The schematic diagram of the filter is shown in Figure 11a to Figure 11i As shown, it includes steps S41 to S48, wherein:

[0217] S41, providing a dielectric substrate 1.

[0218] Please refer to the detailed description of step S31 above, and the repeated parts will not be repeated here.

[0219] S42, such as Fig.11a As shown, a fourth interlayer insulating layer 44 is formed on the dielectric substrate 1 .

[0220] The fourth interlayer insulating layer 44 includes a first receiving portion 441 penetrating along a thickness direction thereof.

[0221] Exemplarily, the material of the fourth interlayer insulating layer 44 can be a photosensitive PI material, or an oxide film such as SiNx or SiO2. If SiNx or SiO2 is used, a film layer needs to be deposited on the glass surface first, and then the fourth interlayer insulating layer 44 pattern is formed by exposing and developing the PR glue and dry etching the oxide film. The advantage of selecting the photosensitive PI material is that the material stress is small, which can effectively reduce the warping of the glass caused by stress, which is beneficial to improve the uniformity of the pattern. The fourth interlayer insulating layer 44 is used as a cut-off layer of the CMP process, and at the same time shares the pressure applied to the metal layer during the CMP process to avoid the collapse of the metal under pressure. Fig.11a As shown, the process flow is demonstrated using photosensitive PI material.

[0222] Exemplarily, the material of the fourth interlayer insulating layer 44 is a photosensitive PI material, and the thickness is determined according to the thickness requirement of the first conductive pattern M1. The thickness of the fourth interlayer insulating layer 44 is usually between 3 and 8 um. The PI material in the graphic area of ​​the first conductive pattern M1 can be removed by exposure and development, and then cured to change the PI layer from a soft film to a hard film, thereby increasing the strength of the film layer. Since the PI material is usually a negative photoresist, the bottom size of the PI graphic is smaller than the top size of the via hole, and the closer the slope angle is to a right angle, the better, so as to avoid the chamfer at the bottom of the graphic affecting the deposition of the subsequent seed layer.

[0223] S43, such as Fig.11b As shown, the first receiving portion 441 is filled with the integrally formed first electrode plate 21 and the first coil structure 31 to form a first conductive pattern M1.

[0224] The surface of the integrally formed first pole plate 21 and the first coil structure 31 facing away from the dielectric substrate 1 is flush with the surface of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1 .

[0225] like Fig.11b As shown, step S42 may include preparing a first conductive film on the dielectric substrate 1 by electroplating, chemical plating, etc., or by sputtering, as a first seed layer; then, spin coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the first seed layer away from the dielectric substrate 1 to form a first conductive pattern M1 including a first electrode 21 and a first coil structure 31.

[0226] Among them, the material of the first seed layer is generally a metal or metal nitride with high adhesion such as Ti, Ta, TiN, TaN, etc., and the thickness of the first seed layer can be adjusted according to demand. The material of the first conductive pattern M1 is generally a metal material such as Au, Al, Ag, Cu, etc. The first pole plate 21 and the first coil structure 31 can be an integrally formed structure, and the thickness of the integrally formed first pole plate 21 and the first coil structure 31 is generally 3 to 7 um. In order to ensure the flatness of the integrally formed first pole plate 21 and the first coil structure 31, the upper surface of the first coil structure 31 (that is, the surface away from the dielectric substrate 1) can be processed by chemical mechanical polishing (CMP).

[0227] Exemplarily, a first seed layer is deposited on the fourth interlayer insulating layer 44 by a PVD process, ensuring that the first seed layer completely covers the fourth interlayer insulating layer 44, especially ensuring that the first seed layer completely covers the side wall of the first accommodating portion 441 in the fourth interlayer insulating layer 44 without breaking. Cu can be electroplated on the surface of the first seed layer away from the dielectric substrate 1 by an additive method, usually ensuring that the electroplated Cu metal grows beyond the first accommodating portion 441, and electroplated Cu also exists on the surface of the fourth interlayer insulating layer 44 away from the dielectric substrate 1. Afterwards, the electroplated metal and the first seed layer above the PI surface are removed by a CMP process to form an integrally formed first pole plate 21 and a first coil structure 31, and the surface of the integrally formed first pole plate 21 and the first coil structure 31 away from the dielectric substrate 1 is flush with the surface of the fourth interlayer insulating layer 44 away from the dielectric substrate 1.

[0228] S44, such as Fig.11c As shown, a second conductive pattern M2 is formed on a side of the first conductive pattern M1 away from the dielectric substrate 1 .

[0229] The second conductive pattern M2 includes the second electrode plate 22 of the capacitor 2 . The first electrode plate 21 is electrically connected to the inductor 3 .

[0230] Please refer to the detailed description of step S33 above, and the repeated parts will not be repeated here.

[0231] S45, such as Fig.11d As shown, a fifth interlayer insulating layer 45 is formed on a side of the second conductive pattern M2 away from the first conductive pattern M1.

[0232] The surface of the fifth interlayer insulating layer 45 facing away from the dielectric substrate 1 is parallel to the reference plane of the dielectric substrate 1 extending along the first direction X.

[0233] The step of forming the fifth insulating layer can refer to the detailed description of the above step S34, and the repeated parts will not be repeated.

[0234] A first connection via hole via1 penetrating the fifth interlayer insulating layer 45 in a thickness direction is formed on the fifth interlayer insulating layer 45 , and the first coil structure 31 is electrically connected to the second coil structure 32 adjacent thereto through the first connection via hole via1 .

[0235] S46 , forming a plurality of third conductive patterns M3 on a side of the fifth interlayer insulating layer 45 away from the dielectric substrate 1 , and forming at least one first interlayer insulating layer 41 between adjacent third conductive patterns M3 .

[0236] Taking the inductor 3 including a three-layer coil structure as an example, the process specifically includes steps S461 to S463, wherein:

[0237] S461, such as Fig.11eAs shown, a second coil structure 32 is formed on the side of the fifth interlayer insulating layer 45 facing away from the dielectric substrate 1 .

[0238] The process of forming the second coil structure 32 in step S461 can refer to the above step S351, and the repeated parts will not be repeated.

[0239] S462, such as Fig.11f As shown, a first interlayer insulating layer 41 is formed on a side of the second coil structure 32 facing away from the dielectric substrate 1 .

[0240] The process of forming the first interlayer insulating layer 41 in step S462 can refer to the above step S352, and the repeated parts will not be repeated.

[0241] S463, such as Figure 11g As shown, a third coil structure 33 is formed on a side of the first interlayer insulating layer 41 facing away from the dielectric substrate 1 .

[0242] The principle of forming the third coil structure 33 in this step S463 is the same as the principle of forming the second coil structure 32 in the above step S351. Please refer to the specific implementation process of forming the second coil structure 32 in the above step S351, and the repeated parts will not be repeated here.

[0243] S47, such as Fig.11h As shown, a sixth interlayer insulating layer 46 is formed on the side of the third coil structure 33 facing away from the dielectric substrate 1 .

[0244] Here, the principle of forming the sixth interlayer insulating layer 46 is the same as the process of forming the third interlayer insulating layer 43 in the above step S34. Please refer to the specific implementation process of forming the third interlayer insulating layer 43 in the above step S34, and the repeated parts will not be repeated.

[0245] S48, such as Fig.11i As shown, a connection structure 5 is formed on the side of the sixth interlayer insulating layer 46 facing away from the dielectric substrate 1 .

[0246] Here, the principle of forming the connection structure 5 is the same as the principle of forming the connection structure 5 in the above step S24. Please refer to the specific implementation process of forming the connection structure 5 in the above step S24, and the repeated parts will not be repeated.

[0247] In the above steps S41 to S48, the surface of the fourth interlayer insulating layer 44 facing away from the dielectric substrate 1 is flush with the surfaces of the integrally formed first electrode plate 21 and the first coil structure 31 facing away from the dielectric substrate 1, so that the surface of the fifth interlayer insulating layer 45 located on the fourth interlayer insulating layer 44, which is relatively arranged in the thickness direction, is parallel to the reference surface of the dielectric substrate 1 extending along the first direction X, thereby reducing the undulation of some film layers, and even more, forming an interlayer insulating layer surface without high and low undulations, which is conducive to improving the thickness uniformity of some film layers at different positions, thereby improving the uniformity of device performance.

[0248] In addition, this embodiment uses the CMP process to reduce the roughness of the electroplated metal surface of the first conductive pattern M1, improves the uniformity of the thickness of the first conductive pattern M1, is beneficial to control the uniformity of the thickness of the insulating layer 40, and is more beneficial to improve the uniformity of the capacitance value. Figure 7 The preparation process of the filter shown also reduces a PR glue process, shortens the process flow and reduces costs.

[0249] In some embodiments, Figure 12a to Figure 12h Preparation provided for the embodiments of the present disclosure Figure 7 The schematic diagram of the filter is shown in Figure 12a to Figure 12h As shown, it includes steps S51 to S57, wherein:

[0250] S51, providing a dielectric substrate 1.

[0251] Please refer to the detailed description of step S31 above, and the repeated parts will not be repeated here.

[0252] S52, such as Fig.12a As shown, a first conductive pattern M1 including a first pole plate 21 and a first coil structure 31 is formed on a dielectric substrate 1 .

[0253] The first coil structure 31 includes a first sub-coil 311 and a second sub-coil 321 which are stacked, and the first sub-coil 311 is located on a side of the second sub-coil 321 close to the dielectric substrate 1 .

[0254] Step S52 may include forming a first conductive film on the dielectric substrate 1 as a first seed layer by preparing it by methods including electroplating, chemical plating, etc., or by sputtering; wherein at least a portion of the structure of the first seed layer serves as the first sub-coil 311; and then spin coating photoresist, exposing and developing, electroplating, and chemically plating metal on the side of the first seed layer away from the dielectric substrate 1 to form a second sub-coil 321 opposite to the first sub-coil 311.

[0255] The material of the first conductive film is generally a metal or metal nitride with high adhesion such as Ti, Ta, TiN, TaN, etc. The material of the second sub-coil 321 is generally a metal material such as Au, Al, Ag, Cu, etc. The thickness of the second sub-coil 321 is generally 3 to 7 um. In order to ensure the flatness of the first coil structure 31, the upper surface of the first coil structure 31 (i.e., the surface away from the dielectric substrate 1) can be processed by chemical mechanical polishing (CMP).

[0256] For example, Fig.12a As shown, the first conductive film can be formed by electroplating by an additive method or a subtractive method; for example, taking the additive method as an example, a first conductive film material is deposited on the dielectric substrate 1 by a PVD process, and the first conductive film material is generally Ti. Then, a layer of PR glue is coated on the side of the first conductive film material away from the dielectric substrate 1. The PR glue is a common photosensitive PR glue, and a positive PR glue or a negative PR glue can be selected. The thickness can be determined according to the thickness of the electroplated first coil structure 31. Under normal circumstances, the thickness of the PR glue is greater than the thickness of the electroplated second sub-coil 321; then, the PR glue is exposed and developed using a mask to form a pattern of the second sub-coil 321, and the PR glue outside the pattern of the second sub-coil 321 is removed; if a positive photoresist is selected, the slope angle of the pattern is generally an acute angle. Combined with the slope angle of the edge of the subsequent electroplated metal pattern and the subsequent process, the closer the slope angle of the PR glue pattern is to a right angle, the better. If a negative photoresist is selected, the slope angle of the pattern is generally an obtuse angle. Afterwards, Cu is electroplated on the first seed layer to form the material of the second sub-coil 321. The thickness of the material of the second sub-coil 321 is determined according to the needs, and can usually be selected between 3 and 7 um. Afterwards, the remaining PR glue is removed to expose the remaining first seed layer. Afterwards, PR glue is applied again on the exposed first seed layer and the surface of the second sub-coil 321 away from the dielectric substrate 1. The thickness of the PR glue is sufficient to cover the surface of the second sub-coil 321. The thickness of the PR glue is generally selected between 5 um and 10 um. Afterwards, the PR glue is exposed and developed using a mask. The PR glue above the pattern of the first electrode plate 21 that needs to be retained is retained, and the PR glue in other areas is completely removed. Afterwards, the first seed layer corresponding to the portion other than the pattern covered by the PR glue is removed to form an integrally formed first electrode plate 21, a first sub-coil 311, and a second sub-coil 321.

[0257] S53, such as Figure 12b As shown, a second conductive pattern M2 is formed on a side of the first conductive pattern M1 away from the dielectric substrate 1 .

[0258] The second conductive pattern M2 includes the second electrode plate 22 of the capacitor 2. The first electrode plate 21 and the first sub-coil 311 are integrally formed.

[0259] Here, the principle of forming the second conductive pattern M2 is the same as the principle of forming the second conductive pattern M2 in the above step S33. Please refer to the specific implementation process of forming the second conductive pattern M2 in the above step S33, and the repeated parts will not be repeated.

[0260] S54, such as Fig.12c As shown, a third interlayer insulating layer 43 is formed on a side of the second conductive pattern M2 away from the first conductive pattern M1.

[0261] Here, the principle of forming the third interlayer insulating layer 43 is the same as the principle of forming the third interlayer insulating layer 43 in the above step S34. The specific implementation process of forming the third interlayer insulating layer 43 in the above step S34 can be referred to, and the repeated parts will not be repeated.

[0262] S55 , forming a plurality of third conductive patterns M3 on a side of the third interlayer insulating layer 43 away from the dielectric substrate 1 , and forming at least one first interlayer insulating layer 41 between adjacent third conductive patterns M3 .

[0263] Taking the inductor 3 including a three-layer coil structure as an example, the process specifically includes steps S551 to S553, wherein:

[0264] S551, such as Fig.12d As shown, a second coil structure 32 is formed on a side of the third interlayer insulating layer 43 facing away from the dielectric substrate 1 .

[0265] S552, such as Fig.12e As shown, a first interlayer insulating layer 41 is formed on a side of the second coil structure 32 facing away from the dielectric substrate 1 .

[0266] S553, such as Fig.12f As shown, a third coil structure 33 is formed on a side of the first interlayer insulating layer 41 facing away from the dielectric substrate 1 .

[0267] S56, such as Figure 12g As shown, a sixth interlayer insulating layer 46 is formed on the side of the third coil structure 33 facing away from the dielectric substrate 1 .

[0268] S57, such as Figure 12h As shown, a connection structure 5 is formed on the side of the sixth interlayer insulating layer 46 facing away from the dielectric substrate 1 .

[0269] The principle of forming each third conductive pattern M3, the sixth interlayer insulating layer 46 and the connecting structure 5 in the above steps S55~S57 is the same as the principle of forming each third conductive pattern M3, the sixth interlayer insulating layer 46 and the connecting structure 5 in the above steps S35~S37. For details, please refer to the specific implementation process of the above steps S35~S37, and the repeated parts will not be repeated.

[0270] The above steps S51 to S57 prepare a filter, wherein the common first electrode and the first sub-coil are formed by PVD, so the roughness of the metal surface is higher than that of the electroplated metal, which is beneficial to controlling the uniformity of the thickness of the insulating layer 40 and improving the uniformity of the capacitance value. Since the common first electrode and the first sub-coil are the seed layer of the second sub-coil, there is no need to add an additional PVD process of a thin layer of metal for the first coil structure. In addition, the first electrode and the first sub-coil can be directly connected to the second sub-coil through metal, and there is no need to overlap through vias between the insulating layers, thereby reducing process risks.

[0271] In some embodiments, Figure 13a to Figure 13k Preparation provided for the embodiments of the present disclosure Figure 8 The schematic diagram of the filter is shown in Figure 13a to Figure 13k As shown, steps S61 to S68 are included, wherein:

[0272] S61, providing a dielectric substrate 1.

[0273] Please refer to the detailed description of step S41 above, and the repeated parts will not be repeated here.

[0274] S62, such as Fig.13a As shown, a fourth interlayer insulating layer 44 is formed on the dielectric substrate 1 .

[0275] Please refer to the detailed description of step S42 above, and the repeated parts will not be repeated here.

[0276] S63, such as Fig.13b As shown, the first receiving portion 441 is filled with the integrally formed first electrode plate 21 and the first coil structure 31 to form a first conductive pattern M1.

[0277] Please refer to the detailed description of step S43 above, and the repeated parts will not be repeated here.

[0278] S64, such as Fig.13c As shown, a second conductive pattern M2 is formed on a side of the first conductive pattern M1 away from the dielectric substrate 1 .

[0279] Please refer to the detailed description of step S44 above, and the repeated parts will not be repeated here.

[0280] S65, such as Fig.13d As shown, a fifth interlayer insulating layer 45 is formed on a side of the second conductive pattern M2 away from the first conductive pattern M1.

[0281] Please refer to the detailed description of step S45 above, and the repeated parts will not be repeated here.

[0282] S66 , forming a plurality of third conductive patterns M3 on a side of the fifth interlayer insulating layer 45 away from the dielectric substrate 1 , and forming at least one first interlayer insulating layer 41 between adjacent third conductive patterns M3 .

[0283] Taking the inductor 3 including a three-layer coil structure as an example, the process specifically includes steps S661 to S665, wherein:

[0284] S661, such as Fig.13e As shown, a first seventh interlayer insulating layer 47 is formed on the side of the fifth interlayer insulating layer 45 facing away from the dielectric substrate 1 .

[0285] The first seventh interlayer insulating layer 47 includes a second receiving portion 471 penetrating along a thickness direction thereof.

[0286] Here, the principle of forming the seventh interlayer insulating layer 47 is the same as the principle of forming the fourth interlayer insulating layer 44 in the above step S42. The specific implementation process of forming the fourth interlayer insulating layer 44 in the above step S42 can be referred to, and the repeated parts will not be repeated.

[0287] S662, such as Fig.13f As shown, the coil structure material of the inductor 3 is filled in the second receiving portion 471 of the first seventh interlayer insulating layer 47 to form a second coil structure 32 .

[0288] The surface of the second coil structure 32 facing away from the dielectric substrate 1 is flush with the surface of the seventh interlayer insulating layer 47 facing away from the dielectric substrate 1 .

[0289] Here, the principle of forming the second coil structure 32 is the same as the principle of forming the integrally formed first electrode plate 21 and first coil structure 31 in step S43 above. The specific implementation process of forming the first conductive pattern M1 in step S43 above can be referred to, and the repeated parts will not be repeated here.

[0290] S663, such as Figure 13g As shown, a first interlayer insulating layer 41 is formed on a side of the second coil structure 32 facing away from the dielectric substrate 1 .

[0291] Here, the principle of forming the first interlayer insulating layer 41 is the same as the principle of forming the fifth interlayer insulating layer 45 in the above step S45. The specific implementation process of forming the fifth interlayer insulating layer 45 in the above step S45 can be referred to, and the repeated parts will not be repeated.

[0292] Here, the first interlayer structure includes a first surface and a second surface that are arranged opposite to each other along the thickness direction thereof, and both the first surface and the second surface are parallel to a reference plane extending along the first direction X of the dielectric substrate 1 .

[0293] S664, such as Fig.13hAs shown, a second seventh interlayer insulating layer 47 is formed on the side of the first interlayer insulating layer 41 facing away from the dielectric substrate 1 .

[0294] The second seventh interlayer insulating layer 47 includes a second receiving portion 471 penetrating along the thickness direction thereof.

[0295] Here, the principle of forming the seventh interlayer insulating layer 47 is the same as the principle of forming the fourth interlayer insulating layer 44 in the above step S42. The specific implementation process of forming the fourth interlayer insulating layer 44 in the above step S42 can be referred to, and the repeated parts will not be repeated.

[0296] S665, such as Fig.13i As shown, the second receiving portion 471 of the second seventh interlayer insulating layer 47 is filled with the coil structure material of the inductor 3 to form a third coil structure 33 .

[0297] The surface of the third coil structure 33 facing away from the dielectric substrate 1 is flush with the surface of the second interlayer insulating layer 42 facing away from the dielectric substrate 1 .

[0298] The principle of forming the third coil structure 33 in this step S665 is the same as the principle of forming the first conductive pattern M1 in the above step S43. The specific implementation process of forming the first conductive pattern M1 in the above step S43 can be referred to, and the repeated parts will not be repeated here.

[0299] S67, such as Fig.13j As shown, a sixth interlayer insulating layer 46 is formed on the side of the third coil structure 33 facing away from the dielectric substrate 1 .

[0300] Here, the principle of forming the sixth interlayer insulating layer 46 is the same as the principle of forming the fifth interlayer insulating layer 45 in the above S45. The specific implementation process of forming the fifth interlayer insulating layer 45 in the above step S45 can be referred to, and the repeated parts will not be repeated.

[0301] Here, the sixth interlayer structure includes a first surface and a second surface that are arranged opposite to each other along the thickness direction thereof, and both the first surface and the second surface are parallel to a reference plane extending along the first direction X of the dielectric substrate 1 .

[0302] S68, such as Figure 13k As shown, a connection structure 5 is formed on the side of the sixth interlayer insulating layer 46 facing away from the dielectric substrate 1 .

[0303] Here, the principle of forming the connection structure 5 is the same as the principle of forming the connection structure 5 in the above step S24. Please refer to the specific implementation process of forming the connection structure 5 in the above step S24, and the repeated parts will not be repeated.

[0304] The process of steps S61 to S68 forms an interlayer insulating layer surface with no ups and downs, which is beneficial to improving the thickness uniformity of each film layer at different positions, thereby improving the uniformity of device performance.

[0305] In addition, the embodiment of the present disclosure provides an electronic device, which may include the above-mentioned filter. Other essential components of the electronic device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0306] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A filter comprising a dielectric substrate, at least one capacitor and at least one inductor arranged on the dielectric substrate; The capacitor comprises a first plate and a second plate which are arranged opposite to each other, wherein the first plate is located on a side of the second plate close to the dielectric substrate; at least one of the first plate and the second plate is electrically connected to the inductor; The inductor comprises a multi-layer coil structure sequentially arranged on the dielectric substrate, and at least one first interlayer insulating layer is arranged between adjacent coil structures; the coil structures of adjacent layers are electrically connected through a first connecting via penetrating the first interlayer insulating layer therebetween; The orthographic projections of any two of the multiple layers of the coil structures on the dielectric substrate partially overlap.

2. The filter according to claim 1, wherein The capacitor is arranged on a side of the inductor close to the dielectric substrate, and at least one second interlayer insulating layer is arranged between the capacitor and the inductor.

3. The filter according to claim 2, wherein: The coil structure closest to the dielectric substrate in the multi-layer coil structure is the first coil structure; the second pole plate is electrically connected to the first coil structure.

4. The filter according to claim 3, wherein: The capacitor further includes a first lead terminal; The first lead end and the second electrode plate are arranged in the same layer, and the two are an integrally formed structure; the first lead end and the first coil structure are electrically connected through a second connecting via, and the second connecting via passes through the second interlayer insulating layer between the second electrode plate and the first coil structure.

5. The filter according to claim 1, wherein The coil structure closest to the dielectric substrate in the multi-layer coil structure is a first coil structure; The first pole plate and the first coil structure are arranged in the same layer and are electrically connected.

6. The filter according to claim 5, wherein The first pole plate and the first coil structure are an integrally formed structure.

7. The filter according to claim 6, wherein: The coil structure adjacent to the first coil structure in the multi-layer coil structure is a second coil structure; A third interlayer insulating layer is provided between the second coil structure and the dielectric substrate, and the third interlayer insulating layer covers the second pole plate, and the first pole plate and the first coil structure formed in one piece.

8. The filter according to claim 6, wherein: The coil structure adjacent to the first coil structure in the multi-layer coil structure is a second coil structure; A fourth interlayer insulating layer and a fifth interlayer insulating layer are provided between the second coil structure and the dielectric substrate, the fourth interlayer insulating layer is provided with a first accommodating portion penetrating along the thickness direction thereof, the first pole plate and the first coil structure formed integrally are confined in the first accommodating portion, and the surfaces of the first pole plate and the first coil structure formed integrally away from the dielectric substrate are flush with the surface of the fourth interlayer insulating layer away from the dielectric substrate; The fifth interlayer insulating layer is arranged on a side of the fourth interlayer insulating layer away from the dielectric substrate, and the fifth interlayer insulating layer covers the second electrode plate.

9. The filter according to claim 1, wherein: The coil structure closest to the dielectric substrate in the multi-layer coil structure is a first coil structure; The first coil structure includes a first sub-coil and a second sub-coil which are stacked, and the first sub-coil is located on a side of the second sub-coil close to the dielectric substrate; The first pole plate and the first sub-coil are arranged in the same layer and are electrically connected.

10. The filter according to claim 9, wherein The first pole plate and the first sub-coil are an integrally formed structure.

11. The filter according to any one of claims 1 to 10, wherein: It also includes a connection structure, which is arranged on a side of the inductor away from the dielectric substrate and is electrically connected to a third coil structure in the inductor farthest from the dielectric substrate through a third connection via hole; the third connection via hole penetrates a sixth interlayer insulating layer between the connection structure and the third coil structure.

12. The filter according to any one of claims 1 to 10, wherein: The first interlayer insulating layer between any adjacent coil structures includes a first surface and a second surface that are arranged opposite to each other along a thickness direction thereof, and the first surface and the second surface are parallel to a reference plane of the dielectric substrate extending along a first direction.

13. The filter according to any one of claims 1 to 10, wherein: Any seventh interlayer insulating layer in the same layer as the coil structure includes a first surface and a second surface arranged opposite to each other along the thickness direction thereof, and the first surface and the second surface are parallel to a reference surface of the dielectric substrate extending along the first direction.

14. A method for preparing a filter, comprising: A dielectric substrate is provided, and at least one capacitor and at least one inductor are formed on the dielectric substrate; wherein the steps of forming at least one capacitor and at least one inductor include: A first conductive pattern is formed on the dielectric substrate; the first conductive pattern at least includes a first electrode plate of the capacitor; A second conductive pattern is formed on a side of the first conductive pattern away from the dielectric substrate; the second conductive pattern includes a second electrode plate of the capacitor; at least one of the second electrode plate and the first electrode plate is electrically connected to the inductor; A multi-layer third conductive pattern is formed on a side of the second conductive pattern away from the dielectric substrate, and at least one first interlayer insulating layer is formed between adjacent third conductive patterns; the third conductive pattern includes a coil structure of the inductor, and the coil structures of adjacent layers are electrically connected through a first connecting via penetrating the first interlayer insulating layer therebetween; and the orthographic projections of any two of the multi-layer coil structures on the dielectric substrate partially overlap.

15. The method for preparing a filter according to claim 14, wherein: The forming of the first conductive pattern on the dielectric substrate comprises: forming a first conductive pattern including the first electrode plate on the dielectric substrate; The forming of a multi-layer third conductive pattern on a side of the second conductive pattern away from the dielectric substrate comprises: forming a multi-layer coil structure on a side of the second conductive pattern away from the dielectric substrate, wherein the coil structure closest to the dielectric substrate among the multi-layer coil structure is a first coil structure; and the first coil structure is electrically connected to the second pole plate through a second connecting via hole penetrating a second interlayer insulating layer between the first pole plate and the second pole plate.

16. The method for preparing a filter according to claim 14, wherein: The coil structure closest to the dielectric substrate in the multi-layer coil structure of the inductor is the first coil structure; Forming a first conductive pattern on the dielectric substrate includes: A first conductive pattern including the first pole plate and the first coil structure is formed on the dielectric substrate.

17. The method for preparing a filter according to claim 16, wherein: The first electrode plate and the first coil structure are an integrally formed structure; wherein, after forming the second conductive pattern, the method further includes: A third interlayer insulating layer is formed on a side of the second conductive pattern away from the first conductive pattern; the third interlayer insulating layer covers the second electrode plate, and the first electrode plate and the first coil structure formed in one piece.

18. The method for preparing a filter according to claim 16, wherein: The first pole plate and the first coil structure are an integrally formed structure; The first conductive pattern including the first electrode plate and the first coil structure is formed on the dielectric substrate, comprising: forming a fourth interlayer insulating layer on the dielectric substrate; the fourth interlayer insulating layer comprises a first accommodating portion penetrating along a thickness direction thereof; The first accommodating portion is filled with the first pole plate and the first coil structure formed integrally to form the first conductive pattern; the first pole plate and the first coil structure formed integrally are away from the surface of the dielectric substrate and are flush with the surface of the fourth interlayer insulating layer away from the dielectric substrate.

19. The method for preparing a filter according to claim 18, wherein: After forming the second conductive pattern, the method further includes: A fifth interlayer insulating layer is formed on a side of the second conductive pattern away from the first conductive pattern, and a surface of the fifth interlayer insulating layer away from the dielectric substrate is parallel to a reference plane of the dielectric substrate extending along the first direction.

20. The method for preparing a filter according to any one of claims 14 to 19, wherein the step of forming any layer of the third conductive pattern comprises: forming a seventh interlayer insulating layer on the dielectric substrate having the second conductive pattern formed thereon; The seventh interlayer insulating layer includes a second receiving portion penetrating along the thickness direction thereof; The coil structure material of the inductor is filled in the second accommodation portion to form the third conductive pattern; the third conductive pattern faces away from the surface of the dielectric substrate and is flush with the surface of the seventh interlayer insulating layer faces away from the dielectric substrate.

21. The method for preparing a filter according to any one of claims 14 to 19, wherein the step of forming any layer of the third conductive pattern comprises: A third conductive pattern including the coil structure is formed by electroplating on a side of the first interlayer insulating layer facing away from the dielectric substrate.

22. The method for preparing a filter according to any one of claims 14 to 19, wherein: The dielectric substrate includes a glass substrate.

23. An electronic device, wherein: The invention comprises the filter according to any one of claims 1 to 13.

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