Formation method of semiconductor structure

Abstract

A semiconductor structure forming method comprises the steps that a wafer is provided, a metal structure is formed in the wafer, and the top of the metal structure is exposed out of the surface of the wafer; carrying out warping degree detection on the surface of the wafer; carrying out heating treatment on the metal structure according to a warping degree detection result; and after heating treatment, the metal structure is cooled. According to the method, the warping degree of the wafer surface is improved, the process is simple and easy to operate, the process compatibility with a mature platform is high, and a semiconductor structure with high surface quality can be obtained.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor packaging technology, and in particular to a method for forming a semiconductor structure. Background Art

[0002] TSV (Through-Silicon Vias) technology is the core of advanced packaging technology. TSV is significantly different from conventional packaging technology in that the production of TSV can be integrated into different stages of the manufacturing process. The completion of through-silicon vias before the wafer manufacturing CMOS or BEOL step is usually called TSV-First. At this time, the production of TSV can be carried out before the front-end metal interconnection of the Fab plant to achieve Core-to-Core connection. This solution is currently being studied more in the field of high-performance devices such as microprocessors, mainly as an alternative to SoC. TSV-First can also be produced after CMOS is completed, and then the device manufacturing and back-end packaging are completed. TSV-Middle refers to the implementation of TSV before the front-end process and the back-end process of wafer manufacturing. Placing TSV after the back-end process is usually called TSV-Last.

[0003] TSV increases the speed of interconnect signals by reducing the distance between interconnects and the resistance of interconnects. After TSV is completed, it is usually necessary to make subsequent metal connections and continue stacking using bonding processes such as Fusion Bonding or Hybrid Bonding. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, which is conducive to obtaining a semiconductor structure with higher surface quality.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a wafer, a metal structure formed in the wafer, and the top of the metal structure exposed on the surface of the wafer; performing a warpage detection on the surface of the wafer; heating the metal structure according to the result of the warpage detection; and cooling the metal structure after the heat treatment.

[0006] Optionally, in the step of detecting the warpage of the wafer surface, the warpage values ​​of different areas of the wafer surface are obtained; in the step of heat-treating the metal structure according to the result of the warpage detection, the metal structure in each area is heat-treated separately according to the warpage value of each area of ​​the wafer surface.

[0007] Optionally, in the step of heating the metal structure in each area separately according to the warpage value at each location on the wafer surface, in an area where the warpage value is lower than that of the surrounding area, the set temperature for heating the metal structure is higher than that of the surrounding area.

[0008] Optionally, in the step of performing heat treatment on the metal structure according to the result of the warpage detection, corresponding heating parameters are set according to the result of the warpage detection, so as to perform heat treatment on the metal structure under the heating parameters.

[0009] Optionally, in the step of heating the metal structure according to the result of the warpage detection, the metal structure is heated by an electromagnetic induction heating method.

[0010] Optionally, in the step of providing a wafer, the wafer is placed on a stage in which an electromagnetic induction coil is disposed; in the step of heating the metal structure according to the result of the warpage detection, the metal structure is heated using an electromagnetic induction heating coil.

[0011] Optionally, a plurality of electromagnetic induction coils are disposed in the stage, and the plurality of electromagnetic induction coils are evenly distributed in a projection area of ​​the wafer on the surface of the stage.

[0012] Optionally, the step of heating the metal structure according to the result of the warpage detection is also used to expand the metal structure.

[0013] Optionally, in the step of providing a wafer, the step of forming a metal structure includes: patterning the wafer to form a plurality of through holes; forming a metal material layer that fills the through holes and covers the surface of the wafer; flattening the metal material layer, removing the metal material layer above the wafer surface, and retaining the metal material layer located in the through holes as a metal structure.

[0014] Optionally, the metal structure is cooled, and the forming method further includes: flattening the wafer surface and removing a portion of the metal structure protruding from the wafer surface.

[0015] Optionally, in the step of providing a wafer, the metal structure includes one or more of a through silicon via interconnect structure, a metal through hole interconnect structure or a metal line.

[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0017] In the method for forming a semiconductor structure provided in an embodiment of the present invention, the warpage of the wafer surface is detected, and the metal structure is heat-treated according to the result of the warpage detection. After the heat treatment, the metal structure is cooled. In the embodiment of the present invention, the metal structure is heat-treated according to the result of the warpage detection. The metal structure can be heated in a targeted manner according to the actual concave-convex condition of the wafer surface, and then cooled. The concave-convex condition of the wafer surface is adjusted by controlling the expansion and contraction degree of the metal structure, that is, the warpage of the wafer surface is adjusted. The warpage of the wafer surface can be improved without the deposition of an additional film layer. The process is simple and easy to operate, and has high process compatibility with mature platforms, which is conducive to obtaining a semiconductor structure with higher surface quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figures 1 to 3 It is a schematic structural diagram corresponding to each step of an embodiment of a method for forming a semiconductor structure of the present invention;

[0019] Figure 4 A graph showing a volume-warpage change value of a metal structure after a heat treatment under the same temperature conditions according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0020] As can be seen from the background technology, compared with the holes in the conventional wafer process, the size of the through-silicon-via (TSV) is larger. The diameter of the common TSV hole is between 3um-15um and the depth is between 3um-120um. Since the TSV hole needs to be filled with metal, such as Cu, this will have a great change in the warpage of the wafer. The bow value of the wafer is very large, resulting in the following two problems.

[0021] (1) Subsequent metal line production usually uses conventional photolithography (Litho ET) and planarization (ECP) processes. Litho has very high requirements for the wafer warpage. When the wafer surface is uneven, that is, the warpage is very poor, it will cause Litho focus failure and the Litho Process cannot proceed normally.

[0022] (2) During the bonding process, there are usually special requirements for the wafer's warpage. The top wafer and the bottom wafer's warpage need to be as small as possible, that is, the two wafers need to be as flat as possible, otherwise bonding problems will occur.

[0023] There are several common ways to improve the Warpage of Wafer after TSV Loop:

[0024] (1) Improving the Warpage of Wafer by Depositing Film Layers: The Warpage of Wafer can be controlled by depositing films such as oxide films on the wafer. Usually, the deposition of film layers is a high-temperature process. After the film layers are deposited, when the temperature is cooled to room temperature, different materials have different CTEs (coefficient of thermal expansion), that is, different thermal expansion coefficients. Different film layers shrink to different degrees relative to the substrate Si, which will generate horizontal friction in different directions, thereby changing the Warpage of Wafer.

[0025] (2) Post-processing of the deposited film structure, such as UV curing (UV Cure): UV Cure can further increase the tensile stress of the deposited film layer. The principle is that ultraviolet radiation can reduce the hydrogen content of the deposited material, thereby increasing the stress value of the film layer. At the same time, we can control the radiation wavelength of UV Cure to replace the unwanted hydrogen bonds (for example, replacing NH bond Si-H bond), increase the content of Si-N bonds (where Si-N bonds determine the tensile stress of the material), thereby increasing the tensile stress of the film layer, thereby better controlling the warpage of the wafer.

[0026] Currently, the main way to improve Wafer Warpage is to deposit film layers. The deposited film layers need to be subsequently processed by Litho Etch, ECP, CMP and other processes to make Metal lines to connect. Due to the increase in the deposited film layers, the thickness of the film layers we need to etch increases, and the thickness of the photoresist also needs to be increased accordingly; the thickness of the etched film layer increases, and the etching difficulty also increases accordingly; the aspect ratio of the hole becomes larger, resulting in an increase in the difficulty of filling ECP; when the aspect ratio of the hole increases, the thickness of the copper behind the ECP also increases accordingly, which causes the Cu CMP process time to be extended.

[0027] The hole size of TSV is relatively large, with a depth of tens of microns and a diameter of the order of microns. The amount of Cu filled inside is large, and the CTE difference of Cu is even greater. If the Wafer Warpage is improved by depositing a film layer, the film layer that needs to be deposited will be very thick and cannot meet the needs of large-scale mass production.

[0028] At the same time, this method can only adjust the Warpage of the entire wafer, and cannot achieve fine adjustment of the wafer Warpage of different areas.

[0029] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a wafer, a metal structure formed in the wafer, and the top of the metal structure exposed on the surface of the wafer; performing a warpage detection on the surface of the wafer; heating the metal structure according to the result of the warpage detection; and cooling the metal structure after the heat treatment.

[0030] In the embodiment of the present invention, the metal structure is heated according to the result of the warpage detection. The metal structure can be heated in a targeted manner according to the actual unevenness of the wafer surface, and then cooled. The unevenness of the wafer surface is adjusted by controlling the expansion and contraction degree of the metal structure, that is, the warpage of the wafer surface is adjusted. The warpage of the wafer surface can be improved without the deposition of additional film layers. The process is simple and easy to operate, and has high process compatibility with mature platforms, which is conducive to obtaining semiconductor structures with higher surface quality.

[0031] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] Figures 1 to 3 It is a schematic structural diagram corresponding to each step of an embodiment of a method for forming a semiconductor structure of the present invention.

[0033] refer to Figure 1 , a wafer 200 is provided, a metal structure 210 is formed in the wafer 200, and a top of the metal structure 210 is exposed on the surface of the wafer 200.

[0034] Wafer 200 is used for bonding with a wafer to be integrated in a subsequent process.

[0035] Wafer 200 has a circuit structure. After the device wafer 200 and the wafer to be integrated are subsequently bonded, the wafer to be integrated can be electrically connected to the circuit structure in wafer 200, thereby realizing the normal function of the packaging structure. Wafer 200 is also used to achieve vertical conduction with the wafer to be integrated, and to electrically lead out the devices of the wafer to be integrated, thereby realizing 3D packaging between wafers.

[0036] In this embodiment, the material of the wafer 200 includes silicon. In other embodiments, the material of the wafer may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the wafer may also be other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the wafer may be a material suitable for process requirements or easy to integrate.

[0037] In the present embodiment, in the step of providing the wafer 200 , the metal structure 210 includes one or more of a through silicon via interconnect structure, a metal through via interconnect structure or a metal line.

[0038] As an example, in this embodiment, the metal structure 210 is a through-silicon-via (TSV) structure, which is used to achieve vertical conduction of the wafer 200 , that is, electrical connection with other circuits can be achieved through the TSV structure in the wafer 200 .

[0039] In other embodiments, the metal structure may also be other metal hole structures.

[0040] The TSV structure enables the wafer 200 to have a higher stacking density in three dimensions and a smaller external size, and greatly improves chip speed and reduces chip power consumption.

[0041] In this embodiment, in the step of providing the wafer 200 , the step of forming the metal structure 210 includes: patterning the wafer 200 to form a plurality of through holes.

[0042] The plurality of through holes are used to provide spatial locations for forming the metal structure 210 .

[0043] In this embodiment, a metal material layer is formed to fill the through holes and cover the surface of the wafer 200 .

[0044] The metal material layer is used to form the metal structure 210 .

[0045] The metal material layer covers the entire wafer 200 . Therefore, the formation of the metal material layer will affect the warpage of the surface of the wafer 200 .

[0046] In this embodiment, the metal material layer is planarized, the metal material layer above the surface of the wafer 200 is removed, and the metal material layer located in the through hole is retained as the metal structure 210 .

[0047] The metal material layer has a large coverage area, and planarizing the metal material layer will also affect the warpage of the surface of the wafer 200 .

[0048] refer to Figure 2 In the step of providing the wafer 200 , the wafer 200 is placed on the stage 100 , and an electromagnetic induction coil 110 is disposed inside the stage 100 .

[0049] An electromagnetic induction coil 110 is disposed in the stage 100 for subsequently heating the metal structure 210 in the wafer 200 .

[0050] In this embodiment, a plurality of electromagnetic induction coils 110 are disposed in the stage 100 , and the plurality of electromagnetic induction coils 110 are evenly distributed in a projection area of ​​the wafer 200 on the surface of the stage 100 .

[0051] The multiple electromagnetic induction coils 110 are evenly distributed, so that the heating can be more uniform during the subsequent heating process of the metal structure 210 in the wafer 200, and each area of ​​the wafer 200 is distributed with an electromagnetic induction coil 110 that can be used for heating treatment.

[0052] Specifically, in this embodiment, the plurality of electromagnetic induction coils 110 may be evenly arranged as a plurality of concentric circles that surround in order from small to large, or the plurality of electromagnetic induction coils 110 may also be evenly arranged as a matrix array.

[0053] In this embodiment, the warpage detection is performed on the surface of the wafer 200 .

[0054] The warpage detection is performed on the surface of the wafer 200 so as to perform subsequent targeted heating treatment according to the detection result.

[0055] In this embodiment, in the step of detecting the warpage of the surface of the wafer 200 , the warpage values ​​of different areas of the surface of the wafer 200 are obtained.

[0056] The warpage values ​​of different areas on the surface of the wafer 200 are obtained, that is, the warpage value of the entire surface of the entire wafer 200 is obtained. The warpage value can characterize the concave-convex condition of the surface of the wafer 200 in detail, so that the subsequent adjustment of the wafer surface according to the warpage value is more accurate.

[0057] like Figure 3 (a), (b) and (c) show the warpage detection results of three types of wafers 200.

[0058] In this embodiment, the metal structure 210 is heated according to the result of the warpage detection.

[0059] The metal structure 210 is heated according to the result of the warpage detection, so that the expansion of the metal structure 210 in different areas can be used to specifically adjust the concave-convex conditions of the wafer 200 in different areas, thereby adjusting the warpage value of the wafer 200 .

[0060] It should be noted that in this embodiment, the metal structure 210 is heated in a targeted manner based on the result of the warpage detection, rather than heating the entire wafer 200. Thus, the warpage of the wafer 200 in different areas can be adjusted in a targeted manner by adjusting the metal structure 210 in each area.

[0061] In this embodiment, in the step of performing heat treatment on the metal structure 210 according to the result of the warpage detection, the metal structure 210 in each area is heated separately according to the warpage value of each area on the surface of the wafer 200 .

[0062] According to the warpage value of each area on the surface of the wafer 200, the metal structure 210 in each area is heated separately. In other words, the metal structure 210 of the wafer 200 can be zoned and heated at corresponding temperatures according to the warpage value of each area. This allows targeted adjustments to the warpage of the wafer 200 in different areas to obtain a wafer 200 with better flatness.

[0063] Specifically, in this embodiment, a special machine is designed, that is, electromagnetic induction coils 110 capable of independently controlling parameters such as power and frequency are added in different regions. According to the distribution of the wafer warpage, the principle of induction heating is used to adjust the parameters of each region in different regions, thereby controlling the temperature of the metal structure 210 in each region and the expansion degree of the metal structure 210 in different regions, thereby finely adjusting the wafer warpage to an ideal value.

[0064] In this embodiment, in the step of heating the metal structure 210 in each area according to the warpage value at each location on the surface of the wafer 200, the set temperature for heating the metal structure 210 is higher than that of the surrounding area in the area where the warpage value is lower than that of the surrounding area.

[0065] The higher the set temperature for heating the metal structure 210, the greater the degree of expansion of the metal structure 210. Therefore, in an area where the warpage value is lower than that of the surrounding area, the higher the set temperature for heating the metal structure 210 is relative to the surrounding area, the greater the warpage of the wafer 200 in the area caused by the metal structure 210 can be improved, thereby making the warpage value of the area closer to the warpage values ​​of other surrounding areas, which is beneficial to improving the surface flatness of the entire wafer 200.

[0066] Specifically, in the present embodiment, in the step of performing a heating treatment on the metal structure 210 according to the result of the warpage detection, corresponding heating parameters are set according to the result of the warpage detection, so as to perform a heating treatment on the metal structure 210 under the heating parameters.

[0067] In this embodiment, in the step of heating the metal structure 210 according to the result of the warpage detection, the metal structure 210 is heated by using an electromagnetic induction heating method.

[0068] Using electromagnetic induction heating to heat the metal structure 210 is beneficial to achieving the effect of heating only the metal structure 210 in the wafer 200. Using electromagnetic induction heating to heat the metal structure 210 can also achieve zoned heating, which is beneficial to separately heat the metal structures 210 in different areas of the wafer 200, achieve targeted heating treatment of different temperatures for areas with different warping degrees, and targeted adjustment of the warping degrees of different areas of the wafer 200.

[0069] Specifically, in the present embodiment, in the step of heating the metal structure 210 according to the result of the warpage detection, the metal structure 210 is heated by using the electromagnetic induction heating coil 110 .

[0070] In this embodiment, the step of performing a heating treatment on the metal structure 210 according to the result of the warpage detection is also used to perform an expansion treatment on the metal structure 210 .

[0071] The metal structure 210 is expanded, for example, by copper expansion, so that the metal structure 210 can better fill the space, reduce the probability of having gaps in the metal structure 210, and improve the performance of the semiconductor structure.

[0072] In this embodiment, the step of heating the metal structure 210 according to the result of the warpage detection and the step of expanding the metal structure 210 are simultaneously implemented by one heating treatment, which is beneficial to improving the process efficiency.

[0073] In this embodiment, after the heating treatment, the metal structure 210 is cooled.

[0074] After the heating treatment, the metal structure 210 is cooled, and the metal structure 210 expands and contracts, thereby adjusting the surface warpage of the wafer 200 through the metal structure 210 .

[0075] In the method for forming a semiconductor structure provided in the present embodiment, a warpage detection is performed on the surface of the wafer 200, and the metal structure 210 is heat-treated according to the result of the warpage detection. After the heat treatment, the metal structure 210 is cooled. In the present embodiment, the metal structure 210 is heat-treated according to the result of the warpage detection. The metal structure 210 can be heated in a targeted manner according to the actual unevenness of the surface of the wafer 200, and then cooled. The unevenness of the surface of the wafer 200 is adjusted by controlling the expansion and contraction degree of the metal structure 210, that is, the warpage of the surface of the wafer 200 is adjusted. The warpage of the surface of the wafer 200 can be improved without the deposition of an additional film layer. The process is simple and easy to operate, and has high process compatibility with mature platforms, which is conducive to obtaining a semiconductor structure with high surface quality.

[0076] Referring to Table 1, a temperature-warpage experimental result data table is shown. Specifically, Table 1 shows the warpage detection results after the wafer 200 is heated at different temperatures, wherein the heating treatment time is set to 60 minutes (min), and the heating treatment temperatures are set to 410°C, 350°C and 200°C, respectively. Bow X change represents the warpage change value of the wafer 200 in the X direction, and Bow Y change represents the warpage change value of the wafer 200 in the Y direction. From the degree of change of the warpage values ​​of the two wafers 200 (Wafer 1 and Wafer 2) after the heating treatment at different temperatures in Table 1, it can be seen that the heating treatment of this embodiment can better improve the warpage of the surface of the wafer 200, and it can also be seen that the higher the temperature of the heating treatment, the greater the improvement of the warpage of the wafer 200.

[0077] Wafer 1 Wafer 2 Bow X Changes Bow Y Changes Bow X Changes Bow Y Changes 410℃60min 57.42 54.30 56.66 50.95 350℃60min 30.03 22.88 28.60 22.73 200℃60min 25.61 19.15 27.67 19.76

[0078] Table 1

[0079] refer to Figure 4 , shows a curve diagram of the volume-warpage change value of the metal structure 210 after the heating treatment under the same temperature conditions, wherein the abscissa is the volume of the metal structure 210, and the ordinate is the warpage change value before and after the wafer 200 is heated. In this embodiment, the wafer 200 with metal structures 210 of different volumes is heated under the same temperature conditions. Figure 4 It can be seen that under the same temperature conditions, the change in the warpage of the wafer 200 is positively correlated with the volume of the metal structure 210. Correspondingly, the mechanism is that the thermal expansion coefficients of the material of the metal structure 210 (e.g., copper) and the material of the wafer 200 (e.g., silicon) are different. As a result, the larger the volume of the internal metal material, that is, the larger the volume of the metal structure 210, the greater the change in the warpage of the wafer.

[0080] In this embodiment, after the metal structure 210 is cooled, the forming method further includes: planarizing the surface of the wafer 200 and removing the portion of the metal structure 210 protruding from the surface of the wafer 200 .

[0081] After the metal structure 210 is cooled, the surface of the wafer 200 is planarized and the portion of the metal structure 210 protruding from the surface of the wafer 200 is removed, which is beneficial to improving the surface planarity of the wafer 200 .

[0082] It should be noted that at this time, the metal structure 210 on the surface of the wafer 200 has fewer protrusions. Therefore, planarizing the surface of the wafer 200 and removing the portion of the metal structure 210 protruding from the surface of the wafer 200 has little effect on the warpage of the surface of the wafer 200.

[0083] Referring to Table 2, there is shown a data table of experimental results of the warpage change value after different planarization treatments. Specifically, in the present embodiment, in the step of forming the metal structure 210, after forming a metal material layer that fills the through hole and covers the surface of the wafer 200, the metal material layer needs to be planarized to remove the metal material layer on the surface of the wafer 200 and retain the metal material layer in the through hole as the metal structure 210. This is the first planarization treatment, i.e., the 1st CMP (chemical mechanical planarization) in Table 2.

[0084] Next, in order to improve the warpage of the wafer 200, a heating treatment is used. After heating different positions of the wafer 200 in different zones, the metal in the metal structure 210 will expand due to the heat and form certain protrusions on the surface of the wafer 200. Therefore, it is necessary to perform another flattening treatment on the protruding metal material to remove the portion of the metal structure 210 protruding from the surface of the wafer 200. This is the second flattening treatment, i.e., the 2nd CMP in Table 2.

[0085] Specifically, the second planarization process is a CMP rework process, so generally speaking, compared with the first planarization process, the second planarization process removes less, exerts less pressure on the wafer 200 , and has a shorter process time. Therefore, the second planarization process has little effect on the warpage of the wafer 200 .

[0086] In addition, the area of ​​the metal structure 210 in the wafer 200 is usually relatively small, so the second planarization process has little effect on the warpage of the wafer 200 .

[0087] As an example, after the wafer 200 is heated for 60 minutes (min) at a process temperature of 410°C, the thickness of the protrusion of the metal structure 210 is about 2000 angstroms. After the second planarization treatment, the thickness of the remaining protrusion is about 400 angstroms-500 angstroms, that is, the removal amount of the second planarization treatment is small.

[0088] As an example, the total time of the first planarization process is 1025 seconds (s), and the total time of the second planarization process is 30s. Compared with the first planarization process, the time of the second planarization process is shorter, and thus the effect time on the wafer 200 is shorter.

[0089] Referring to Table 2, for two wafers 200 (Wafer 1 and Wafer 2), the warpage change values ​​after the first planarization process and the second planarization process are collected. After the first planarization process, the change in the warpage value of the wafer is large, while after the second planarization process, the change in the warpage value of the wafer is small, so it can be seen that the second planarization process has little effect on the warpage value of the wafer 200.

[0090]

[0091] Table 2

[0092] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a wafer, wherein a metal structure is formed in the wafer, and a top of the metal structure is exposed on a surface of the wafer; Performing warpage detection on the surface of the wafer; performing a heating treatment on the metal structure according to the result of the warpage detection; After the heating treatment, the metal structure is cooled.

2. The method for forming a semiconductor structure according to claim 1, wherein: In the step of detecting the warpage of the wafer surface, warpage values ​​of different areas of the wafer surface are obtained; In the step of performing heat treatment on the metal structure according to the result of the warpage detection, the metal structure in each area is heated separately according to the warpage value of each area on the surface of the wafer.

3. The method for forming a semiconductor structure according to claim 2, wherein: In the step of heating the metal structure in each area according to the warpage value at each location on the wafer surface, the set temperature for heating the metal structure is higher relative to the surrounding area in an area where the warpage value is lower than that of the surrounding area.

4. The method for forming a semiconductor structure according to any one of claims 1 to 3, characterized in that: In the step of performing a heating treatment on the metal structure according to the result of the warpage detection, corresponding heating parameters are set according to the result of the warpage detection, so as to perform a heating treatment on the metal structure under the heating parameters.

5. The method for forming a semiconductor structure according to claim 1, wherein: In the step of heating the metal structure according to the result of the warpage detection, the metal structure is heated by using an electromagnetic induction heating method.

6. The method for forming a semiconductor structure according to claim 1 or 5, characterized in that: In the step of providing a wafer, the wafer is placed on a stage, wherein an electromagnetic induction coil is disposed inside the stage; In the step of heating the metal structure according to the result of the warpage detection, the metal structure is heated by using the electromagnetic induction heating coil.

7. The method for forming a semiconductor structure according to claim 6, wherein: A plurality of electromagnetic induction coils are arranged in the stage, and the plurality of electromagnetic induction coils are evenly distributed in the projection area of ​​the wafer on the surface of the stage.

8. The method for forming a semiconductor structure according to claim 1, wherein: The step of heating the metal structure according to the result of the warpage detection is also used to expand the metal structure.

9. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing a wafer, the step of forming the metal structure includes: patterning the wafer to form a plurality of through holes; forming a metal material layer filling the through hole and covering the surface of the wafer; The metal material layer is planarized, the metal material layer above the surface of the wafer is removed, and the metal material layer in the through hole is retained as the metal structure.

10. The method for forming a semiconductor structure according to claim 1, wherein: After cooling the metal structure, the forming method further comprises: flattening the surface of the wafer and removing the portion of the metal structure protruding from the surface of the wafer.

11. The method for forming a semiconductor structure according to claim 1, wherein: In the step of providing the wafer, the metal structure includes one or more of a through silicon via interconnect structure, a metal through hole interconnect structure or a metal line.

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