Semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method thereof, and the method for manufacturing the semiconductor element mainly comprises the steps: firstly, defining a cutting channel on the front surface of a wafer, and enabling the wafer to comprise an intermetallic dielectric layer disposed on a substrate and a staggered stacking structure disposed on the intermetallic dielectric layer; a portion of the interlaced stacked structure is removed to form a groove in the front surface of the wafer, a dielectric layer is formed in the groove, and a dicing process is performed from the back surface of the wafer along the dicing channel to divide the wafer into a plurality of chips.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor element, and more particularly to a method for filling a dielectric layer with a higher dielectric constant in a cutting path before cutting a wafer. Background Art

[0002] With the advancement of science and technology, technologies such as augmented reality (AR) and virtual reality (VR) have gradually matured. In the foreseeable future, technologies such as augmented reality and virtual reality will be widely used in human life, such as in education, logistics, medical care, and military fields.

[0003] At present, augmented reality and virtual reality are mainly realized by head-mounted display devices. Among them, the current head-mounted display devices usually connect display driver integrated circuits (DDIC) containing high-voltage components, medium-voltage components and / or low-voltage components to a display module via very long wires or metal internal connections. The products presented by this design are usually larger in size, which not only takes up space but also increases the difficulty of wearing. Therefore, how to provide a display that can be used in AR or VR environments by improving the current manufacturing process is an important issue at present. Summary of the invention

[0004] An embodiment of the present invention discloses a method for manufacturing a semiconductor device, which mainly defines a cutting path on the front side of a chip, wherein the chip includes an intermetallic dielectric layer disposed on a substrate and a staggered stacking structure disposed on the intermetallic dielectric layer. Then, a portion of the staggered stacking structure is removed to form a groove on the front side of the chip, a dielectric layer is formed in the groove, and then a cutting process is performed from the back side of the chip along the cutting path to separate the chip into a plurality of chips.

[0005] Another embodiment of the present invention discloses a semiconductor device, which mainly includes a chip obtained after a cutting process, wherein the chip further includes an intermetallic dielectric layer disposed on a substrate, a staggered stacking structure disposed on the intermetallic dielectric layer, and a dielectric layer disposed on a sidewall of the staggered stacking structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1 to 5 A schematic diagram of a method for manufacturing a micro display according to an embodiment of the present invention;

[0007] Figure 6 A top view of a lower wafer after the bonding pad is fabricated according to an embodiment of the present invention;

[0008] Figure 7 It is a cross-sectional schematic diagram of a lower wafer after the bonding pad is fabricated according to an embodiment of the present invention;

[0009] Figure 8 Flow chart for cutting the upper wafer;

[0010] Figures 9 to 11 A schematic cross-sectional view of cutting the upper wafer;

[0011] Fig.12 It is a schematic structural diagram of a semiconductor chip obtained after a cutting process according to an embodiment of the present invention.

[0012] Explanation of symbols

[0013] 12: Chip

[0014] 14: Chip

[0015] 16: Base

[0016] 18: First Area

[0017] 20: Second Area

[0018] 22: The third area

[0019] 24: Intermetallic dielectric layer

[0020] 26: Metal interconnects

[0021] 28: Solder pad

[0022] 30: Solder pad

[0023] 32: Solder pad

[0024] 34: Chip

[0025] 36: Microdisplay

[0026] 38: Display pixels

[0027] 40: Wire

[0028] 52: Grain area

[0029] 62: Circuit area

[0030] 64: Junction area

[0031] 66: Solder pad area

[0032] 70: Secondary junction area

[0033] 72: Solder pad

[0034] 74: Solder pad

[0035] 76: Stop layer

[0036] 78: Intermetallic dielectric layer

[0037] 80: Stop layer

[0038] 82: Intermetallic dielectric layer

[0039] 84: Stop layer

[0040] 86: Intermetallic dielectric layer

[0041] 88: Stop layer

[0042] 92: Lower half

[0043] 94: Upper part

[0044] 96: Lower half

[0045] 98: Upper part

[0046] 100: Solder pad

[0047] 102: Lower half

[0048] 104: Upper part

[0049] 106:Metal winding

[0050] 108:Metal interconnect

[0051] 112: staggered stacking structure

[0052] 114: Ultra-low dielectric constant dielectric layer

[0053] 116: Barrier layer

[0054] 118: Groove

[0055] 120: Dielectric layer

[0056] 128: Cutting Road

[0057] 140:Lamination process

[0058] 142: Invisible laser cutting production process

[0059] 144: Grinding process

[0060] 146: Expanded production process DETAILED DESCRIPTION

[0061] Although specific configurations and arrangements are discussed herein, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

[0062] It should be noted that references in the specification to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such terms do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a technician in the relevant field to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0063] Typically, terms can be understood at least in part based on usage in context. For example, the term "one or more" as used herein (depending at least in part on the context) can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a plural combination of features, structures or features. Similarly, terms such as "one", "an" or "the" can again be understood to express singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and can instead allow for the presence of additional factors that are not necessarily explicitly described, and depending at least in part on the context.

[0064] It should be easily understood that the meanings of “on,” “over,” and “above” in the disclosure of this case should be interpreted in the broadest manner, so that “on” not only means “directly” on something, but also includes the meaning of being on something and having intermediate features or layers therebetween, and “on” or “above” not only means being on something or over something, but also includes the meaning of having no intermediate features or layers (i.e., directly on something).

[0065] Additionally, for ease of description, as represented in the drawings, spatially relative terms such as "below," "beneath," "lower," "above," "higher," etc. may be used to describe the relationship of one element or feature to another element(s) or feature(s). The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0066] As used herein, the term "substrate" refers to a material to which a layer of material is subsequently added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0067] As used herein, the term "layer" refers to a portion of a material including an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a uniform or non-uniform continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers above and / or below it. A layer may contain multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (in which contacts, interconnects and / or through-holes are formed) and one or more dielectric layers.

[0068] Please refer to Figures 1 to 5 , Figures 1 to 5 FIG. 1 is a schematic diagram of a method for manufacturing a micro display according to an embodiment of the present invention. Figure 1 As shown, firstly, a chip 12 and a chip 14 made of semiconductor material are provided, wherein the chip 12 is preferably provided with medium voltage components, high voltage components and pixel circuits, etc., and the chip 14 is preferably provided with low voltage components of low voltage driving circuits and / or a graphics processing unit (GPU). More specifically, each chip 12, 14 includes a substrate 16 made of semiconductor material, and each substrate 16 can be a semiconductor substrate such as a silicon substrate, an epitaxial silicon substrate, a silicon carbide substrate, etc., or even a substrate made of silicon-on-insulator (SOI), and these material selections are all within the scope of the present invention.

[0069] It should be noted that since the chip 12 is preferably used to carry or connect some low-voltage components and display modules of the chip 14 after cutting in the subsequent manufacturing process, a plurality of die areas 52 can be first defined on the chip 12 to be cut after subsequent bonding with other chips. The area or size of each die area 52 is preferably much larger than the chip to be bonded later, and three regions are preferably defined on each die area 52, including a first region 18, a second region 20 and a third region 22, wherein the first region 18 includes a bonding region for subsequent connection to an external circuit, the second region 20 includes a chip to wafer region for subsequent bonding after the cut chip 14 is formed into multiple die or chips, and the third region 22 is a micro display region for connecting a micro display module.

[0070] In addition, the chips 12 and 14 in the present embodiment may each include, for example, metal oxide semiconductor (MOS) transistors, oxide field effect semiconductor transistors (OS FETs), fin-shaped structure transistors (FinFETs) or other active (active) elements and / or other passive (passive) elements according to the manufacturing process or product selection. Taking the manufacturing of metal oxide semiconductor transistors as an example, it may include a gate structure disposed on the substrate 16, a spacer (not shown) disposed on the sidewall of the gate structure, a source / drain region disposed in the substrate on both sides of the spacer, an interlayer dielectric layer or an intermetallic dielectric layer 24 disposed on each metal oxide semiconductor transistor, and a metal interconnect 26 disposed in the interlayer dielectric layer or the intermetallic dielectric layer 24 and connecting each metal oxide semiconductor transistor. In the present embodiment, each element on the chip 12 is preferably manufactured using a 65-80 nanometer technology node, and each element on the chip 14 is preferably manufactured using a 28-40 nanometer technology node.

[0071] In addition, at this stage or before other cut chips are bonded to the wafer 12, a plurality of solder pads 28, 30, 32 are preferably provided on the wafer 12 in each of the first region 18, the second region 20, and the third region 22 to electrically connect the aforementioned active components or passive components. In order to make the best connection with subsequent components, the solder pads 28, 30, 32 in the first region 18, the second region 20, and the third region 22 on the wafer 12 may be selected to include the same or different materials as the objects to which the solder pads 28, 30, 32 are subsequently connected, and the solder pads 28, 30, 32 between each of the first region 18, the second region 20, and the third region 22 may also include the same or different materials.

[0072] For example, in this embodiment, the pads 28 disposed in the first region 18 and the pads 30 disposed in the second region 20 may include the same or different materials, the pads 28 disposed in the first region 18 and the pads 32 disposed in the third region 22 may include the same or different materials, and the pads 30 disposed in the second region 20 and the pads 32 disposed in the third region 22 may include the same or different materials. In this embodiment, the pads 28 disposed in the first region 18 are used for external circuit connection later, so it is preferred to use a material with lower impedance such as but not limited to gold, the pads 30 disposed in the second region 20 are preferably made of copper, and the pads 32 disposed in the third region 22 are used to connect the solder balls or bumps of the subsequent micro display module and may therefore be made of copper or aluminum. It should be noted that, compared to the chip 12 having a plurality of pads 28, 30, 32 disposed in each of the first region 18, the second region 20 and the third region 22 at this stage, the chip 14 is only provided with the aforementioned active components and metal interconnects 26 for connecting the active components at this stage but without any pads.

[0073] In addition, the pads 28, 30, 32 in each of the first region 18, the second region 20, and the third region 22 preferably include different line widths (pitch) or spacings. For example, in the present embodiment, the line width or spacing between the pads 28 in the first region 18 is preferably greater than the line width or spacing between the pads 30 in the second region 20 and the line width or spacing between the pads 32 in the third region 22. The line width or spacing between the pads 30 in the second region 20 may be equal to or slightly smaller than the line width or spacing between the pads 32 in the third region 22. In the present embodiment, the line width or spacing between the pads 28 in the first region 18 is preferably between 20 and 200 microns, the line width or spacing between the pads 30 in the second region 20 is preferably between 1 and 20 microns, and the line width or spacing between the pads 32 in the third region 22 is preferably between 2 and 20 microns.

[0074] It should also be noted that the line width or spacing between the pads 28, 30, 32 in each region mentioned above preferably means that the line width or spacing between each pad 28, 30, 32 in each region is smaller or larger than the line width or spacing between each pad 28, 30, 32 in other regions. That is, the line width or spacing between the pads 28 in the first region 18 is larger than the line width or spacing between the pads 30 in the second region 20 and the line width or spacing between the pads 32 in the third region 22. It preferably means that the line width or spacing between each pad 28 in the first region 18 is larger than the line width or spacing between each pad 30 in the second region 20 and the line width or spacing between each pad 32 in the third region 22.

[0075] Then as Figure 2 As shown, a thinning process is performed on the wafer 14 to remove a portion of the substrate 16 of the wafer 14 so that the total thickness is slightly reduced, and then a wafer cutting process is performed to separate the wafer 14 into a plurality of dies or chips 34.

[0076] like Figure 3 As shown, the aforementioned cut chip 34 is then flipped over and subjected to a bonding process to bond the components carrying the low-voltage driving circuit and / or the graphics processor to the uncut wafer 12 provided with the medium-voltage components and the high-voltage components. In this embodiment, the metal interconnects 26 on the chip 34 are preferably bonded to the pads 30 of the second region 20 on the wafer 12 using a hybrid bonding process, wherein the metal interconnects 26 on the chip 34 are preferably made of copper and the pads 30 on the second region 20 are also preferably made of copper, so the two are preferably bonded in a face-to-face manner using hybrid bonding.

[0077] like Figure 4 As shown, a display module manufacturing process is then performed to form a micro display 36 on the third region 22 of the chip 12 to connect the pads 32 on the third region 22. In this embodiment, the micro display 36 may include display elements such as an organic light emitting diode display (OLED display), a mini light emitting diode display, or a micro light emitting diode display according to the manufacturing process or product requirements, and each micro display 36 may include display pixels 38 such as red, green, and blue.

[0078] Afterwards Figure 5 As shown, a wire 40 for connecting to an external circuit is formed and connected to a pad 28 provided on the first region 18 of the chip 12, and then the chip 12 is cut into chips or dies of a desired size along the die region 52 defined at the beginning for subsequent packaging according to the manufacturing process requirements. In this embodiment, the wire 40 for connecting to an external circuit is preferably made of copper, and the pad 28 on the first region 18 is preferably made of a low-impedance material such as gold. Thus, the manufacturing of a micro display of the present invention is completed.

[0079] Please refer to Figure 6 to Figure 7 , Figure 6 to Figure 7 They are respectively a top view and a cross-sectional schematic diagram of the lower wafer after the pad is made in the above embodiment of the present invention, wherein Figure 6 The right half is a top view of the entire lower wafer and the left half is a top view of the secondary bonding area in the right half bonding area. Figure 6As shown, the semiconductor element mainly includes a circuit area 62 disposed on the substrate 16 or the chip 12, a bonding area 64 surrounding the circuit area 62, and a pad area 66 surrounding the bonding area 64, wherein a plurality of pads 28 are disposed on the pad area 66 in the right half, and the bonding area 64 further includes a plurality of sub-bonding areas 70, and each sub-bonding area 70 further includes a pad 72 and a pad 74 as shown in the left half.

[0080] If compared with the previous manufacturing process diagram, the pad area 66 is preferably the aforementioned first area 18 and the pad 28 is preferably the pad 28 of the first area 18, the bonding area 64 is the aforementioned second area 20 or the third area 22 on the die area 52, and the pads 72 and 74 can be the pads 30 on the second area 20 or the pads 32 on the third area 22.

[0081] From a detailed perspective, the multiple sub-joining areas 70 are preferably evenly distributed on the joining area 64 and surround the circuit area 62. Each sub-joining area 70 is approximately rectangular when viewed from a top view. Each sub-joining area 70 includes a plurality of solder pads 72 and solder pads 74, and the solder pads 72 and solder pads 74 are arranged on different layers. The solder pads 72 and solder pads 74 preferably include different shapes when viewed from a top view, for example, the solder pads 72 include squares when viewed from a top view, and the solder pads 74 include hexagons when viewed from a top view.

[0082] In this embodiment, the distance a from the edge of the pad 72 to the edge of the pad 74 is preferably between 0 and 6 microns or more preferably about 0.3 microns. The distance b from the edge of the secondary bonding area 70 to the edge of the pad 28 in the pad area 66 is preferably between 0 and 8 microns or more preferably 4 microns, and the distance c from the edge of the secondary bonding area 70 to the edge of the circuit area 62 is preferably between 0 and 6 microns or more preferably 3 microns.

[0083] from Figure 7 From a cross-sectional perspective, first, as described above, active components such as MOS transistors can be formed on the substrate 16 of the substrate or chip 12 according to the manufacturing process or product requirements, and then an interlayer dielectric layer or an intermetallic dielectric layer 24 is formed on each metal oxide semiconductor transistor and a metal interconnect 26 is disposed in the interlayer dielectric layer or the intermetallic dielectric layer 24 and connects each metal oxide semiconductor transistor. In this embodiment, the circuit area 62 is provided with a plurality of dummy pads such as the pad 100 and the metal winding 106, the joint area 64 is provided with pads 72 and 74, and the pad area 66 is provided with a pad 28. Each pad 28, 72, 74 is preferably provided on the active component and connected to the metal interconnect 26, and the upper metal inter-dielectric layer structure provided on the metal interconnect 26 and surrounding the pads 28, 72, 74, 100 may include a stop layer 76, an inter-metal dielectric layer 78, a stop layer 80, an inter-metal dielectric layer 82, a stop layer 84, an inter-metal dielectric layer 86 and a stop layer 88.

[0084] From a detailed perspective, the metal interconnect 26 preferably extends from the bonding area 64 to the pad area 66 and the metal interconnect 26 preferably simultaneously connects the pads 72, 74 respectively disposed in the bonding area 64 and the pad 28 disposed in the pad area 66, wherein the pad 72 in the bonding area 64 includes a lower half 92 connected to the metal interconnect 26 and an upper half 94 disposed on the lower half 92, the pad 74 includes a lower half 96 connected to the upper half 94 of the pad 72 and an upper half 98 disposed on the lower half 96, and the pad 28 disposed in the pad area 66 also includes a lower half 102 connected to the metal interconnect 26 and an upper half 104 disposed on the lower half 102.

[0085] Overall, the top surface of the lower half 92 of the pad 72 in the bonding area 64 is preferably aligned with the top surface of the intermetallic dielectric layer 78 and the top surface of the lower half 102 of the pad 28 in the pad area 66, the top surface of the upper half 94 of the pad 72 in the bonding area 64 is preferably aligned with the top surface of the upper half 104 of the pad 28 in the pad area 66, the top surface of the lower half 96 of the pad 74 in the bonding area 64 is preferably aligned with the top surface of the intermetallic dielectric layer 82, and the top surface of the upper half 98 of the pad 74 in the bonding area 64 is preferably aligned with the top surface of the pad 100 in the circuit area 62. The distance a from the left side wall of the lower half 92 of the pad 72 in the bonding area 64 to the right side wall of the lower half 96 of the upper pad 74 is the same as described above. Figure 6 As shown, the preferred value is between 0-6 microns or more preferably about 0.3 microns, the distance b from the approximately left side wall of the upper half 94 of the pad 72 in the bonding area 64 to the approximately right side wall of the upper half 104 of the pad 28 in the pad area 66 is preferably between 0 and 8 microns or optimally 4 microns, and the distance c from the right side wall of the upper half 98 of the pad 74 in the bonding area 64 to the left side wall of the pad 100 in the circuit area 62 is preferably between 0 and 6 microns or optimally 3 microns.

[0086] From the material aspect, each pad 28, 72, 74, 100 may further include a barrier layer and a metal layer, wherein the barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta) and tantalum nitride (TaN), and the metal layer may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but not limited thereto. In this example, the pads 28 and 72 directly contacting and connected to the metal interconnect 26 preferably include the same material, such as aluminum, and the upper layer including the pad 74 and the pad 100 is preferably made of copper. However, it is not limited thereto, according to other embodiments of the present invention, the pad 28 may be made of gold as described in the above embodiment. In addition, the intermetal dielectric layers 78, 82, 86 preferably include silicon oxide or ultra-low dielectric constant dielectric layers, and the stop layers 76, 80, 84, 88 include nitrogen doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but are not limited thereto.

[0087] Please continue to refer to Figures 8 to 9 , Figures 8 to 12 For the aforementioned Figure 1 to Figure 2 Schematic diagram of the manufacturing process when cutting the wafer 14, wherein Figure 8 For the above-mentioned flow chart when the wafer 14 is cut Figures 9 to 12 It is a cross-sectional schematic diagram of the wafer 14 when it is cut and after the wafer 14 is separated. Figures 1 to 5 The manufacturing processes are preferably completed in a wafer fab or an outsourced semiconductor assembly and test (OSAT). For example, the manufacturing processes such as forming active components and bonding pads on the wafer 12 are preferably manufactured in a wafer fab, while the wafer 14 is preferably separated and bonded to the wafer 12 in an outsourced semiconductor assembly and test (OSAT).

[0088] like Figures 8 to 9 As shown, the present invention is Figure 2A staggered stacking structure 112 is preferably provided on the multiple intermetallic dielectric layers 24 and the metal interconnects 26 of the front-end manufacturing process before the manufacturing process or after the manufacturing of active devices or passive devices is completed on the wafer 14, wherein the staggered stacking structure 112 further comprises multiple ultra-low dielectric constant layers 114 and multiple metal barrier layers or barrier layers 116 that are staggered and stacked with each other. In the present embodiment, the ultra-low dielectric constant layer 114 preferably comprises a dielectric material with a dielectric constant of 2.4 to 3.6, which may include a porous dielectric material such as but not limited to silicon oxycarbide (SiOC) or silicon oxycarbide hydrogen (SiOCH), and the barrier layer 116 preferably comprises a dielectric material with a dielectric constant of 3.8 to 7.5 such as nitrogen-doped carbide layer (NDC), silicon nitride, or silicon nitride carbide (SiCN).

[0089] Then, a plurality of scribe lines 128 required in the scribe manufacturing process may be defined on the wafer 14, and then a portion of the staggered stacked structure 112 may be removed along the scribe lines 128 using photolithography and etching processes to form a groove 118 on the front side of the wafer 14. It should be noted that the width of the formed groove 118 is preferably smaller than the width of the scribe line 128. According to one embodiment of the present invention, the width of the groove 118 is preferably about 60-80% of the width of the scribe line 128, for example, the width of the groove 118 is preferably between 20-80 microns and the width of the scribe line 128 is preferably between 82-100 microns.

[0090] like Fig.10 As shown, a dielectric layer 120 is then formed in the groove 118, not only filling the groove 118 but also covering the staggered stacked structure 112 on both sides of the groove 118, wherein the dielectric layer 120 preferably comprises a dielectric material with a higher dielectric constant than the ultra-low dielectric constant dielectric layers 114 on both sides, such as a dielectric material with a dielectric constant of 3.8 to 4.6. In the present embodiment, the dielectric layer 120 preferably comprises silicon oxide, but is not limited thereto.

[0091] like Fig.11 As shown, a planarization process is then performed, such as using a chemical mechanical polishing (CMP) process to remove a portion of the dielectric layer 120, so that the remaining dielectric layer 120 has a flat surface and the top surface of the dielectric layer 120 is still higher than the top surfaces of the staggered stacked structures 112 on both sides.

[0092] Afterwards Figure 8 and Fig.12As shown, a laminating process 140 can be performed in the outsourcing packaging and testing foundry to form a tape and affix it to the front side of the wafer 14 to prevent the surface of the wafer 14 from being contaminated during subsequent grinding. It should be noted that since the grooves 118 in the scribe line 128 on the front side of the wafer 14 have been filled with the dielectric layer 120, the tape affixed by the laminating process 140 is preferably also affixed to the surface of the dielectric layer 120.

[0093] Then, a dicing process or more specifically a stealth dicing process 142 may be performed to cut the substrate 16 portion of the wafer 14 from the back side of the wafer 14 but not to completely separate the wafer 14 into multiple chips. Then, a grinding process 144 is performed on the back side of the wafer 14 to remove part of the wafer 14 and remove the tape on the front side of the wafer, and then an expanding process 146 is performed to separate the wafer 14 into multiple dies or chips 34 using a device such as a wafer expander.

[0094] like Fig.12 As shown, in this embodiment, after the wafer 14 is divided into a plurality of chips 34 by using the expansion process 146, each chip 34 preferably includes an intermetallic dielectric layer 24 disposed on the substrate 16, a staggered stacking structure 112 disposed on the intermetallic dielectric layer 24, and a dielectric layer 120 disposed on the sidewalls of the staggered stacking structure 112 and the intermetallic dielectric layer 24. As mentioned above, the staggered stacking structure 112 further includes a plurality of ultra-low dielectric constant dielectric layers 114 and a plurality of barrier layers 116 staggered and stacked with each other. It should be noted that, since the expansion process 146 gradually separates the wafer 14 from the back side of the wafer 14 or the substrate 16 toward the dielectric layer 120 in the cutting path 128 on the front side of the wafer 14, the sidewalls of each chip 34 finally separated preferably include the remaining dielectric layer 120 disposed on the sidewalls of the staggered stacking structure 112, and the sidewalls of the dielectric layer 120 are preferably cut flush with the sidewalls of the substrate 16 below along the vertical direction. According to an embodiment of the present invention, the thickness of the entire chip 14 is preferably about 700-800 microns or more preferably 750 microns, and the thickness of the dielectric layer 120 is preferably less than half of the thickness of the entire chip 34, such as less than one-third, one-quarter or even one-fifth of the thickness of the entire chip 34.

[0095] In summary, the present invention mainly forms a groove in the cutting path on the front side of the wafer before cutting the wafer, and then fills a dielectric layer 120 in the groove, wherein the dielectric constant of the dielectric layer 120 composed of silicon oxide is preferably greater than the dielectric constant of the ultra-low dielectric constant dielectric layer 114 on both sides of the groove or the cutting path. Since debris pollution is easily generated when the material with a lower dielectric constant is separated by the expansion process in the later stage during the general cutting process, the present invention first fills the material with a higher dielectric constant into part of the cutting path, and then cuts and separates the dielectric layer 120 with a higher dielectric constant from the back side of the wafer, which can greatly reduce the generation of debris and pollution and improve the overall chip quality.

[0096] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: Include: Defining scribe lines on the front side of the wafer; forming a groove on the front side of the wafer; forming a dielectric layer in the groove; and A cutting process is performed along the cutting street from the back side of the wafer.

2. The method of claim 1, further comprising: performing a lamination process to form an adhesive tape on the front side of the wafer; and The dicing process is performed to separate the wafer into a plurality of chips.

3. The method of claim 1, wherein the wafer comprises: an intermetallic dielectric layer disposed on the substrate; and The staggered stacking structure is arranged on the intermetallic dielectric layer.

4. The method of claim 3, further comprising: removing the staggered stacking structure to form the groove; and The dielectric layer is formed in the groove. 5 . The method of claim 3 , wherein the staggered stack structure comprises a plurality of ultra-low-k dielectric layers and a plurality of barrier layers stacked alternately with each other. The method according to claim 1 , wherein the groove width is smaller than the scribe line width. The method of claim 1 , wherein the dielectric layer comprises silicon oxide.

8. A semiconductor element, characterized in that: Include: The chip obtained after the cutting process includes: The staggered stacking structure is disposed on the substrate; and The dielectric layer is disposed on the sidewall of the staggered stacking structure.

9. The semiconductor device according to claim 8, further comprising: an intermetallic dielectric layer disposed on the substrate; and The staggered stacking structure is arranged on the intermetallic dielectric layer. 10 . The semiconductor device as claimed in claim 8 , wherein the sidewall of the dielectric layer is flush with the sidewall of the substrate. 11 . The semiconductor device as claimed in claim 8 , wherein the staggered stack structure comprises a plurality of ultra-low-k dielectric layers and a plurality of barrier layers stacked alternately with each other.

12. The semiconductor device as claimed in claim 8, wherein the dielectric layer comprises silicon oxide.

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